Re: [flashrom] [commit] r885 - trunk

[Luc Verhaegen]

On Thu, Jan 28, 2010 at 08:02:37PM +0100, [e-mail] wrote:
> Author: uwe
> Date: 2010-01-28 20:02:36 +0100 (Thu, 28 Jan 2010)
> New Revision: 885
>
> Modified:
>    trunk/board_enable.c
> Log:
> The GIGABYTE GA-7ZM has a maximum decode size (parallel chips) of 512 KB.
>
> Add this information to the new field in the board-enable table. We match the
> board via two sets of PCI IDs. However, as we don't need a board-enable
> function for this board (it works out of the box; well, at least if you remove
> the JP9 jumper on the board), change the code to allow NULL as value for
> the board-enable function. There will likely be more boards in the future where
> we want to record a maximum decode size but which don't need a board-enable.
>
> This is hardware-tested on the GIGABYTE GA-7ZM by successfully writing a 512KB
> image of random bytes to a chip in this board.
>
> Signed-off-by: Uwe Hermann 
> Acked-by: Sean Nelson
> Modified: trunk/board_enable.c
>
> --- trunk/board_enable.c	2010-01-27 10:08:33 UTC (rev 884)
> +++ trunk/board_enable.c	2010-01-28 19:02:36 UTC (rev 885)
> @@ -1208,6 +1208,7 @@
>    {0x1106, 0x3177, 0x1106, 0x3177,  0x1106, 0x3059, 0x1695, 0x3005, NULL,          NULL,         NULL,          "EPoX",        "EP-8K5A2",              0,   w836xx_memw_enable_2e},
>    {0x10EC, 0x8139, 0x1695, 0x9001,  0x11C1, 0x5811, 0x1695, 0x9015, NULL,          NULL,         NULL,          "EPoX",        "EP-8RDA3+",             0,   nvidia_mcp_gpio31_raise},
>    {0x8086, 0x7110,      0,      0,  0x8086, 0x7190,      0,      0, NULL,          "epox",       "ep-bx3",      "EPoX",        "EP-BX3",                0,   board_epox_ep_bx3},
> {0x1106, 0x0686, 0x1106, 0x0686,  0x1106, 0x3058, 0x1458, 0xa000, NULL,          NULL,         NULL,          "GIGABYTE",    "GA-7ZM",                512, NULL},
> {0x1039, 0x0761,      0,      0,  0x10EC, 0x8168,      0,      0, NULL,          "gigabyte",   "2761gxdk",    "GIGABYTE",    "GA-2761GXDK",           0,   it87xx_probe_spi_flash},
> {0x1106, 0x3227, 0x1458, 0x5001,  0x10ec, 0x8139, 0x1458, 0xe000, NULL,          NULL,         NULL,          "GIGABYTE",    "GA-7VT600",             0,   it8705f_write_enable_2e},
> {0x10DE, 0x0050, 0x1458, 0x0C11,  0x10DE, 0x005e, 0x1458, 0x5000, NULL,          NULL,         NULL,          "GIGABYTE",    "GA-K8N-SLI",            0,   nvidia_mcp_gpio21_raise},

http://www.google.de/#q=1106%3A0686+1106%3A0686+1106%3A3058+1458%3Aa000&...

reveals that there are at least two different boards which matches this.

You are only matching the southbridge here, and a relatively bogus (and common)
subsystem id, which only tells us that it's a gigabyte board.

The VT82C686 was a _hugely_ successful southbridge. I cannot even begin to
count how many gigabyte boards use this chipset.

So, first; swap the pairs around.
Second, use 0x1106, 0x0305, 0, 0 to at least narrow the northbridge down.

A further check on the gigabyte gives me 17 possible combinations of the
different kt133 variations and the 686 southbridge. This makes it completely
impossible to even consider the above change a sufficient match.

Please provide the output of flashrom -V so we can identify a DMI match.

The above logic should give you some idea of the investigation required
to get a good match. It just takes a few minutes to do so too.

Luc Verhaegen.