ACER ASPIRE L5100

[Gildas Le Nadan]

Hi

Here are the informations you asked for on #flashrom (I've added 
dmidecode as well).

Cheers,
Gildas aka mael_

[Luc Verhaegen]

On Tue, Sep 01, 2009 at 01:37:05AM +0200, Gildas Le Nadan wrote:
> Hi
>
> Here are the informations you asked for on #flashrom (I've added 
> dmidecode as well).
>
> Cheers,
> Gildas aka mael_
> 00:14.0 SMBus [0c05]: ATI Technologies Inc SBx00 SMBus Controller [1002:4385] (rev 14)
>    Subsystem: Foxconn International, Inc. Device [105b:0e0b]
> 00:14.3 ISA bridge [0601]: ATI Technologies Inc SB600 PCI to LPC Bridge [1002:438d]
>    Subsystem: Foxconn International, Inc. Device [105b:0e0b]

Psuedo code for flash enable on this board:

pci8(00:14.0, 0x79) |= 0x01;
pci8(00:14.3, 0x48) |= 0x21;
io(0xc6f) |= 0x40;
io(0xcd6) = 0x03;
io(0xcd7) &= ~0x01;

This doesn't really match the chipset enable for the SB600.
> From irc:

<carldani> pci(00:14.0, 0x79) |= 0x01; enables 0xC6F decoding.
<carldani> pci(00:14.3, 0x48) |= 0x21; enables 0x2E-0x2F passthrough 
 and enables LPC memory target range (lowest 64k)
<carldani> io(0xc6f) |= 0x40; is Flash program enable (but only if the 
 flash lives on the PCI bus, otherwise that setting is ignored)
<carldani> finally,  io(0xcd6) = 0x03; io(0xcd7) &= ~0x01; clears 
 IRQ0->SMI triggering

<carldani> and since flashrom does not support flashing ROMs living on 
 the PCI bus yet, this doesn't look odd. maybe we should add that
 setting to flashrom

So it seems that we need more than just board enable work.

Luc Verhaegen.