[PATCH 7/7] check if write enable is really set in nicintel_spi_init (and minor comment changes).

[Stefan Tauner]

Signed-off-by: Stefan Tauner 
---
 nicintel_spi.c |   15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/nicintel_spi.c b/nicintel_spi.c
index 811ed6e..88d86af 100644
--- a/nicintel_spi.c
+++ b/nicintel_spi.c
@@ -34,11 +34,14 @@

#define MEMMAP_SIZE getpagesize()

+/* EEPROM/Flash Control & Data Register */
 #define EECD	0x10
+/* Flash Access Register */
 #define FLA	0x1c

/*
  * Register bits of EECD.
+ * Table 13-6
  * 
  * Bit 04, 05: FWE (Flash Write Enable Control)
  * 00b = not allowed
@@ -49,8 +52,9 @@
 #define FLASH_WRITES_DISABLED	0x10 /* FWE: 10000b */
 #define FLASH_WRITES_ENABLED	0x20 /* FWE: 100000b */

-/* Flash Access register bits */
-/* Table 13-9 */
+/* Flash Access register bits
+ * Table 13-9
+ */
 #define FL_SCK	0
 #define FL_CS	1
 #define FL_SI	2
@@ -157,6 +161,13 @@ int nicintel_spi_init(void)
    tmp |= FLASH_WRITES_ENABLED;
    pci_mmio_writel(tmp, nicintel_spibar + EECD);

+	/* test if FWE is really set to allow writes */
+	tmp = pci_mmio_readl(nicintel_spibar + EECD);
+	if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp &
FLASH_WRITES_ENABLED) ) {
+		msg_perr("Enabling flash write access failed.\n");
+		return 1;
+	}
+
    /* 1 usec halfperiod delay for now. */
    if (bitbang_spi_init(&bitbang_spi_master_nicintel, 1))
    	return 1;