Tested mainboards: OK: - ASRock Fatal1ty 970 Performance and P4i65G Reported by anonymous email message ID: 932677687262b1300eaf14260999d9262c31@guerrillamail.com The latter actually had a tested board enable already.
Flash chips: - GigaDevice GD25VQ41B to PREW (+PREW) Reported by David Hendricks - Winbond W39V040FB to PREW (+EW) Reported by fjed on IRC
Miscellaneous: - Change PCI IDs of "MS-6577 (Xenon)" board enable. The previous IDs contained the on-board display adapter which is disabled when a dedicated graphics card is installed. - Add a note to the README how to overcome the clang warning if only a single programmer is enabled. - Fix some typo and manpage problems found by lintian - r1920 introduced some explicit calls to pkg-config instead of $(PKG_CONFIG). This patch corrects that. - Add some overrides to the Makefile in case someone/something sets variables like CPPFLAGS or LDFLAGS as command line parameters
Signed-off-by: Stefan Tauner stefan.tauner@alumni.tuwien.ac.at Acked-by: Stefan Tauner stefan.tauner@alumni.tuwien.ac.at --- Makefile | 34 ++++++++++++++--------------- README | 6 ++++++ board_enable.c | 2 +- flashchips.c | 66 ++++++++++++++++++++++++++++----------------------------- flashrom.8.tmpl | 38 ++++++++++++++++++--------------- pickit2_spi.c | 2 +- print.c | 4 ++-- sb600spi.c | 2 +- 8 files changed, 82 insertions(+), 72 deletions(-)
diff --git a/Makefile b/Makefile index 927105d..d9a70b3 100644 --- a/Makefile +++ b/Makefile @@ -314,7 +314,7 @@ UNSUPPORTED_FEATURES += CONFIG_PONY_SPI=yes else override CONFIG_PONY_SPI = no endif -# Dediprog, USB-Blaster, PICkit2, CH341A and FT2232 are not supported with libpayload (missing libusb support) +# Dediprog, USB-Blaster, PICkit2, CH341A and FT2232 are not supported with libpayload (missing libusb support). ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -661,22 +661,22 @@ override CONFIG_CH341A_SPI = no override CONFIG_DEDIPROG = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) -override CONFIG_INTERNAL = no -override CONFIG_NIC3COM = no -override CONFIG_GFXNVIDIA = no -override CONFIG_SATASII = no -override CONFIG_ATAHPT = no -override CONFIG_ATAVIA = no -override CONFIG_ATAPROMISE = no -override CONFIG_IT8212 = no -override CONFIG_DRKAISER = no -override CONFIG_NICREALTEK = no -override CONFIG_NICNATSEMI = no -override CONFIG_NICINTEL = no -override CONFIG_NICINTEL_SPI = no -override CONFIG_NICINTEL_EEPROM = no -override CONFIG_OGP_SPI = no -override CONFIG_SATAMV = no +override CONFIG_INTERNAL = no +override CONFIG_NIC3COM = no +override CONFIG_GFXNVIDIA = no +override CONFIG_SATASII = no +override CONFIG_ATAHPT = no +override CONFIG_ATAVIA = no +override CONFIG_ATAPROMISE = no +override CONFIG_IT8212 = no +override CONFIG_DRKAISER = no +override CONFIG_NICREALTEK = no +override CONFIG_NICNATSEMI = no +override CONFIG_NICINTEL = no +override CONFIG_NICINTEL_SPI = no +override CONFIG_NICINTEL_EEPROM = no +override CONFIG_OGP_SPI = no +override CONFIG_SATAMV = no endif
# Bitbanging SPI infrastructure, default off unless needed. diff --git a/README b/README index 604e793..ab761f7 100644 --- a/README +++ b/README @@ -136,6 +136,12 @@ Processor architecture dependent features: use port-based I/O which is not directly available on non-x86. Those programmers will be disabled automatically if you run "make".
+Compiler quirks: + +If you are using clang and if you want to enable only one driver, you may hit an +overzealous compiler warning from clang. Compile with "make WARNERROR=no" to +force it to continue and enjoy. + Installation ------------
diff --git a/board_enable.c b/board_enable.c index 7b152d1..2d52fe1 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2440,7 +2440,7 @@ const struct board_match board_matches[] = { {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise}, {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise}, {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e}, - {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e}, + {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x24C3, 0x1462, 0x5770, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, "^MS-7094$", NULL, NULL, P3, "MSI", "MS-7094 (K8T Neo2-F V2.0)", 0, OK, w83627thf_gpio44_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, diff --git a/flashchips.c b/flashchips.c index 238389b..f8d3628 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5368,13 +5368,13 @@ const struct flashchip flashchips[] = { .probe_timing = TIMING_ZERO, .block_erasers = { - { - .eraseblocks = { {64 * 1024, 8} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {512 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } + { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } }, .printlock = spi_prettyprint_status_register_bp2_srwd, .unlock = spi_disable_blockprotect_bp2_srwd, @@ -5399,13 +5399,13 @@ const struct flashchip flashchips[] = { .probe_timing = TIMING_ZERO, .block_erasers = { - { - .eraseblocks = { {64 * 1024, 16} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } + { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } }, .printlock = spi_prettyprint_status_register_bp2_srwd, .unlock = spi_disable_blockprotect_bp2_srwd, @@ -6303,27 +6303,27 @@ const struct flashchip flashchips[] = { .page_size = 256, /* OTP: 1536B total; read 0x48, write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = + .block_erasers = { - { - .eraseblocks = { { 4 * 1024, 128} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { { 32 * 1024, 16} }, - .block_erase = spi_block_erase_52, - }, { - .eraseblocks = { { 64 * 1024, 8} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {512 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { {512 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } + { + .eraseblocks = { { 4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { { 32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { { 64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } }, /* TODO: 2nd Status Register; read 0x35 */ .printlock = spi_prettyprint_status_register_bp4_srwd, @@ -15469,7 +15469,7 @@ const struct flashchip flashchips[] = { .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .block_erasers = diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index cb77e46..5de735b 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -1,9 +1,11 @@ ." Load the www device when using groff; provide a fallback for groff's MTO macro that formats email addresses. .ie \n[.g] \ . mso www.tmac -.el \ -. de MTO \$2 (la\$1 (ra\$3 +.el { +. de MTO + \$2 (la\$1 (ra\$3 \ . . +.} ." Create wrappers for .MTO and .URL that print only text on systems w/o groff or if not outputting to a HTML ." device. To that end we need to distinguish HTML output on groff from other configurations first. .nr groffhtml 0 @@ -208,7 +210,7 @@ Please note that MediaWiki output is not compiled in by default. Specify the programmer device. This is mandatory for all operations involving any chip access (probe/read/write/...). Currently supported are: .sp -.BR "* internal" " (default, for in-system flashing in the mainboard)" +.BR "* internal" " (for in-system flashing in the mainboard)" .sp .BR "* dummy" " (virtual programmer for testing flashrom)" .sp @@ -237,16 +239,10 @@ cards)" .sp .BR "* it8212" " (for flash ROMs on ITE IT8212F ATA/RAID controller)" .sp -.BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H/FT232H family \ -based USB SPI programmer), including the DLP Design DLP-USB1232H, \ -FTDI FT2232H Mini-Module, FTDI FT4232H Mini-Module, openbiosprog-spi, Amontec \ -JTAGkey/JTAGkey-tiny/JTAGkey-2, Dangerous Prototypes Bus Blaster, \ -Olimex ARM-USB-TINY/-H, Olimex ARM-USB-OCD/-H, TIAO/DIYGADGET USB -Multi-Protocol Adapter (TUMPA), TUMPA Lite, GOEPEL PicoTAP and Google Servo v1/v2. +.BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H/FT232H family based USB SPI programmer). .sp .BR "* serprog" " (for flash ROMs attached to a programmer speaking serprog, \ -including Arduino-based devices as well as various programmers by Urja Rannikko, \ -Juhana Helovuo, Stefan Tauner and others)." +including some Arduino-based devices)." .sp .BR "* buspirate_spi" " (for SPI flash ROMs attached to a Bus Pirate)" .sp @@ -684,13 +680,18 @@ size (padding to 32 kB is required). .IP This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their -size nor allow to be identified, the controller relies on correct size values written to predefined addresses -within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed -EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) -M95128, M95256 and OnSemi (Catalyst) CAT25CS128. +size nor allow themselves to be identified, the controller relies on correct size values written to predefined +addresses within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an +unprogrammed EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: +Atmel AT25128, AT25256, Micron (ST) M95128, M95256 and OnSemi (Catalyst) CAT25CS128. .SS .BR "ft2232_spi " programmer .IP +This module supports various programmers based on FTDI FT2232/FT4232H/FT232H chips including the DLP Design +DLP-USB1232H, openbiosprog-spi, Amontec JTAGkey/JTAGkey-tiny/JTAGkey-2, Dangerous Prototypes Bus Blaster, +Olimex ARM-USB-TINY/-H, Olimex ARM-USB-OCD/-H, OpenMoko Neo1973 Debug board (V2+), TIAO/DIYGADGET USB +Multi-Protocol Adapter (TUMPA), TUMPA Lite, GOEPEL PicoTAP and Google Servo v1/v2. +.sp An optional parameter specifies the controller type and channel/interface/port it should support. For that you have to use the .sp @@ -736,6 +737,9 @@ syntax. .SS .BR "serprog " programmer .IP +This module supports all programmers speaking the serprog protocol. This includes some Arduino-based devices +as well as various programmers by Urja Rannikko, Juhana Helovuo, Stefan Tauner, Chi Zhang and many others. +.sp A mandatory parameter specifies either a serial device (and baud rate) or an IP/port combination for communicating with the programmer. The device/baud combination has to start with @@ -981,7 +985,7 @@ Please note that the linux_spi driver only works on Linux. .BR "mstarddc_spi " programmer .IP The Display Data Channel (DDC) is an I2C bus present on VGA and DVI connectors, that allows exchanging -informations between a computer and attached displays. Its most common uses are getting display capabilities +information between a computer and attached displays. Its most common uses are getting display capabilities through EDID (at I2C address 0x50) and sending commands to the display using the DDC/CI protocol (at address 0x37). On displays driven by MSTAR SoCs, it is also possible to access the SoC firmware flash (connected to the Soc through another SPI bus) using an In-System Programming (ISP) port, usually at address 0x49. @@ -1016,7 +1020,7 @@ Example that does not reset the display at the end of the operation: .sp .B " flashrom -p mstarddc_spi:dev=/dev/i2c-1:49,noreset=1 .sp -Please note that sending the reset command is also inhibited in the event an error occured during the operation. +Please note that sending the reset command is also inhibited in the event an error occurred during the operation. To send the reset command afterwards, you can simply run flashrom once more, in chip probe mode (not specifying an operation), without the .B noreset diff --git a/pickit2_spi.c b/pickit2_spi.c index f1f60a2..f6aa676 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -400,7 +400,7 @@ static int pickit2_shutdown(void *data)
int pickit2_spi_init(void) { - unsigned int usedevice = 0; // FIXME: allow to select one of multiple devices + unsigned int usedevice = 0; // FIXME: allows one to select one of multiple devices
uint8_t buf[CMD_LENGTH] = { CMD_EXEC_SCRIPT, diff --git a/print.c b/print.c index 7b0e8e9..08bad02 100644 --- a/print.c +++ b/print.c @@ -490,11 +490,9 @@ int print_supported(void) case USB: print_supported_devs(prog, "USB"); break; -#if NEED_PCI == 1 case PCI: print_supported_devs(prog, "PCI"); break; -#endif case OTHER: if (prog.devs.note != NULL) { msg_ginfo("\nSupported devices for the %s programmer:\n", prog.name); @@ -571,6 +569,7 @@ const struct board_info boards_known[] = { B("ASRock", "AMCP7AION-HT", OK, "http://www.asrock.com/nettop/NVIDIA/ION%20330HT/", "Used in ION 330HT(-BD) barebones."), B("ASRock", "ConRoeXFire-eSATA2", OK, "http://www.asrock.com/mb/overview.asp?model=conroexfire-esata2", NULL), B("ASRock", "E350M1/USB3", OK, "http://www.asrock.com/mb/overview.asp?model=e350m1/usb3", "Vendor firmware writes to flash at shutdown. This probably corrupts the flash in case you write coreboot while running the vendor firmware. Simply updating the vendor firmware should be fine."), + B("ASRock", "Fatal1ty 970 Performance", OK, "http://www.asrock.com/mb/overview.asp?Model=Fatal1ty%20970%20Performance", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASRock", "Fatal1ty Z77 Performance", BAD, "http://www.asrock.com/mb/overview.asp?Model=Fatal1ty%20Z77%20Performance", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASRock", "G31M-GS", OK, "http://www.asrock.com/mb/overview.asp?Model=G31M-GS", NULL), B("ASRock", "G31M-S rev 2.0", OK, "http://www.asrock.com/mb/overview.asp?model=G31M-S", NULL), @@ -585,6 +584,7 @@ const struct board_info boards_known[] = { B("ASRock", "M3A790GXH/128M", OK, "http://www.asrock.com/mb/overview.asp?Model=M3A790GXH/128M", NULL), B("ASRock", "N61P-S", OK, "http://www.asrock.com/mb/overview.asp?Model=N61P-S", NULL), B("ASRock", "N68C-S UCC", OK, "http://www.asrock.com/mb/overview.asp?Model=N68C-S%20UCC", NULL), + B("ASRock", "P4i65G", OK, "http://www.asrock.com/mb/overview.asp?Model=P4i65G", NULL), B("ASRock", "P4i65GV", OK, "http://www.asrock.com/mb/overview.asp?Model=P4i65GV", NULL), B("ASRock", "Z68 Extreme4", BAD, "http://www.asrock.com/mb/overview.asp?Model=Z68%20Extreme4", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "A7N8X Deluxe", OK, "http://www.asus.com/Motherboards/AMD_Socket_A/A7N8X_Deluxe/", NULL), diff --git a/sb600spi.c b/sb600spi.c index 37ecfd9..9cedbff 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -511,7 +511,7 @@ static int handle_imc(struct pci_dev *dev) msg_pinfo("Writes have been disabled for safety reasons because the presence of the IMC\n" "was detected and it could interfere with accessing flash memory. Flashrom will\n" "try to disable it temporarily but even then this might not be safe:\n" - "when it is reenabled and after a reboot it expects to find working code\n" + "when it is re-enabled and after a reboot it expects to find working code\n" "in the flash and it is unpredictable what happens if there is none.\n" "\n" "To be safe make sure that there is a working IMC firmware at the right\n"
-
Stefan Tauner