# flashrom -p internal:boardenable=force -m iBASE:MB899 -w coreboot.rom flashrom v0.9.1-runknown on Linux 2.6.18-skas3-v9-pre9-default (i686), built with libpci 2.2.4-pre4, GCC 3.4.6 (Debian 3.4.6-5) No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. NOTE: Running an untested board enable procedure. Please report success/failure to flashrom@flashrom.org. Disabling flash write protection for board "iBASE MB899"... Intel ICH LPC Bridge: Raising GPIO26. OK. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Writing flash chip... Erasing flash chip... SUCCESS. Programming page: DONE!ss: 0x0007f000 COMPLETE. Verifying flash... VERIFIED.
On Tue, Apr 20, 2010 at 12:01:53PM +0200, Bernhard M. Wiedemann wrote:
# flashrom -p internal:boardenable=force -m iBASE:MB899 -w coreboot.rom flashrom v0.9.1-runknown on Linux 2.6.18-skas3-v9-pre9-default (i686), built with libpci 2.2.4-pre4, GCC 3.4.6 (Debian 3.4.6-5) No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. NOTE: Running an untested board enable procedure. Please report success/failure to flashrom@flashrom.org. Disabling flash write protection for board "iBASE MB899"...
Thanks, marked the board-enable of the board as tested.
Uwe.
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Bernhard M. Wiedemann -
Uwe Hermann