On the most recent version of the Chromium flashrom effort, there was a patch for Apollo Lake. I have applied it to the latest, fixed up one issue in the get_target_bus_from_chipset() to return the right BBS strapping. It finds the Winbond chip and starts to read, and gets an error when reading the ROM using the HWSEQ style. I have tracked it down to the function that waits for complete, where it fails.
Any thoughts?
Thanks,
Tim Lewis
P.S. I have this working with other flash utilities, so I know that the hardware is working and the flash part is present and responds.
FAILED.p@p-desktop:~/Desktop/Blinkflash-Linux64-100.00.00.03$ sudo ./flashrom -p internal -r 123.bin -VV flashrom v0.9.7-unknown on Linux 4.4.0-21-generic (x86_64), built with libpci 3.2.1, GCC 4.8.4, little endian flashrom is free software, get the source code at http://www.flashrom.org
Initializing internal programmer No coreboot table found. get_target_bus_from_chipset() returns 0x10. Found chipset "Intel Apollolake" with PCI ID 8086:5af0. Enabling flash write... Vendor ID: 8086, Device ID: 5a96, BAR: fed01000
BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x89 SPI BAR is = 0xfed01000 GCS = 0x89: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) SPIBAR = 0xfed01000 + 0x0000 0x04: 0x3f00e000 (HSFSC) WARNING: SPI Configuration Lockdown activated. 0x08: 0x00000000 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-write 0x58: 0x06fe0001 (FREG1: BIOS) 0x00001000-0x006fefff is read-write 0x5C: 0x00007fff (FREG2: Management Engine) Management Engine region is unused. 0x60: 0x00007fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00007fff (FREG4: Platform Data) Platform Data region is unused. 0x84: 0x00000000 (PR0, unused) 0x88: 0x00000000 (PR1, unused) 0x8C: 0x00000000 (PR2, unused) 0x90: 0x00000000 (PR3, unused) 0x94: 0x00000000 (PR4, unused) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x00040003 FLMAP1 0x13100208 FLMAP2 0x00000000
--- Details --- NR (Number of Regions): 1 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 19 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x080 MSL/PSL (MCH/PROC Strap Length): 0 FMSBA (Flash MCH/PROC Strap Base Address): 0x000
=== Component Section === FLCOMP 0x649c02f4 FLILL 0xad604221
--- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: reserved Read ID and Status Clock Freq.: 50 MHz Write and Erase Clock Freq.: 50 MHz Fast Read is supported. Fast Read Clock Frequency: 50 MHz Invalid instruction 0: 0x21 Invalid instruction 1: 0x42 Invalid instruction 2: 0x60 Invalid instruction 3: 0xad
=== Region Section === FLREG0 0x00000000 FLREG1 0x06fe0001
--- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00001000 - 0x006fefff
=== Master Section === FLMSTR1 0xffffff00 FLMSTR2 0xffffff00 FLMSTR3 0x7ff7ff00
--- Details --- Descr. BIOS ME GbE Platf. BIOS rw rw rw rw rw ME rw rw rw rw rw GbE rw rw rw w rw
SPI Read Configuration: prefetching enabled, caching enabled, OK. This programmer supports the following protocols: FWH, Programmer-specific. Probing for Winbond W25Q128.V, 0 kB: Found 1 attached SPI flash chip with a density of 8192 kB. There are 2048 erase blocks with 4096 B each. Found Winbond flash chip "W25Q128.V" (8192 kB, Programmer-specific) at physical address 0x0. Found Winbond flash chip "W25Q128.V" (8192 kB, Programmer-specific). === The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading flash... Reading 8388608 bytes starting at 0x000000. Transaction error between offset 0x00000000 and 0x0000003f (= 0x00000000 + 63) failed to read 0x0-0x7fffff Read operation failed! FAILED.p@p-desktop:~/Desktop/Blinkflash-Linux64-100.00.00.03$
Hi Tim,
On Tue, Nov 8, 2016 at 1:02 PM, Tim Lewis tim.lewis@insyde.com wrote:
On the most recent version of the Chromium flashrom effort, there was a patch for Apollo Lake. I have applied it to the latest, fixed up one issue in the get_target_bus_from_chipset() to return the right BBS strapping.
Do you mean that you applied it to the latest upstream flashrom version?
I'm afraid upstream and chromium.org's flashrom branches have diverged quite significantly, so there are likely other patches needed to get Apollo Lake support fully functioning. Ramya Vijaykumar at Intel submitted a few patches to update hardware sequencing logic (for Skylake support).
Here are a few gleaned from the commit log: https://chromium-review.googlesource.com/#/c/265818/ https://chromium-review.googlesource.com/#/c/322078/ https://chromium-review.googlesource.com/#/c/360192/ https://chromium-review.googlesource.com/#/c/359981/ https://chromium-review.googlesource.com/#/c/385186/
Have you tried using chromium.org's flashrom? It might be a better starting point for the platform you're working on.
Transaction error between offset 0x00000000 and 0x0000003f (= 0x00000000 + 63)
This is pretty interesting since your flash descriptor permissions are set to read-write. Hmmm...
Further, upstream flashrom will fail once it encounters a region that is fully locked by the ME, whereas chromium.org's flashrom will ignore such errors. So you'll need to be careful not to try accessing locked regions.
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David Hendricks -
Tim Lewis