[commit] r1754 - trunk

[repository service]

Author: stefanct
Date: Wed Oct  2 03:21:57 2013
New Revision: 1754
URL: http://flashrom.org/trac/flashrom/changeset/1754

Log:
rayer_spi: Add pinout for Altera ByteBlasterMV.

There is a ByteBlasterII product that is only almost compatible.

Signed-off-by: Maksim Kuleshov 
Signed-off-by: Kyösti Mälkki 
Tested-by: Maksim Kuleshov 
Acked-by: Kyösti Mälkki 
Signed-off-by: Stefan Tauner 
Acked-by: Stefan Tauner

Modified:
   trunk/flashrom.8.tmpl
   trunk/rayer_spi.c

Modified: trunk/flashrom.8.tmpl
==============================================================================
--- trunk/flashrom.8.tmpl	Wed Oct  2 03:21:45 2013	(r1753)
+++ trunk/flashrom.8.tmpl	Wed Oct  2 03:21:57 2013	(r1754)
@@ -759,12 +759,15 @@
 syntax where
 .B model
 can be
-.BR rayer " for the RayeR cable or " xilinx " for the Xilinx Parallel Cable III
-(DLC 5).
+.BR rayer " for the RayeR cable, " byteblastermv " for the Altera ByteBlasterMV, or " xilinx \
+" for the Xilinx Parallel Cable III (DLC 5)."
 .sp
 More information about the RayeR hardware is available at
 .nh
 .BR "http://rayer.ic.cz/elektro/spipgm.htm " .
+The Altera ByteBlasterMV datasheet can be obtained from
+.nh
+.BR "http://www.altera.co.jp/literature/ds/dsbytemv.pdf " .
 The schematic of the Xilinx DLC 5 was published in
 .nh
 .BR "http://www.xilinx.com/support/documentation/user_guides/xtp029.pdf " .

Modified: trunk/rayer_spi.c
==============================================================================
--- trunk/rayer_spi.c	Wed Oct  2 03:21:45 2013	(r1753)
+++ trunk/rayer_spi.c	Wed Oct  2 03:21:57 2013	(r1754)
@@ -70,9 +70,22 @@
    .miso_bit = 4,
 };

+static void byteblaster_preinit(const void *);
+static int byteblaster_shutdown(void *);
+
+static const struct rayer_pinout altera_byteblastermv = {
+	.cs_bit = 1,
+	.sck_bit = 0,
+	.mosi_bit = 6,
+	.miso_bit = 7,
+	.preinit =  byteblaster_preinit,
+	.shutdown = byteblaster_shutdown,
+};
+
 static const struct rayer_programmer rayer_spi_types[] = {
    {"rayer",		NT,	"RayeR SPIPGM",					&rayer_spipgm},
    {"xilinx",		NT,	"Xilinx Parallel Cable III (DLC 5)",		&xilinx_dlc5},
+	{"byteblastermv",	OK,	"Altera ByteBlasterMV",				&altera_byteblastermv},
    {0},
 };

@@ -195,6 +208,19 @@
    return 0;
 }

+static void byteblaster_preinit(const void *data){
+	msg_pdbg("byteblaster_preinit\n");
+	/* Assert #EN signal. */
+	OUTB(2, lpt_iobase + 2 );
+}
+
+static int byteblaster_shutdown(void *data){
+	msg_pdbg("byteblaster_shutdown\n");
+	/* De-Assert #EN signal. */
+	OUTB(0, lpt_iobase + 2 );
+	return 0;
+}
+
 #else
 #error PCI port I/O access is not supported on this architecture yet.
 #endif