
Hello My PIIX machines has only paralell, i doubt if there is any other option for that chipset. One line patch in attachment. Signed-Off: Maciej Pijanka <maciej.pijanka@gmail.com> -- Maciej Pijanka reg. Linux user #133161

On Thu, 03 Dec 2009, Maciej Pijanka wrote:
Hello
My PIIX machines has only paralell, i doubt if there is any other option for that chipset.
One line patch in attachment.
Signed-Off: Maciej Pijanka <maciej.pijanka@gmail.com>
Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 791) +++ chipset_enable.c (working copy) @@ -270,6 +270,8 @@ uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
+ buses_supported = CHIP_BUSTYPE_PARALLEL; + old = pci_read_word(dev, xbcs);
/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
ping? I hoped this is enough trivial to be applied without long review procedure. best regards Maciej -- Maciej Pijanka reg. Linux user #133161

On Sat, Dec 05, 2009 at 10:13:51AM +0100, Maciej Pijanka wrote:
Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 791) +++ chipset_enable.c (working copy) @@ -270,6 +270,8 @@ uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
+ buses_supported = CHIP_BUSTYPE_PARALLEL; + old = pci_read_word(dev, xbcs);
/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
ping? I hoped this is enough trivial to be applied without long review procedure.
Thanks, r793. I checked the PIIX* datasheets and didn't see any signs of LPC or FWH (definately no SPI) in there, as expected. Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
participants (2)
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Maciej Pijanka
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Uwe Hermann