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[commit] r665 - trunk
by svn＠flashrom.org 23 Jul '09

23 Jul '09

Author: hailfinger Date: 2009-07-23 14:42:01 +0200 (Thu, 23 Jul 2009) New Revision: 665 Modified: trunk/flashchips.c Log: Improve flashchip comments to be more readable and precise. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-07-23 01:44:38 UTC (rev 664) +++ trunk/flashchips.c 2009-07-23 12:42:01 UTC (rev 665) @@ -32,11 +32,20 @@ */ struct flashchip flashchips[] = { - /* Vendor, Chip, Vendor ID, Chip ID, - * Bus Type, - * Total size (kB), Page size (B), - * Test status, - * Probe function, Probe function timing, Erase function, Write function, Read function + /* + * .vendor = Vendor name + * .name = Chip name + * .bustype = Supported flash bus types (Parallel, LPC...) + * .manufacture_id = Manufacturer chip ID + * .model_id = Model chip ID + * .total_size = Total size in (binary) kbytes + * .page_size = Page or eraseblock(?) size in bytes + * .tested = Test status + * .probe = Probe function + * .probe_timing = Probe function delay + * .erase = Chip erase function + * .write = Chip write function + * .read = Chip read function */ {

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Re: [flashrom] flashrom UNTESTED for operations: ERASE WRITE
by Carl-Daniel Hailfinger 23 Jul '09

23 Jul '09

Hi Bryan, could you try latest flashrom from svn? The flashrom svn tree is now at a different location. More info at http://www.coreboot.org/Flashrom#Download_.26_Installation . You are hitting a corner-case bug and I'm not sure if it is still present. On 04.04.2009 04:46, Bryan C. Lesiuk wrote: > I ran flashrom -r on my D201GLY. Flashrom told me to send you the output. > I didn't trust flashrom to erase/write, so I can't tell if erase/write > would work. > Cheers -- Bryan > > bryan@wica:~/bios/coreboot-v3/util/flashrom$ sudo ./flashrom -r old.bios > Calibrating delay loop... OK. > No coreboot table found. > WARNING: No chipset found. Flash detection will most likely fail. The line above should find the chipset. > Found board "Intel Desktop Board D201GLY", enabling flash write... > W83627 not found at 0x2e, id=0xff want=0xa0. > OK. The line above should say "failed". > wbsio_spi_command: unsupported command type wr=1 rd=3 This should never happen. I think I understand the bug, but could you try to run "flashrom -V" and mail the output? This will only run the identification step, but in verbose mode. Thanks. Regards, Carl-Daniel -- http://www.hailfinger.org/

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flashrom status for GA-MA790X-UD4
by Yann Droneaud 23 Jul '09

23 Jul '09

Hi, Flashrom seems to not support Gigabyte GA-MA790X-UD4. I've only tested read operation, which failed, so I did try the write operation. Here are messages from flashrom: flashrom v0.9.0-r643 No coreboot table found. Found chipset "AMD SB700", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Found board "GIGABYTE GA-MA78GM-S2H", enabling flash write... FAILED! Calibrating delay loop... OK. Found chip "SST unknown SST SPI chip" (0 KB, SPI) at physical address 0x100000000. If you need details, you can downloads flashrom -V, dmidecode, lspci outputs at: https://mais.quest-ce.net/flashrom/ga-ma790x-ud4/ output_dmidecode.txt.gz output_flashrom_V.txt.gz output_flashrom_rV.txt.gz output_lspci.txt.gz output_lspci_vvvxxx.txt.gz Regards. -- Yann Droneaud <yann(a)droneaud.fr>

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chipset Intel ICH2-M eeprom read works
by David Thornton 23 Jul '09

23 Jul '09

Hi, I tested flashrom on a previously untested eeprom flash chip in my laptop; it said to tell you guys so here is the output! gotta love TheCrapTop TheCrapTop:/tmp# flashrom -r bios Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH2-M", enabling flash write... OK. Found chip "Intel 82802AC" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Reading Flash...done TheCrapTop:/tmp# du bios 1028 bios

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Re: [flashrom] report "SST SST25VF080B"
by Carl-Daniel Hailfinger 23 Jul '09

23 Jul '09

Hi Cédric, thanks for your report. The flash chip status has been updated. Unfortunately, it seems your BIOS readout is not 100% complete due to chipset restrictions. Please do not try to write. Laptops are very difficult to recover if something goes wrong. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] Fix erase for SST49LF020A
by Carl-Daniel Hailfinger 22 Jul '09

22 Jul '09

Fix erase for SST49LF020A. The chip supports multiple erase functions, but the function we use has an eraseblock size of 4k. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-sst49lf020a/flashchips.c =================================================================== --- flashrom-sst49lf020a/flashchips.c (Revision 659) +++ flashrom-sst49lf020a/flashchips.c (Arbeitskopie) @@ -2160,7 +2160,7 @@ .manufacture_id = SST_ID, .model_id = SST_49LF020A, .total_size = 256, - .page_size = 16 * 1024, + .page_size = 4 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ -- http://www.hailfinger.org/

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[commit] r664 - trunk
by svn＠flashrom.org 22 Jul '09

22 Jul '09

Author: hailfinger Date: 2009-07-23 03:44:38 +0200 (Thu, 23 Jul 2009) New Revision: 664 Modified: trunk/flashchips.c Log: Fix erase for SST49LF020A. The chip supports multiple erase functions, but the function we use has an eraseblock size of 4k. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-07-23 01:42:56 UTC (rev 663) +++ trunk/flashchips.c 2009-07-23 01:44:38 UTC (rev 664) @@ -2160,7 +2160,7 @@ .manufacture_id = SST_ID, .model_id = SST_49LF020A, .total_size = 256, - .page_size = 16 * 1024, + .page_size = 4 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */

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[PATCH] Continue verifying after first error
by Carl-Daniel Hailfinger 22 Jul '09

22 Jul '09

Continue erase/write verification after the first error. The first error is printed in detail and all subsequent errors are listed in statistics. This allows users to check if there was just one error or if the failure was widespread. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-verify_keep_going/flashrom.c =================================================================== --- flashrom-verify_keep_going/flashrom.c (Revision 659) +++ flashrom-verify_keep_going/flashrom.c (Arbeitskopie) @@ -278,6 +278,7 @@ int i, j, starthere, lenhere, ret = 0; int page_size = flash->page_size; uint8_t *readbuf = malloc(page_size); + int failcount = 0; if (!len) goto out_free; @@ -318,15 +319,21 @@ flash->read(flash, readbuf, starthere, lenhere); for (j = 0; j < lenhere; j++) { if (cmpbuf[starthere - start + j] != readbuf[j]) { - fprintf(stderr, "%s FAILED at 0x%08x! " - "Expected=0x%02x, Read=0x%02x\n", - message, starthere + j, - cmpbuf[starthere - start + j], readbuf[j]); - ret = -1; - goto out_free; + /* Only print the first failure. */ + if (!failcount++) + fprintf(stderr, "%s FAILED at 0x%08x! " + "Expected=0x%02x, Read=0x%02x,", + message, starthere + j, + cmpbuf[starthere - start + j], + readbuf[j]); } } } + if (failcount) { + fprintf(stderr, " failed byte count from 0x%08x-0x%08x: 0x%x\n", + start, start + len - 1, failcount); + ret = -1; + } out_free: free(readbuf); -- http://www.hailfinger.org/

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[commit] r663 - trunk
by svn＠flashrom.org 22 Jul '09

22 Jul '09

Author: hailfinger Date: 2009-07-23 03:42:56 +0200 (Thu, 23 Jul 2009) New Revision: 663 Modified: trunk/flashrom.c Log: Continue erase/write verification after the first error. The first error is printed in detail and all subsequent errors are listed in statistics. This allows users to check if there was just one error or if the failure was widespread. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-07-23 01:40:20 UTC (rev 662) +++ trunk/flashrom.c 2009-07-23 01:42:56 UTC (rev 663) @@ -278,6 +278,7 @@ int i, j, starthere, lenhere, ret = 0; int page_size = flash->page_size; uint8_t *readbuf = malloc(page_size); + int failcount = 0; if (!len) goto out_free; @@ -318,15 +319,21 @@ flash->read(flash, readbuf, starthere, lenhere); for (j = 0; j < lenhere; j++) { if (cmpbuf[starthere - start + j] != readbuf[j]) { - fprintf(stderr, "%s FAILED at 0x%08x! " - "Expected=0x%02x, Read=0x%02x\n", - message, starthere + j, - cmpbuf[starthere - start + j], readbuf[j]); - ret = -1; - goto out_free; + /* Only print the first failure. */ + if (!failcount++) + fprintf(stderr, "%s FAILED at 0x%08x! " + "Expected=0x%02x, Read=0x%02x,", + message, starthere + j, + cmpbuf[starthere - start + j], + readbuf[j]); } } } + if (failcount) { + fprintf(stderr, " failed byte count from 0x%08x-0x%08x: 0x%x\n", + start, start + len - 1, failcount); + ret = -1; + } out_free: free(readbuf);

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[PATCH] ST M25P RES support
by Carl-Daniel Hailfinger 22 Jul '09

22 Jul '09

Add support for old ST M25P05/M25P10 chips which only respond to the RES command and not the RDID command. Unfortunately, either the datasheets are wrong or both chips have exactly the same ID. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-sst25_res/flashchips.c =================================================================== --- flashrom-sst25_res/flashchips.c (Revision 659) +++ flashrom-sst25_res/flashchips.c (Arbeitskopie) @@ -2249,8 +2249,29 @@ .read = spi_chip_read, }, + /* The ST M25P05 is a bit of a problem. It has the same ID as the + * ST M25P05-A in RES mode, but supports only 128 byte writes instead + * of 256 byte writes. We rely heavily on the fact that probe_spi_res + * only is successful if RDID does not work. + */ { .vendor = "ST", + .name = "M25P05.RES", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P05_RES, + .total_size = 64, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_res, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_1, /* 128 */ + .read = spi_chip_read, + }, + + { + .vendor = "ST", .name = "M25P10-A", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = ST_ID, @@ -2265,8 +2286,25 @@ .read = spi_chip_read, }, + /* The ST M25P10 has the same problem as the M25P05. */ { .vendor = "ST", + .name = "M25P10.RES", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P10_RES, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_res, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_1, /* 128 */ + .read = spi_chip_read, + }, + + { + .vendor = "ST", .name = "M25P20", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = ST_ID, Index: flashrom-sst25_res/flashchips.h =================================================================== --- flashrom-sst25_res/flashchips.h (Revision 659) +++ flashrom-sst25_res/flashchips.h (Arbeitskopie) @@ -322,7 +322,9 @@ */ #define ST_ID 0x20 /* ST / SGS/Thomson */ #define ST_M25P05A 0x2010 +#define ST_M25P05_RES 0x10 /* Same code as M25P10. */ #define ST_M25P10A 0x2011 +#define ST_M25P10_RES 0x10 /* Same code as M25P05. */ #define ST_M25P20 0x2012 #define ST_M25P40 0x2013 #define ST_M25P40_RES 0x12 -- http://www.hailfinger.org/

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