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Am Sonntag, den 22.03.2009, 19:43 +0100 schrieb Paul Menzel:
> Am Montag, den 23.03.2009, 02:29 +0800 schrieb FENG Yu Ning:
> > 2009/3/23 Paul Menzel <paulepanter(a)users.sourceforge.net>:
>
> […]
>
> > > I tried flashrom with the different delays (10, 100, 1000, 10000, 40000
> > > all in us) afterwards, but the image did not differ.
> >
> > How about probing? does auto-detect work now?
>
> I am afraid it does not.
>
> $ cat /proc/mtrr
> reg00: base=0x00000000 ( 0MB), size= 512MB: write-back, count=1
> reg01: base=0xd0000000 (3328MB), size= 128MB: write-combining, count=1
> reg02: base=0xd0000000 (3328MB), size= 128MB: write-combining, count=1
> reg03: base=0xd8000000 (3456MB), size= 64MB: write-combining, count=1
> reg04: base=0xfffc0000 (4095MB), size= 256KB: uncachable, count=1
> $ $ sudo ./flashrom -V
> Calibrating delay loop... 490M loops per second, 100 myus = 141 us. OK.
[…]
Currently I am having access to this machine again, so I tried with
v0.9.2-r1033. Unfortunately I still cannot report success on
auto-detection.
Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0x25, id2 0xe4, id1 is normal flash content, id2 is normal flash content
[…]
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
Did something change in the flashrom infrastructure/source, that makes
adding support for this board easier than over a year ago?
I checked different probe timings (10, 100, 1000, 10000, 40000; all in
us) modifying `flashchips.c` and with and without modifying the MTRR
settings.
$ cat /proc/mtrr
reg00: base=0x000000000 ( 0MB), size= 512MB, count=1: write-back
reg01: base=0x0d0000000 ( 3328MB), size= 128MB, count=1: write-combining
reg02: base=0x0d0000000 ( 3328MB), size= 128MB, count=1: write-combining
reg03: base=0x0d8000000 ( 3456MB), size= 128MB, count=1: write-combining
$ sudo sh -c 'echo "base=0xfffc0000 size=0x40000 type=uncachable" >| /proc/mtrr'
$ more /proc/mtrr
reg00: base=0x000000000 ( 0MB), size= 512MB, count=1: write-back
reg01: base=0x0d0000000 ( 3328MB), size= 128MB, count=1: write-combining
reg02: base=0x0d0000000 ( 3328MB), size= 128MB, count=1: write-combining
reg03: base=0x0d8000000 ( 3456MB), size= 128MB, count=1: write-combining
reg04: base=0x0fffc0000 ( 4095MB), size= 256KB, count=1: uncachable
Probably unrelated but back then the output for `reg03` was different.
reg03: base=0xd8000000 (3456MB), size= 64MB: write-combining, count=1
I am probably forced to do a BIOS upgrade on this board. Is there a
chance I will be able to do this using flashrom?
Thanks,
Paul
Split AMD CS5536 chipset enable in a processor function (Geode RCONF)
and a southbridge function (CS5536 NOR flash control).
This patch has no functional changes.
Is it possible to combine a Geode LX with a CS5535 or even a CS5530?
Is it possible to combine a Geode GX (or earlier) with a CS5536?
If the answer to any of the questions above is "yes", the split probably
makes sense and we should execute the processor specific enable function
inside the new processor enable routine in flashrom.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-geodelx_cs5536_chipsetenable_split/chipset_enable.c
===================================================================
--- flashrom-geodelx_cs5536_chipsetenable_split/chipset_enable.c (Revision 1035)
+++ flashrom-geodelx_cs5536_chipsetenable_split/chipset_enable.c (Arbeitskopie)
@@ -728,16 +728,12 @@
/**
* Geode systems write protect the BIOS via RCONFs (cache settings similar
- * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
- *
- * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
- * To enable write to NOR Boot flash for the benefit of systems that have such
- * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
+ * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
+ * FIXME: Is this only for Geode LX or also for other Geode models?
*/
-static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
+static int enable_flash_geode(void)
{
#define MSR_RCONF_DEFAULT 0x1808
-#define MSR_NORF_CTL 0x51400018
msr_t msr;
@@ -751,6 +747,30 @@
wrmsr(MSR_RCONF_DEFAULT, msr);
}
+ cleanup_cpu_msr();
+
+#undef MSR_RCONF_DEFAULT
+ return 0;
+}
+
+/**
+ * CS5536 systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
+ * To enable write to NOR Boot flash for the benefit of systems that have such
+ * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
+ */
+static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
+{
+#define MSR_NORF_CTL 0x51400018
+
+ msr_t msr;
+
+ if (enable_flash_geode())
+ return -1;
+
+ /* Geode only has a single core */
+ if (setup_cpu_msr(0))
+ return -1;
+
msr = rdmsr(MSR_NORF_CTL);
/* Raise WE_CS3 bit. */
msr.lo |= 0x08;
@@ -758,7 +778,6 @@
cleanup_cpu_msr();
-#undef MSR_RCONF_DEFAULT
#undef MSR_NORF_CTL
return 0;
}
--
http://www.hailfinger.org/
With the attached patch it is no longer necessary to have an extra
dependency step.
--
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Tel.: +49 761 7668825 . Fax: +49 761 7664613
Email: info(a)coresystems.de . http://www.coresystems.de/
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On 30.05.2010 19:43, Michael Karcher wrote:
> Not ready for commit because of the pending list refactoring.
>
> Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de>
>
This was committed with some changes as part of r1025.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/