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[PATCH] Modernize SPI AAI code
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

Modernize SPI AAI code, blacklist IT87 SPI for AAI, allow AAI to run without warnings on ICH/VIA SPI. Add some code to make conversion to partial write possible for AAI. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_aai_modernize/spi25.c =================================================================== --- flashrom-spi_aai_modernize/spi25.c (Revision 1049) +++ flashrom-spi_aai_modernize/spi25.c (Arbeitskopie) @@ -1018,15 +1018,44 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf) { - uint32_t pos = 2, size = flash->total_size * 1024; - unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]}; + uint32_t addr = 0; + uint32_t len = flash->total_size * 1024; + uint32_t pos = addr; int result; + unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { + JEDEC_AAI_WORD_PROGRAM, + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_AAI_WORD_PROGRAM, + (pos >> 16) & 0xff, + (pos >> 8) & 0xff, + (pos & 0xff), + buf[0], + buf[1] + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; switch (spi_controller) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: - msg_cerr("%s: impossible with Winbond SPI masters," + msg_cerr("%s: impossible with this SPI controller," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif @@ -1034,24 +1063,46 @@ default: break; } + + /* The data sheet requires a start address with the low bit cleared. */ + if (addr % 2) { + msg_cerr("%s: start address not even! Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return SPI_GENERIC_ERROR; + } + /* The data sheet requires total AAI write length to be even. */ + if (len % 2) { + msg_cerr("%s: total write length not even! Please report a " + "bug at flashrom(a)flashrom.org\n", __func__); + return SPI_GENERIC_ERROR; + } + if (erase_flash(flash)) { msg_cerr("ERASE FAILED!\n"); return -1; } - /* FIXME: This will fail on ICH/VIA SPI. */ - result = spi_write_enable(); - if (result) + + result = spi_send_multicommand(cmds); + if (result) { + msg_cerr("%s failed during start command execution\n", + __func__); return result; - spi_send_command(6, 0, w, NULL); + } while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ - while (pos < size) { - w[1] = buf[pos++]; - w[2] = buf[pos++]; - spi_send_command(3, 0, w, NULL); + programmer_delay(10); + + /* We already wrote 2 bytes in the multicommand step. */ + pos += 2; + + while (pos < addr + len) { + cmd[1] = buf[pos++]; + cmd[2] = buf[pos++]; + spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(10); } + + /* Use WRDI to exit AAI mode. */ spi_write_disable(); return 0; } Index: flashrom-spi_aai_modernize/spi.h =================================================================== --- flashrom-spi_aai_modernize/spi.h (Revision 1049) +++ flashrom-spi_aai_modernize/spi.h (Arbeitskopie) @@ -112,6 +112,12 @@ #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 #define JEDEC_BYTE_PROGRAM_INSIZE 0x00 +/* Write AAI word (SST25VF080B) */ +#define JEDEC_AAI_WORD_PROGRAM 0xad +#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 -- http://www.hailfinger.org/

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[commit] r1052 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: hailfinger Date: Sun Jun 20 12:41:35 2010 New Revision: 1052 URL: http://flashrom.org/trac/coreboot/changeset/1052 Log: Modernize SPI AAI code, blacklist IT87 SPI for AAI, allow AAI to run without warnings on ICH/VIA SPI. Add some code to make conversion to partial write possible for AAI. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/spi.h trunk/spi25.c Modified: trunk/spi.h ============================================================================== --- trunk/spi.h Sun Jun 20 12:39:33 2010 (r1051) +++ trunk/spi.h Sun Jun 20 12:41:35 2010 (r1052) @@ -112,6 +112,12 @@ #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 #define JEDEC_BYTE_PROGRAM_INSIZE 0x00 +/* Write AAI word (SST25VF080B) */ +#define JEDEC_AAI_WORD_PROGRAM 0xad +#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sun Jun 20 12:39:33 2010 (r1051) +++ trunk/spi25.c Sun Jun 20 12:41:35 2010 (r1052) @@ -1012,15 +1012,44 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf) { - uint32_t pos = 2, size = flash->total_size * 1024; - unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]}; + uint32_t addr = 0; + uint32_t len = flash->total_size * 1024; + uint32_t pos = addr; int result; + unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { + JEDEC_AAI_WORD_PROGRAM, + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_AAI_WORD_PROGRAM, + (pos >> 16) & 0xff, + (pos >> 8) & 0xff, + (pos & 0xff), + buf[0], + buf[1] + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; switch (spi_controller) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: - msg_cerr("%s: impossible with Winbond SPI masters," + msg_cerr("%s: impossible with this SPI controller," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif @@ -1028,24 +1057,46 @@ default: break; } + + /* The data sheet requires a start address with the low bit cleared. */ + if (addr % 2) { + msg_cerr("%s: start address not even! Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return SPI_GENERIC_ERROR; + } + /* The data sheet requires total AAI write length to be even. */ + if (len % 2) { + msg_cerr("%s: total write length not even! Please report a " + "bug at flashrom(a)flashrom.org\n", __func__); + return SPI_GENERIC_ERROR; + } + if (erase_flash(flash)) { msg_cerr("ERASE FAILED!\n"); return -1; } - /* FIXME: This will fail on ICH/VIA SPI. */ - result = spi_write_enable(); - if (result) + + result = spi_send_multicommand(cmds); + if (result) { + msg_cerr("%s failed during start command execution\n", + __func__); return result; - spi_send_command(6, 0, w, NULL); + } while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ - while (pos < size) { - w[1] = buf[pos++]; - w[2] = buf[pos++]; - spi_send_command(3, 0, w, NULL); + programmer_delay(10); + + /* We already wrote 2 bytes in the multicommand step. */ + pos += 2; + + while (pos < addr + len) { + cmd[1] = buf[pos++]; + cmd[2] = buf[pos++]; + spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(10); } + + /* Use WRDI to exit AAI mode. */ spi_write_disable(); return 0; }

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[PATCH] SPI fixups
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

Fix message printing for SPI RES on spew level. Use a blacklist instead of a whitelist for 4-byte SPI RDID. Tell users where to report bugs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_fixups/spi25.c =================================================================== --- flashrom-spi_fixups/spi25.c (Revision 1049) +++ flashrom-spi_fixups/spi25.c (Arbeitskopie) @@ -72,6 +72,7 @@ unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; uint32_t readaddr; int ret; + int i; ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { @@ -84,7 +85,10 @@ } if (ret) return ret; - msg_cspew("RES returned %02x. ", readarr[0]); + msg_cspew("RES returned"); + for (i = 0; i < bytes; i++) + msg_cspew(" 0x%02x", readarr[i]); + msg_cspew(". "); return 0; } @@ -122,7 +126,9 @@ if (!oddparity(readarr[0])) msg_cdbg("RDID byte 0 parity violation. "); - /* Check if this is a continuation vendor ID */ + /* Check if this is a continuation vendor ID. + * FIXME: Handle continuation device IDs. + */ if (readarr[0] == 0x7f) { if (!oddparity(readarr[1])) msg_cdbg("RDID byte 1 parity violation. "); @@ -166,35 +172,23 @@ return probe_spi_rdid_generic(flash, 3); } -/* support 4 bytes flash ID */ int probe_spi_rdid4(struct flashchip *flash) { - /* only some SPI chipsets support 4 bytes commands */ + /* Some SPI controllers do not support commands with writecnt=1 and + * readcnt=4. + */ switch (spi_controller) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - case SPI_CONTROLLER_SB600: + case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: + msg_cinfo("4 byte RDID not supported on this SPI controller\n"); + return 0; + break; #endif #endif -#if CONFIG_FT2232_SPI == 1 - case SPI_CONTROLLER_FT2232: -#endif -#if CONFIG_DUMMY == 1 - case SPI_CONTROLLER_DUMMY: -#endif -#if CONFIG_BUSPIRATE_SPI == 1 - case SPI_CONTROLLER_BUSPIRATE: -#endif -#if CONFIG_DEDIPROG == 1 - case SPI_CONTROLLER_DEDIPROG: -#endif - return probe_spi_rdid_generic(flash, 4); default: - msg_cinfo("4b ID not supported on this SPI controller\n"); + return probe_spi_rdid_generic(flash, 4); } return 0; Index: flashrom-spi_fixups/spi.c =================================================================== --- flashrom-spi_fixups/spi.c (Revision 1049) +++ flashrom-spi_fixups/spi.c (Arbeitskopie) @@ -132,7 +132,8 @@ { if (!spi_programmer[spi_controller].command) { msg_perr("%s called, but SPI is unsupported on this " - "hardware. Please report a bug.\n", __func__); + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -144,7 +145,8 @@ { if (!spi_programmer[spi_controller].multicommand) { msg_perr("%s called, but SPI is unsupported on this " - "hardware. Please report a bug.\n", __func__); + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -183,8 +185,9 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].read) { - msg_perr("%s called, but SPI read is unsupported on this" - " hardware. Please report a bug.\n", __func__); + msg_perr("%s called, but SPI read is unsupported on this " + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -198,8 +201,9 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { if (!spi_programmer[spi_controller].write_256) { - msg_perr("%s called, but SPI page write is unsupported " - " on this hardware. Please report a bug.\n", __func__); + msg_perr("%s called, but SPI page write is unsupported on this " + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } -- http://www.hailfinger.org/

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[commit] r1051 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: hailfinger Date: Sun Jun 20 12:39:33 2010 New Revision: 1051 URL: http://flashrom.org/trac/coreboot/changeset/1051 Log: Fix message printing for SPI RES on spew level. Use a blacklist instead of a whitelist for 4-byte SPI RDID. Tell users where to report bugs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/spi.c trunk/spi25.c Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Sun Jun 20 00:06:35 2010 (r1050) +++ trunk/spi.c Sun Jun 20 12:39:33 2010 (r1051) @@ -132,7 +132,8 @@ { if (!spi_programmer[spi_controller].command) { msg_perr("%s called, but SPI is unsupported on this " - "hardware. Please report a bug.\n", __func__); + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -144,7 +145,8 @@ { if (!spi_programmer[spi_controller].multicommand) { msg_perr("%s called, but SPI is unsupported on this " - "hardware. Please report a bug.\n", __func__); + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -183,8 +185,9 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].read) { - msg_perr("%s called, but SPI read is unsupported on this" - " hardware. Please report a bug.\n", __func__); + msg_perr("%s called, but SPI read is unsupported on this " + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -198,8 +201,9 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { if (!spi_programmer[spi_controller].write_256) { - msg_perr("%s called, but SPI page write is unsupported " - " on this hardware. Please report a bug.\n", __func__); + msg_perr("%s called, but SPI page write is unsupported on this " + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sun Jun 20 00:06:35 2010 (r1050) +++ trunk/spi25.c Sun Jun 20 12:39:33 2010 (r1051) @@ -72,6 +72,7 @@ unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; uint32_t readaddr; int ret; + int i; ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { @@ -84,7 +85,10 @@ } if (ret) return ret; - msg_cspew("RES returned %02x. ", readarr[0]); + msg_cspew("RES returned"); + for (i = 0; i < bytes; i++) + msg_cspew(" 0x%02x", readarr[i]); + msg_cspew(". "); return 0; } @@ -122,7 +126,9 @@ if (!oddparity(readarr[0])) msg_cdbg("RDID byte 0 parity violation. "); - /* Check if this is a continuation vendor ID */ + /* Check if this is a continuation vendor ID. + * FIXME: Handle continuation device IDs. + */ if (readarr[0] == 0x7f) { if (!oddparity(readarr[1])) msg_cdbg("RDID byte 1 parity violation. "); @@ -166,35 +172,23 @@ return probe_spi_rdid_generic(flash, 3); } -/* support 4 bytes flash ID */ int probe_spi_rdid4(struct flashchip *flash) { - /* only some SPI chipsets support 4 bytes commands */ + /* Some SPI controllers do not support commands with writecnt=1 and + * readcnt=4. + */ switch (spi_controller) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - case SPI_CONTROLLER_SB600: + case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: + msg_cinfo("4 byte RDID not supported on this SPI controller\n"); + return 0; + break; #endif #endif -#if CONFIG_FT2232_SPI == 1 - case SPI_CONTROLLER_FT2232: -#endif -#if CONFIG_DUMMY == 1 - case SPI_CONTROLLER_DUMMY: -#endif -#if CONFIG_BUSPIRATE_SPI == 1 - case SPI_CONTROLLER_BUSPIRATE: -#endif -#if CONFIG_DEDIPROG == 1 - case SPI_CONTROLLER_DEDIPROG: -#endif - return probe_spi_rdid_generic(flash, 4); default: - msg_cinfo("4b ID not supported on this SPI controller\n"); + return probe_spi_rdid_generic(flash, 4); } return 0;

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[commit] r1050 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: mkarcher Date: Sun Jun 20 00:06:35 2010 New Revision: 1050 URL: http://flashrom.org/trac/coreboot/changeset/1050 Log: Add EMST F25L008A SPI chip Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Jun 17 02:01:56 2010 (r1049) +++ trunk/flashchips.c Sun Jun 20 00:06:35 2010 (r1050) @@ -1366,6 +1366,37 @@ }, { + .vendor = "EMST", + .name = "F25L008A", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EMST_ID, + .model_id = EMST_F25L008A, + .total_size = 1024, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .write = spi_aai_write, + .read = read_memmapped, + }, + + { .vendor = "Eon", .name = "EN25B05", .bustype = CHIP_BUSTYPE_SPI, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Thu Jun 17 02:01:56 2010 (r1049) +++ trunk/flashchips.h Sun Jun 20 00:06:35 2010 (r1050) @@ -151,6 +151,7 @@ #define CATALYST_ID 0x31 /* Catalyst */ #define EMST_ID 0x8C /* EMST / EFST Elite Flash Storage */ +#define EMST_F25L008A 0x2014 #define EMST_F49B002UA 0x00 /*

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Re: [flashrom] [PATCH] Add EMST E25L008A SPI chip
by Sean Nelson 20 Jun '10

20 Jun '10

On 6/12/10 10:49 AM, Michael Karcher wrote: > Sorry for the late replay, somehow I forgot to send the patch for your > board. > > Signed-off-by: Michael Karcher<flashrom(a)mkarcher.dialup.fu-berlin.de> > Acked-by: Sean Nelson <audiohacked(a)gmail.com>

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Abit IP35 board enable not working
by Gunter Keilholz 20 Jun '10

20 Jun '10

hi, although my board is supposed to be supported by flashrom i couldn't update my bios. i have attached several logfiles. motherboard: Abit IP35 latest BIOS download link: http://file.abit.com.tw/pub/download/bios/ip35//m630a18.zip gunter

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Re: [flashrom] Flash erasing failed mid way on Atmel AT25DF321 flash chip
by Carl-Daniel Hailfinger 19 Jun '10

19 Jun '10

Hi Ramakrishna, On 18.06.2010 17:28, Ramakrishna.Koduri(a)emerson.com wrote: > On June 18, 2010 5:27 AM, Carl-Daniel Hailfinger wrote: >> is this a production system you have to recover now, or can you reflash >> externally if something goes wrong? > > Yes. It is the production that I need to recover. This failure wiped > out the existing BIOS on the flash. > I am exploring to see any other option other than JTAG interface for > bringing back. > Do you have a SPI connector on the board? If yes, you can use flashrom to attach a Bus Pirate or a SPIPGM parallel port programmer or a FT2232H USB-serial controller to recover. > Flashrom worked many times for this. I don't know somehow this got > failed in this attempt. > > >> On 17.06.2010 16:26, Ramakrishna.Koduri(a)emerson.com wrote: >>> I have tried upgrading BIOS image using flashrom v0.9.2-r1001. >>> Surprisingly it failed in this attempt. >>> >>> I did many times upgrade of BIOS using flashrom utility of above said >>> version. >>> Earlier it was done by internal programmer with erase function-2. >>> >>> [root@localhost images]# flashrom -V -w atca-7360-cpu-v1.1.1.rom >>> flashrom v0.9.2-r1001 on Linux 2.6.18-194.el5xen (x86_64), built with The failing flashrom run happened on a Xen kernel. >>> libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48) >>> Initializing internal programmer >>> No coreboot table found. >>> DMI string system-manufacturer: "Emerson" >>> DMI string system-product-name: "PCA,ATCA-7360/R1.0/6E " >>> DMI string system-version: "R1.0 " >>> DMI string baseboard-manufacturer: "Emerson" >>> DMI string baseboard-product-name: "ATCA-7360/7365" >>> DMI string baseboard-version: "0106865F01A " >>> DMI string chassis-type: "" >>> Found chipset "Intel ICH10R", enabling flash write... >>> Maximum FWH chip size: 0x380000 bytes >>> BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is >>> 0x9 >>> Root Complex Register Block address = 0xfed1c000 GCS = 0x460: BIOS >>> Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 >>> (SPI) >>> Top Swap : not enabled >>> SPIBAR = 0xfed1c000 + 0x3800 >>> 0x04: 0x6008 (HSFS) >>> FLOCKDN 0, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 >>> 0x50: 0x00001b1b (FRAP) >>> BMWAG 0, BMRAG 0, BRWA 27, BRRA 27 >>> 0x54: 0x00010000 (FREG0) >>> 0x58: 0x03ff0080 (FREG1) >>> 0x5C: 0x00001fff (FREG2) >>> 0x60: 0x00030002 (FREG3) >>> 0x64: 0x007f0004 (FREG4) >>> 0x74: 0x00000000 (PR0) >>> 0x78: 0x00000000 (PR1) >>> 0x7C: 0x00000000 (PR2) >>> 0x80: 0x00000000 (PR3) >>> 0x84: 0x00000000 (PR4) >>> 0x90: 0x007f100c (SSFS, SSFC) >>> 0x94: 0x0006 (PREOP) >>> 0x96: 0x463b (OPTYPE) >>> 0x98: 0x05d80302 (OPMENU) >>> 0x9C: 0xc79f0190 (OPMENU+4) >>> 0xA0: 0x00000000 (BBAR) >>> 0xB0: 0x00004000 (FDOC) >>> Programming OPCODES... >>> program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done >>> SPI Read Configuration: prefetching enabled, caching enabled, OK. >>> This chipset supports the following protocols: FWH,SPI. >>> Calibrating delay loop... 1062M loops per second, 10 myus = 12 us, 100 >>> myus = 101 us, 1000 myus = 999 us, 10000 myus = 10005 us, OK. >>> Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 >>> 0x1f, >>> id2 0x4700 >>> Chip status register is 10 >>> Found chip "Atmel AT25DF321" (4096 KB, SPI) at physical address >>> 0xffc00000. >>> Flash image seems to be a legacy BIOS. Disabling checks. >>> Writing flash chip... Some block protection in effect, disabling >>> Erasing flash before programming... Erasing flash chip... Looking at >>> blockwise erase function 0... trying... 0x000000-0x000fff, >>> ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the >>> chipset opcode list. >>> Invalid OPCODE 0x20 >>> spi_block_erase_20 failed during command execution at address 0x0 >>> >>> Looking at blockwise erase function 1... trying... 0x000000-0x007fff, >>> ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the >>> chipset opcode list. >>> Invalid OPCODE 0x52 >>> spi_block_erase_52 failed during command execution at address 0x0 >>> >>> Looking at blockwise erase function 2... trying... 0x000000-0x00ffff, >>> 0x010000-0x01ffff, 0x020000-0x02ffff, 0x030000-0x03ffff, >>> 0x040000-0x04ffff, 0x050000-0x05ffff, 0x060000-0x06ffff, >>> 0x070000-0x07ffff, 0x080000-0x08ffff, 0x090000-0x09ffff, >>> 0x0a0000-0x0affff, ERASE FAILED at 0x000a0800! Expected=0xff, >>> Read=0x1f,Transaction error! >>> run OPCODE 0x03 failed >>> Transaction error! >>> [...] >>> run OPCODE 0x03 failed >>> Transaction error! >> Ah yes. This means your current BIOS version somehow blocks reading of >> some regions. You could try flashrom r1016 or later which has improved >> region protection handling. > > I am surprised to see why it should block some regions. > May be once the board is UP, I shall give a try using flashrom r1016 > version. > > >>> failed byte count from 0x000a0000-0x000affff: 0x1a ERASE FAILED! >>> >>> Looking at blockwise erase function 3... trying... 0x000000-0x3fffff, >>> Some block protection in effect, disabling >>> ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the >>> chipset opcode list. >>> Invalid OPCODE 0x60 >>> spi_chip_erase_60 failed during command execution >>> >>> Looking at blockwise erase function 4... trying... 0x000000-0x3fffff, >>> Some block protection in effect, disabling >> It would be interesting to check if reading the complete chip works. >> I think it probably won't work. Please report back with the verbose >> results of a pure read test. > > The current state of the system is not usable any more due to > boardreset immediately after the flashrom failed. > It didn't give me any chance to repair system back. > Oh, that is very unfortunate. The board should not have resetted. > I have the traces of previously successful write operation. Please > find the same here. > > [root@localhost flashrom-0.9.2]# ./flashrom -V -l layout -w > atca7360-bios.img -i part_2000_4000.log > What does "-i part_2000_4000.log" do? > flashrom v0.9.2-r1001 on Linux 2.6.18-194.el5PAE (i686), built with > libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48) > The working flashrom run happened on a PAE kernel. > flashrom is free software, get the source code at > http://www.flashrom.org > romlayout 00002000 - 00003fff named > /mnt/root/ramki/flashrom-0.9.2/part_2000_4000.log > Looking for "part_2000_4000.log"... not found. > It seems you told flashrom that part_2000_4000.log is the image name in the layout file. Is that intentional? > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Emerson" > DMI string system-product-name: "PCA,ATCA-7360/R1.0/6E > " > DMI string system-version: "R1.0 " > DMI string baseboard-manufacturer: "Emerson" > DMI string baseboard-product-name: "ATCA-7360/7365" > DMI string baseboard-version: "0106865F01A " > DMI string chassis-type: "" > Found chipset "Intel ICH10R", enabling flash write... > Maximum FWH chip size: 0x380000 bytes > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x9 > Root Complex Register Block address = 0xfed1c000 > GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 > (SPI) > Top Swap : not enabled > SPIBAR = 0xfed1c000 + 0x3800 > 0x04: 0x6008 (HSFS) > FLOCKDN 0, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 > 0x50: 0x00001b1b (FRAP) > BMWAG 0, BMRAG 0, BRWA 27, BRRA 27 > 0x54: 0x00010000 (FREG0) > 0x58: 0x03ff0080 (FREG1) > 0x5C: 0x00001fff (FREG2) > 0x60: 0x00030002 (FREG3) > 0x64: 0x007f0004 (FREG4) > 0x74: 0x00000000 (PR0) > 0x78: 0x00000000 (PR1) > 0x7C: 0x00000000 (PR2) > 0x80: 0x00000000 (PR3) > 0x84: 0x00000000 (PR4) > 0x90: 0x007f100c (SSFS, SSFC) > 0x94: 0x0006 (PREOP) > 0x96: 0x463b (OPTYPE) > 0x98: 0x05d80302 (OPMENU) > 0x9C: 0xc79f0190 (OPMENU+4) > 0xA0: 0x00000000 (BBAR) > 0xB0: 0x00004000 (FDOC) > Programming OPCODES... > program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 > done > SPI Read Configuration: prefetching enabled, caching enabled, OK. > This chipset supports the following protocols: FWH,SPI. > Calibrating delay loop... 1091M loops per second, 10 myus = 10 us, 100 > myus = 103 us, 1000 myus = 1029 us, 10000 myus = 10073 us, OK. > Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4700 > Chip status register is 10 > Found chip "Atmel AT25DF321" (4096 KB, SPI) at physical address > 0xffc00000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Some block protection in effect, disabling > Erasing flash before programming... Erasing flash chip... Looking at > blockwise erase function 0... trying... 0x000000-0x000fff, > ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the > chipset opcode list. > Invalid OPCODE 0x20 > spi_block_erase_20 failed during command execution at address 0x0 > > Looking at blockwise erase function 1... trying... 0x000000-0x007fff, > ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the > chipset opcode list. > Invalid OPCODE 0x52 > spi_block_erase_52 failed during command execution at address 0x0 > > Looking at blockwise erase function 2... trying... 0x000000-0x00ffff, > 0x010000-0x01ffff, 0x020000-0x02ffff, 0x030000-0x03ffff, > 0x040000-0x04ffff, 0x050000-0x05ffff, 0x060000-0x06ffff, > 0x070000-0x07ffff, 0x080000-0x08ffff, 0x090000-0x09ffff, > 0x0a0000-0x0affff, 0x0b0000-0x0bffff, 0x0c0000-0x0cffff, > 0x0d0000-0x0dffff, 0x0e0000-0x0effff, 0x0f0000-0x0fffff, > 0x100000-0x10ffff, 0x110000-0x11ffff, 0x120000-0x12ffff, > 0x130000-0x13ffff, 0x140000-0x14ffff, 0x150000-0x15ffff, > 0x160000-0x16ffff, 0x170000-0x17ffff, 0x180000-0x18ffff, > 0x190000-0x19ffff, 0x1a0000-0x1affff, 0x1b0000-0x1bffff, > 0x1c0000-0x1cffff, 0x1d0000-0x1dffff, 0x1e0000-0x1effff, > 0x1f0000-0x1fffff, 0x200000-0x20ffff, 0x210000-0x21ffff, > 0x220000-0x22ffff, 0x230000-0x23ffff, 0x240000-0x24ffff, > 0x250000-0x25ffff, 0x260000-0x26ffff, 0x270000-0x27ffff, > 0x280000-0x28ffff, 0x290000-0x29ffff, 0x2a0000-0x2affff, > 0x2b0000-0x2bffff, 0x2c0000-0x2cffff, 0x2d0000-0x2dffff, > 0x2e0000-0x2effff, 0x2f0000-0x2fffff, 0x300000-0x30ffff, > 0x310000-0x31ffff, 0x320000-0x32ffff, 0x330000-0x33ffff, > 0x340000-0x34ffff, 0x350000-0x35ffff, 0x360000-0x36ffff, > 0x370000-0x37ffff, 0x380000-0x38ffff, 0x390000-0x39ffff, > 0x3a0000-0x3affff, 0x3b0000-0x3bffff, 0x3c0000-0x3cffff, > 0x3d0000-0x3dffff, 0x3e0000-0x3effff, 0x3f0000-0x3fffff, > SUCCESS. > done. > Programming page: > > COMPLETE. > Verifying flash... VERIFIED. > I think that the crash was related to the Xen kernel. Regards, Carl-Daniel -- http://www.hailfinger.org/

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New BIOS chip
by Wolfgang Schnitker 19 Jun '10

19 Jun '10

Hi there, as requested, please find attached file for output of flashrom -V for my computer. Regards Wolfgang Schnitker

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Re: [flashrom] Flash erasing failed mid way on Atmel AT25DF321 flash chip
by Carl-Daniel Hailfinger 18 Jun '10

18 Jun '10

Hi Ramakrishna, is this a production system you have to recover now, or can you reflash externally if something goes wrong? On 17.06.2010 16:26, Ramakrishna.Koduri(a)emerson.com wrote: > I have tried upgrading BIOS image using flashrom v0.9.2-r1001. > Surprisingly it failed in this attempt. > > I did many times upgrade of BIOS using flashrom utility of above said > version. > Earlier it was done by internal programmer with erase function-2. > > [root@localhost images]# flashrom -V -w atca-7360-cpu-v1.1.1.rom > flashrom v0.9.2-r1001 on Linux 2.6.18-194.el5xen (x86_64), built with > libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48) > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Emerson" > DMI string system-product-name: "PCA,ATCA-7360/R1.0/6E > " > DMI string system-version: "R1.0 " > DMI string baseboard-manufacturer: "Emerson" > DMI string baseboard-product-name: "ATCA-7360/7365" > DMI string baseboard-version: "0106865F01A " > DMI string chassis-type: "" > Found chipset "Intel ICH10R", enabling flash write... > Maximum FWH chip size: 0x380000 bytes > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x9 > > Root Complex Register Block address = 0xfed1c000 > GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 > (SPI) > Top Swap : not enabled > SPIBAR = 0xfed1c000 + 0x3800 > 0x04: 0x6008 (HSFS) > FLOCKDN 0, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 > 0x50: 0x00001b1b (FRAP) > BMWAG 0, BMRAG 0, BRWA 27, BRRA 27 > 0x54: 0x00010000 (FREG0) > 0x58: 0x03ff0080 (FREG1) > 0x5C: 0x00001fff (FREG2) > 0x60: 0x00030002 (FREG3) > 0x64: 0x007f0004 (FREG4) > 0x74: 0x00000000 (PR0) > 0x78: 0x00000000 (PR1) > 0x7C: 0x00000000 (PR2) > 0x80: 0x00000000 (PR3) > 0x84: 0x00000000 (PR4) > 0x90: 0x007f100c (SSFS, SSFC) > 0x94: 0x0006 (PREOP) > 0x96: 0x463b (OPTYPE) > 0x98: 0x05d80302 (OPMENU) > 0x9C: 0xc79f0190 (OPMENU+4) > 0xA0: 0x00000000 (BBAR) > 0xB0: 0x00004000 (FDOC) > Programming OPCODES... > program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 > done > SPI Read Configuration: prefetching enabled, caching enabled, OK. > This chipset supports the following protocols: FWH,SPI. > Calibrating delay loop... 1062M loops per second, 10 myus = 12 us, 100 > myus = 101 us, 1000 myus = 999 us, 10000 myus = 10005 us, OK. > Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4700 > Chip status register is 10 > Found chip "Atmel AT25DF321" (4096 KB, SPI) at physical address > 0xffc00000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Some block protection in effect, disabling > Erasing flash before programming... Erasing flash chip... Looking at > blockwise erase function 0... trying... 0x000000-0x000fff, > ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the > chipset opcode list. > Invalid OPCODE 0x20 > spi_block_erase_20 failed during command execution at address 0x0 > > Looking at blockwise erase function 1... trying... 0x000000-0x007fff, > ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the > chipset opcode list. > Invalid OPCODE 0x52 > spi_block_erase_52 failed during command execution at address 0x0 > > Looking at blockwise erase function 2... trying... 0x000000-0x00ffff, > 0x010000-0x01ffff, 0x020000-0x02ffff, 0x030000-0x03ffff, > 0x040000-0x04ffff, 0x050000-0x05ffff, 0x060000-0x06ffff, > 0x070000-0x07ffff, 0x080000-0x08ffff, 0x090000-0x09ffff, > 0x0a0000-0x0affff, ERASE FAILED at 0x000a0800! Expected=0xff, > Read=0x1f,Transaction error! > run OPCODE 0x03 failed > Transaction error! > [...] > run OPCODE 0x03 failed > Transaction error! > Ah yes. This means your current BIOS version somehow blocks reading of some regions. You could try flashrom r1016 or later which has improved region protection handling. > failed byte count from 0x000a0000-0x000affff: 0x1a > ERASE FAILED! > > Looking at blockwise erase function 3... trying... 0x000000-0x3fffff, > Some block protection in effect, disabling > ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the > chipset opcode list. > Invalid OPCODE 0x60 > spi_chip_erase_60 failed during command execution > > Looking at blockwise erase function 4... trying... 0x000000-0x3fffff, > Some block protection in effect, disabling > It would be interesting to check if reading the complete chip works. I think it probably won't work. Please report back with the verbose results of a pure read test. Regards, Carl-Daniel -- http://www.hailfinger.org/

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