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VIA VT6421A LPC programmer
by XVilka Haos of System 16 May '11

16 May '11

This board contain Winbond W39V040BPZ chip http://paste.flashrom.org/view.php?id=569 Best regards, XVilka.

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XW9400 upgrade
by Nigel R 16 May '11

16 May '11

Sorry if this has been gone through before but... I've been put off by the various problems I've read about updating the BIOS on my XW9400 motherboard to support quad core processors. There seem to be various problems ( mac addresses going awol ) and things that need to be done ( connecting jumpers etc. ) which have made me think it isn't worth it. But - I've decided I want to give it a go... My understanding is that I need to short out a jumper on the board - I think I know which points I have to bridge - but does anyone have a picture - just to make me feel sure I'm not going to blow the entire board up :-/ I have the latest version of flashrom - the process I think I need to go through is ... I've used sudo flashrom -r biosbackup.rom -m hp:xw9400 to copy the current image. I'm assuming I have to use sudo flashrom -m hp:xw9400 -w 7D6_0403.bin to flash it with the 4.03 image off the HP web site. I'm assuming that with the write enable, this will update the boot block - but will this also remove the MAC addresses - or is that some other problem people have had? Thanks for any help. Nigel

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My USB+AVR-based flasher (w/ serprog protocol fw) gets spi support and a little webpage
by Urja Rannikko 15 May '11

15 May '11

Hi, I didnt want to mix this randomness into my patch mail, so I'm sending two. I set up a simple web page for serving all the files related to this little project of mine: http://urjaman.dyndns.info/usbavrprog/ . You might be able to see that there is a reason for why I dont normally do web design stuff ;), but it gets this stuff out. (FYI: This webserver is going to be down starting 2011/05/21, hopefully ending before end of 2011/06.) Also, I've written code for it and for flashrom to support SPI protocol over serprog, so I will be sending a patch to flashrom next. -- Urja Rannikko aka urjaman

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jidacmos
by Taylor Thomson Wisbeck 13 May '11

13 May '11

Hi, Someone can send me the executable "jidacmos.exe". Thanks Taylor

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fail update bios
by Abashev Danila 12 May '11

12 May '11

Hello! I have EPoX EP-8RDAEI. I I can not update bios. Details in the attached files. Restored the bios from a previously created backup. The system reboots normally.

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Re: [flashrom] Erase faild
by Stefan Reinauer 12 May '11

12 May '11

* Marco Runge <Marco_Runge(a)raykiel.com> [110512 14:46]: > I am a Software Engineer from Raytheon Ansch tz Germany and wanted to use > flashrom to update the bios of our embedded bord form emerson. Unfortuneately > s.th. must have gone wrong. First write of the bios was fine but after reboot I > got a crisis report that the two flash banks are corrupt. I could boot from > thumb drive anyway and wanted to write the backup copy but got the following > error message: > > Erase failed at 0x00000010! Expected=0xff, Read=0x5a, failed byte count from > 0x00000000 - 0x0000ffff: 0xd092. > > We are using the following board: http://www.emersonnetworkpower.com/en-US/ > Products/EmbeddedComputing/CompactPCI/Pages/EmbCompCPCI7203.aspx > > Chipset: Intel Ibex Peak > Found chipset: Atmel AT25DF641 8192Kb SPI at 0xff800000 > > I hope you can help Please post the full log (possibly with --verbose) Also, does the image in flash match what you previously read from the chip? In that case it's most likely that the flash is write protected Stefan

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Erase faild
by Marco Runge 12 May '11

12 May '11

Hi, I am a Software Engineer from Raytheon Anschütz Germany and wanted to use flashrom to update the bios of our embedded bord form emerson. Unfortuneately s.th. must have gone wrong. First write of the bios was fine but after reboot I got a crisis report that the two flash banks are corrupt. I could boot from thumb drive anyway and wanted to write the backup copy but got the following error message: Erase failed at 0x00000010! Expected=0xff, Read=0x5a, failed byte count from 0x00000000 - 0x0000ffff: 0xd092. We are using the following board: http://www.emersonnetworkpower.com/en-US/Products/EmbeddedComputing/Compact… Chipset: Intel Ibex Peak Found chipset: Atmel AT25DF641 8192Kb SPI at 0xff800000 I hope you can help Best regards Marco Runge Marco Runge Software Engineer EDA BAD Raytheon Anschuetz GmbH +49 431 3019 646 office +49 431 3019 291 fax Marco_Runge(a)raykiel.com Zeyestrasse 16 - 24 D-24106 Kiel Germany www.raytheon-anschuetz.com Raytheon Anschuetz GmbH Sitz der Gesellschaft: Kiel Registergericht: Amtsgericht Kiel HRB 4086 Geschaeftsfuehrer: Dr. Lueder Hogrefe Vorsitzender des Aufsichtsrats: Patrick K. Peppe Diese Nachricht enthaelt vertrauliche oder rechtlich geschuetzte Informationen. Wenn Sie nicht der beabsichtigte Empfaenger sind, informieren Sie bitte sofort den Absender und loeschen Sie diese Nachricht. Das unbefugte Kopieren dieser Nachricht oder die unbefugte Weitergabe der enthaltenen Informationen ist nicht gestattet. The information contained in this message is confidential or protected by law. If you are not the intended recipient, please contact the sender and delete this message. Any unauthorized copying of this message or unauthorized distribution of the information contained herein is prohibited.

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Re: [flashrom] [PATCH 1/3] Factor out SPI write/read chunking wrappers.
by Carl-Daniel Hailfinger 11 May '11

11 May '11

Hi Michael, thanks for your patch! Am 05.05.2011 03:04 schrieb Michael Karcher: > diff --git a/dummyflasher.c b/dummyflasher.c > index d818a84..b6e67db 100644 > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -507,12 +507,6 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > -{ > - /* Maximum read length is unlimited, use 64kB. */ > - return spi_read_chunked(flash, buf, start, len, 64 * 1024); > -} > - > int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, > Any reason you didn't kill dummy_write_256()? If you kill it, please remove it from programmer.h and adjust SPI_CONTROLLER_DUMMY in spi.c accordingly. Thanks. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 3/3] kill central list of SPI programmers
by Carl-Daniel Hailfinger 11 May '11

11 May '11

Am 05.05.2011 03:04 schrieb Michael Karcher: > Remove the array spi_programmer, replace it by dynamic registration > instead. Also initially start with no busses supported, and switch to > the default non-SPI only for the internal programmer. > > Signed-off-by: Michael Karcher<flashrom(a)mkarcher.dialup.fu-berlin.de> > Thanks for your patch! I have a few minor nitpicks and design questions, but the code changes seem to be bug-free, so you get an Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Your patch is very readable and got me thinking about future directions of that code, especially multiple registrations... so take the review with a grain of salt. > diff --git a/dummyflasher.c b/dummyflasher.c > index c4c9c4e..fdaa5f2 100644 > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -339,7 +339,7 @@ static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt > } > #endif > > -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -375,12 +375,22 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, > spi_write_256_chunksize); > } > > +static const struct spi_programmer spi_programmer_dummyflasher = { > + .type = SPI_CONTROLLER_DUMMY, > + .max_data_read = MAX_DATA_READ_UNLIMITED, > + .max_data_write = MAX_DATA_UNSPECIFIED, > 256 instead? > + .command = dummy_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = default_spi_read, > + .write_256 = dummy_spi_write_256, > Same comment as for patch 1 of the series. AFAICS dummy_spi_write_256 should be replaced by the default one. > +}; > + > int dummy_init(void) > { > char *bustext = NULL; > Please fix the whitespace (spaces instead of tabs) in it87spi.c and dummyflasher.c. Apparently a newline is missing at the end of spi.c. > diff --git a/bitbang_spi.c b/bitbang_spi.c > index be30944..ca28434 100644 > --- a/bitbang_spi.c > +++ b/bitbang_spi.c > @@ -81,7 +81,7 @@ static uint8_t bitbang_spi_readwrite_byte(uint8_t val) > return ret; > } > > -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -106,6 +106,16 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > +static const struct spi_programmer spi_programmer_bitbang = { > Can you make this one non-const to allow changing .type? > + .type = SPI_CONTROLLER_BITBANG, > And leave type empty, to be filled by bitbang_spi_init()? > + .max_data_read = MAX_DATA_READ_UNLIMITED, > + .max_data_write = MAX_DATA_WRITE_UNLIMITED, > + .command = bitbang_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = default_spi_read, > + .write_256 = default_spi_write_256, > +}; > + > int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) > Could you extend this function signature to have an additional enum spi_controller parameter? If each bitbang-using programmer calls bitbang_spi_init(spi_controller, master, halfperiod) we can keep the spi_controller enums unchanged for now which would help us keep things consistent (for example, ichspi.c uses 3 different spi_controller enums for the same functions). > { > /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, > Insert in this function: spi_programmer_bitbang.type=spi_controller; > diff --git a/programmer.h b/programmer.h > index fefb9cd..53a50f6 100644 > --- a/programmer.h > +++ b/programmer.h > @@ -527,7 +518,6 @@ enum spi_controller { > SPI_CONTROLLER_SB600, > SPI_CONTROLLER_VIA, > SPI_CONTROLLER_WBSIO, > - SPI_CONTROLLER_MCP6X_BITBANG, > #endif > #endif > #if CONFIG_FT2232_SPI == 1 > @@ -542,16 +532,9 @@ enum spi_controller { > #if CONFIG_DEDIPROG == 1 > SPI_CONTROLLER_DEDIPROG, > #endif > -#if CONFIG_RAYER_SPI == 1 > - SPI_CONTROLLER_RAYER, > -#endif > -#if CONFIG_NICINTEL_SPI == 1 > - SPI_CONTROLLER_NICINTEL, > -#endif > -#if CONFIG_OGP_SPI == 1 > - SPI_CONTROLLER_OGP, > +#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || (CONFIG_INTERNAL == 1&& (defined(__i386__) || defined(__x86_64__))) > + SPI_CONTROLLER_BITBANG, > #endif > - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ > }; > extern const int spi_programmer_count; > If you use enum spi_controller as parameter for bitbang_spi_init(), we don't need an extra SPI_CONTROLLER_BITBANG and can keep the programmer-specific ones. The calls to bitbang_spi_init() in mcp6x_spi.c, nicintel_spi.c, ogp_spi.c and rayer_spi.c would need to be adjusted as well. I plan to add a union private_data{} to struct spi_programmer to allow storing stuff like struct bitbang_spi_master, avoiding the need for programmer-internal static configuration variables. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1299 - trunk
by repository service 11 May '11

11 May '11

Author: mkarcher Date: Wed May 11 19:07:07 2011 New Revision: 1299 URL: http://flashrom.org/trac/flashrom/changeset/1299 Log: kill central list of SPI programmers Remove the array spi_programmer, replace it by dynamic registration instead. Also initially start with no busses supported, and switch to the default non-SPI only for the internal programmer. Also this patch changes the initialization for the buses_supported variable from "everything-except-SPI" to "nothing". All programmers have to set the bus type on their own, and this enables register_spi_programmer to just add the SPI both for on-board SPI interfaces (where the internal programmer already detected the other bus types), as well as for external programmers (where we have the default "none"). Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/bitbang_spi.c trunk/buspirate_spi.c trunk/dediprog.c trunk/dummyflasher.c trunk/flashrom.c trunk/ft2232_spi.c trunk/ichspi.c trunk/internal.c trunk/it85spi.c trunk/it87spi.c trunk/mcp6x_spi.c trunk/nicintel_spi.c trunk/ogp_spi.c trunk/programmer.h trunk/rayer_spi.c trunk/sb600spi.c trunk/spi.c trunk/spi25.c trunk/wbsio_spi.c Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/bitbang_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -64,6 +64,19 @@ bitbang_spi_master->release_bus(); } +static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + +static const struct spi_programmer spi_programmer_bitbang = { + .type = SPI_CONTROLLER_BITBANG, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, @@ -85,6 +98,8 @@ bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; + register_spi_programmer(&spi_programmer_bitbang); + /* FIXME: Run bitbang_spi_request_bus here or in programmer init? */ bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); @@ -127,7 +142,7 @@ return ret; } -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/buspirate_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -81,6 +81,19 @@ return 0; } +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + +static const struct spi_programmer spi_programmer_buspirate = { + .type = SPI_CONTROLLER_BUSPIRATE, + .max_data_read = 12, + .max_data_write = 12, + .command = buspirate_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + static const struct buspirate_spispeeds spispeeds[] = { {"30k", 0x0}, {"125k", 0x1}, @@ -230,8 +243,7 @@ return 1; } - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_BUSPIRATE; + register_spi_programmer(&spi_programmer_buspirate); return 0; } @@ -271,7 +283,7 @@ return 0; } -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { static unsigned char *buf = NULL; Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/dediprog.c Wed May 11 19:07:07 2011 (r1299) @@ -248,7 +248,7 @@ return 0; } -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int ret; /* chunksize must be 512, other sizes will NOT work at all. */ @@ -293,7 +293,7 @@ return 0; } -int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { int ret; @@ -310,7 +310,7 @@ return ret; } -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int ret; @@ -526,6 +526,16 @@ return millivolt; } +static const struct spi_programmer spi_programmer_dediprog = { + .type = SPI_CONTROLLER_DEDIPROG, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = dediprog_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = dediprog_spi_read, + .write_256 = dediprog_spi_write_256, +}; + /* URB numbers refer to the first log ever captured. */ int dediprog_init(void) { @@ -606,8 +616,7 @@ return 1; } - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DEDIPROG; + register_spi_programmer(&spi_programmer_dediprog); /* RE leftover, leave in until the driver is complete. */ #if 0 Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/dummyflasher.c Wed May 11 19:07:07 2011 (r1299) @@ -60,6 +60,19 @@ static int spi_write_256_chunksize = 256; +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + +static const struct spi_programmer spi_programmer_dummyflasher = { + .type = SPI_CONTROLLER_DUMMY, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = dummy_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = dummy_spi_write_256, +}; int dummy_init(void) { char *bustext = NULL; @@ -91,8 +104,7 @@ msg_pdbg("Enabling support for %s flash.\n", "FWH"); } if (strstr(bustext, "spi")) { - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DUMMY; + register_spi_programmer(&spi_programmer_dummyflasher); msg_pdbg("Enabling support for %s flash.\n", "SPI"); } if (buses_supported == CHIP_BUSTYPE_NONE) @@ -471,7 +483,7 @@ } #endif -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -507,7 +519,7 @@ return 0; } -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, spi_write_256_chunksize); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/flashrom.c Wed May 11 19:07:07 2011 (r1299) @@ -521,10 +521,7 @@ .fwh = 0xffffffff, .spi = 0xffffffff }; - /* Default to Parallel/LPC/FWH flash devices. If a known host controller - * is found, the init routine sets the buses_supported bitfield. - */ - buses_supported = CHIP_BUSTYPE_NONSPI; + buses_supported = CHIP_BUSTYPE_NONE; /* Default to top aligned flash at 4 GB. */ flashbase = 0; /* Registering shutdown functions is now allowed. */ @@ -1712,10 +1709,6 @@ msg_gerr("Programmer table miscompilation!\n"); ret = 1; } - if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { - msg_gerr("SPI programmer table miscompilation!\n"); - ret = 1; - } for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1; Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/ft2232_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -128,6 +128,19 @@ return 0; } +static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + +static const struct spi_programmer spi_programmer_ft2232 = { + .type = SPI_CONTROLLER_FT2232, + .max_data_read = 64 * 1024, + .max_data_write = 256, + .command = ft2232_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int ft2232_spi_init(void) { int f; @@ -261,13 +274,12 @@ // msg_pdbg("\nft2232 chosen\n"); - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_FT2232; + register_spi_programmer(&spi_programmer_ft2232); return 0; } -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct ftdi_context *ftdic = &ftdic_context; Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/ichspi.c Wed May 11 19:07:07 2011 (r1299) @@ -313,7 +313,7 @@ return -1; } - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: preop = REGREAD16(ICH7_REG_PREOP); @@ -388,7 +388,7 @@ } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: /* Register undo only for enable_undo=1, i.e. first call. */ @@ -432,7 +432,7 @@ { #define BBAR_MASK 0x00ffff00 minaddr &= BBAR_MASK; - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; @@ -801,7 +801,7 @@ static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: if (datalength > 16) { msg_perr("%s: Internal command size error for " @@ -834,7 +834,7 @@ return -1; } -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int result; @@ -900,7 +900,7 @@ opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_ICH9: @@ -953,7 +953,7 @@ return result; } -int ich_spi_send_multicommand(struct spi_command *cmds) +static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; int i; @@ -1051,6 +1051,26 @@ access_names[rwperms]); } +static const struct spi_programmer spi_programmer_ich7 = { + .type = SPI_CONTROLLER_ICH7, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + +static const struct spi_programmer spi_programmer_ich9 = { + .type = SPI_CONTROLLER_ICH9, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1059,20 +1079,19 @@ uint16_t spibar_offset, tmp2; uint32_t tmp; - buses_supported |= CHIP_BUSTYPE_SPI; switch (ich_generation) { case 7: - spi_controller = SPI_CONTROLLER_ICH7; + register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - spi_controller = SPI_CONTROLLER_ICH9; + register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - spi_controller = SPI_CONTROLLER_ICH9; + register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1083,7 +1102,7 @@ /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); @@ -1211,6 +1230,16 @@ return 0; } +static const struct spi_programmer spi_programmer_via = { + .type = SPI_CONTROLLER_VIA, + .max_data_read = 16, + .max_data_write = 16, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int via_init_spi(struct pci_dev *dev) { uint32_t mmio_base; @@ -1221,8 +1250,8 @@ ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); /* Not sure if it speaks all these bus protocols. */ - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_VIA; + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + register_spi_programmer(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/internal.c Wed May 11 19:07:07 2011 (r1299) @@ -179,6 +179,11 @@ get_io_perms(); + /* Default to Parallel/LPC/FWH flash devices. If a known host controller + * is found, the init routine sets the buses_supported bitfield. + */ + buses_supported = CHIP_BUSTYPE_NONSPI; + /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ /* Set all options you want -- here we stick with the defaults */ Modified: trunk/it85spi.c ============================================================================== --- trunk/it85spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/it85spi.c Wed May 11 19:07:07 2011 (r1299) @@ -262,12 +262,22 @@ ce_low = (unsigned char*)(base + 0xD00); /* 0xFFFFFD00 */ #endif - /* Set this as spi controller. */ - spi_controller = SPI_CONTROLLER_IT85XX; - return 0; } +static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + +static const struct spi_programmer spi_programmer_it85xx = { + .type = SPI_CONTROLLER_IT85XX, + .max_data_read = 64, + .max_data_write = 64, + .command = it85xx_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int it85xx_spi_init(struct superio s) { int ret; @@ -284,7 +294,8 @@ if (buses_supported & CHIP_BUSTYPE_FWH) msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); /* Really leave FWH enabled? */ - buses_supported |= CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + /* Set this as spi controller. */ + register_spi_programmer(&spi_programmer_it85xx); } return ret; } @@ -303,7 +314,7 @@ * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get * data from MISO) */ -int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/it87spi.c Wed May 11 19:07:07 2011 (r1299) @@ -104,6 +104,21 @@ return; } +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + +static const struct spi_programmer spi_programmer_it87xx = { + .type = SPI_CONTROLLER_IT87XX, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = it8716f_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = it8716f_spi_chip_read, + .write_256 = it8716f_spi_chip_write_256, +}; + static uint16_t it87spi_probe(uint16_t port) { uint8_t tmp = 0; @@ -180,9 +195,8 @@ it8716f_flashport = flashport; if (buses_supported & CHIP_BUSTYPE_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); - spi_controller = SPI_CONTROLLER_IT87XX; /* FIXME: Add the SPI bus or replace the other buses with it? */ - buses_supported |= CHIP_BUSTYPE_SPI; + register_spi_programmer(&spi_programmer_it87xx); return 0; } @@ -234,7 +248,7 @@ * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; @@ -327,7 +341,7 @@ * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Need to read this big flash using firmware cycles 3 byte at a time. */ -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { fast_spi = 0; @@ -344,7 +358,7 @@ return 0; } -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { /* * IT8716F only allows maximum of 512 kb SPI chip size for memory Modified: trunk/mcp6x_spi.c ============================================================================== --- trunk/mcp6x_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/mcp6x_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -166,9 +166,6 @@ return 1; } - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_MCP6X_BITBANG; - return 0; } Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/nicintel_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -162,9 +162,6 @@ if (bitbang_spi_init(&bitbang_spi_master_nicintel, 1)) return 1; - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_NICINTEL; - return 0; } Modified: trunk/ogp_spi.c ============================================================================== --- trunk/ogp_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/ogp_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -128,9 +128,6 @@ if (bitbang_spi_init(&bitbang_spi_master_ogp, 0)) return 1; - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_OGP; - return 0; } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed May 11 19:07:02 2011 (r1298) +++ trunk/programmer.h Wed May 11 19:07:07 2011 (r1299) @@ -372,9 +372,6 @@ uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ @@ -485,7 +482,6 @@ const char *device_name; }; int ft2232_spi_init(void); -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); extern const struct usbdev_status devs_ft2232spi[]; void print_supported_usbdevs(const struct usbdev_status *devs); #endif @@ -505,7 +501,6 @@ /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_shutdown(const struct bitbang_spi_master *master); -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* buspirate_spi.c */ struct buspirate_spispeeds { @@ -514,14 +509,10 @@ }; int buspirate_spi_init(void); int buspirate_spi_shutdown(void); -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* dediprog.c */ int dediprog_init(void); int dediprog_shutdown(void); -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* flashrom.c */ struct decode_sizes { @@ -552,7 +543,6 @@ SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, - SPI_CONTROLLER_MCP6X_BITBANG, #endif #endif #if CONFIG_FT2232_SPI == 1 @@ -567,16 +557,9 @@ #if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, #endif -#if CONFIG_RAYER_SPI == 1 - SPI_CONTROLLER_RAYER, -#endif -#if CONFIG_NICINTEL_SPI == 1 - SPI_CONTROLLER_NICINTEL, -#endif -#if CONFIG_OGP_SPI == 1 - SPI_CONTROLLER_OGP, +#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__))) + SPI_CONTROLLER_BITBANG, #endif - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; @@ -584,6 +567,7 @@ #define MAX_DATA_READ_UNLIMITED 64 * 1024 #define MAX_DATA_WRITE_UNLIMITED 256 struct spi_programmer { + enum spi_controller type; int max_data_read; int max_data_write; int (*command)(unsigned int writecnt, unsigned int readcnt, @@ -595,13 +579,13 @@ int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); }; -extern enum spi_controller spi_controller; -extern const struct spi_programmer spi_programmer[]; +extern const struct spi_programmer *spi_programmer; int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +void register_spi_programmer(const struct spi_programmer *programmer); /* ichspi.c */ #if CONFIG_INTERNAL == 1 @@ -609,40 +593,26 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation); int via_init_spi(struct pci_dev *dev); -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int ich_spi_send_multicommand(struct spi_command *cmds); #endif /* it85spi.c */ int it85xx_spi_init(struct superio s); int it85xx_shutdown(void); -int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); void probe_superio_ite(void); int init_superio_ite(void); -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ #if CONFIG_INTERNAL == 1 int sb600_probe_spi(struct pci_dev *dev); -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); #endif /* wbsio_spi.c */ #if CONFIG_INTERNAL == 1 int wbsio_check_for_spi(void); -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* serprog.c */ Modified: trunk/rayer_spi.c ============================================================================== --- trunk/rayer_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/rayer_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -134,9 +134,6 @@ if (bitbang_spi_init(&bitbang_spi_master_rayer, 0)) return 1; - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_RAYER; - return 0; } Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/sb600spi.c Wed May 11 19:07:07 2011 (r1299) @@ -89,7 +89,7 @@ ; } -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; @@ -192,6 +192,16 @@ return 0; } +static const struct spi_programmer spi_programmer_sb600 = { + .type = SPI_CONTROLLER_SB600, + .max_data_read = 8, + .max_data_write = 5, + .command = sb600_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int sb600_probe_spi(struct pci_dev *dev) { struct pci_dev *smbus_dev; @@ -304,8 +314,7 @@ /* Bring the FIFO to a clean state. */ reset_internal_fifo_pointer(); - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_SB600; + register_spi_programmer(&spi_programmer_sb600); return 0; } Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/spi.c Wed May 11 19:07:07 2011 (r1299) @@ -30,200 +30,42 @@ #include "programmer.h" #include "spi.h" -enum spi_controller spi_controller = SPI_CONTROLLER_NONE; - -const struct spi_programmer spi_programmer[] = { - { /* SPI_CONTROLLER_NONE */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = NULL, - .multicommand = NULL, - .read = NULL, - .write_256 = NULL, - }, - -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - { /* SPI_CONTROLLER_ICH7 */ - .max_data_read = 64, - .max_data_write = 64, - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_ICH9 */ - .max_data_read = 64, - .max_data_write = 64, - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_IT85XX */ - .max_data_read = 64, - .max_data_write = 64, - .command = it85xx_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_IT87XX */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = it8716f_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = it8716f_spi_chip_read, - .write_256 = it8716f_spi_chip_write_256, - }, - - { /* SPI_CONTROLLER_SB600 */ - .max_data_read = 8, - .max_data_write = 5, - .command = sb600_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_VIA */ - .max_data_read = 16, - .max_data_write = 16, - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_WBSIO */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = wbsio_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = wbsio_spi_read, - .write_256 = spi_chip_write_1, - }, - - { /* SPI_CONTROLLER_MCP6X_BITBANG */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif -#endif - -#if CONFIG_FT2232_SPI == 1 - { /* SPI_CONTROLLER_FT2232 */ - .max_data_read = 64 * 1024, - .max_data_write = 256, - .command = ft2232_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_DUMMY == 1 - { /* SPI_CONTROLLER_DUMMY */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = dummy_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = dummy_spi_write_256, - }, -#endif - -#if CONFIG_BUSPIRATE_SPI == 1 - { /* SPI_CONTROLLER_BUSPIRATE */ - .max_data_read = 12, - .max_data_write = 12, - .command = buspirate_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_DEDIPROG == 1 - { /* SPI_CONTROLLER_DEDIPROG */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = dediprog_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = dediprog_spi_read, - .write_256 = dediprog_spi_write_256, - }, -#endif - -#if CONFIG_RAYER_SPI == 1 - { /* SPI_CONTROLLER_RAYER */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_NICINTEL_SPI == 1 - { /* SPI_CONTROLLER_NICINTEL */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_OGP_SPI == 1 - { /* SPI_CONTROLLER_OGP */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - - {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ +const struct spi_programmer spi_programmer_none = { + .type = SPI_CONTROLLER_NONE, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = NULL, + .multicommand = NULL, + .read = NULL, + .write_256 = NULL, }; -const int spi_programmer_count = ARRAY_SIZE(spi_programmer); +const struct spi_programmer *spi_programmer = &spi_programmer_none; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - if (!spi_programmer[spi_controller].command) { + if (!spi_programmer->command) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].command(writecnt, readcnt, + return spi_programmer->command(writecnt, readcnt, writearr, readarr); } int spi_send_multicommand(struct spi_command *cmds) { - if (!spi_programmer[spi_controller].multicommand) { + if (!spi_programmer->multicommand) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].multicommand(cmds); + return spi_programmer->multicommand(cmds); } int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -257,7 +99,7 @@ int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - int max_data = spi_programmer[spi_controller].max_data_read; + int max_data = spi_programmer->max_data_read; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI read chunk size not defined " "on this hardware. Please report a bug at " @@ -269,7 +111,7 @@ int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int max_data = spi_programmer[spi_controller].max_data_write; + int max_data = spi_programmer->max_data_write; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI write chunk size not defined " "on this hardware. Please report a bug at " @@ -282,7 +124,7 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int addrbase = 0; - if (!spi_programmer[spi_controller].read) { + if (!spi_programmer->read) { msg_perr("%s called, but SPI read is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); @@ -308,7 +150,7 @@ "access window.\n"); msg_perr("Read will probably return garbage.\n"); } - return spi_programmer[spi_controller].read(flash, buf, addrbase + start, len); + return spi_programmer->read(flash, buf, addrbase + start, len); } /* @@ -320,14 +162,14 @@ /* real chunksize is up to 256, logical chunksize is 256 */ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!spi_programmer[spi_controller].write_256) { + if (!spi_programmer->write_256) { msg_perr("%s called, but SPI page write is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].write_256(flash, buf, start, len); + return spi_programmer->write_256(flash, buf, start, len); } /* @@ -337,7 +179,7 @@ */ uint32_t spi_get_valid_read_addr(void) { - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: @@ -349,3 +191,9 @@ return 0; } } + +void register_spi_programmer(const struct spi_programmer *pgm) +{ + spi_programmer = pgm; + buses_supported |= CHIP_BUSTYPE_SPI; +} \ No newline at end of file Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/spi25.c Wed May 11 19:07:07 2011 (r1299) @@ -178,7 +178,7 @@ /* Some SPI controllers do not support commands with writecnt=1 and * readcnt=4. */ - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: @@ -1351,7 +1351,7 @@ .readarr = NULL, }}; - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/wbsio_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -60,6 +60,20 @@ return flashport; } +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); + +static const struct spi_programmer spi_programmer_wbsio = { + .type = SPI_CONTROLLER_WBSIO, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = wbsio_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = wbsio_spi_read, + .write_256 = spi_chip_write_1, +}; + int wbsio_check_for_spi(void) { if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) @@ -68,8 +82,7 @@ msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_WBSIO; + register_spi_programmer(&spi_programmer_wbsio); msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 KB!\n", __func__); max_rom_decode.spi = 1024 * 1024; @@ -97,7 +110,7 @@ * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -181,7 +194,7 @@ return 0; } -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return read_memmapped(flash, buf, start, len); }

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