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[PATCH 03/11] add macros and pretty printing for HSFS and HSFC
by Stefan Tauner 28 May '11

28 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 62 insertions(+), 12 deletions(-) diff --git a/ichspi.c b/ichspi.c index 7e4a363..12727d1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -43,6 +43,37 @@ #include "spi.h" /* ICH9 controller register definition */ +#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ +#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ +#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF) +#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */ +#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF) +#define HSFS_AEL_OFF 2 /* 2: Access Error Log */ +#define HSFS_AEL (0x1 << HSFS_AEL_OFF) +#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */ +#define HSFS_BERASE (0x1 << HSFS_BERASE_OFF) +#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ +#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF) + /* 6-12: reserved */ +#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */ +#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF) +#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */ +#define HSFS_FDV (0x1 << HSFS_FDV_OFF) +#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */ +#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF) + +#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */ +#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */ +#define HSFC_FGO (0x1 << HSFC_FGO_OFF) +#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ +#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) + /* 3-7: reserved */ +#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ +#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) + /* 14: reserved */ +#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */ +#define HSFC_SME (0x1 << HSFC_SME_OFF) + #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ @@ -260,6 +291,28 @@ static void pretty_print_opcodes(OPCODES *ops) } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) +{ + msg_pdbg("HSFS: "); + pprint_reg(HSFS, FDONE, reg_val, ", "); + pprint_reg(HSFS, FCERR, reg_val, ", "); + pprint_reg(HSFS, AEL, reg_val, ", "); + pprint_reg(HSFS, BERASE, reg_val, ", "); + pprint_reg(HSFS, SCIP, reg_val, ", "); + pprint_reg(HSFS, FDOPSS, reg_val, ", "); + pprint_reg(HSFS, FDV, reg_val, ", "); + pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) +{ + msg_pdbg("HSFC: "); + pprint_reg(HSFC, FGO, reg_val, ", "); + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + pprint_reg(HSFC, FDBC, reg_val, ", "); + pprint_reg(HSFC, SME, reg_val, "\n"); +} + static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) { msg_pdbg("SSFS: "); @@ -1204,14 +1257,15 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, case SPI_CONTROLLER_ICH9: tmp2 = mmio_readw(ich_spibar + 4); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); + prettyprint_ich9_reg_hsfs(tmp2); + if (tmp2 & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + + tmp2 = mmio_readw(ich_spibar + 6); + msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); + prettyprint_ich9_reg_hsfc(tmp2); tmp = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); @@ -1258,10 +1312,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(ich_spibar + 0xB0)); - if (tmp2 & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } ich_init_opcodes(); break; default: -- 1.7.1

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[PATCH 02/11] add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them
by Stefan Tauner 28 May '11

28 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 51 +++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 45 insertions(+), 6 deletions(-) diff --git a/ichspi.c b/ichspi.c index 676b93a..7e4a363 100644 --- a/ichspi.c +++ b/ichspi.c @@ -243,6 +243,44 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; +/* pretty printing functions */ +static void pretty_print_opcodes(OPCODES *ops) +{ + if(ops == NULL) + return; + + msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], ops->preop[1]); + + OPCODE oc; + uint8_t i; + for (i = 0; i < 8; i++) { + oc = ops->opcode[i]; + msg_pdbg("op[%d]=0x%02x, %d, %d\n", i, oc.opcode, oc.spi_type, oc.atomic); + } +} + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) +{ + msg_pdbg("SSFS: "); + pprint_reg(SSFS, SCIP, reg_val, ", "); + pprint_reg(SSFS, FDONE, reg_val, ", "); + pprint_reg(SSFS, FCERR, reg_val, ", "); + pprint_reg(SSFS, AEL, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) +{ + msg_pdbg("SSFC: "); + pprint_reg(SSFC, SCGO, reg_val, ", "); + pprint_reg(SSFC, ACS, reg_val, ", "); + pprint_reg(SSFC, SPOP, reg_val, ", "); + pprint_reg(SSFC, COP, reg_val, ", "); + pprint_reg(SSFC, DBC, reg_val, ", "); + pprint_reg(SSFC, SME, reg_val, ", "); + pprint_reg(SSFC, SCF, reg_val, "\n"); +} + static uint8_t lookup_spi_type(uint8_t opcode) { int a; @@ -519,6 +557,8 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); + pretty_print_opcodes(curopcodes); + msg_pdbg("\n"); return 0; } } @@ -793,6 +833,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); if (temp32 & SSFS_FCERR) { msg_perr("Transaction error!\n"); + prettyprint_ich9_reg_ssfs(temp32); + prettyprint_ich9_reg_ssfc(temp32); /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ @@ -1195,16 +1237,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + 0x90); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); - msg_pdbg("AEL %i, ", (tmp >> 4) & 1); - msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); - msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); - msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + prettyprint_ich9_reg_ssfs(tmp); if (tmp & (1 << 3)) { msg_pdbg("Clearing SSFS.FCERR\n"); mmio_writeb(1 << 3, ich_spibar + 0x90); } - tmp >>= 8; - msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); + prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x94)); -- 1.7.1

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[PATCH 01/11] improve macros for SSFS and SSFC bits
by Stefan Tauner 28 May '11

28 May '11

- introduce offset macros and use them to (re)define the existing mask macros - add comments - rename SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) - use those for refactoring and magic number elemination. - following patch uses them for pretty printing Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 48 ++++++++++++++++++++++++++++++------------------ 1 files changed, 30 insertions(+), 18 deletions(-) diff --git a/ichspi.c b/ichspi.c index 299cbf3..676b93a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -47,24 +47,36 @@ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ -#define SSFS_SCIP 0x00000001 -#define SSFS_CDS 0x00000004 -#define SSFS_FCERR 0x00000008 -#define SSFS_AEL 0x00000010 +#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ +#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) +#define SSFS_FDONE_OFF 2 /* Cycle Done Status */ +#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF) +#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */ +#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF) +#define SSFS_AEL_OFF 4 /* Access Error Log */ +#define SSFS_AEL (0x1 << SSFS_AEL_OFF) /* The following bits are reserved in SSFS: 1,5-7. */ #define SSFS_RESERVED_MASK 0x000000e2 #define ICH9_REG_SSFC 0x91 /* 24 Bits */ -#define SSFC_SCGO 0x00000200 -#define SSFC_ACS 0x00000400 -#define SSFC_SPOP 0x00000800 -#define SSFC_COP 0x00001000 -#define SSFC_DBC 0x00010000 -#define SSFC_DS 0x00400000 -#define SSFC_SME 0x00800000 -#define SSFC_SCF 0x01000000 -#define SSFC_SCF_20MHZ 0x00000000 -#define SSFC_SCF_33MHZ 0x01000000 +#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */ +#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF) +#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */ +#define SSFC_ACS (0x1 << SSFC_ACS_OFF) +#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */ +#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF) +#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */ +#define SSFC_COP (0x7 << SSFC_COP_OFF) +#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */ +#define SSFC_DBC (0x3f << SSFC_DBC_OFF) +#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */ +#define SSFC_DS (0x1 << SSFC_DS_OFF) +#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */ +#define SSFC_SME (0x1 << SSFC_SME_OFF) +#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */ +#define SSFC_SCF (0x7 << SSFC_SCF_OFF) +#define SSFC_SCF_20MHZ 0x00000000 +#define SSFC_SCF_33MHZ 0x01000000 /* We combine SSFS and SSFC to one 32-bit word, * therefore SSFC bits are off by 8. * The following bits are reserved in SSFC: 23-19,7,0. */ @@ -709,8 +721,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; - /* clear error status registers */ - temp32 |= (SSFS_CDS + SSFS_FCERR); + /* Clear cycle done and cycle error status registers */ + temp32 |= (SSFS_FDONE + SSFS_FCERR); REGWRITE32(ICH9_REG_SSFS, temp32); /* Use 20 MHz */ @@ -720,7 +732,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; - datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); + datatemp = (uint32_t) (((datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC); temp32 |= datatemp; } @@ -767,7 +779,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_SSFS, temp32); /* Wait for Cycle Done Status or Flash Cycle Error. */ - while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10); } -- 1.7.1

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[PATCH 00/11] ichspi patches 4.0 (includes draft version of hw sequencing support)
by Stefan Tauner 28 May '11

28 May '11

hardware sequencing is almost complete (as in fully implemented, but not tested). we still need a solution for the const flashchips elements. besides hwseq there are also a few other new improvements and fixes of old patches. Stefan Tauner (11): improve macros for SSFS and SSFC bits add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them add macros and pretty printing for HSFS and HSFC use the max_data_read field of the new spi_programmer struct to simplify run_opcode. warn if SMM BIOS Write Protection is detected in BIOS_CNTL add missing ICH9 register macros and use them to eliminate magic numbers add ICH/PCH flash descriptor decoding simplify ich_set_bbar add macros and pretty printing for "Host Lower Vendor Specific Component Capabilities" registers add FPB (Flash Partition Boundary) macros and init printing add support for Intel Hardware Sequencing Makefile | 2 +- chipdrivers.h | 6 + chipset_enable.c | 11 +- flashchips.c | 40 ++- ich_descriptors.c | 451 +++++++++++++++ ich_descriptors.h | 408 ++++++++++++++ ichspi.c | 646 ++++++++++++++++++---- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 226 ++++++++ 11 files changed, 1719 insertions(+), 119 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

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[commit] r1321 - trunk
by repository service 28 May '11

28 May '11

Author: stefanct Date: Sat May 28 04:37:14 2011 New Revision: 1321 URL: http://flashrom.org/trac/flashrom/changeset/1321 Log: small fixes - missing spaces in code and output - improved documentation/naming/output - missing line breaks in spi probing functions Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flash.h trunk/flashrom.c trunk/ichspi.c trunk/print.c trunk/spi25.c Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu May 26 16:28:51 2011 (r1320) +++ trunk/flash.h Sat May 28 04:37:14 2011 (r1321) @@ -136,6 +136,8 @@ unsigned int size; /* Eraseblock size */ unsigned int count; /* Number of contiguous blocks with that size */ } eraseblocks[NUM_ERASEREGIONS]; + /* a block_erase function should try to erase one block of size + * 'blocklen' at address 'blockaddr' and return 0 on success. */ int (*block_erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); } block_erasers[NUM_ERASEFUNCTIONS]; Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Thu May 26 16:28:51 2011 (r1320) +++ trunk/flashrom.c Sat May 28 04:37:14 2011 (r1321) @@ -1312,7 +1312,7 @@ goto out_free; } - ret = write_buf_to_file(buf, flash->total_size * 1024, filename); + ret = write_buf_to_file(buf, size, filename); out_free: free(buf); msg_cinfo("%s.\n", ret ? "FAILED" : "done"); @@ -1489,13 +1489,13 @@ if (!eraser.block_erase && eraser.eraseblocks[0].count) { if (log) msg_cdbg("eraseblock layout is known, but matching " - "block erase function is not implemented. "); + "block erase function is not implemented. "); return 1; } if (eraser.block_erase && !eraser.eraseblocks[0].count) { if (log) msg_cdbg("block erase function found, but " - "eraseblock layout is not defined. "); + "eraseblock layout is not defined. "); return 1; } return 0; Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu May 26 16:28:51 2011 (r1320) +++ trunk/ichspi.c Sat May 28 04:37:14 2011 (r1321) @@ -159,9 +159,9 @@ return mmio_readb(ich_spibar + X); } -#define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X) -#define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X) -#define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X) +#define REGWRITE32(off,val) mmio_writel(val, ich_spibar+off) +#define REGWRITE16(off,val) mmio_writew(val, ich_spibar+off) +#define REGWRITE8(off,val) mmio_writeb(val, ich_spibar+off) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); @@ -856,7 +856,8 @@ if (!ichspi_lock) opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); if (opcode_index == -1) { - msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); + msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n", + cmd); return SPI_INVALID_OPCODE; } } Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu May 26 16:28:51 2011 (r1320) +++ trunk/print.c Sat May 28 04:37:14 2011 (r1321) @@ -43,18 +43,18 @@ ret = strcat_realloc(ret, "Non-SPI,"); } else { if (bustype & CHIP_BUSTYPE_PARALLEL) - ret = strcat_realloc(ret, "Parallel,"); + ret = strcat_realloc(ret, "Parallel, "); if (bustype & CHIP_BUSTYPE_LPC) - ret = strcat_realloc(ret, "LPC,"); + ret = strcat_realloc(ret, "LPC, "); if (bustype & CHIP_BUSTYPE_FWH) - ret = strcat_realloc(ret, "FWH,"); + ret = strcat_realloc(ret, "FWH, "); if (bustype & CHIP_BUSTYPE_SPI) - ret = strcat_realloc(ret, "SPI,"); + ret = strcat_realloc(ret, "SPI, "); if (bustype == CHIP_BUSTYPE_NONE) - ret = strcat_realloc(ret, "None,"); + ret = strcat_realloc(ret, "None, "); } /* Kill last comma. */ - ret[strlen(ret) - 1] = '\0'; + ret[strlen(ret) - 2] = '\0'; ret = realloc(ret, strlen(ret) + 1); return ret; } Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Thu May 26 16:28:51 2011 (r1320) +++ trunk/spi25.c Sat May 28 04:37:14 2011 (r1321) @@ -119,8 +119,10 @@ uint32_t id1; uint32_t id2; - if (spi_rdid(readarr, bytes)) + if (spi_rdid(readarr, bytes)) { + msg_cdbg("\n"); return 0; + } if (!oddparity(readarr[0])) msg_cdbg("RDID byte 0 parity violation. "); @@ -198,8 +200,10 @@ unsigned char readarr[JEDEC_REMS_INSIZE]; uint32_t id1, id2; - if (spi_rems(readarr)) + if (spi_rems(readarr)) { + msg_cdbg("\n"); return 0; + } id1 = readarr[0]; id2 = readarr[1]; @@ -254,15 +258,19 @@ return 0; } - if (spi_res(readarr, 1)) + if (spi_res(readarr, 1)) { + msg_cdbg("\n"); return 0; + } id2 = readarr[0]; msg_cdbg("%s: id 0x%x\n", __func__, id2); - if (id2 != flash->model_id) + if (id2 != flash->model_id) { + msg_cdbg("\n"); return 0; + } /* Print the status register to tell the * user about possible write protection. @@ -276,8 +284,10 @@ unsigned char readarr[2]; uint32_t id1, id2; - if (spi_res(readarr, 2)) + if (spi_res(readarr, 2)) { + msg_cdbg("\n"); return 0; + } id1 = readarr[0]; id2 = readarr[1];

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Hardware Sequencing for ichspi.c
by Stefan Tauner 27 May '11

27 May '11

Hello list! i am researching hardware sequencing at the moment and i am thinking about how it should be implemented and integrated. == INTRODUCTION == newer intel chipsets allow two modes of operation when talking to spi flashes: software and hw sequencing. in sw sequencing the software needs to provide the spi opcodes (or use the predefined ones if applicable) in a table that it can later invoke. to do so the id of the opcode, data lengths and data content is written to some ich registers and a bit is flipped to trigger the execution. the opcodes can be reprogrammed by the software at any time (which allows pretty much everything - as long as there is no locking/protection activated, but that's another story). sw sequencing is already fully supported by flashrom. in hw sequencing the list of opcodes is fixed (with the exception of the erase command). this does of course only work if the flash chip adheres to strict specifications which are documented in the datasheets (erase sector size, write enable procedures/status register semantics etc). if ME or GbE firmware should be supported then the restrictions are even more severe (and HW seq is required for those features). another requirement for hw seq is that the flash must contain a valid descriptor section. in that data structure the layout of the flash contents it described among other things. this way the ME and the GbE processors can find their firmware at startup (my guess). the descriptors also define the locking of the flash regions we had so much trouble in the past. it is also possible to use more than one flash chip to store bios and firmware information with descriptors. this is transparent to the software when using hw seq (and sw seq is not able to speak to the second chip/toggle the second CS at all afaics). == DETAILS == requirements for hw seq (besides the reqs for sw seq like unlocked regions and the properties mentioned in "SPI Based BIOS Requirements" in the data sheets etc.): - a compatible flash device as defined in "Hardware Sequencing Requirements" in intel's ICH/PCH datasheets. that is not easy to check right now, but we probably do not care anyway (or is anyone interested in using ICHs as general purpose flashing devices? actually this would be possible with the second chip select and hardware sequencing... :). - HSFS.FDV=1 i.e. a valid flash descriptor signature is found at the bottom of the flash (some steppings seem to have an offset of 0x10, but that's not our problem when we are using HSFS.FDV). limitations of hw seq: - only read, write and erase operations can be committed. this has lots of implications for an integration into flashrom; see IMPLEMENTATION. other interesting bits: - there is support for shadowing two flash chips into one contiguous address space. the use of multiple flash chips can be checked in flash descriptor bit FLMAP0.NC. there is limited support for chips with different attributes: different sizes are no problem (defined in fd FCBA). other attributes can be assigned to two parts of the SPI address space by the lower and upper VSCC (Host Lower/Upper Vendor Specific Component Capabilities Register). the border between them is defined by register FPB.FPBA. this can be used for flash chips that differ for example in the erase opcode. NB: this also allows the use of a single flash chip with different erase granularities in different address spaces. the two attribute registers (LVSCC and UVSCC) can be locked independently from each other and from the FLOCKDN bit. - there is a table of jedec ids and the (erase/write (enable)) abilities of associated flash chips in the flash descriptor (unreachable via ICH/PCH registers). the ability words have the same semantic as the VSCC mentioned above. quoting the (confidential) ibex peak SPI programming guide AN: "The Intel® ME VSCC Table defines how the Intel® ME will communicate with the installed SPI flash. This table is defined in the descriptor and is the responsibility of who puts together the NVM image. LVSCC and/or UVSCC registers are defined in memory space and must be set by BIOS. This table must define every flash part that is intended to be used." == IMPLEMENTATION == the very simple access model of hw seq is too simple for flashrom, or put in another way: flashrom is too sophisticated to integrate hw seq easily. in hw seq the target device is not a single flashchip from the flashchips table, but a contiguous address space which we can access by just setting an address, filling in the data (like in sw seq) and then committing the command by setting the read/write or erase mode and the go-flag in HSFC. i have identified the following problems and am asking for possible solutions: - "dynamic" target device. we dont have one single flash chip, but only certain attributes available (total size, erase block sizes for currently up to two address spaces). there are many combinations of flash chips that could be wired up on boards. theoretically we could define them all and use a customized probe function to "detect" them, but that's of course(?) not the way to go. the main problem here is the constant flashrom array. an alternative may be a const array of pointers to (mostly const) flashchips, where one of them is a non-const generic ich hw seq device with a custom probe function that sets the important fields of that chip. dunno if that would work (i.e. compile to mostly text section data). maybe we could probably live with a const generic device anyway, because we can read the flash size anytime via the ich registers. but there are problems with the generic flashrom methods: e.g. they check for matching file and flash sizes. - different programmer function semantics. there are no opcodes to deal with, so the existing spi functions in ichspi.c are not really useful. i think the best way would be to add a new programmer for this. since we only allow one spi programmer atm(?), the registering of the programmer in ich_init_spi would have to be changed. how would we want to specify if hw seq should be used? there is no way to get command line arguments in there (yet). another way would be to deduce that just from the register contents: - if the opcodes are locked and dont contain enough opcodes to succeed, use hw seq. this is probably not so easy to check, so it would be easier to just do the following: - if the opcodes are locked down, use hw seq - also if there are (>=) 2 flash components, we have to use hw seq. - another way may be to use sw seq and retry with sw seq when we fail, but that's also complicated and i would love to avoid that at least for the near future. i may have missed a thing or a dozen, but please dont shoot me my brain is already wounded from digging through all that information ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Intel SandyBridge serie 6 chipsets support
by Mohammed-Amine.Rebai＠bull.net 27 May '11

27 May '11

Dear Flahsrom representant, I am a Bios engineer at BULL, a major european server and supercomputer company «www.bull.com » . First of all, I would like to thank you for the great job you are doing, we use your utility a lot. I would like to know if you are planning to support the Bios SPI flash flashing on the Intel SandyBridge architecture, especially the Intel 6 series chipset/C200/Patsburg platform controller hub? Thanks in advance for your answer. Best regards +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | Amine REBAI | BIOS engineer | Bull SAS, Architect of an Open World(TM) | BP 68 - Rue Jean Jaures - 78340 Les Clayes sous Bois (France) | Email : MOHAMMED-AMINE.REBAI(a)BULL.NET | Tel : +33 (0)1 30 80 31 38 | | R&D/Server_Design_Development - http://www.bull.com/hpc | - http://www.bull.com/novascale | | Ce message contient des informations confidentielles, couvertes par | le secret professionnel ou réservées exclusivement à leur destinataire. | Toute lecture, utilisation, diffusion ou divulgation sans autorisation | expresse est rigoureusement interdite. | Si vous n'en êtes pas le destinataire, merci de prendre contact avec | l'expéditeur et de détruire ce message. | | This e-mail contains material that is confidential for the sole use of | the intended recipient. Any review, reliance or distribution by others | or forwarding without express permission is strictly prohibited. | If you are not the intended recipient, please contact the sender and | delete all copies. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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Requested Verbose Output
by Lee Daugherty 27 May '11

27 May '11

This is the output of the BIOS found on the MSI MS-7309.

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[commit] r1320 - trunk
by repository service 26 May '11

26 May '11

Author: stefanct Date: Thu May 26 16:28:51 2011 New Revision: 1320 URL: http://flashrom.org/trac/flashrom/changeset/1320 Log: add a bunch of new/tested motherboards, board enables and flash chips tested motherboards: - MSI MS-7599 (870-C45) http://www.flashrom.org/pipermail/flashrom/2011-May/006420.html - Gigabyte GA-P55A-UD4 (rev 1.0) http://www.flashrom.org/pipermail/flashrom/2011-May/006415.html - Supermicro X8DTU-F http://www.flashrom.org/pipermail/flashrom/2011-May/006329.html - Supermicro X8STi http://www.flashrom.org/pipermail/flashrom/2011-May/006436.html tested board enable: - abit NF-M2 nView success report (without a log though): http://www.flashrom.org/pipermail/flashrom/2011-April/006167.html tested flash chips: - ST M50FW080 (+EW) http://www.flashrom.org/pipermail/flashrom/2011-May/006409.html - ST M25P32 (+EW) http://www.flashrom.org/pipermail/flashrom/2011-May/006398.html - Winbond W25x64 (+P) http://www.flashrom.org/pipermail/flashrom/2011-March/006012.html - Winbond W39V040FA (+W) http://www.flashrom.org/pipermail/flashrom/2010-December/005642.html new flash chip - Winbond W25Q128 http://www.flashrom.org/pipermail/flashrom/2011-April/006309.html W25Q128 is: Signed-off-by: Antony Rheneus <rheneus.paul(a)gmail.com> everything else is: Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/flashchips.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu May 26 15:30:51 2011 (r1319) +++ trunk/board_enable.c Thu May 26 16:28:51 2011 (r1320) @@ -1959,7 +1959,7 @@ {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, - {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower}, + {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu May 26 15:30:51 2011 (r1319) +++ trunk/flashchips.c Thu May 26 16:28:51 2011 (r1320) @@ -6467,7 +6467,7 @@ .model_id = ST_M25P32, .total_size = 4096, .page_size = 256, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7064,7 +7064,7 @@ .total_size = 1024, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (82802ab.c) */ .block_erasers = @@ -7525,6 +7525,42 @@ { .vendor = "Winbond", + .name = "W25Q128", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q128, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PROBE, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Winbond", .name = "W25x10", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, @@ -7724,7 +7760,7 @@ .total_size = 8192, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PROBE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7963,9 +7999,9 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu May 26 15:30:51 2011 (r1319) +++ trunk/print.c Thu May 26 16:28:51 2011 (r1320) @@ -535,6 +535,7 @@ B("GIGABYTE", "GA-MA790FX-DQ6", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), B("GIGABYTE", "GA-MA790GP-DS4H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), B("GIGABYTE", "GA-MA790XT-UD4P (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3010", NULL), + B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0 (and 2.0?))", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL), B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-33…", NULL), @@ -587,6 +588,7 @@ B("MSI", "MS-7368 (K9AG Neo2-Digital)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1241", NULL), B("MSI", "MS-7376 (K9A2 Platinum)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1332", NULL), B("MSI", "MS-7596 (785GM-E51)", 1, "http://eu.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1866", NULL), + B("MSI", "MS-7599 (870-C45)", 1, "http://www.msi.com/product/mb/870-C45.html", NULL), B("MSI", "MS-7640 (890FXA-GD70)",1, "http://www.msi.com/product/mb/890FXA-GD70.html", "Reported by \"Linux User #330250\" http://flashrom.org/pipermail/flashrom/2011-March/006072.html"), B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=2012", NULL), B("NEC", "PowerMate 2000", 1, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), @@ -617,6 +619,8 @@ B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), B("Supermicro", "X8DTH-6F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm", NULL), B("Supermicro", "X8DTT-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm", NULL), + B("Supermicro", "X8DTU-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU-F.cfm", NULL), + B("Supermicro", "X8STi", 1, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm", NULL), B("T-Online", "S-100", 1, "http://wiki.freifunk-hannover.de/T-Online_S_100", NULL), B("Tekram", "P6Pro-A5", 1, "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL), B("Termtek", "TK-3370 (Rev:2.5B)", 1, NULL, NULL),

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[PATCH] ichspi: fix unused FREG detection
by Joshua Roys 26 May '11

26 May '11

Hello, This patch will fix incorrect output from my original patch: 0x64: 0x00000fff (FREG4: Platform Data) 0x00fff000-0x00000fff is locked Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Thanks, Josh

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