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Re: [flashrom] [PATCH 06/12] add missing ICH9 register macros and use them to eliminate magic numbers
by Carl-Daniel Hailfinger 12 Jun '11

12 Jun '11

Am 08.06.2011 04:55 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> with two minor changes: > @@ -537,15 +549,15 @@ static int program_opcodes(OPCODES *op, int enable_undo) > */ > void ich_set_bbar(uint32_t minaddr) > { > -#define BBAR_MASK 0x00ffff00 > minaddr &= BBAR_MASK; > switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_VIA: > ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; > - if (ichspi_bbar) > + if (ichspi_bbar) { > msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", > ichspi_bbar); > + } > Kill the additional braces, please. I know this is a multiline statement, but it is only a single statement and the indentation of the second line makes it obvious where it belongs to. > @@ -556,13 +568,14 @@ void ich_set_bbar(uint32_t minaddr) > msg_perr("Setting BBAR failed!\n"); > break; > case SPI_CONTROLLER_ICH9: > - ichspi_bbar = mmio_readl(ich_spibar + 0xA0) & ~BBAR_MASK; > - if (ichspi_bbar) > + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR) & ~BBAR_MASK; > + if (ichspi_bbar) { > msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", > ichspi_bbar); > + } > Same here. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1334 - trunk
by repository service 12 Jun '11

12 Jun '11

Author: stefanct Date: Sun Jun 12 10:14:10 2011 New Revision: 1334 URL: http://flashrom.org/trac/flashrom/changeset/1334 Log: ichspi.c: add missing ICH9 register macros and eliminate magic numbers - add macros for FRAP, FREG0, PR0-PR4 and BBAR - eliminate magic numbers representing those registers and some other bits too - remove printing out the contents of FDOC because it is useless Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Jun 11 21:44:31 2011 (r1333) +++ trunk/ichspi.c Sun Jun 12 10:14:10 2011 (r1334) @@ -77,6 +77,15 @@ #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ +#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */ +#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */ + +#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */ +#define ICH9_REG_PR1 0x78 /* 32 Bytes Protected Range 1 */ +#define ICH9_REG_PR2 0x7c /* 32 Bytes Protected Range 2 */ +#define ICH9_REG_PR3 0x80 /* 32 Bytes Protected Range 3 */ +#define ICH9_REG_PR4 0x84 /* 32 Bytes Protected Range 4 */ + #define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ #define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) @@ -119,6 +128,9 @@ #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ #define ICH9_REG_OPMENU 0x98 /* 64 Bits */ +#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ +#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ + // ICH9R SPI commands #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 @@ -545,7 +557,6 @@ */ void ich_set_bbar(uint32_t minaddr) { -#define BBAR_MASK 0x00ffff00 minaddr &= BBAR_MASK; switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: @@ -564,13 +575,13 @@ msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - ichspi_bbar = mmio_readl(ich_spibar + 0xA0) & ~BBAR_MASK; + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR) & ~BBAR_MASK; if (ichspi_bbar) msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", ichspi_bbar); ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + 0xA0); - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); + rmmio_writel(ichspi_bbar, ich_spibar + ICH9_REG_BBAR); + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); /* We don't have any option except complaining. And if the write * failed, the restore will fail as well, so no problem there. */ @@ -1154,7 +1165,7 @@ uint32_t base, limit; int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | (((ICH_BRRA(frap) >> i) & 1) << 0); - int offset = 0x54 + i * 4; + int offset = ICH9_REG_FREG0 + i * 4; uint32_t freg = mmio_readl(ich_spibar + offset); msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", @@ -1264,19 +1275,19 @@ ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(ich_spibar + 4); + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); - if (tmp2 & (1 << 15)) { + if (tmp2 & HSFS_FLOCKDN) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } - tmp2 = mmio_readw(ich_spibar + 6); + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); prettyprint_ich9_reg_hsfc(tmp2); - tmp = mmio_readl(ich_spibar + 0x50); + tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); @@ -1288,39 +1299,37 @@ do_ich9_spi_frap(tmp, i); msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(ich_spibar + 0x74)); + mmio_readl(ich_spibar + ICH9_REG_PR0)); msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(ich_spibar + 0x78)); + mmio_readl(ich_spibar + ICH9_REG_PR1)); msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(ich_spibar + 0x7C)); + mmio_readl(ich_spibar + ICH9_REG_PR2)); msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(ich_spibar + 0x80)); + mmio_readl(ich_spibar + ICH9_REG_PR3)); msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(ich_spibar + 0x84)); + mmio_readl(ich_spibar + ICH9_REG_PR4)); - tmp = mmio_readl(ich_spibar + 0x90); + tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); prettyprint_ich9_reg_ssfs(tmp); - if (tmp & (1 << 3)) { + if (tmp & SSFS_FCERR) { msg_pdbg("Clearing SSFS.FCERR\n"); - mmio_writeb(1 << 3, ich_spibar + 0x90); + mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS); } msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x94)); + mmio_readw(ich_spibar + ICH9_REG_PREOP)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x96)); + mmio_readw(ich_spibar + ICH9_REG_OPTYPE)); msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x98)); + mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x9C)); - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); + mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); - msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(ich_spibar + 0xB0)); ich_init_opcodes(); break; default:

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[PATCH 2/2] Bonus payload reads flash, sends on serial console
by Tadas Slotkus 12 Jun '11

12 Jun '11

Signed-off-by: Tadas Slotkus <devtadas(a)gmail.com> --- flashrom.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/flashrom.c b/flashrom.c index b145037..f66a85d 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1291,6 +1291,12 @@ int write_buf_to_file(unsigned char *buf, unsigned long size, char *filename) filename); return 1; } +#else + unsigned long i; + serial_putcmd("\n\nRomStartMarker\n\n\0"); + for (i = 0; i < size; i++) + serial_putchar(*(buf++)); + serial_putcmd("\n\nRomEndMarker\n\n\0"); #endif return 0; } @@ -1800,6 +1806,14 @@ void check_chip_supported(const struct flashchip *flash) int main(int argc, char *argv[]) { +#ifdef __LIBPAYLOAD__ + while (1) { + argc=3; + char *argt[3] = {"./flashrom\0", "-r\0", "out.txt\0"}; + argt[1][1] = getchar(); + cli_classic(argc, argt); + } +#endif return cli_classic(argc, argv); } -- 1.7.0.4

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Re: [flashrom] [PATCH 04/12] use the max_data_read field of the new spi_programmer struct to simplify run_opcode.
by Carl-Daniel Hailfinger 11 Jun '11

11 Jun '11

Am 08.06.2011 04:55 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 41 +++++++++++++++++------------------------ > 1 files changed, 17 insertions(+), 24 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index 12727d1..dff6f32 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -913,37 +913,30 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > static int run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data) > { > + uint8_t maxlength = spi_programmer->max_data_read; > Mh. I see what you're doing here, and it makes sense, but a comment would be appreciated in the code: /* The maximum data length is identical on ICH/VIA for the maximum read length and for the maximum write length without opcode and address. Opcode and address are stored in separate registers, not in the data registers. The only exception applies if the opcode definition (un)intentionally classifies said opcode incorrectly as non-address opcode or vice versa. */ Any suggestions on how to improve that comment? > + > + if (spi_programmer->type == SPI_CONTROLLER_NONE) { > + msg_perr("%s: unsupported chipset\n", __func__); > + return -1; > + } > + > + if (datalength > maxlength) { > + msg_perr("%s: Internal command size error for " > + "opcode 0x%02x, got datalength=%i, want <=%i\n", > + __func__, op.opcode, datalength, maxlength); > + return SPI_INVALID_LENGTH; > + } > + > switch (spi_programmer->type) { > case SPI_CONTROLLER_VIA: > - if (datalength > 16) { > - msg_perr("%s: Internal command size error for " > - "opcode 0x%02x, got datalength=%i, want <=16\n", > - __func__, op.opcode, datalength); > - return SPI_INVALID_LENGTH; > - } > - return ich7_run_opcode(op, offset, datalength, data, 16); > case SPI_CONTROLLER_ICH7: > - if (datalength > 64) { > - msg_perr("%s: Internal command size error for " > - "opcode 0x%02x, got datalength=%i, want <=16\n", > - __func__, op.opcode, datalength); > - return SPI_INVALID_LENGTH; > - } > - return ich7_run_opcode(op, offset, datalength, data, 64); > + return ich7_run_opcode(op, offset, datalength, data, maxlength); > case SPI_CONTROLLER_ICH9: > - if (datalength > 64) { > - msg_perr("%s: Internal command size error for " > - "opcode 0x%02x, got datalength=%i, want <=16\n", > - __func__, op.opcode, datalength); > - return SPI_INVALID_LENGTH; > - } > return ich9_run_opcode(op, offset, datalength, data); > default: > - msg_perr("%s: unsupported chipset\n", __func__); > + /* If we ever get here, something really weird happened */ > + return -1; > } > - > - /* If we ever get here, something really weird happened */ > - return -1; > } > > static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > Apart from the comment issue (which can be fixed without resubmitting), this is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1333 - trunk
by repository service 11 Jun '11

11 Jun '11

Author: stefanct Date: Sat Jun 11 21:44:31 2011 New Revision: 1333 URL: http://flashrom.org/trac/flashrom/changeset/1333 Log: use the max_data_read field of the new spi_programmer struct to simplify run_opcode also, explain the transformation of the read/write array/count in ich_spi_send_command better. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Jun 11 20:16:50 2011 (r1332) +++ trunk/ichspi.c Sat Jun 11 21:44:31 2011 (r1333) @@ -922,37 +922,31 @@ static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { + /* max_data_read == max_data_write for all Intel/VIA SPI masters */ + uint8_t maxlength = spi_programmer->max_data_read; + + if (spi_programmer->type == SPI_CONTROLLER_NONE) { + msg_perr("%s: unsupported chipset\n", __func__); + return -1; + } + + if (datalength > maxlength) { + msg_perr("%s: Internal command size error for " + "opcode 0x%02x, got datalength=%i, want <=%i\n", + __func__, op.opcode, datalength, maxlength); + return SPI_INVALID_LENGTH; + } + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: - if (datalength > 16) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 64); + return ich7_run_opcode(op, offset, datalength, data, maxlength); case SPI_CONTROLLER_ICH9: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } return ich9_run_opcode(op, offset, datalength, data); default: - msg_perr("%s: unsupported chipset\n", __func__); + /* If we ever get here, something really weird happened */ + return -1; } - - /* If we ever get here, something really weird happened */ - return -1; } static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -1038,7 +1032,13 @@ } } - /* translate read/write array/count */ + /* Translate read/write array/count. + * The maximum data length is identical for the maximum read length and + * for the maximum write length excluding opcode and address. Opcode and + * address are stored in separate registers, not in the data registers + * and are thus not counted towards data length. The only exception + * applies if the opcode definition (un)intentionally classifies said + * opcode incorrectly as non-address opcode or vice versa. */ if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) { data = (uint8_t *) (writearr + 1); count = writecnt - 1;

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Re: [flashrom] [PATCH 05/12] warn if SMM BIOS Write Protection is detected in BIOS_CNTL
by Stefan Tauner 11 Jun '11

11 Jun '11

already committed (in r1332), dont bother to review :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 05/11] warn if SMM BIOS Write Protection is detected in BIOS_CNTL
by Carl-Daniel Hailfinger 11 Jun '11

11 Jun '11

Am 28.05.2011 05:38 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > With minor changes: Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > --- > chipset_enable.c | 11 ++++++++++- > 1 files changed, 10 insertions(+), 1 deletions(-) > > diff --git a/chipset_enable.c b/chipset_enable.c > index 83b49ad..1f6f74c 100644 > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -264,8 +264,17 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, > (old & (1 << 0)) ? "en" : "dis"); > msg_pdbg("BIOS_CNTL is 0x%x\n", old); > > - new = old | 1; > + /* > + * Quote from the 6 Series datasheet: > Please include a datasheet number so others can find it easily. > + * "5: SMM BIOS Write Protect Disable (SMM_BWP) > Maybe "Bit 5: SMM..." > + * 1 = BIOS region SMM protection is enabled. > + * The BIOS Region is not writable unless all processors are in SMM." > + * In earlier chipsets this bit is reserved. */ > + if (old & (1 << 5)) { > + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); > + } > > + new = old | 1; > if (new == old) > return 0; > > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1332 - trunk
by repository service 11 Jun '11

11 Jun '11

Author: stefanct Date: Sat Jun 11 20:16:50 2011 New Revision: 1332 URL: http://flashrom.org/trac/flashrom/changeset/1332 Log: enable_flash_ich: warn if SMM BIOS Write Protection is detected in BIOS_CNTL Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sat Jun 11 14:21:37 2011 (r1331) +++ trunk/chipset_enable.c Sat Jun 11 20:16:50 2011 (r1332) @@ -264,8 +264,17 @@ (old & (1 << 0)) ? "en" : "dis"); msg_pdbg("BIOS_CNTL is 0x%x\n", old); - new = old | 1; + /* + * Quote from the 6 Series datasheet (Document Number: 324645-004): + * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP) + * 1 = BIOS region SMM protection is enabled. + * The BIOS Region is not writable unless all processors are in SMM." + * In earlier chipsets this bit is reserved. */ + if (old & (1 << 5)) { + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); + } + new = old | 1; if (new == old) return 0;

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[commit] r1331 - trunk
by repository service 11 Jun '11

11 Jun '11

Author: stefanct Date: Sat Jun 11 14:21:37 2011 New Revision: 1331 URL: http://flashrom.org/trac/flashrom/changeset/1331 Log: add support for Olimex programmers to ft2232_spi - add support for Olimex' ARM-USB-TINY, ARM-USB-TINY-H, ARM-USB-OCD AND ARM-USB-OCD-H and adjust man page - minor string change ("First International Computer, Inc." -> "FIC") Signed-off-by: Pete Batard <pbatard(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashrom.8 trunk/ft2232_spi.c Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Sat Jun 11 11:53:22 2011 (r1330) +++ trunk/flashrom.8 Sat Jun 11 14:21:37 2011 (r1331) @@ -183,7 +183,7 @@ .BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI \ translation unit)" .sp -.BR "* ft2232_spi" " (for SPI flash ROMs attached to a FT2232H/FT4232H/JTAGkey \ +.BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H family \ based USB SPI programmer)" .sp .BR "* serprog" " (for flash ROMs attached to a programmer speaking serprog)" @@ -361,8 +361,9 @@ .sp syntax where .B model -can be any of -.BR 2232H ", " JTAGkey ", or " 4232H +can be one of +.BR 2232H ", " 4232H ", " jtagkey ", " openmoko ", " arm-usb-tiny ", " \ +arm-usb-tiny-h ", " arm-usb-ocd " or " arm-usb-ocd-h and .B interface can be any of Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Sat Jun 11 11:53:22 2011 (r1330) +++ trunk/ft2232_spi.c Sat Jun 11 14:21:37 2011 (r1331) @@ -38,13 +38,22 @@ #define FIC_VID 0x1457 #define OPENMOKO_DBGBOARD_PID 0x5118 +#define OLIMEX_VID 0x15BA +#define OLIMEX_ARM_OCD_PID 0x0003 +#define OLIMEX_ARM_TINY_PID 0x0004 +#define OLIMEX_ARM_OCD_H_PID 0x002B +#define OLIMEX_ARM_TINY_H_PID 0x002A + const struct usbdev_status devs_ft2232spi[] = { {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "FT2232H"}, {FTDI_VID, FTDI_FT4232H_PID, OK, "FTDI", "FT4232H"}, {FTDI_VID, AMONTEC_JTAGKEY_PID, OK, "Amontec", "JTAGkey"}, - {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, - "First International Computer, Inc.", + {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"}, + {OLIMEX_VID, OLIMEX_ARM_OCD_PID, NT, "Olimex", "ARM-USB-OCD"}, + {OLIMEX_VID, OLIMEX_ARM_TINY_PID, OK, "Olimex", "ARM-USB-TINY"}, + {OLIMEX_VID, OLIMEX_ARM_OCD_H_PID, NT, "Olimex", "ARM-USB-OCD-H"}, + {OLIMEX_VID, OLIMEX_ARM_TINY_H_PID, NT, "Olimex", "ARM-USB-TINY-H"}, {}, }; @@ -167,6 +176,22 @@ ft2232_vid = FIC_VID; ft2232_type = OPENMOKO_DBGBOARD_PID; ft2232_interface = INTERFACE_A; + } else if (!strcasecmp(arg, "arm-usb-ocd")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_OCD_PID; + ft2232_interface = INTERFACE_A; + } else if (!strcasecmp(arg, "arm-usb-tiny")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_TINY_PID; + ft2232_interface = INTERFACE_A; + } else if (!strcasecmp(arg, "arm-usb-ocd-h")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_OCD_H_PID; + ft2232_interface = INTERFACE_A; + } else if (!strcasecmp(arg, "arm-usb-tiny-h")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_TINY_H_PID; + ft2232_interface = INTERFACE_A; } else { msg_perr("Error: Invalid device type specified.\n"); free(arg);

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Re: [flashrom] [PATCH 03/12] add macros and pretty printing for HSFS and HSFC
by Carl-Daniel Hailfinger 11 Jun '11

11 Jun '11

Am 08.06.2011 04:55 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++---------- > 1 files changed, 62 insertions(+), 12 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index 7e4a363..12727d1 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -43,6 +43,37 @@ > #include "spi.h" > > /* ICH9 controller register definition */ > +#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ > +#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ > +#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF) > +#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */ > +#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF) > +#define HSFS_AEL_OFF 2 /* 2: Access Error Log */ > +#define HSFS_AEL (0x1 << HSFS_AEL_OFF) > +#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */ > +#define HSFS_BERASE (0x1 << HSFS_BERASE_OFF) > Code change! Please explain/fix. > +#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ > +#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF) > + /* 6-12: reserved */ > +#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */ > +#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF) > +#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */ > +#define HSFS_FDV (0x1 << HSFS_FDV_OFF) > +#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */ > +#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF) > + > +#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */ > +#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */ > +#define HSFC_FGO (0x1 << HSFC_FGO_OFF) > +#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ > +#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) > + /* 3-7: reserved */ > +#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ > +#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) > + /* 14: reserved */ > +#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */ > +#define HSFC_SME (0x1 << HSFC_SME_OFF) > + > #define ICH9_REG_FADDR 0x08 /* 32 Bits */ > #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ > > @@ -260,6 +291,28 @@ static void pretty_print_opcodes(OPCODES *ops) > } > > #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) > +static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) > +{ > + msg_pdbg("HSFS: "); > + pprint_reg(HSFS, FDONE, reg_val, ", "); > + pprint_reg(HSFS, FCERR, reg_val, ", "); > + pprint_reg(HSFS, AEL, reg_val, ", "); > + pprint_reg(HSFS, BERASE, reg_val, ", "); > + pprint_reg(HSFS, SCIP, reg_val, ", "); > + pprint_reg(HSFS, FDOPSS, reg_val, ", "); > + pprint_reg(HSFS, FDV, reg_val, ", "); > + pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); > +} > + > +static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) > +{ > + msg_pdbg("HSFC: "); > + pprint_reg(HSFC, FGO, reg_val, ", "); > + pprint_reg(HSFC, FCYCLE, reg_val, ", "); > + pprint_reg(HSFC, FDBC, reg_val, ", "); > + pprint_reg(HSFC, SME, reg_val, "\n"); > +} > + > static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) > { > msg_pdbg("SSFS: "); > @@ -1204,14 +1257,15 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > case SPI_CONTROLLER_ICH9: > tmp2 = mmio_readw(ich_spibar + 4); > msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); > - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); > - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); > - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); > - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); > - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); > - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); > - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); > - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); > + prettyprint_ich9_reg_hsfs(tmp2); > + if (tmp2 & (1 << 15)) { > + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > + ichspi_lock = 1; > + } > + > + tmp2 = mmio_readw(ich_spibar + 6); > + msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); > + prettyprint_ich9_reg_hsfc(tmp2); > > tmp = mmio_readl(ich_spibar + 0x50); > msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); > @@ -1258,10 +1312,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > ichspi_bbar); > msg_pdbg("0xB0: 0x%08x (FDOC)\n", > mmio_readl(ich_spibar + 0xB0)); > - if (tmp2 & (1 << 15)) { > - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > - ichspi_lock = 1; > - } > Was it intentional to move that code a few lines up? > ich_init_opcodes(); > break; > default: > With an explanation/fix for the HSFS_BERASE code change this is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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