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[PATCH 4/8] ichspi.c: preserve reserved bits in address registers
by Stefan Tauner 28 Jun '11

28 Jun '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 13 ++++++++----- 1 files changed, 8 insertions(+), 5 deletions(-) diff --git a/ichspi.c b/ichspi.c index f35ea37..19e52d2 100644 --- a/ichspi.c +++ b/ichspi.c @@ -659,10 +659,11 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, return 1; } - /* Programm Offset in Flash into FADDR */ - REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ + /* Program offset in flash into SPIA while preserving reserved bits. */ + temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF; + REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); - /* Program data into FDATA0 to N */ + /* Program data into SPID0 to N */ if (write_cmd && (datalength != 0)) { temp32 = 0; for (a = 0; a < datalength; a++) { @@ -803,8 +804,10 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, return 1; } - /* Programm Offset in Flash into FADDR */ - REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ + /* Program offset in flash into FADDR while preserve the reserved bits + * and clearing the 25. address bit which is only useable in hwseq. */ + temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ if (write_cmd && (datalength != 0)) { -- 1.7.1

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[PATCH 3/8] ichspi.c: add FPB (Flash Partition Boundary) macros and init printing
by Stefan Tauner 28 Jun '11

28 Jun '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index 7e777f1..f35ea37 100644 --- a/ichspi.c +++ b/ichspi.c @@ -131,6 +131,10 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ +#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ +#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) + // ICH9R SPI commands #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 @@ -1324,6 +1328,9 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + ich_init_opcodes(); break; default: -- 1.7.1

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[PATCH 2/8] ichspi.c: simplify ich_set_bbar
by Stefan Tauner 28 Jun '11

28 Jun '11

less code, documenting better what the differences are (i.e. offset of BBAR only). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 48 +++++++++++++++++++++--------------------------- 1 files changed, 21 insertions(+), 27 deletions(-) diff --git a/ichspi.c b/ichspi.c index a78034a..7e777f1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -555,43 +555,37 @@ static int program_opcodes(OPCODES *op, int enable_undo) * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -void ich_set_bbar(uint32_t minaddr) +static void ich_set_bbar(uint32_t min_addr) { - minaddr &= BBAR_MASK; + int bbar_off; switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: - ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; - if (ichspi_bbar) - msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", - ichspi_bbar); - ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + 0x50); - ichspi_bbar = mmio_readl(ich_spibar + 0x50); - /* We don't have any option except complaining. And if the write - * failed, the restore will fail as well, so no problem there. - */ - if (ichspi_bbar != minaddr) - msg_perr("Setting BBAR failed!\n"); + bbar_off = 0x50; break; case SPI_CONTROLLER_ICH9: - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR) & ~BBAR_MASK; - if (ichspi_bbar) - msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", - ichspi_bbar); - ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + ICH9_REG_BBAR); - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - /* We don't have any option except complaining. And if the write - * failed, the restore will fail as well, so no problem there. - */ - if (ichspi_bbar != minaddr) - msg_perr("Setting BBAR failed!\n"); + bbar_off = ICH9_REG_BBAR; break; default: msg_perr("Unknown chipset for BBAR setting!\n"); - break; + return; + } + + ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK; + if (ichspi_bbar) { + msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n", + ichspi_bbar); } + min_addr &= BBAR_MASK; + ichspi_bbar |= min_addr; + rmmio_writel(ichspi_bbar, ich_spibar + bbar_off); + ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK; + + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ + if (ichspi_bbar != min_addr) + msg_perr("Setting BBAR failed!\n"); } /* This function generates OPCODES from or programs OPCODES to ICH according to -- 1.7.1

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[PATCH 1/8] ichspi.c: make REGWRITE* macros safer
by Stefan Tauner 28 Jun '11

28 Jun '11

'+' does have a quite high precedence so "calling" those macros with a term including weaker operators in the off parameter may have unexpected consequences Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ichspi.c b/ichspi.c index b4eb236..a78034a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -216,9 +216,9 @@ static uint16_t REGREAD8(int X) return mmio_readb(ich_spibar + X); } -#define REGWRITE32(off,val) mmio_writel(val, ich_spibar+off) -#define REGWRITE16(off,val) mmio_writew(val, ich_spibar+off) -#define REGWRITE8(off,val) mmio_writeb(val, ich_spibar+off) +#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off)) +#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off)) +#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off)) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); -- 1.7.1

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[PATCH 0/8] ichspi 6.0
by Stefan Tauner 28 Jun '11

28 Jun '11

hwseq does use all data registers now with the help of new refactored read/write functions which are also used for swseq in all versions. main problem remains descriptor decoding (not new changes in this set). dhendrix: i was pretty tired so i fear that the quality of the previous one could be maintained, beware ;) Stefan Tauner (8): ichspi.c: make REGWRITE* macros safer ichspi.c: simplify ich_set_bbar ichspi.c: add FPB (Flash Partition Boundary) macros and init printing ichspi.c: preserve reserved bits in address registers ichspi.c: refactor filling and reading the fdata/spid registers add ICH/PCH flash descriptor decoding ichspi:c add support for Intel Hardware Sequencing squash! ichspi:c add support for Intel Hardware Sequencing Makefile | 3 +- chipdrivers.h | 6 + flashchips.c | 23 +- flashchips.h | 2 + ich_descriptors.c | 490 +++++++++++++++++++ ich_descriptors.h | 447 +++++++++++++++++ ichspi.c | 552 +++++++++++++++++----- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 226 +++++++++ 11 files changed, 1685 insertions(+), 112 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

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[Patch] NVIDIA Tegra2 SPI controller support
by David Hendricks 28 Jun '11

28 Jun '11

This patch set makes Flashrom a bit more ARM-friendly and adds raw Tegra2 SPI controller support. It isolates a few PCI-isms, adds some low-level hardware access stubs, adds Tegra2 processor detection, and adds Tegra2 raw SPI controller code. I've attached some logfiles for read/erase/write operations. This particular patch set was tested using a board based off NVIDIA's Tegra2 reference board ("Seaboard"). Earlier revisions were tested on a Seaboard. All three attached patches are: Signed-off-by: David Hendricks <dhendrix(a)google.com> Much of the original U-Boot --> Flashrom porting work was done by Stefan Reinauer <reinauer(a)google.com>, and the FIFO code updated / fixed up by Louis Lo <yjlou(a)google.com>. A few notes: 1. A few programmers must be disabled due to reliance on PCI. You can hack up your Makefile or compile with "CONFIG_RAYER_SPI=no CONFIG_NIC3COM=no CONFIG_NICREALTEK=no CONFIG_SATAMV=no". 2. Due to issues with libpci, you can't use the same binary on machines with PCI and without PCI. So for example, you can't program a SPI ROM onboard a PCI card that is connected to your ARM SoC. 3. For those who wish to try this code on Seaboard, please be aware that the UART is disabled during operation and then re-enabled afterward. This is because the MISO/MOSI are muxed with the UART (See comments in tegra2_spi.c). You will not see any Flashrom output on your serial console. 4. The tegra2_spi code was originally contributed by NVIDIA to the Chromium OS U-Boot<http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=blob;…> branch and was later grafted into Flashrom so we could more easily perform SPI ROM updates from userspace. Please excuse minor style inconsistencies as we are trying to stay reasonably close to the code checked into the U-Boot tree ;-) -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Re: [flashrom] [PATCH] Macronix MX25L6445E
by Stefan Tauner 27 Jun '11

27 Jun '11

On Mon, 30 May 2011 14:08:09 +0200 "Wagner, Helge (GE Intelligent Platforms)" <Helge.Wagner(a)ge.com> wrote: > Hi, > > i have tried to reprogram a Macronix MX25L6445E flash chip. This worked, but gave me an error message: > > ERASE FAILED at 0x0001107f! Expected=0xff, Read=0x00, failed byte count from 0x00010000-0x0001ffff: 0x9c15 > ERASE FAILED! > > Looking deeper into the datasheet, i saw that the MX25L6445E has the same ID as the MX25L6405, but with (at least) one difference: > The MX25L6405 has a block size of 64KByte for erase function 20h, while the MX25L6445E is using 4KByte sector size for the same erase function 20h. As a result the spi_block_erase_20() will fail for the MX25L6445E (while the spi_block_erase_d8() which is used then will succeed). > > I have now re-ordered the erase functions for the MX25L6405/MX25L6445E: > spi_block_erase_d8 - first > spi_block_erase_60 - second > spi_block_erase_c7 - third > spi_block_erase_20 - last > So if one of the d8/60/c7 erase functions are successfull, the spi_block_erase_20 will never be called. > > To be sure that the spi_block_erase_20 works for both the MX25L6405 and the MX25L6445E, we could change the block erase size from 64K to 4K. This should work even for the MX25L6405, but with the side effect of the erase taking longer than needed. > > Any comments? > > Please find my patches included. > Signed-off-by: Helge Wagner <Helge.Wagner(a)ge.com> hello helge thanks for your patch! i have not looked at the datasheet(s), but maybe there is a way to distinguish the two devices (with another id command for example)? if we change the order of eraser functions as your patch suggests we should comment the reason precisely in the code. else we may introduce the previous behavior sometime later e.g. when we refine partial writes. i personally don't see a problem apart from that, but i am not sure if it is safe either and wont break pending patches. so others have to ack it. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] don't print dmidecode shell error
by Stefan Reinauer 27 Jun '11

27 Jun '11

See patch

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flashrom -V output
by DeLa 27 Jun '11

27 Jun '11

flashrom v0.9.3-r1357 on Linux 2.6.38-8-generic (i686), built with libpci 3.1.7, GCC 4.5.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 3 usecs, 1352M loops per second, 10 myus = 11 us, 100 myus = 102 us, 1000 myus = 998 us, 10000 myus = 10012 us, 12 myus = 13 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "To Be Filled By O.E.M." DMI string system-product-name: "To Be Filled By O.E.M." DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: " " DMI string baseboard-product-name: "ALiveNF6G-GLAN" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP61", enabling flash write... chipset PCI ID is 10de:03e0, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0x00000000 MCP SPI is not used. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found chip "Winbond W39V040C" (512 kB, LPC) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified. Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88

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[PATCH 2/2] add printing of chip voltage ranges to print_wiki.c
by Stefan Tauner 27 Jun '11

27 Jun '11

- add voltage ranges - center some headers (test values OK, No, ? are centered via wiki templates) - fix style error in header (align:right -> text-align:right) Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- print_wiki.c | 46 ++++++++++++++++++++++++++++++++-------------- 1 files changed, 32 insertions(+), 14 deletions(-) diff --git a/print_wiki.c b/print_wiki.c index 6280aff..e1fe045 100644 --- a/print_wiki.c +++ b/print_wiki.c @@ -29,7 +29,8 @@ static const char wiki_header[] = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ -background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ +background-color:#eeeeee; text-align:right; border:1px solid #aabbcc;\">\ +<small>\n\ Please do '''not''' edit these tables in the wiki directly, they are \ generated by pasting '''flashrom -z''' output.<br />\ '''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; @@ -37,12 +38,13 @@ generated by pasting '''flashrom -z''' output.<br />\ #if CONFIG_INTERNAL == 1 static const char chipset_th[] = "{| border=\"0\" style=\"font-size: smaller\"\n\ |- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Southbridge\n! align=\"left\" | PCI IDs\n\ -! align=\"left\" | Status\n\n"; +! align=\"left\" | Southbridge\n! align=\"center\" | PCI IDs\n\ +! align=\"center\" | Status\n\n"; static const char board_th[] = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n! align=\"left\" | Status\n\n"; +! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n\ +! align=\"center\" | Status\n\n"; static const char board_intro[] = "\ \n== Supported mainboards ==\n\n\ @@ -57,20 +59,26 @@ not work (we don't know, someone has to give it a try). Please report any \ further verified mainboards on the [[Mailinglist|mailing list]].\n"; #endif -static const char chip_th[] = "{| border=\"0\" style=\"font-size: smaller\" \ -valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Device\n! align=\"left\" | Size / kB\n\ -! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ +static const char chip_th[] = "{\ +| border=\"0\" style=\"font-size: smaller\"valign=\"top\"\n\ +|- bgcolor=\"#6699dd\"\n\ +! align=\"left\" | Vendor\n\ +! align=\"left\" | Device\n\ +! align=\"center\" | Size [kB]\n\ +! align=\"center\" | Type\n\ +! align=\"center\" colspan=\"4\" | Status\n\ +! align=\"center\" colspan=\"2\" | Voltage [V]\n\n\ |- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ -| Probe\n| Read\n| Erase\n| Write\n\n"; +| Probe\n| Read\n| Erase\n| Write\n\ +| align=\"center\" | min \n| align=\"center\" | max\n\n"; static const char programmer_section[] = "\ \n== Supported programmers ==\n\nThis is a list \ of supported PCI devices flashrom can use as programmer:\n\n{| border=\"0\" \ valign=\"top\"\n| valign=\"top\"|\n\n{| border=\"0\" style=\"font-size: \ smaller\" valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Device\n! align=\"left\" | PCI IDs\n\ -! align=\"left\" | Status\n\n"; +! align=\"left\" | Device\n! align=\"center\" | PCI IDs\n\ +! align=\"center\" | Status\n\n"; #if CONFIG_INTERNAL == 1 static const char laptop_intro[] = "\n== Supported laptops/notebooks ==\n\n\ @@ -204,6 +212,9 @@ static void print_supported_chips_wiki(int cols) const struct flashchip *f, *old = NULL; uint32_t t; char *s; + char vmax[6]; + char vmin[6]; + const char *na = "N/A"; for (f = flashchips; f->name != NULL; f++) chipcount++; @@ -223,8 +234,13 @@ static void print_supported_chips_wiki(int cols) t = f->tested; s = flashbuses_to_text(f->bustype); - printf("|- bgcolor=\"#%s\"\n| %s || %s || %d " - "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}\n", + sprintf(vmin, "%0.03f", f->voltage.min/(double)1000); + sprintf(vmax, "%0.03f", f->voltage.max/(double)1000); + /* '{{%s}}' is used in combination with 'OK', 'No' and '?3' to + * select special formatting templates for the bg color. */ + printf("|- bgcolor=\"#%s\"\n| %s || %s || align=\"right\" | %d " + "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}" + "|| %s || %s \n", (c == 1) ? "eeeeee" : "dddddd", f->vendor, f->name, f->total_size, s, (t & TEST_OK_PROBE) ? "OK" : @@ -234,7 +250,9 @@ static void print_supported_chips_wiki(int cols) (t & TEST_OK_ERASE) ? "OK" : (t & TEST_BAD_ERASE) ? "No" : "?3", (t & TEST_OK_WRITE) ? "OK" : - (t & TEST_BAD_WRITE) ? "No" : "?3"); + (t & TEST_BAD_WRITE) ? "No" : "?3", + f->voltage.min ? vmin : na, + f->voltage.min ? vmax : na); free(s); /* Split table into 'cols' columns. */ -- 1.7.1

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