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[PATCH 3/4] add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file
by Stefan Tauner 15 Jul '11

15 Jul '11

additionally to what is available via FDOC/FDOD...<TODO> TODO: - fix msg_perr - decode all ibex straps Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ich_descriptors.c | 186 ++++++++++++++++++++ ich_descriptors.h | 200 ++++++++++++++++++++++ util/ich_descriptors_tool/Makefile | 42 +++++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 197 +++++++++++++++++++++ 5 files changed, 630 insertions(+), 0 deletions(-) create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/ich_descriptors.c b/ich_descriptors.c index 43b2c52..0281488 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -22,8 +22,21 @@ #if defined(__i386__) || defined(__x86_64__) #include "ich_descriptors.h" + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +#define DESCRIPTOR_MODE_MAGIC 0x0ff0a55a +#define msg_pdbg printf +#define msg_pspew printf +#define msg_perr printf +#include <stdio.h> + +#else + #include "flash.h" /* for msg_* */ +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + uint32_t getFCBA(const struct flash_content *cont) { return (cont->FLMAP0 << 4) & 0x00000ff0; @@ -59,12 +72,26 @@ uint32_t getFISBA(const struct flash_content *cont) return (cont->FLMAP1 >> 12) & 0x00000ff0; } +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +uint32_t getVTBA(const struct flash_upper_map *flumap) +{ /* The bits in FLUMAP1 describe bits 4-11 out of 24 in total; + * others are 0. */ + return (flumap->FLUMAP1 << 4) & 0x0ff0; +} +#endif + void prettyprint_ich_descriptors(enum chipset cs, const struct flash_descriptors *desc) { prettyprint_ich_descriptor_content(&desc->content); prettyprint_ich_descriptor_component(desc); prettyprint_ich_descriptor_region(&desc->region); prettyprint_ich_descriptor_master(&desc->master); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + if (cs >= CHIPSET_ICH8) { + prettyprint_ich_descriptor_upper_map(&desc->upper); + prettyprint_ich_descriptor_straps(cs, &desc->straps); + } +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP } void prettyprint_ich_descriptor_content(const struct flash_content *cont) @@ -208,6 +235,164 @@ void prettyprint_ich9_reg_vscc(uint32_t reg_val) pprint_reg(VSCC, VCL, reg_val, "\n"); } +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +void prettyprint_ich_descriptor_straps_ich8(const struct flash_strap *straps) +{ + const char * const str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + "GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + msg_pdbg1("=== FISBA ===\n"); + msg_pdbg1("STRP0 0x%8.8x\n", straps->ich8.STRPs[0]); + msg_pdbg1("\n"); + + msg_pdbg2("--- FISBA details ---\n"); + msg_pdbg2("ME SMBus addr2 0x%2.2x\n", straps->ich8.ASD2); + msg_pdbg2("ME SMBus addr1 0x%2.2x\n", straps->ich8.ASD); + msg_pdbg2("ME SMBus Controller is connected to %s\n", straps->ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg2("SPI CS1 is used for %s\n", straps->ich8.SPICS1_LANPHYPC_SEL ? "LAN PHY Power Control Function" : "SPI Chip Select"); + msg_pdbg2("GPIO12_SEL is used as %s\n", str_GPIO12[straps->ich8.GPIO12_SEL]); + msg_pdbg2("PCIe Port 6 is used for %s\n", straps->ich8.GLAN_PCIE_SEL ? "integrated GLAN" : "PCI Express"); + msg_pdbg2("Intel AMT SMBus Controller 1 is connected to %s\n", straps->ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg2("TCO slave is on %s. Intel AMT SMBus Controller 1 is %sabled\n", + straps->ich8.TCOMODE ? "SMBus" : "SMLink", straps->ich8.TCOMODE ? "en" : "dis"); + msg_pdbg2("ME A is %sabled\n", straps->ich8.ME_DISABLE ? "dis" : "en"); + + msg_pdbg2("\n"); + msg_pdbg2("=== FMSBA ===\n"); + msg_pdbg2("STRP1 0x%8.8x\n", straps->ich8.STRPs[1]); + + msg_pdbg2("\n"); + msg_pdbg2("--- FMSBA details ---\n"); + msg_pdbg2("ME B is %sabled\n", straps->ich8.ME_disable_B ? "dis" : "en"); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps_ibex(const struct flash_strap *straps) +{ + int i; + msg_pdbg2("=== FPSBA ===\n"); + /* TODO: decode properly */ + for(i = 0; i <= 15; i++) + msg_pdbg2("STRP%-2d = 0x%8.8x\n", i, straps->ibex.STRPs[i]); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps(enum chipset cs, const struct flash_strap *straps) +{ + switch (cs) { + case CHIPSET_ICH8: + prettyprint_ich_descriptor_straps_ich8(straps); + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + /* PCH straps only. PROCSTRPs are unknown. */ + prettyprint_ich_descriptor_straps_ibex(straps); + break; + case CHIPSET_UNKNOWN: + break; + default: + msg_pdbg2("The meaning of the descriptor straps are unknown yet.\n"); + msg_pdbg2("\n"); + break; + } +} + +void prettyprint_rdid(uint32_t reg_val) +{ + uint8_t mid = reg_val & 0xFF; + uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00); + msg_pdbg2("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did); +} + +void prettyprint_ich_descriptor_upper_map(const struct flash_upper_map *umap) +{ + int i; + msg_pdbg1("=== FLUMAP ===\n"); + msg_pdbg1("FLUMAP1 0x%8.8x\n", umap->FLUMAP1); + msg_pdbg1("\n"); + + msg_pdbg2("--- FLUMAP details ---\n"); + msg_pdbg2("VTL (length) = %d\n", umap->VTL); + msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap)); + msg_pdbg2("\n"); + + msg_pdbg2("VSCC Table:\n"); + for (i=0; i < umap->VTL/2; i++) + { + uint32_t jid = umap->vscc_table[i].JID; + uint32_t vscc = umap->vscc_table[i].VSCC; + msg_pdbg2(" JID%d = 0x%8.8x\n", i, jid); + msg_pdbg2(" VSCC%d = 0x%8.8x\n", i, vscc); + msg_pdbg2(" "); /* indention */ + prettyprint_rdid(jid); + msg_pdbg2(" "); /* indention */ + prettyprint_ich9_reg_vscc(vscc); + } + msg_pdbg2("\n"); +} + +int read_ich_descriptors_from_dump(const uint32_t *dump, enum chipset cs, struct flash_descriptors *desc) +{ + int i; + uint8_t pch_bug_offset = 0; + if (dump[0] != DESCRIPTOR_MODE_MAGIC) { + if (dump[4] == DESCRIPTOR_MODE_MAGIC) + pch_bug_offset = 4; + else + return -1; + } + + /* map */ + desc->content.FLVALSIG = dump[0 + pch_bug_offset]; + desc->content.FLMAP0 = dump[1 + pch_bug_offset]; + desc->content.FLMAP1 = dump[2 + pch_bug_offset]; + desc->content.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0]; + desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1]; + desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2]; + + /* region */ + desc->region.FLREG0 = dump[(getFRBA(&desc->content) >> 2) + 0]; + desc->region.FLREG1 = dump[(getFRBA(&desc->content) >> 2) + 1]; + desc->region.FLREG2 = dump[(getFRBA(&desc->content) >> 2) + 2]; + desc->region.FLREG3 = dump[(getFRBA(&desc->content) >> 2) + 3]; + + /* master */ + desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0]; + desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1]; + desc->master.FLMSTR3 = dump[(getFMBA(&desc->content) >> 2) + 2]; + + /* upper map */ + desc->upper.FLUMAP1 = dump[(0x0efc >> 2) + 0]; + + for (i=0; i < desc->upper.VTL; i++) + { + desc->upper.vscc_table[i].JID = dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 0]; + desc->upper.vscc_table[i].VSCC = dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 1]; + } + /* straps */ + switch (cs) { + case CHIPSET_ICH8: + desc->straps.ich8.STRPs[0] = dump[(getFISBA(&desc->content) >> 2) + 0]; + desc->straps.ich8.STRPs[1] = dump[(getFMSBA(&desc->content) >> 2) + 0]; + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + for(i = 0; i <= 15; i++) + desc->straps.ibex.STRPs[i] = dump[(getFISBA(&desc->content) >> 2) + i]; + break; + default: + break; + } + + return 0; +} +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; @@ -247,4 +432,5 @@ void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc) msg_pdbg1(" done\n"); } +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP #endif // defined(__i386__) || defined(__x86_64__) diff --git a/ich_descriptors.h b/ich_descriptors.h index 9954149..1129805 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -238,11 +238,202 @@ struct flash_master { }; }; +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +struct flash_strap { + union { + union { + uint32_t STRPs[2]; + struct { + struct { + uint32_t ME_DISABLE :1; + uint32_t :6; + uint32_t TCOMODE :1; + uint32_t ASD :7; + uint32_t BMCMODE :1; + uint32_t :3; + uint32_t GLAN_PCIE_SEL :1; + uint32_t GPIO12_SEL :2; + uint32_t SPICS1_LANPHYPC_SEL :1; + uint32_t MESM2SEL :1; + uint32_t :1; + uint32_t ASD2 :7; + }; + struct { + uint32_t ME_disable_B :1; + uint32_t :31; + }; + }; + }ich8; + union { + uint32_t STRPs[15]; + struct { + struct { + uint32_t :1; + uint32_t cs_ss2 :1; + uint32_t :5; + uint32_t SMB_EN :1; + uint32_t SML0_EN :1; + uint32_t SML1_EN :1; + uint32_t SML1FRQ :2; + uint32_t SMB0FRQ :2; + uint32_t SML0FRQ :2; + uint32_t :4; + uint32_t LANPHYPC_GP12_SEL :1; + uint32_t cs_ss1 :1; + uint32_t :2; + uint32_t DMI_REQID_DIS :1; + uint32_t :4; + uint32_t BBBS :2; + uint32_t :1; + }; + struct { + uint32_t cs_ss3 :4; + uint32_t :28; + }; + struct { + uint32_t :8; + uint32_t MESMASDEN :1; + uint32_t MESMASDA :7; + uint32_t :8; + uint32_t MESMI2CEN :1; + uint32_t MESMI2CA :7; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t PHYCON :2; + uint32_t :6; + uint32_t GBEMAC_SMBUS_ADDR_EN :1; + uint32_t GBEMAC_SMBUS_ADDR :7; + uint32_t :1; + uint32_t GBEPHY_SMBUS_ADDR :7; + uint32_t :8; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t MESMA2UDID_DEVICE :16; + uint32_t MESMA2UDID_VENDOR :16; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t PCIEPCS1 :2; + uint32_t PCIEPCS2 :2; + uint32_t PCIELR1 :1; + uint32_t PCIELR2 :1; + uint32_t DMILR :1; + uint32_t :1; + uint32_t PHY_PCIEPORTSEL :3; + uint32_t PHY_PCIE_EN :1; + uint32_t :20; + }; + struct { + uint32_t :1; + uint32_t ME_BOOT_FLASH :1; + uint32_t cs_ss5 :1; + uint32_t VE_EN :1; + uint32_t :4; + uint32_t MMDDE :1; + uint32_t MMADDR :7; + uint32_t cs_ss7 :1; + uint32_t :1; + uint32_t ICC_SEL :3; + uint32_t MER_CL1 :1; + uint32_t :10; + }; + struct { + uint32_t SML1GPAEN :1; + uint32_t SML1GPA :7; + uint32_t :10; + uint32_t SML1I2CAEN :1; + uint32_t SML1I2CA :7; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t :8; + uint32_t VE_EN2 :1; + uint32_t :5; + uint32_t VE_BOOT_FLASH :1; + uint32_t :1; + uint32_t BW_SSD :1; + uint32_t NVMHCI_EN :1; + uint32_t :14; + }; + struct { + uint32_t :3; + uint32_t cs_ss6 :2; + uint32_t :1; + uint32_t IWL_EN :1; + uint32_t :1; + uint32_t t209min :2; + uint32_t :22; + }; + }; + }ibex; + }; +}; + +struct flash_upper_map { + union { + uint32_t FLUMAP1; + struct { + uint32_t VTBA :8; + uint32_t VTL :8; + uint32_t :16; + }; + }; + struct { + union { + uint32_t JID; + struct { + uint8_t vid :8; + uint8_t cid0 :8; + uint8_t cid1 :8; + uint32_t :8; + }; + }; + union { + uint32_t VSCC; + struct { + uint32_t ubes :2; + uint32_t uwg :1; + uint32_t uwsr :1; + uint32_t uwews :1; + uint32_t :3; + uint32_t ueo :8; + uint32_t lbes :2; + uint32_t lwg :1; + uint32_t lwsr :1; + uint32_t lwews :1; + uint32_t :3; + uint32_t leo :16; + }; + }; + }vscc_table[128]; +}; +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + struct flash_descriptors { struct flash_content content; struct flash_component component; struct flash_region region; struct flash_master master; +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + struct flash_strap straps; + struct flash_upper_map upper; +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP }; void prettyprint_ich_descriptors(enum chipset, const struct flash_descriptors *desc); @@ -252,7 +443,16 @@ void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc); void prettyprint_ich_descriptor_region(const struct flash_region *region); void prettyprint_ich_descriptor_master(const struct flash_master *master); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void prettyprint_ich_descriptor_upper_map(const struct flash_upper_map *umap); +void prettyprint_ich_descriptor_straps(enum chipset cs, const struct flash_strap *straps); +int read_ich_descriptors_from_dump(const uint32_t *dump, enum chipset cs, struct flash_descriptors *desc); + +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP #endif // __ICH_DESCRIPTORS_H__ #endif // defined(__i386__) || defined(__x86_64__) diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..1d7f056 --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,42 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS=-Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain binary dumps +CFLAGS += -D ICH_DESCRIPTORS_FROM_MMAP_DUMP +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to share source files without simultaneously sharing .o files +# with flashrom, which would lead to unexpected results (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..e3933ee --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,5 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly \ No newline at end of file diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..f6fd77a --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,197 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (C) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * dump information and binaries from BIOS images that are in descriptor mode + */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "ich_descriptors.h" + +static void dump_file(const char *filename, const char *suf, uint32_t offset, uint32_t length, const uint32_t *dump) +{ + int ret; + char *n = malloc(strlen(filename) + strlen(suf) + 1); + + if (!n) { + fprintf(stderr, "Out of memory!\n"); + exit(1); + } + snprintf(n, strlen(filename) + strlen(suf) + 1, "%s%s", filename, suf); + printf("\n"); + printf("+++ dumping %s... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) { + fprintf(stderr, + "ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + ret = write(fh, &dump[offset >> 2], length); + if (ret != length) { + fprintf(stderr, "FAILED.\n"); + exit(1); + } + + printf("done.\n"); + close(fh); +} + +void dump_files(const char *n, const uint32_t *fm, struct flash_region *freg) +{ + printf("=== dumping section files ===\n"); + if (freg->reg0_limit) + dump_file(n, ".descr.bin", freg->reg0_base, freg->reg0_limit, fm); + if (freg->reg1_limit) + dump_file(n, ".BIOS.bin", freg->reg1_base, freg->reg1_limit, fm); + if (freg->reg2_limit) + dump_file(n, ".ME.bin", freg->reg2_base, freg->reg2_limit, fm); + if (freg->reg3_limit) { + uint8_t *pMAC = (uint8_t *) &fm[freg->reg3_base >> 2]; + dump_file(n, ".GbE.bin", freg->reg2_base, freg->reg2_limit, fm); + printf("the MAC-address might be: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + pMAC[0], + pMAC[1], + pMAC[2], + pMAC[3], + pMAC[4], + pMAC[5] + ); + } +} + +static void usage(char *argv[], char *error) +{ + if (error != NULL) { + fprintf(stderr, "%s\n", error); + } + printf("usage: '%s -f <image file name> [-c <chipset name>] [-d]'\n\n" +"where <image file name> points to an image of the contents of the SPI flash.\n" +"In case that image is really in descriptor mode %s\n" +"will pretty print some of the contained information.\n" +"To also print the data stored in the descriptor strap you have to indicate\n" +"the chipset series with the '-c' parameter and one of the possible arguments:\n" +"\t- \"ich8\",\n" +"\t- \"ich9\",\n" +"\t- \"ich10\",\n" +"\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" +"\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" +"\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"If '-d' is specified some sections such as the BIOS image as seen by the CPU or\n" +"the GbE blob that is required to initialize the GbE are also dumped to files.\n", + argv[0], argv[0]); + exit(1); +} + +int main(int argc, char *argv[]) +{ + int f; /* file descriptor to flash file */ + unsigned int fs; /* file size */ + uint32_t *fm; /* mmap'd file */ + + int opt; + int dump = 0; + const char *fn = NULL; + const char *csn = NULL; + enum chipset cs = CHIPSET_UNKNOWN; + struct flash_descriptors desc = {{ 0 }}; + + while ((opt = getopt(argc, argv, "df:c:")) != -1) { + switch (opt) { + case 'd': + dump = 1; + break; + case 'f': + fn = optarg; + break; + case 'c': + csn = optarg; + break; + default: /* '?' */ + usage(argv, NULL); + } + } + if (fn == NULL) + usage(argv, + "Need a file name of a descriptor image to read from."); + + f = open(fn, O_RDONLY); + if (f < 0) + usage(argv, "No such file"); + fs = lseek(f, 0, SEEK_END); + if (fs < 0) + usage(argv, "Seeking to the end of the file failed"); + + fm = mmap(NULL, fs, PROT_READ, MAP_PRIVATE, f, 0); + if (fm == (void *) -1) { + /* fallback for stupid OSes like cygwin */ + int ret; + fm = malloc(fs); + if (!fm) + usage(argv, "Could not allocate memory"); + lseek(f, 0, SEEK_SET); + ret = read(f, fm, fs); + if (ret != fs) + usage(argv, "Seeking to the end of the file failed"); + } + printf("flash image has a size of %d [0x%x] bytes.\n", fs, fs); + close(f); + + if (csn != NULL) { + if (strcmp(csn, "ich8") == 0) + cs = CHIPSET_ICH8; + else if (strcmp(csn, "ich9") == 0) + cs = CHIPSET_ICH9; + else if (strcmp(csn, "ich10") == 0) + cs = CHIPSET_ICH10; + else if ((strcmp(csn, "5") == 0) || + (strcmp(csn, "ibex") == 0)) + cs = CHIPSET_SERIES_5_IBEX_PEAK; + else if ((strcmp(csn, "6") == 0) || + (strcmp(csn, "cougar") == 0)) + cs = CHIPSET_SERIES_6_COUGAR_POINT; + else if ((strcmp(csn, "7") == 0) || + (strcmp(csn, "panther") == 0)) + cs = CHIPSET_SERIES_7_PANTHER_POINT; + } + + if(read_ich_descriptors_from_dump(fm, cs, &desc)){ + printf("not in descriptor mode\n"); + exit(1); + } + + prettyprint_ich_descriptors(cs, &desc); + + if (dump == 1) + dump_files(fn, fm, &desc.region); + + return 0; +} + -- 1.7.1

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[PATCH 2/4] add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Stefan Tauner 15 Jul '11

15 Jul '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptors that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content descriptor: describes the image and some generic properties (number of regions, offset of regions, PCH/ICH and MCH/PROC strap offsets and lengths) - component descriptor: identify the different SPI Flash Components and their capabilities. - region descriptor similarly to a partition table this describes the different regions - master descriptor defines access rights of the individual regions this is only a part of the data included in the descriptor. other information can be retreived from a complete binary dump of the descriptor image only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of flash chips supported by the ME are stored in the same format in a descriptor table. a later patch will uses them outside of ichspi.c which is also the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h. TODO: - is endianess important? and other questions related to the struct/union pattern used. - file naming and partitioning was not discussed. we may want a ichspi.h. and/or rename ichspi.c to ich_spi.c or similar... - checking derived offsets for OOB errors Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 3 +- ich_descriptors.c | 250 +++++++++++++++++++++++++++++++++++++++++++++++++++ ich_descriptors.h | 258 +++++++++++++++++++++++++++++++++++++++++++++++++++++ ichspi.c | 31 ++++++- 4 files changed, 539 insertions(+), 3 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h diff --git a/Makefile b/Makefile index a35df06..7f73452 100644 --- a/Makefile +++ b/Makefile @@ -308,7 +308,8 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o ifeq ($(ARCH),"x86") -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif NEED_PCI := yes diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..43b2c52 --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,250 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include "ich_descriptors.h" +#include "flash.h" /* for msg_* */ + +uint32_t getFCBA(const struct flash_content *cont) +{ + return (cont->FLMAP0 << 4) & 0x00000ff0; +} + +uint32_t getFRBA(const struct flash_content *cont) +{ + return (cont->FLMAP0 >> 12) & 0x00000ff0; +} + +uint32_t getFMBA(const struct flash_content *cont) +{ + return (cont->FLMAP1 << 4) & 0x00000ff0; +} + +uint32_t getFMSBA(const struct flash_content *cont) +{ + return (cont->FLMAP2 << 4) & 0x00000ff0; +} + +uint32_t getFLREG_limit(uint32_t flreg) +{ + return (flreg >> 4) & 0x01fff000; +} + +uint32_t getFLREG_base(uint32_t flreg) +{ + return (flreg << 12) & 0x01fff000; +} + +uint32_t getFISBA(const struct flash_content *cont) +{ + return (cont->FLMAP1 >> 12) & 0x00000ff0; +} + +void prettyprint_ich_descriptors(enum chipset cs, const struct flash_descriptors *desc) +{ + prettyprint_ich_descriptor_content(&desc->content); + prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_region(&desc->region); + prettyprint_ich_descriptor_master(&desc->master); +} + +void prettyprint_ich_descriptor_content(const struct flash_content *cont) +{ + msg_pdbg1("=== Content Section ===\n"); + msg_pdbg1("FLVALSIG 0x%8.8x\n", cont->FLVALSIG); + msg_pdbg1("FLMAP0 0x%8.8x\n", cont->FLMAP0 ); + msg_pdbg1("FLMAP1 0x%8.8x\n", cont->FLMAP1 ); + msg_pdbg1("FLMAP2 0x%8.8x\n", cont->FLMAP2 ); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("0x%02x NR Number of Regions (%d)\n", cont->NR, cont->NR + 1); + msg_pdbg2("0x%06x FRBA Flash Region Base Address\n", getFRBA(cont)); + msg_pdbg2("0x%02x NC Number of Components (%d)\n", cont->NC, cont->NC + 1); + msg_pdbg2("0x%06x FCBA Flash Component Base Address\n", getFCBA(cont)); + msg_pdbg2("\n"); + msg_pdbg2("0x%02x ISL ICH Strap Length (%d)\n", cont->ISL, cont->ISL); + msg_pdbg2("0x%06x FISBA Flash ICH Strap Base Address\n", getFISBA(cont)); + msg_pdbg2("0x%02x NM Number of Masters (%d)\n", cont->NM, cont->NM + 1); + msg_pdbg2("0x%06x FMBA Flash Master Base Address\n", getFMBA(cont)); + msg_pdbg2("\n"); + msg_pdbg2("0x%02x MSL MCH Strap Length (%d)\n", cont->MSL, cont->MSL); + msg_pdbg2("0x%06x FMSBA Flash MCH Strap Base Address\n", getFMSBA(cont)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc) +{ + const char * const str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved", /* 010 */ + "reserved", /* 011 */ + "50 MHz", /* 100 */ + "reserved", /* 101 */ + "reserved", /* 110 */ + "reserved" /* 111 */ + }; + const char * const str_mem[8] = { + "512kB", + "1 MB", + "2 MB", + "4 MB", + "8 MB", + "16 MB", + "reserved", + "reserved" + }; + + msg_pdbg1("=== Component Section ===\n"); + msg_pdbg1("FLCOMP 0x%8.8x\n", desc->component.FLCOMP); + msg_pdbg1("FLILL 0x%8.8x\n", desc->component.FLILL ); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("0x%2.2x freq_read_id %s\n", + desc->component.freq_read_id , str_freq[desc->component.freq_read_id ]); + msg_pdbg2("0x%2.2x freq_write %s\n", + desc->component.freq_write , str_freq[desc->component.freq_write ]); + msg_pdbg2("0x%2.2x freq_fastread %s\n", + desc->component.freq_fastread, str_freq[desc->component.freq_fastread]); + msg_pdbg2("0x%2.2x fastread %ssupported\n", + desc->component.fastread, desc->component.fastread ? "" : "not "); + msg_pdbg2("0x%2.2x freq_read %s\n", + desc->component.freq_read, str_freq[desc->component.freq_read ]); + msg_pdbg2("0x%2.2x comp 1 density %s\n", + desc->component.comp1_density, str_mem[desc->component.comp1_density]); + if (desc->content.NC) + msg_pdbg2("0x%2.2x comp 2 density %s\n", + desc->component.comp2_density, str_mem[desc->component.comp2_density]); + else + msg_pdbg2("0x%2.2x comp 2 is not used (FLMAP0.NC=0)\n", + desc->component.comp2_density); + msg_pdbg2("\n"); + msg_pdbg2("0x%2.2x invalid instr 0\n", desc->component.invalid_instr0); + msg_pdbg2("0x%2.2x invalid instr 1\n", desc->component.invalid_instr1); + msg_pdbg2("0x%2.2x invalid instr 2\n", desc->component.invalid_instr2); + msg_pdbg2("0x%2.2x invalid instr 3\n", desc->component.invalid_instr3); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_region(const struct flash_region *reg) +{ + msg_pdbg1("=== Region Section ===\n"); + msg_pdbg1("FLREG0 0x%8.8x\n", reg->FLREG0); + msg_pdbg1("FLREG1 0x%8.8x\n", reg->FLREG1); + msg_pdbg1("FLREG2 0x%8.8x\n", reg->FLREG2); + msg_pdbg1("FLREG3 0x%8.8x\n", reg->FLREG3); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("0x%8.8x region 0 limit (descr)\n", getFLREG_limit(reg->FLREG0)); + msg_pdbg2("0x%8.8x region 0 base (descr)\n", getFLREG_base(reg->FLREG0)); + msg_pdbg2("0x%8.8x region 1 limit ( BIOS)\n", getFLREG_limit(reg->FLREG1)); + msg_pdbg2("0x%8.8x region 1 base ( BIOS)\n", getFLREG_base(reg->FLREG1)); + msg_pdbg2("0x%8.8x region 2 limit ( ME )\n", getFLREG_limit(reg->FLREG2)); + msg_pdbg2("0x%8.8x region 2 base ( ME )\n", getFLREG_base(reg->FLREG2)); + msg_pdbg2("0x%8.8x region 3 limit ( GbE )\n", getFLREG_limit(reg->FLREG3)); + msg_pdbg2("0x%8.8x region 3 base ( GbE )\n", getFLREG_base(reg->FLREG3)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_master(const struct flash_master *mstr) +{ + msg_pdbg1("=== Master Section ===\n"); + msg_pdbg1("FLMSTR1 0x%8.8x\n", mstr->FLMSTR1); + msg_pdbg1("FLMSTR2 0x%8.8x\n", mstr->FLMSTR2); + msg_pdbg1("FLMSTR3 0x%8.8x\n", mstr->FLMSTR3); + msg_pdbg1("\n"); + + #define R(r) (r)?'r':' ' + #define W(w) (w)?'w':' ' + msg_pdbg2("--- Details ---\n"); + msg_pdbg2(" Descr. BIOS ME GbE\n"); + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c\n", + R(mstr->BIOS_descr_read), W(mstr->BIOS_descr_write), + R(mstr->BIOS_BIOS_read), W(mstr->BIOS_BIOS_write), + R(mstr->BIOS_ME_read), W(mstr->BIOS_ME_write), + R(mstr->BIOS_GbE_read), W(mstr->BIOS_GbE_write)); + msg_pdbg2("ME %c%c %c%c %c%c %c%c\n", + R(mstr->ME_descr_read), W(mstr->ME_descr_write), + R(mstr->ME_BIOS_read), W(mstr->ME_BIOS_write), + R(mstr->ME_ME_read), W(mstr->ME_ME_write), + R(mstr->ME_GbE_read), W(mstr->ME_GbE_write)); + msg_pdbg2("GbE %c%c %c%c %c%c %c%c\n", + R(mstr->GbE_descr_read), W(mstr->GbE_descr_write), + R(mstr->GbE_BIOS_read), W(mstr->GbE_BIOS_write), + R(mstr->GbE_ME_read), W(mstr->GbE_ME_write), + R(mstr->GbE_GbE_read), W(mstr->GbE_GbE_write)); + msg_pdbg2("\n"); +} + +void prettyprint_ich9_reg_vscc(uint32_t reg_val) +{ + pprint_reg_hex(VSCC, BES, reg_val, ", "); + pprint_reg(VSCC, WG, reg_val, ", "); + pprint_reg(VSCC, WSR, reg_val, ", "); + pprint_reg(VSCC, WEWS, reg_val, ", "); + pprint_reg_hex(VSCC, EO, reg_val, ", "); + pprint_reg(VSCC, VCL, reg_val, "\n"); +} + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); +} + +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc) +{ + msg_pdbg1("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* content section */ + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + desc->region.FLREG0 = read_descriptor_reg(2, 0, spibar); + desc->region.FLREG1 = read_descriptor_reg(2, 1, spibar); + desc->region.FLREG2 = read_descriptor_reg(2, 2, spibar); + desc->region.FLREG3 = read_descriptor_reg(2, 3, spibar); + + /* master section */ + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* accessing strap section and upper map is impossible via FDOC/D(?) */ + msg_pdbg1(" done\n"); +} + +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..9954149 --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,258 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +#include <stdint.h> + +/* most of the following should probably be in a new file named ichspi.h */ +#define msg_pdbg1 msg_pdbg +#define msg_pdbg2 msg_pspew + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +#define pprint_reg_hex(reg, bit, val, sep) msg_pdbg("%s=0x%x" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +void prettyprint_ich9_reg_vscc(uint32_t reg_val); + +enum chipset { + CHIPSET_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_SERIES_5_IBEX_PEAK, + CHIPSET_SERIES_6_COUGAR_POINT, + CHIPSET_SERIES_7_PANTHER_POINT +}; + +struct flash_content { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint32_t FCBA :8; + uint32_t NC :2; + uint32_t :6; + uint32_t FRBA :8; + uint32_t NR :3; + uint32_t :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint32_t FMBA :8; + uint32_t NM :3; + uint32_t :5; + union { + uint32_t FISBA :8; + uint32_t FPSBA :8; + }; + uint32_t ISL :8; + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint32_t FMSBA :8; + uint32_t MSL :8; + uint32_t :16; + }; + }; +}; + +struct flash_component { + union { /* 0x00 */ + uint32_t FLCOMP; + struct { + uint32_t comp1_density :3; + uint32_t comp2_density :3; + uint32_t :11; + uint32_t freq_read :3; + uint32_t fastread :1; + uint32_t freq_fastread :3; + uint32_t freq_write :3; + uint32_t freq_read_id :3; + uint32_t :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; + struct { + uint32_t invalid_instr0; + uint32_t invalid_instr1; + uint32_t invalid_instr2; + uint32_t invalid_instr3; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; + struct { + uint32_t FPBA :13; + uint32_t :19; + }; + }; +}; + +struct flash_region { + + union { + uint32_t FLREG0; /* Flash Descriptor */ + struct { + uint32_t reg0_base :13; + uint32_t :3; + uint32_t reg0_limit :13; + uint32_t :3; + }; + }; + union { + uint32_t FLREG1; /* BIOS */ + struct { + uint32_t reg1_base :13; + uint32_t :3; + uint32_t reg1_limit :13; + uint32_t :3; + }; + }; + union { + uint32_t FLREG2; /* ME */ + struct { + uint32_t reg2_base :13; + uint32_t :3; + uint32_t reg2_limit :13; + uint32_t :3; + }; + }; + union { + uint32_t FLREG3; /* GbE */ + struct { + uint32_t reg3_base :13; + uint32_t :3; + uint32_t reg3_limit :13; + uint32_t :3; + }; + }; +}; + +struct flash_master { + union { + uint32_t FLMSTR1; + struct { + uint32_t BIOS_req_ID :16; + uint32_t BIOS_descr_read :1; + uint32_t BIOS_BIOS_read :1; + uint32_t BIOS_ME_read :1; + uint32_t BIOS_GbE_read :1; + uint32_t BIOS_plat_read :1; + uint32_t :3; + uint32_t BIOS_descr_write :1; + uint32_t BIOS_BIOS_write :1; + uint32_t BIOS_ME_write :1; + uint32_t BIOS_GbE_write :1; + uint32_t BIOS_plat_write :1; + uint32_t :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint32_t ME_req_ID :16; + uint32_t ME_descr_read :1; + uint32_t ME_BIOS_read :1; + uint32_t ME_ME_read :1; + uint32_t ME_GbE_read :1; + uint32_t ME_plat_read :1; + uint32_t :3; + uint32_t ME_descr_write :1; + uint32_t ME_BIOS_write :1; + uint32_t ME_ME_write :1; + uint32_t ME_GbE_write :1; + uint32_t ME_plat_write :1; + uint32_t :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint32_t GbE_req_ID :16; + uint32_t GbE_descr_read :1; + uint32_t GbE_BIOS_read :1; + uint32_t GbE_ME_read :1; + uint32_t GbE_GbE_read :1; + uint32_t GbE_plat_read :1; + uint32_t :3; + uint32_t GbE_descr_write :1; + uint32_t GbE_BIOS_write :1; + uint32_t GbE_ME_write :1; + uint32_t GbE_GbE_write :1; + uint32_t GbE_plat_write :1; + uint32_t :3; + }; + }; +}; + +struct flash_descriptors { + struct flash_content content; + struct flash_component component; + struct flash_region region; + struct flash_master master; +}; + +void prettyprint_ich_descriptors(enum chipset, const struct flash_descriptors *desc); + +void prettyprint_ich_descriptor_content(const struct flash_content *content); +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc); +void prettyprint_ich_descriptor_region(const struct flash_region *region); +void prettyprint_ich_descriptor_master(const struct flash_master *master); + +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); + +#endif // __ICH_DESCRIPTORS_H__ +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ichspi.c b/ichspi.c index 2480fa5..edca654 100644 --- a/ichspi.c +++ b/ichspi.c @@ -30,6 +30,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -120,6 +121,14 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same fields are also used in the + * flash descriptors to define the properties of the different flash chips + * supported by the BIOS image. These descriptors are also the source for the + * registers above. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -302,8 +311,6 @@ static void prettyprint_opcodes(OPCODES *ops) } } -#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) - static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) { msg_pdbg("HSFS: "); @@ -1191,6 +1198,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1262,6 +1270,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1312,9 +1322,26 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + msg_pdbg("\n"); + if (ichspi_desc) { + struct flash_descriptors desc = {{ 0 }}; + read_ich_descriptors_via_fdo(ich_spibar, &desc); + prettyprint_ich_descriptors(CHIPSET_UNKNOWN, &desc); + } ich_init_opcodes(); break; default: -- 1.7.1

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[PATCH 1/4] ichspi.c: refactor filling and reading the fdata/spid registers
by Stefan Tauner 15 Jul '11

15 Jul '11

- add ich_fill_data to fill the chipset registers from an array - add ich_read_data to copy the data from the chipset register into an array - replace the existing code with calls to those functions - minor cosmetic changes Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- ichspi.c | 135 ++++++++++++++++++++++++++------------------------------------ 1 files changed, 57 insertions(+), 78 deletions(-) diff --git a/ichspi.c b/ichspi.c index 99c4613..2480fa5 100644 --- a/ichspi.c +++ b/ichspi.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,18 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * This module is designed for supporting the devices - * ST M25P40 - * ST M25P80 - * ST M25P16 - * ST M25P32 already tested - * ST M25P64 - * AT 25DF321 already tested - * ... and many more SPI flash devices - * - */ - #if defined(__i386__) || defined(__x86_64__) #include <string.h> @@ -293,7 +282,7 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; /* pretty printing functions */ -static void pretty_print_opcodes(OPCODES *ops) +static void prettyprint_opcodes(OPCODES *ops) { if(ops == NULL) return; @@ -592,6 +581,51 @@ static void ich_set_bbar(uint32_t min_addr) msg_perr("Setting BBAR failed!\n"); } +/* Read len bytes from the fdata/spid register into the data array. + * + * Note that using len > spi_programmer->max_data_read will return garbage or + * may even crash. + */ + static void ich_read_data(uint8_t *data, int len, int reg0_off) + { + int i; + uint32_t temp32 = 0; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = REGREAD32(reg0_off + i); + + data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; + } +} + +/* Fill len bytes from the data array into the fdata/spid registers. + * + * Note that using len > spi_programmer->max_data_write will trash the registers + * following the data registers. + */ +static void ich_fill_data(const uint8_t *data, int len, int reg0_off) +{ + uint32_t temp32 = 0; + int i; + + if (len <= 0) + return; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = 0; + + temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + + if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); + } + i--; + if ((i % 4) != 3) /* Write remaining data to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -627,7 +661,7 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); - pretty_print_opcodes(curopcodes); + prettyprint_opcodes(curopcodes); msg_pdbg("\n"); return 0; } @@ -638,9 +672,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, { int write_cmd = 0; int timeout; - uint32_t temp32 = 0; + uint32_t temp32; uint16_t temp16; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -664,26 +697,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); /* Program data into SPID0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH7_REG_SPID0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH7_REG_SPID0); /* Assemble SPIS */ temp16 = REGREAD16(ICH7_REG_SPIS); @@ -764,17 +779,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH7_REG_SPID0); return 0; } @@ -785,7 +791,6 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, int write_cmd = 0; int timeout; uint32_t temp32; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -810,25 +815,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH9_REG_FDATA0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH9_REG_FDATA0); /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); @@ -916,17 +904,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH9_REG_FDATA0); return 0; } -- 1.7.1

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[PATCH 0/4] ichspi 7.0
by Stefan Tauner 15 Jul '11

15 Jul '11

the first one is already acked, but not committed yet, because i want it to be tested first (again :). i have worked a lot on the descriptor patch: - i have split the main part which integrates into flashrom directly (2/4) from the stand-alone utility (3/4). - the global variables are all gone. references to the memory holding the descriptors have to be passed as arguments instead. this is a problem for the hwseq patch, because ich_hwseq_probe no longer has access to the descriptors and can't know number of flashes or their densities without this. a workaround has been added while we are working on the generic opaque programmer framwork. - the structs for the ibex peak straps are now complete, but the big chunk of work - the decoding into human readable output - is not even started. - lots of cleanup done, lots of cleanup to come :) Stefan Tauner (4): ichspi.c: refactor filling and reading the fdata/spid registers add ICH/PCH flash descriptor decoding via FDOC/FDOD add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file ichspi.c: add support for Intel Hardware Sequencing Makefile | 3 +- chipdrivers.h | 6 + flashchips.c | 23 +- flashchips.h | 2 + ich_descriptors.c | 471 ++++++++++++++++++++ ich_descriptors.h | 459 ++++++++++++++++++++ ichspi.c | 495 ++++++++++++++++++---- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 197 +++++++++ 11 files changed, 1612 insertions(+), 92 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

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[PATCH] add known board MSI-7369 (K9N Neo V2) ... unsupported
by Melchior FRANZ 14 Jul '11

14 Jul '11

In case this board isn't missing for a particular reason, you may want to add it as unsupported. The problem is its usage of NVIDIA MCP65. I reported the output a while ago, but here again the short form: $ sudo ./flashrom flashrom v0.9.3-r1370 on Linux 2.6.39.3 (x86_64), built with libpci 3.1.7, \ GCC 4.5.1 20101208 [gcc-4_5-branch revision 167585], little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP65", enabling flash write... \ This chipset is not really supported yet. Guesswork... SPI on this chipset is WIP. Write is unsupported! Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Found chip "Winbond W25X80" (1024 kB, SPI) at physical address 0xfff00000. No operations were specified. m.

3 5

MS-7369 (MSI K9N Neo V2): flashrom -V
by Melchior FRANZ 14 Jul '11

14 Jul '11

flashrom v0.9.3-r1370 on Linux 2.6.39.3 (x86_64) works: reading verifying untested: erasing writing m.

2 3

Re: [flashrom] [PATCH 1/3] ichspi.c: refactor filling and reading the fdata/spid registers
by Carl-Daniel Hailfinger 13 Jul '11

13 Jul '11

Am 01.07.2011 05:38 schrieb Stefan Tauner: > - add ich_fill_data to fill the chipset registers from an array > - add ich_read_data to copy the data from the chipset register into an array > - replace the existing code with calls to those functions > > NB: this changes the semantic of the *run_opcode functions a bit: > previously they could trash the chipset registers following the data registers because there > was no (explicit) length check (it was and is checked by the dispatching run_opcode method). > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > I know you're just moving code, but this is a chance to clean up the code and improve readability. > diff --git a/ichspi.c b/ichspi.c > index 19e52d2..905ed70 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -592,6 +592,57 @@ static void ich_set_bbar(uint32_t min_addr) > msg_perr("Setting BBAR failed!\n"); > } > > +/* Reads up to len byte from the fdata/spid register into the data array. > + * The amount actually read is limited by the maximum read size of the > + * chipset. */ > Can you put the terminating */ on its own line like the multiline comments in other files? > + static void ich_read_data(uint8_t *data, int len, int reg0_off) > + { > + int a; > int i would be a nicer name... although you just moved that code, so it's not your fault. > + uint32_t temp32 = 0; > + > + if (len > spi_programmer->max_data_read) > + len = spi_programmer->max_data_read; > Can this really happen? If yes, does it depend on bugs elsewhere in the code? This needs at least a msg_perr("bug in blabla, please report to flashrom@"), we might even want to have the function return int to handle errors. > + > + for (a = 0; a < len; a++) { > + if ((a % 4) == 0) > + temp32 = REGREAD32(reg0_off + (a)); > Are the extra parentheses around a really needed? > + > + data[a] = (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) > + >> ((a % 4) * 8); > I think David had a suggestion on how to simplify this formula a bit. > + } > +} > + > +/* Fills up to len bytes from the data array into the fdata/spid registers. > + * The amount actually written is limited by the maximum write size of the > + * chipset and is returned by the function. */ > The result is discarded anyway, and we probably shouldn't call this function with a too big len in the first place, so a return type of void may be the best choice. That said, if you decide to care about the result of this function, please make sure that ich_fill_data and ich_read_data have identical return types and check that the comments above the functions match the prototypes. > +static uint8_t ich_fill_data(const uint8_t *data, int len, int reg0_off) > +{ > + uint32_t temp32 = 0; > + int a; > See ich_read_data. > + > + if (len > spi_programmer->max_data_write) > + len = spi_programmer->max_data_write; > See ich_read_data. > + > + if (len <= 0) > + return 0; > Superfluous check? len<0 should not happen, and len==0 won't execute the for loop below. > + > + for (a = 0; a < len; a++) { > + if ((a % 4) == 0) { > + temp32 = 0; > + } > Please kill superfluous {}. > + > + temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); > + > + if ((a % 4) == 3) { > + REGWRITE32(reg0_off + (a - (a % 4)), temp32); > + } > Please kill superfluous {}. > + } > + if (((a - 1) % 4) != 3) { > Yeargh! AFAIK modulo for negative integers is implementation-defined. So your len<=0 check a few lines above may have been a good idea. That said, it is a good idea to add a comment so others won't fall into that trap. And all this (a-1) stuff in the line above and below would be a lot more readable if you inserted a--; before the if. > + REGWRITE32(reg0_off + ((a - 1) - ((a - 1) % 4)), temp32); > + } > Please kill superfluous {}. > + return len; > +} > + > /* This function generates OPCODES from or programs OPCODES to ICH according to > * the chipset's SPI configuration lock. > * > @@ -638,9 +689,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, > { > int write_cmd = 0; > int timeout; > - uint32_t temp32 = 0; > + uint32_t temp32; > uint16_t temp16; > - uint32_t a; > uint64_t opmenu; > int opcode_index; > > @@ -664,26 +714,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, > REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); > > /* Program data into SPID0 to N */ > - if (write_cmd && (datalength != 0)) { > - temp32 = 0; > - for (a = 0; a < datalength; a++) { > - if ((a % 4) == 0) { > - temp32 = 0; > - } > - > - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); > - > - if ((a % 4) == 3) { > - REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), > - temp32); > - } > - } > - if (((a - 1) % 4) != 3) { > - REGWRITE32(ICH7_REG_SPID0 + > - ((a - 1) - ((a - 1) % 4)), temp32); > - } > - > - } > + if (write_cmd && (datalength != 0)) > + ich_fill_data(data, datalength, ICH7_REG_SPID0); > Nice! Killed superfluous {}. > > /* Assemble SPIS */ > temp16 = REGREAD16(ICH7_REG_SPIS); > @@ -765,15 +797,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, > } > > if ((!write_cmd) && (datalength != 0)) { > - for (a = 0; a < datalength; a++) { > - if ((a % 4) == 0) { > - temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); > - } > - > - data[a] = > - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) > - >> ((a % 4) * 8); > - } > + ich_read_data(data, datalength, ICH7_REG_SPID0); > Can you kill {} here as well? > } > > return 0; > @@ -785,7 +809,6 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > int write_cmd = 0; > int timeout; > uint32_t temp32; > - uint32_t a; > uint64_t opmenu; > int opcode_index; > > @@ -810,25 +833,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); > > /* Program data into FDATA0 to N */ > - if (write_cmd && (datalength != 0)) { > - temp32 = 0; > - for (a = 0; a < datalength; a++) { > - if ((a % 4) == 0) { > - temp32 = 0; > - } > - > - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); > - > - if ((a % 4) == 3) { > - REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), > - temp32); > - } > - } > - if (((a - 1) % 4) != 3) { > - REGWRITE32(ICH9_REG_FDATA0 + > - ((a - 1) - ((a - 1) % 4)), temp32); > - } > - } > + if (write_cmd && (datalength != 0)) > + ich_fill_data(data, datalength, ICH9_REG_FDATA0); > > /* Assemble SSFS + SSFC */ > temp32 = REGREAD32(ICH9_REG_SSFS); > @@ -917,15 +923,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > } > > if ((!write_cmd) && (datalength != 0)) { > - for (a = 0; a < datalength; a++) { > - if ((a % 4) == 0) { > - temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); > - } > - > - data[a] = > - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) > - >> ((a % 4) * 8); > - } > + ich_read_data(data, datalength, ICH9_REG_FDATA0); > Kill superfluous {} > } > > return 0; > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

Desktop Summit 2011 in Berlin
by Paul Menzel 13 Jul '11

13 Jul '11

Dear coreboot folks, the Desktop Summit 2011 [1] will take place in Berlin from August 6th– 12th. The first three days will consist of keynotes and talks [2]. There seem to be some open slots on Monday and maybe on the weekend evening too. I am CCing Lennart Poettering as one of the organizers(?). Knowing that some coreboot or flashrom developers live in Berlin it would be awesome if one of them could present coreboot or flashrom. For coreboot a short introduction and demonstration of for example the ThinkPad X60/T60 and ASRock E350M1 would be a good idea. I know this is on short notice and the Desktop Summit is normally associated with GNOME and KDE and therefore coreboot seems out of place. But in my opinion – if accepted – coreboot could reach *developers* who might be interested in the possibilities of coreboot and do not know about this. flashrom could be interesting for the desktop developers to know that there are tools to upgrade the BIOS from the desktop and maybe someone is motivated to code up a GUI (graphical user interface) for flashrom. That is just a thought and I do not know how easy that would be and if flashrom provides these kinds of means to be hooked up to a GUI. I would do it, but I am only able to be there on Saturday and not being that knowledgeable with the internals I would rather not do it. Thanks, Paul [1] https://desktopsummit.org/ [2] https://desktopsummit.org/program

2 1

[commit] r1372 - trunk
by repository service 13 Jul '11

13 Jul '11

Author: stefanct Date: Wed Jul 13 22:48:54 2011 New Revision: 1372 URL: http://flashrom.org/trac/flashrom/changeset/1372 Log: enable writing on mcp6x_7x this was deliberately disabled until now, but seems to work well enough. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Jul 13 13:22:03 2011 (r1371) +++ trunk/chipset_enable.c Wed Jul 13 22:48:54 2011 (r1372) @@ -912,8 +912,9 @@ */ buses_supported = CHIP_BUSTYPE_NONE; msg_pdbg("Flash bus type is SPI\n"); - msg_perr("SPI on this chipset is WIP. Write is unsupported!\n"); - programmer_may_write = 0; + msg_pinfo("SPI on this chipset is WIP. Please report any " + "success or failure by mailing us the verbose " + "output to flashrom(a)flashrom.org, thanks!\n"); break; default: /* Should not happen. */

1 0

[commit] r1371 - trunk
by repository service 13 Jul '11

13 Jul '11

Author: uwe Date: Wed Jul 13 13:22:03 2011 New Revision: 1371 URL: http://flashrom.org/trac/flashrom/changeset/1371 Log: Change "class" parameter name to "devclass" to avoid C++ issues. In C++ "class" is a reserved keyword, and as we'll want to use libflashrom from C++ code at some point, let's make sure it doesn't cause issues. Other places in the code already used "devclass" anyway, so it also increases consistency and readability a bit. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/internal.c trunk/programmer.h Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Wed Jul 13 00:35:21 2011 (r1370) +++ trunk/internal.c Wed Jul 13 13:22:03 2011 (r1371) @@ -35,7 +35,7 @@ return NULL; } -struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class) +struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass) { struct pci_dev *temp; struct pci_filter filter; @@ -48,7 +48,7 @@ if (pci_filter_match(&filter, temp)) { /* Read PCI class */ tmp2 = pci_read_word(temp, 0x0a); - if (tmp2 == class) + if (tmp2 == devclass) return temp; } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed Jul 13 00:35:21 2011 (r1370) +++ trunk/programmer.h Wed Jul 13 13:22:03 2011 (r1371) @@ -289,7 +289,7 @@ #endif #if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); -struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); +struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device);

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