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[PATCH 5/8] ichspi: add support for Intel Hardware Sequencing
by Stefan Tauner 20 Aug '11

20 Aug '11

todo: - revise hwseq activation: when should hwseq be used, when swseq? in the current version i have added a programmer parameter to tell flashrom when one wants to use hwseq _if it is available_ (i.e. descriptor valid), example: flashrom -p internal:laptop=force_I_want_a_brick,hwseq=yes -VV this needs to be documented in the man page if it gets merged like that. - commit message (is a link to my blog post a good idea (additionally)?) - revise (levels of) prints - revise timeout … [View More]values (for optimal performance) - build upon the upcoming opaque interface framework instead Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 + flashchips.c | 23 ++++- flashchips.h | 2 + ich_descriptors.c | 35 +++++ ich_descriptors.h | 3 +- ichspi.c | 357 +++++++++++++++++++++++++++++++++++++++++++++++++++-- programmer.h | 1 + 7 files changed, 414 insertions(+), 13 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 3f5b503..f3781ae 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -86,6 +86,12 @@ void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); +/* ichspi.c */ +int ich_hwseq_probe(struct flashchip *flash); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); diff --git a/flashchips.c b/flashchips.c index 4d741a0..20f7197 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8782,7 +8782,27 @@ const struct flashchip flashchips[] = { .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Intel", + .name = "Hardware Sequencing", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_HWSEQ, + .total_size = 0, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = ich_hwseq_probe, + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = ich_hwseq_block_erase, + } + }, + .write = ich_hwseq_write_256, + .read = ich_hwseq_read, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", @@ -8915,6 +8935,7 @@ const struct flashchip flashchips[] = { .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", diff --git a/flashchips.h b/flashchips.h index ff49d31..1374b2f 100644 --- a/flashchips.h +++ b/flashchips.h @@ -346,6 +346,8 @@ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ +#define INTEL_HWSEQ 0xFFFE /* dummy ID for hardware sequencing */ + #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ /* diff --git a/ich_descriptors.c b/ich_descriptors.c index ce40d9f..8076b09 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -214,6 +214,41 @@ void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) msg_pdbg2("\n"); } +/** Returns the integer representation of the component density with index +idx in bytes or 0 if a correct size can not be determined. */ +int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc) +{ + uint8_t size_enc; + static const int const dec_mem[6] = { + 512 * 1024, + 1 * 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 16 * 1024 * 1024, + }; + + switch(idx) { + case 0: + size_enc = desc->component.comp1_density; + break; + case 1: + if (desc->content.NC == 0) + return 0; + size_enc = desc->component.comp2_density; + break; + default: + msg_perr("Only component index 0 or 1 are supported yet.\n"); + return 0; + } + if (size_enc > 5) { + msg_perr("Density of component with index %d is invalid. " + "Encoded density is 0x%x.\n", idx, size_enc); + return 0; + } + return dec_mem[size_enc]; +} + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; diff --git a/ich_descriptors.h b/ich_descriptors.h index b1da914..8ab798f 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -255,7 +255,8 @@ void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); - +int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc); + #endif /* BITFIELDS == 1 */ #endif /* __ICH_DESCRIPTORS_H__ */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ichspi.c b/ichspi.c index 2e25d34..61c0825 100644 --- a/ichspi.c +++ b/ichspi.c @@ -26,7 +26,10 @@ #if defined(__i386__) || defined(__x86_64__) #include <string.h> +#include <stdlib.h> #include "flash.h" +#include "flashchips.h" +#include "chipdrivers.h" #include "programmer.h" #include "spi.h" #include "ich_descriptors.h" @@ -1084,6 +1087,298 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } +static struct hwseq { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq; + +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. */ +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + static const uint32_t const dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + + ich_hwseq_set_addr(addr); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + return dec_berase[enc_berase]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 10 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (!timeout) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x (=0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + return 0; +} + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_cerr("This chip (%s) is not supported in hardware" + "sequencing mode and should never have been probed.\n", + flash->name); + msg_cerr("%s: Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); + if (spi_programmer->type != SPI_CONTROLLER_ICH_HWSEQ) { + msg_cdbg("not met.\n"); + return 0; + } + msg_cdbg("met.\n"); + + total_size = hwseq.size_comp0 + hwseq.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq.size_comp1 != 0) ? 2 : 1); + if (hwseq.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + return 1; +} + +static int ich_hwseq_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " + "arbitrary commands."); + return -1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode.\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, spi_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, spi_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1207,6 +1502,16 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct spi_programmer spi_programmer_ich_hwseq = { + .type = SPI_CONTROLLER_ICH_HWSEQ, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_hwseq_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_hwseq_read, + .write_256 = ich_hwseq_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1214,21 +1519,20 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + char *arg; int ichspi_desc = 0; + int hwseq_en = 0; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1239,8 +1543,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1277,9 +1581,21 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_lock = 1; } ich_set_bbar(ich_generation, 0); + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ + arg = extract_programmer_param("hwseq"); + if (arg && !strcmp(arg, "yes")) + hwseq_en = 1; + else if (arg && !strlen(arg)) + msg_pinfo("Missing argument for hwseq.\n"); + else if (arg) + msg_pinfo("Unknown argument for hwseq: %s\n", arg); + free(arg); tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1363,18 +1679,37 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pdbg("\n"); #if BITFIELDS == 1 + { /* to be able to declare desc here and avoid another + * "#if BITFIELDS == 1" on top + */ + struct ich_descriptors desc = {{ 0 }}; if (ichspi_desc) { - struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (desc.content.NC != 0) + hwseq_en = 1; + } else + hwseq_en = 0; /* disable it even if the user said yes */ + + if (hwseq_en > 0) { + hwseq.size_comp0 = getFCBA_component_density(0, &desc); + hwseq.size_comp1 = getFCBA_component_density(1, &desc); + register_spi_programmer(&spi_programmer_ich_hwseq); + } else { + register_spi_programmer(&spi_programmer_ich9); + ich_init_opcodes(); } -#endif /* BITFIELDS == 1 */ + } +#else /* BITFIELDS == 1 */ + register_spi_programmer(&spi_programmer_ich9); ich_init_opcodes(); - break; - default: - /* Nothing */ +#endif /* BITFIELDS == 1 */ break; } diff --git a/programmer.h b/programmer.h index 6a28dbe..6e316d1 100644 --- a/programmer.h +++ b/programmer.h @@ -517,6 +517,7 @@ enum spi_controller { #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_ICH_HWSEQ, SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, -- 1.7.1 [View Less]

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[PATCH 4/8] ichspi: improve prettyprint_opcodes
by Stefan Tauner 20 Aug '11

20 Aug '11

add headers for the columns and some decoding into human readable format. --- before: […] Reading OPCODES... done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0x20, 3, 0 op[3]=0x05, 0, 0 op[4]=0x9f, 0, 1 op[5]=0x20, 1, 2 op[6]=0x01, 1, 0 op[7]=0x06, 0, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. […] after: […] Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ … [View More]addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x20, write w/o addr, 1 op[6]: 0x01, write w/o addr, 2 op[7]: 0x06, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. […] i could also print the preops directly in the preop column instead of using that redirection. but i think as debug output it is better to know the index of the two preops too. side note: does it make sense to create an opcode -> string decoder for flashrom-wide usage in user output (in spi25.c)? an erase opcode -> function pointer decoder is used in sfdp, that could also be generalized like that. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 34 +++++++++++++++++++++++----------- 1 files changed, 23 insertions(+), 11 deletions(-) diff --git a/ichspi.c b/ichspi.c index d51a6b2..2e25d34 100644 --- a/ichspi.c +++ b/ichspi.c @@ -294,22 +294,34 @@ static OPCODES O_EXISTING = {}; /* pretty printing functions */ static void prettyprint_opcodes(OPCODES *ops) { - if(ops == NULL) - return; - - msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], - ops->preop[1]); - OPCODE oc; + const char *t; + const char *a; uint8_t i; + static const char *const spi_type[4] = { + "read w/o addr", + "write w/o addr", + "read w/ addr", + "write w/ addr" + }; + static const char *const atomic_type[3] = { + "none", + " 0 ", + " 1 " + }; + + if (ops == NULL) + return; + + msg_pdbg(" OP Type Pre-OP\n"); for (i = 0; i < 8; i++) { oc = ops->opcode[i]; - msg_pdbg("op[%d]=0x%02x, %d, %d\n", - i, - oc.opcode, - oc.spi_type, - oc.atomic); + t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type]; + a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic]; + msg_pdbg("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a); } + msg_pdbg("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0], + ops->preop[1]); } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) -- 1.7.1 [View Less]

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[PATCH 3/8] ichspi: don't touch the nonexistent(?) BBAR register on ICH8
by Stefan Tauner 20 Aug '11

20 Aug '11

There is no sign of BBAR (BIOS Base Address Configuration Register) in the public datasheet (or specification update) of the ICH8. Also, the offset of that register has changed between ICH7 (SPIBAR + 50h) and ICH9 (SPIBAR + A0h), so we have no clue if or where it is on ICH8. Better don't try to touch it at all and assume/hope it is 0. --- Until now we implicitly accessed it via the ICH9 offset. I think this is an evident sign that the naming of the spi controller types in ichspi.c (… [View More]SPI_CONTROLLER_VIA, SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9) might not cut it and we should think about introducing a special ICH8 one, even if its struct is identical to the ICH9. having most of the ICH8 code path guarded/controlled by SPI_CONTROLLER_ICH7 or SPI_CONTROLLER_ICH9 (depending on which is more similar in one situation), is an open invitation to similar bugs because one easily forgets that ICH8 is very special. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 25 ++++++++++++------------- 1 files changed, 12 insertions(+), 13 deletions(-) diff --git a/ichspi.c b/ichspi.c index 343a0af..d51a6b2 100644 --- a/ichspi.c +++ b/ichspi.c @@ -558,20 +558,19 @@ static int program_opcodes(OPCODES *op, int enable_undo) * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -static void ich_set_bbar(uint32_t min_addr) +static void ich_set_bbar(int ich_generation, uint32_t min_addr) { int bbar_off; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case 7: bbar_off = 0x50; break; - case SPI_CONTROLLER_ICH9: + case 8: + msg_perr("BBAR offset is unknown on ICH8!\n"); + return; + default: /* Future version might behave the same */ bbar_off = ICH9_REG_BBAR; break; - default: - msg_perr("Unknown chipset for BBAR setting!\n"); - return; } ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK; @@ -589,6 +588,8 @@ static void ich_set_bbar(uint32_t min_addr) */ if (ichspi_bbar != min_addr) msg_perr("Setting BBAR failed!\n"); + else + msg_pspew("Setting BBAR succeeded!\n"); } /* Read len bytes from the fdata/spid register into the data array. @@ -657,11 +658,6 @@ static int ich_init_opcodes(void) msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done, 1); - /* Technically not part of opcode init, but it allows opcodes - * to run without transaction errors by setting the lowest - * allowed address to zero. - */ - ich_set_bbar(0); } if (rc) { @@ -1268,6 +1264,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + ich_set_bbar(ich_generation, 0); ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: @@ -1349,6 +1346,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + ich_set_bbar(ich_generation, 0); } msg_pdbg("\n"); @@ -1439,6 +1437,7 @@ int via_init_spi(struct pci_dev *dev) ichspi_lock = 1; } + ich_set_bbar(7, 0); ich_init_opcodes(); return 0; -- 1.7.1 [View Less]

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[PATCH 2/8] ichspi: disable writes when locked or read-only regions are detected
by Stefan Tauner 20 Aug '11

20 Aug '11

Until we are able to unlock regions or at least understand better what consequences writing single regions have, disable writing completely whenever a non-writeable region is detected. NB: the registers might not always reflect the real access status. http://www.flashrom.org/pipermail/flashrom/2011-April/006309.html (this is the sole such report i can remember) --- Might not be the best location to do this, but currently i don't recognize a better one. The warnings are repeated for each non-… [View More]

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[PATCH 1/8] ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Stefan Tauner 20 Aug '11

20 Aug '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptor sections that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content section: describes the image and some generic properties (number of sections, offset of sections, PCH/ICH and MCH/PROC strap offsets and lengths) - component section: identify the different SPI flash chips and their … [View More]capabilities. - region section similarly to a partition table this describes the different regions. the content of FLREG* is derived from this section. - master section defines SPI master (host, ME, GbE) access rights of the individual regions. the content of PR* is derived from this section. this is only a part of the data included in the descriptor. other information can be retrieved from a complete binary dump of the descriptor region only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of all supported flash chips (together with their RDIDs) are stored in the same format in table in a descriptor section (which is used by the ME apparently). a later patch will use the macros outside of ichspi.c which is the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h (else they would be moved in the follow-up patch). because this patch relies on (compiler) implementation-specific layouting of bit-fields, it checks for basic compiler support in the makefile and for correct layout before taking any action on runtime. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 25 +++++- ich_descriptors.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++++++++ ich_descriptors.h | 261 ++++++++++++++++++++++++++++++++++++++++++++++++ ichspi.c | 60 +++++++++-- 4 files changed, 622 insertions(+), 12 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h diff --git a/Makefile b/Makefile index 26f978f..247a60c 100644 --- a/Makefile +++ b/Makefile @@ -340,9 +340,11 @@ endif ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "BITFIELDS := yes" .features && printf "%s" "-D'BITFIELDS=1'") PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o ifeq ($(ARCH),"x86") -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif NEED_PCI := yes @@ -635,6 +637,19 @@ int main(int argc, char **argv) endef export UTSNAME_TEST +define BITFIELDS_TEST +#include "ich_descriptors.h" +int main(int argc, char **argv) +{ + struct ich_descriptors desc; + (void) argc; + (void) argv; + desc.region.FLREGs[4] = 0x5aa5a55a; + return desc.region.reg4_base; +} +endef +export BITFIELDS_TEST + features: compiler @echo "FEATURES := yes" > .features.tmp ifeq ($(CONFIG_FT2232_SPI), yes) @@ -649,6 +664,14 @@ endif @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) +# ugly hack to get a logical AND *sigh* +ifeq ($(CONFIG_INTERNAL)$(ARCH), yes"x86") + @printf "Checking if bit-fields support is sufficient... " + @echo "$$BITFIELDS_TEST" > .featuretest.c + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -D BITFIELDS .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ + ( echo "yes."; echo "BITFIELDS := yes" >> .features.tmp ) || \ + ( echo "no."; echo "BITFIELDS := no" >> .features.tmp ) +endif @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..ce40d9f --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,288 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include "ich_descriptors.h" +#include "flash.h" /* for msg_* */ +#include "programmer.h" + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) +{ + print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); + print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF); + print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF); + print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF); + print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF); + print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); +} + +#if BITFIELDS == 1 +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) + +void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) +{ + prettyprint_ich_descriptor_content(&desc->content); + prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_region(desc); + prettyprint_ich_descriptor_master(&desc->master); +} + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) +{ + msg_pdbg2("=== Content Section ===\n"); + msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG); + msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0); + msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1); + msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("NR (Number of Regions): %5d\n", + cont->NR + 1); + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", + getFRBA(cont)); + msg_pdbg2("NC (Number of Components): %5d\n", + cont->NC + 1); + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", + getFCBA(cont)); + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", + cont->ISL); + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", + getFISBA(cont)); + msg_pdbg2("NM (Number of Masters): %5d\n", + cont->NM + 1); + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", + getFMBA(cont)); + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", + cont->MSL); + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", + getFMSBA(cont)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) +{ + static const char * const str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved", /* 010 */ + "reserved", /* 011 */ + "50 MHz", /* 100 */ + "reserved", /* 101 */ + "reserved", /* 110 */ + "reserved" /* 111 */ + }; + static const char * const str_mem[8] = { + "512 kB", /* 000 */ + " 1 MB", /* 001 */ + " 2 MB", /* 010 */ + " 4 MB", /* 011 */ + " 8 MB", /* 100 */ + " 16 MB", /* 101 */ + "reserved", /* 110 */ + "reserved", /* 111 */ + }; + + msg_pdbg2("=== Component Section ===\n"); + msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); + msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL ); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("Component 1 density: %s\n", + str_mem[desc->component.comp1_density]); + if (desc->content.NC) + msg_pdbg2("Component 2 density: %s\n", + str_mem[desc->component.comp2_density]); + else + msg_pdbg2("Component 2 is not used.\n"); + msg_pdbg2("Read Clock Frequency: %s\n", + str_freq[desc->component.freq_read]); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", + str_freq[desc->component.freq_read_id]); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", + str_freq[desc->component.freq_write]); + msg_pdbg2("Fast Read is %ssupported.\n", + desc->component.fastread ? "" : "not "); + if (desc->component.fastread) + msg_pdbg2("Fast Read Clock Frequency: %s\n", + str_freq[desc->component.freq_fastread]); + if (desc->component.FLILL == 0) + msg_pdbg2("No forbidden opcodes.\n"); + else { + msg_pdbg2("Invalid instruction 0: 0x%02x\n", + desc->component.invalid_instr0); + msg_pdbg2("Invalid instruction 1: 0x%02x\n", + desc->component.invalid_instr1); + msg_pdbg2("Invalid instruction 2: 0x%02x\n", + desc->component.invalid_instr2); + msg_pdbg2("Invalid instruction 3: 0x%02x\n", + desc->component.invalid_instr3); + } + msg_pdbg2("\n"); +} + +static void pprint_freg(const struct ich_desc_region *reg, uint32_t i) +{ + static const char *const region_names[5] = { + "Descr.", "BIOS", "ME", "GbE", "Platf." + }; + if (i >= 5) { + msg_pdbg2("%s: region index too high.\n", __func__); + return; + } + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); + if (base > limit) + msg_pdbg2("is unused.\n"); + else + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); +} + +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr = desc->content.NR + 1; + msg_pdbg2("=== Region Section ===\n"); + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d).\n", __func__, + nr); + return; + } + for (i = 0; i <= nr; i++) + msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + for (i = 0; i <= nr; i++) + pprint_freg(&desc->region, i); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) +{ + msg_pdbg2("=== Master Section ===\n"); + msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1); + msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2); + msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); + msg_pdbg2("\n"); +} + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + mmio_le_writel(control, spibar + ICH9_REG_FDOC); + return mmio_le_readl(spibar + ICH9_REG_FDOD); +} + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr; + struct ich_desc_region *r = &desc->region; + + /* Test if bit-fields are working as expected */ + for (i = 0; i < 4; i++) + desc->region.FLREGs[i] = 0x5A << (i * 8); + if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 || + r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 || + r->reg2_base != 0x0000 || r->reg2_limit != 0x005A || + r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) { + msg_pdbg("The combination of compiler and CPU architecture used" + "does not lay out bit-fields as expected, sorry.\n"); + msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base); + msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit); + msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base); + msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit); + msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base); + msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit); + msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base); + msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit); + return RET_ERR; + } + + msg_pdbg2("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* content section */ + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + nr = desc->content.NR + 1; + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d) - failed\n", + __func__, nr); + return RET_ERR; + } + for (i = 0; i <= nr; i++) + desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar); + + /* master section */ + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* Accessing the strap section via FDOC/D is only possible on ICH8 and + * reading the upper map is impossible on all chipsets, so don't bother. + */ + + msg_pdbg2(" done.\n"); + return RET_OK; +} +#endif /* BITFIELDS == 1 */ +#endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..b1da914 --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,261 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +#include <stdint.h> + +#define RET_OK 0 +#define RET_ERR -1 +#define RET_WARN -2 +#define RET_PARAM -3 +#define RET_OOB -4 + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) +#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) + +/* Used to select the right descriptor printing function. + * Currently only ICH8 and Ibex Peak are supported. + */ +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT +}; + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); + +#if BITFIELDS == 1 +struct ich_desc_content { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint32_t FCBA :8, /* Flash Component Base Address */ + NC :2, /* Number Of Components */ + :6, + FRBA :8, /* Flash Region Base Address */ + NR :3, /* Number Of Regions */ + :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint32_t FMBA :8, /* Flash Master Base Address */ + NM :3, /* Number Of Masters */ + :5, + FISBA :8, /* Flash ICH Strap Base Address */ + ISL :8; /* ICH Strap Length */ + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ + MSL :8, /* MCH Strap Length */ + :16; + }; + }; +}; + +struct ich_desc_component { + union { /* 0x00 */ + uint32_t FLCOMP; /* Flash Components Register */ + struct { + uint32_t comp1_density :3, + comp2_density :3, + :11, + freq_read :3, + fastread :1, + freq_fastread :3, + freq_write :3, + freq_read_id :3, + :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; /* Flash Invalid Instructions Register */ + struct { + uint32_t invalid_instr0 :8, + invalid_instr1 :8, + invalid_instr2 :8, + invalid_instr3 :8; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; /* Flash Partition Boundary Register */ + struct { + uint32_t FPBA :13, /* Flash Partition Boundary Addr */ + :19; + }; + }; +}; + +struct ich_desc_region { + union { + uint32_t FLREGs[5]; + struct { + struct { /* FLREG0 Flash Descriptor */ + uint32_t reg0_base :13, + :3, + reg0_limit :13, + :3; + }; + struct { /* FLREG1 BIOS */ + uint32_t reg1_base :13, + :3, + reg1_limit :13, + :3; + }; + struct { /* FLREG2 ME */ + uint32_t reg2_base :13, + :3, + reg2_limit :13, + :3; + }; + struct { /* FLREG3 GbE */ + uint32_t reg3_base :13, + :3, + reg3_limit :13, + :3; + }; + struct { /* FLREG4 Platform */ + uint32_t reg4_base :13, + :3, + reg4_limit :13, + :3; + }; + }; + }; +}; + +struct ich_desc_master { + union { + uint32_t FLMSTR1; + struct { + uint32_t BIOS_req_ID :16, + BIOS_descr_r :1, + BIOS_BIOS_r :1, + BIOS_ME_r :1, + BIOS_GbE_r :1, + BIOS_plat_r :1, + :3, + BIOS_descr_w :1, + BIOS_BIOS_w :1, + BIOS_ME_w :1, + BIOS_GbE_w :1, + BIOS_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint32_t ME_req_ID :16, + ME_descr_r :1, + ME_BIOS_r :1, + ME_ME_r :1, + ME_GbE_r :1, + ME_plat_r :1, + :3, + ME_descr_w :1, + ME_BIOS_w :1, + ME_ME_w :1, + ME_GbE_w :1, + ME_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint32_t GbE_req_ID :16, + GbE_descr_r :1, + GbE_BIOS_r :1, + GbE_ME_r :1, + GbE_GbE_r :1, + GbE_plat_r :1, + :3, + GbE_descr_w :1, + GbE_BIOS_w :1, + GbE_ME_w :1, + GbE_GbE_w :1, + GbE_plat_w :1, + :3; + }; + }; +}; + +struct ich_descriptors { + struct ich_desc_content content; + struct ich_desc_component component; + struct ich_desc_region region; + struct ich_desc_master master; +}; + +void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); + +#endif /* BITFIELDS == 1 */ +#endif /* __ICH_DESCRIPTORS_H__ */ +#endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ichspi.c b/ichspi.c index 8b4210e..09af2b3 100644 --- a/ichspi.c +++ b/ichspi.c @@ -29,6 +29,7 @@ #include "flash.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -119,6 +120,16 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same layout is also used in the + * flash descriptor to define the properties of the different flash chips + * supported. The BIOS (or the ME?) is responsible to populate the ICH registers + * with the information from the descriptor on startup depending on the actual + * chip(s) detected. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -1129,9 +1140,6 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) #define ICH_BRWA(x) ((x >> 8) & 0xff) #define ICH_BRRA(x) ((x >> 0) & 0xff) -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - static void do_ich9_spi_frap(uint32_t frap, int i) { static const char *const access_names[4] = { @@ -1158,9 +1166,8 @@ static void do_ich9_spi_frap(uint32_t frap, int i) return; } - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), + access_names[rwperms]); } static const struct spi_programmer spi_programmer_ich7 = { @@ -1190,6 +1197,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1261,6 +1269,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1308,12 +1318,40 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + if (ich_generation == 8) { + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); + msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); + msg_pdbg("VSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + } else { + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + } + msg_pdbg("\n"); +#if BITFIELDS == 1 + if (ichspi_desc) { + struct ich_descriptors desc = {{ 0 }}; + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == + RET_OK) + prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, + &desc); + } +#endif /* BITFIELDS == 1 */ ich_init_opcodes(); break; default: -- 1.7.1 [View Less]

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[PATCH 0/8] ichspi 8.1
by Stefan Tauner 20 Aug '11

20 Aug '11

i made a few mistakes while reordering the patches (so that the unrelated and kinda unimportant ich_descriptor_tool is the last to apply (and review)). also, i have added two patches regarding PR registers. Stefan Tauner (8): ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD ichspi: disable writes when locked or read-only regions are detected ichspi: don't touch the nonexistent(?) BBAR register on ICH8 ichspi: improve prettyprint_opcodes ichspi: add support for Intel … [View More]

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needs board enable: jetway 865gdmp rev 1.0
by Stefan Tauner 20 Aug '11

20 Aug '11

http://paste.flashrom.org/view.php?id=770 superio http://paste.flashrom.org/view.php?id=769 lspci http://paste.flashrom.org/view.php?id=768 flash http://paste.flashrom.org/view.php?id=767 bin board owned by Андрей толстов aka andrei. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 3/7] layout: Add -i <image>[:<file>] support
by David Hendricks 19 Aug '11

19 Aug '11

one minor nit On Fri, Aug 19, 2011 at 8:00 AM, Stefan Tauner < stefan.tauner(a)student.tuwien.ac.at> wrote: > +static int read_content_from_file(romlayout_t *entry, uint8_t > *newcontents) > +{ > + char *file; > + FILE *fp; > + int len; > + > + file = entry->file; > + len = entry->end - entry->start + 1; > + if (file[0] != '\0') { > + int numbytes; > + if ((fp = fopen(file, "rb"))… [View More]

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Re: [flashrom] [PATCH 2/7] Add deferred -i processing
by David Hendricks 19 Aug '11

19 Aug '11

Oops, disregard that last message. I was looking at find_romentry() and indeed it makes sense to return a negative value to indicate error since it returns an index otherwise. Acked-by: David Hendricks <dhendrix(a)google.com> On Fri, Aug 19, 2011 at 2:53 PM, David Hendricks <dhendrix(a)google.com>wrote: > Did you want to fix the inconsistent use of -1 instead of 1 as the return > code for some functions? > > Other than that it looks good (i'm biased, of course :-)) &… [View More]

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Re: [flashrom] [PATCH 2/7] Add deferred -i processing
by David Hendricks 19 Aug '11

19 Aug '11

Did you want to fix the inconsistent use of -1 instead of 1 as the return code for some functions? Other than that it looks good (i'm biased, of course :-)) -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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