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Re: [flashrom] AMD - SP5100 - take SPI ownership (1/2)
by Thomas Gstädtner 20 Oct '11

20 Oct '11

On -10.01.-28163 20:59, Frederic Temporelli wrote: > Hello, > > > Here's a patch for using SPI from AMD SouthBridge (SB700, SP5100, ...) > without having issue with Integrated MicroControler (IMC) . > This issue has been reported by Carl-Daniel Hailfinger in ChangeSet 1173 > http://flashrom.org/trac/flashrom/changeset/1173 > AMD is now providing details about SP5100 register in document 44413: > http://support.amd.com/us/Embedded_TechDocs/44413.pdf > In this document (rev 3.02), we can see that a register is in charge of > managing access to LPC (p 271 and 283) > With this patch, we take LPC ownership before each set of commands to SPI. > Ownership is released when command is done. > So, there's no more SPI corrupted command due to the IMC. > Note: this patch doesn't remove the write protection. > A second patch will be in charge of removing this write protection. > > Signed-off-by: Frederic Temporelli <frederic.temporelli(a)bull.net> > > --- > The first patch attached to my previous mail has been corrected > according to Stefan and Paul recommandations. Many thanks > > -- > Fred > > -----Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> a écrit : ----- > A : frederic.temporelli(a)bull.net > De : Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Date : 01/08/2011 12:02 > Cc : flashrom(a)flashrom.org > Objet : Re: [flashrom] AMD - SP5100 - take SPI ownership (1/2) > > hello frederic, > > thanks for your patches. > i have not looked at it in detail yet (i'll leave that to those who are > more familiar with the IMC problem), but i have spotted quite some > coding style issues. it would be great if you could fix those. > i'll explain what i noticed inline. > > On Mon, 1 Aug 2011 10:45:24 +0200 > frederic.temporelli(a)bull.net wrote: > >> diff -ur ../flashrom-0.9.4-r1394/sb600spi.c ./sb600spi.c >> --- ../flashrom-0.9.4-r1394/sb600spi.c 2011-05-11 13:07:07.000000000 -0400 >> +++ ./sb600spi.c 2011-07-29 22:45:48.693159918 -0400 >> @@ -5,6 +5,8 @@ >> * Copyright (C) 2008 Joe Bao <Zheng.Bao(a)amd.com> >> * Copyright (C) 2008 Advanced Micro Devices, Inc. >> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger >> + * Copyright (C) 2011 Bull SAS >> + * (Written by Frederic Temporelli <frederic.temporelli(a)bull.net> for Bull SAS ) > space before the closing parenthesis > >> * >> * This program is free software; you can redistribute it and/or modify >> * it under the terms of the GNU General Public License as published by >> @@ -43,6 +45,63 @@ >> >> static uint8_t *sb600_spibar = NULL; >> >> +/* reference to LPC/SPI PCI device, >> + * requested for requesting/releasing >> + * device access, shared with IMC >> + */ >> +struct pci_dev *lpc_isa_bridge = NULL; >> + >> + >> +/* >> + * avoid interaction from IMC while we are working with LPC/SPI >> + * this is done by requesting HostOwnLPC register (LPC_ISA_BRIDGE, write 1 in register 0x98) > line too long, please split (and some punctuation would increase readability then) > >> + * then we have to read this register. >> + * Loop until we have the ownership >> + * see doc AMD 44413 - AMD SP5100 Register Reference Guide >> + */ >> +static int resquest_lpc_ownership (void) >> +{ >> + uint8_t tmp; >> + int i = 0; >> + >> + if (lpc_isa_bridge == NULL) >> + return 1; >> + >> + pci_write_byte(lpc_isa_bridge, 0x98, 0x01); >> + >> + while ( (tmp = pci_read_byte (lpc_isa_bridge, 0x98)) == 0 ){ > we don't use inner space around clauses like here '( (' and '0 )' usually. > also there is a space missing between ')' and '{' > >> + pci_write_byte(lpc_isa_bridge, 0x98, 0x01); >> + if (++i > 1024) { >> + msg_perr("IMC did not release flash.\n"); >> + return 1; >> + } >> + >> + } >> + msg_pspew("flash ownership after %i cycles.\n", i); >> + i = 0; > please drop the line above completely > >> + return 0; >> +} >> + >> + > one line break between functions please > >> +/* >> + * release LPC/SPI ownership (IMC can access to these resources) >> + * this is done by releasing HostOwnLPC register >> + * (write 0 in register 0x98) >> + */ >> +static int release_lpc_ownership (void) >> +{ >> + >> + if (lpc_isa_bridge == NULL) >> + return 1; >> + > > spaces instead of tabs in the following lines: >> + pci_write_byte(lpc_isa_bridge, 0x98, 0x00); >> + >> + msg_pspew("flash ownership is released.\n"); >> + return 0; >> +} >> + >> + >> + > one line break between functions please > >> static void reset_internal_fifo_pointer(void) >> { >> mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); >> @@ -93,6 +152,8 @@ >> const unsigned char *writearr, unsigned char *readarr) >> { >> int count; > spaces instead of tabs >> + int result = 0; >> + >> /* First byte is cmd which can not being sent through FIFO. */ >> unsigned char cmd = *writearr++; >> unsigned int readoffby1; >> @@ -103,16 +164,26 @@ >> msg_pspew("%s, cmd=%x, writecnt=%x, readcnt=%x\n", >> __func__, cmd, writecnt, readcnt); >> >> + if (resquest_lpc_ownership() != 0){ > space missing between ')' and '{' > >> + result = SPI_PROGRAMMER_ERROR; >> + msg_pinfo("can't take ownership of LPC/SPI"); >> + goto return_status; >> + } >> + >> + >> if (readcnt > 8) { >> msg_pinfo("%s, SB600 SPI controller can not receive %d bytes, " >> "it is limited to 8 bytes\n", __func__, readcnt); >> - return SPI_INVALID_LENGTH; >> + >> + result = SPI_INVALID_LENGTH; >> + goto return_status; >> } >> >> if (writecnt > 8) { >> msg_pinfo("%s, SB600 SPI controller can not send %d bytes, " >> "it is limited to 8 bytes\n", __func__, writecnt); >> - return SPI_INVALID_LENGTH; >> + result = SPI_INVALID_LENGTH; >> + goto return_status; >> } >> >> /* This is a workaround for a bug in SB600 and SB700. If we only send >> @@ -142,7 +213,10 @@ >> ÿ * the FIFO pointer to the first byte we want to send. >> ÿ */ >> ÿ if (reset_compare_internal_fifo_pointer(writecnt)) >> - return SPI_PROGRAMMER_ERROR; >> + { > the '{' should be in the same line as the 'if' >> + result = SPI_PROGRAMMER_ERROR; >> + goto return_status; >> + } >> ÿ >> ÿ msg_pspew("Executing: \n"); >> ÿ execute_command(); >> @@ -159,7 +233,10 @@ >> ÿ * Usually, the chip will respond with 0x00 or 0xff. >> ÿ */ >> ÿ if (reset_compare_internal_fifo_pointer(writecnt + readcnt)) >> - return SPI_PROGRAMMER_ERROR; >> + { > here too >> + result = SPI_PROGRAMMER_ERROR; >> + goto return_status; >> + } >> ÿ >> ÿ /* Skip the bytes we sent. */ >> ÿ msg_pspew("Skipping: "); >> @@ -168,8 +245,11 @@ >> ÿ msg_pspew("[%02x]", cmd); >> ÿ } >> ÿ msg_pspew("\n"); >> - if (compare_internal_fifo_pointer(writecnt)) >> - return SPI_PROGRAMMER_ERROR; >> + if (compare_internal_fifo_pointer(writecnt)){ > missing space > >> + >> + result = SPI_PROGRAMMER_ERROR; >> + goto return_status; >> + } >> ÿ >> ÿ msg_pspew("Reading: "); >> ÿ for (count = 0; count < readcnt; count++, readarr++) { >> @@ -177,8 +257,11 @@ >> ÿ msg_pspew("[%02x]", *readarr); >> ÿ } >> ÿ msg_pspew("\n"); >> - if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) >> - return SPI_PROGRAMMER_ERROR; >> + if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) { >> + >> + result = SPI_PROGRAMMER_ERROR; >> + goto return_status; >> + } >> ÿ >> ÿ if (mmio_readb(sb600_spibar + 1) != readwrite) { >> ÿ msg_perr("Unexpected change in SB600 read/write count!\n"); >> @@ -186,10 +269,12 @@ >> ÿ "causes random corruption.\nPlease stop all " >> ÿ "applications and drivers and IPMI which access the " >> ÿ "flash chip.\n"); >> - return SPI_PROGRAMMER_ERROR; >> + result = SPI_PROGRAMMER_ERROR; >> ÿ } >> ÿ >> - return 0; >> +return_status: >> + release_lpc_ownership(); >> + return result; >> ÿ} >> ÿ >> ÿstatic const struct spi_programmer spi_programmer_sb600 = { >> @@ -211,6 +296,9 @@ >> ÿ "Reserved", "33", "22", "16.5" >> ÿ }; >> ÿ >> + >> + lpc_isa_bridge = dev; >> + >> ÿ /* Read SPI_BaseAddr */ >> ÿ tmp = pci_read_long(dev, 0xa0); >> ÿ tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ > > diff -ur ../flashrom-0.9.4-r1394/sb600spi.c ./sb600spi.c > --- ../flashrom-0.9.4-r1394/sb600spi.c 2011-05-11 13:07:07.000000000 -0400 > +++ ./sb600spi.c 2011-08-01 21:17:40.573417039 -0400 > @@ -5,6 +5,8 @@ > * Copyright (C) 2008 Joe Bao <Zheng.Bao(a)amd.com> > * Copyright (C) 2008 Advanced Micro Devices, Inc. > * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger > + * Copyright (C) 2011 Bull SAS > + * (Written by Frederic Temporelli <frederic.temporelli(a)bull.net> for Bull SAS) > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by > @@ -43,6 +45,60 @@ > > static uint8_t *sb600_spibar = NULL; > > +/* reference to LPC/SPI PCI device, > + * requested for requesting/releasing > + * device access, shared with IMC > + */ > +struct pci_dev *lpc_isa_bridge = NULL; > + > + > +/* > + * avoid interaction from IMC, while we are working with LPC/SPI. > + * This is done by requesting HostOwnLPC register > + * (LPC_ISA_BRIDGE, write 1 in register 0x98). > + * Then we have to read this register, > + * and loop until we have the ownership. > + * see doc AMD 44413 - AMD SP5100 Register Reference Guide. > + */ > +static int resquest_lpc_ownership (void) > +{ > + uint8_t tmp; > + int i = 0; > + > + if (lpc_isa_bridge == NULL) > + return 1; > + > + pci_write_byte(lpc_isa_bridge, 0x98, 0x01); > + > + while ((tmp = pci_read_byte (lpc_isa_bridge, 0x98)) == 0) { > + pci_write_byte(lpc_isa_bridge, 0x98, 0x01); > + if (++i > 1024) { > + msg_perr("IMC did not release flash.\n"); > + return 1; > + } > + > + } > + msg_pspew("flash ownership after %i cycles.\n", i); > + return 0; > +} > + > +/* > + * release LPC/SPI ownership (IMC can access to these resources) > + * this is done by releasing HostOwnLPC register > + * (write 0 in register 0x98) > + */ > +static int release_lpc_ownership (void) > +{ > + > + if (lpc_isa_bridge == NULL) > + return 1; > + > + pci_write_byte(lpc_isa_bridge, 0x98, 0x00); > + > + msg_pspew("flash ownership is released.\n"); > + return 0; > +} > + > static void reset_internal_fifo_pointer(void) > { > mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); > @@ -93,6 +149,8 @@ > const unsigned char *writearr, unsigned char *readarr) > { > int count; > + int result = 0; > + > /* First byte is cmd which can not being sent through FIFO. */ > unsigned char cmd = *writearr++; > unsigned int readoffby1; > @@ -103,16 +161,26 @@ > msg_pspew("%s, cmd=%x, writecnt=%x, readcnt=%x\n", > __func__, cmd, writecnt, readcnt); > > + if (resquest_lpc_ownership() != 0) { > + result = SPI_PROGRAMMER_ERROR; > + msg_pinfo("can't take ownership of LPC/SPI"); > + goto return_status; > + } > + > + > if (readcnt > 8) { > msg_pinfo("%s, SB600 SPI controller can not receive %d bytes, " > "it is limited to 8 bytes\n", __func__, readcnt); > - return SPI_INVALID_LENGTH; > + > + result = SPI_INVALID_LENGTH; > + goto return_status; > } > > if (writecnt > 8) { > msg_pinfo("%s, SB600 SPI controller can not send %d bytes, " > "it is limited to 8 bytes\n", __func__, writecnt); > - return SPI_INVALID_LENGTH; > + result = SPI_INVALID_LENGTH; > + goto return_status; > } > > /* This is a workaround for a bug in SB600 and SB700. If we only send > @@ -141,8 +209,10 @@ > * We should send the data by sequence, which means we need to reset > * the FIFO pointer to the first byte we want to send. > */ > - if (reset_compare_internal_fifo_pointer(writecnt)) > - return SPI_PROGRAMMER_ERROR; > + if (reset_compare_internal_fifo_pointer(writecnt)) { > + result = SPI_PROGRAMMER_ERROR; > + goto return_status; > + } > > msg_pspew("Executing: \n"); > execute_command(); > @@ -158,8 +228,10 @@ > * the opcode, the FIFO already stores the response from the chip. > * Usually, the chip will respond with 0x00 or 0xff. > */ > - if (reset_compare_internal_fifo_pointer(writecnt + readcnt)) > - return SPI_PROGRAMMER_ERROR; > + if (reset_compare_internal_fifo_pointer(writecnt + readcnt)) { > + result = SPI_PROGRAMMER_ERROR; > + goto return_status; > + } > > /* Skip the bytes we sent. */ > msg_pspew("Skipping: "); > @@ -168,8 +240,10 @@ > msg_pspew("[%02x]", cmd); > } > msg_pspew("\n"); > - if (compare_internal_fifo_pointer(writecnt)) > - return SPI_PROGRAMMER_ERROR; > + if (compare_internal_fifo_pointer(writecnt)) { > + result = SPI_PROGRAMMER_ERROR; > + goto return_status; > + } > > msg_pspew("Reading: "); > for (count = 0; count < readcnt; count++, readarr++) { > @@ -177,8 +251,10 @@ > msg_pspew("[%02x]", *readarr); > } > msg_pspew("\n"); > - if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) > - return SPI_PROGRAMMER_ERROR; > + if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) { > + result = SPI_PROGRAMMER_ERROR; > + goto return_status; > + } > > if (mmio_readb(sb600_spibar + 1) != readwrite) { > msg_perr("Unexpected change in SB600 read/write count!\n"); > @@ -186,10 +262,12 @@ > "causes random corruption.\nPlease stop all " > "applications and drivers and IPMI which access the " > "flash chip.\n"); > - return SPI_PROGRAMMER_ERROR; > + result = SPI_PROGRAMMER_ERROR; > } > > - return 0; > +return_status: > + release_lpc_ownership(); > + return result; > } > > static const struct spi_programmer spi_programmer_sb600 = { > @@ -211,6 +289,9 @@ > "Reserved", "33", "22", "16.5" > }; > > + > + lpc_isa_bridge = dev; > + > /* Read SPI_BaseAddr */ > tmp = pci_read_long(dev, 0xa0); > tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ Acked-by: Thomas Gstaedtner <thomas(a)gstaedtner.net> I tested this patch (along with 2/2 of course) on live hardware (>10 reads, >10 erase/writes) and it works fine for me. Tested on: Supermicro H8SCM-F-O, AMD SP5100 Please note, that I did no proper code review, I only tested, so let me know if the "acked-by" sign-off should not be used here. It did not seem like you used the Tested-by sign-off. thomasg

2 1

[commit] r1452 - trunk
by repository service 20 Oct '11

20 Oct '11

Author: stefanct Date: Thu Oct 20 14:57:14 2011 New Revision: 1452 URL: http://flashrom.org/trac/flashrom/changeset/1452 Log: ichspi: add (partially) dead support code for Intel Hardware Sequencing This was done to ease the review. Another patch will hook up (and explain) this code later. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ich_descriptors.c trunk/ich_descriptors.h trunk/ichspi.c Modified: trunk/ich_descriptors.c ============================================================================== --- trunk/ich_descriptors.c Fri Oct 14 22:33:14 2011 (r1451) +++ trunk/ich_descriptors.c Thu Oct 20 14:57:14 2011 (r1452) @@ -213,6 +213,34 @@ msg_pdbg2("\n"); } +/** Returns the integer representation of the component density with index +idx in bytes or 0 if a correct size can not be determined. */ +int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx) +{ + uint8_t size_enc; + + switch(idx) { + case 0: + size_enc = desc->component.comp1_density; + break; + case 1: + if (desc->content.NC == 0) + return 0; + size_enc = desc->component.comp2_density; + break; + default: + msg_perr("Only ICH SPI component index 0 or 1 are supported " + "yet.\n"); + return 0; + } + if (size_enc > 5) { + msg_perr("Density of ICH SPI component with index %d is " + "invalid. Encoded density is 0x%x.\n", idx, size_enc); + return 0; + } + return (1 << (19 + size_enc)); +} + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; Modified: trunk/ich_descriptors.h ============================================================================== --- trunk/ich_descriptors.h Fri Oct 14 22:33:14 2011 (r1451) +++ trunk/ich_descriptors.h Thu Oct 20 14:57:14 2011 (r1452) @@ -255,6 +255,7 @@ void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); +int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx); #endif /* __ICH_DESCRIPTORS_H__ */ #endif /* defined(__i386__) || defined(__x86_64__) */ Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Oct 14 22:33:14 2011 (r1451) +++ trunk/ichspi.c Thu Oct 20 14:57:14 2011 (r1452) @@ -26,6 +26,7 @@ #if defined(__i386__) || defined(__x86_64__) #include <string.h> +#include <stdlib.h> #include "flash.h" #include "programmer.h" #include "spi.h" @@ -1080,6 +1081,77 @@ return result; } +#if 0 +/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. May return nonsense if the address is + * not valid. The erase block size for a specific address depends on the flash + * partition layout as specified by FPB and the partition properties as defined + * by UVSCC and LVSCC respectively. An alternative to implement this method + * would be by querying FPB and the respective VSCC register directly. + */ +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + static const uint32_t const dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + + ich_hwseq_set_addr(addr); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + return dec_berase[enc_berase]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + timeout /= 8; /* scale timeout duration to counter */ + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(8); + } + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (!timeout) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x (=0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + return 0; +} +#endif + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1250,21 +1322,18 @@ uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; - int ichspi_desc = 0; + int desc_valid = 0; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1275,8 +1344,8 @@ /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1313,9 +1382,13 @@ ichspi_lock = 1; } ich_set_bbar(ich_generation, 0); + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1324,8 +1397,8 @@ ichspi_lock = 1; } if (tmp2 & HSFS_FDV) - ichspi_desc = 1; - if (!(tmp2 & HSFS_FDOPSS) && ichspi_desc) + desc_valid = 1; + if (!(tmp2 & HSFS_FDOPSS) && desc_valid) msg_pinfo("The Flash Descriptor Security Override " "Strap-Pin is set. Restrictions implied\n" "by the FRAP and FREG registers are NOT in " @@ -1400,18 +1473,16 @@ } msg_pdbg("\n"); - if (ichspi_desc) { + if (desc_valid) { struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); } + register_spi_programmer(&spi_programmer_ich9); ich_init_opcodes(); break; - default: - /* Nothing */ - break; } old = pci_read_byte(dev, 0xdc);

1 0

Re: [flashrom] AMD - SP5100 - take SPI ownership (2/2)
by Thomas Gstädtner 19 Oct '11

19 Oct '11

On -10.01.-28163 20:59, Frederic Temporelli wrote: > Hello, > > > Here's the second patch that will remove the write protection. > If this patch isn't applied, even if SPI owenrship is ok, flashrom won't be able to write BIOS > > Best regards > > --- > Fred > > diff -ur ../flashrom-0.9.4-r1394-sp5100/sb600spi.c ./sb600spi.c > --- ../flashrom-0.9.4-r1394-sp5100/sb600spi.c 2011-07-29 22:45:48.693159918 -0400 > +++ ./sb600spi.c 2011-08-01 12:39:31.043163924 -0400 > @@ -381,23 +381,7 @@ > return 0; > } > > - reg = pci_read_byte(dev, 0x40); > - msg_pdbg("SB700 IMC is %sactive.\n", (reg & (1 << 7)) ? "" : "not "); > - if (reg & (1 << 7)) { > - /* If we touch any region used by the IMC, the IMC and the SPI > - * interface will lock up, and the only way to recover is a > - * hard reset, but that is a bad choice for a half-erased or > - * half-written flash chip. > - * There appears to be an undocumented register which can freeze > - * or disable the IMC, but for now we want to play it safe. > - */ > - msg_perr("The SB700 IMC is active and may interfere with SPI " > - "commands. Disabling write.\n"); > - /* FIXME: Should we only disable SPI writes, or will the lockup > - * affect LPC/FWH chips as well? > - */ > - programmer_may_write = 0; > - } > + programmer_may_write = 1; > > /* Bring the FIFO to a clean state. */ > reset_internal_fifo_pointer(); Acked-by: Thomas Gstaedtner <thomas(a)gstaedtner.net> I tested this patch (along with 1/2 of course) on live hardware (>10 reads, >10 erase/writes) and it works fine for me. Tested on: Supermicro H8SCM-F-O, AMD SP5100 Please note, that I did no proper code review, I only tested, so let me know if the "acked-by" sign-off should not be used here. It did not seem like you used the Tested-by sign-off. thomasg

1 0

foxconn 945GZ7MC-KS2H
by Dimka Shkyratov 19 Oct '11

19 Oct '11

foxconn 945GZ7MC-KS2H lspci -nnvvvxxx http://paste.flashrom.org/view.php?id=863 BIOS httflashrom@flashrom.orgp://www.foxconnsupport.com/download.aspx?models=en-us0000220&category=C000000001&Series=en-us0000002&keywords=&sort=<http://www.foxconnsupport.com/download.aspx?models=en-us0000220&category=C0…> flashrom -VV http://paste.flashrom.org/view.php?id=864 dmidecode + biosdecode http://paste.flashrom.org/view.php?id=865 dmesg http://paste.flashrom.org/view.php?id=866

1 0

Re: [flashrom] Fwd: Intel Z68 - GA-Z68MX-UD2H-B3 mainboard from Gigabyte
by Stefan Tauner 18 Oct '11

18 Oct '11

On Mon, 17 Oct 2011 01:45:45 -0400 Sherwin Price <sherwin.price(a)niksoft.com> wrote: > after write and verified. > > ---------- Forwarded message ---------- > From: Sherwin Price <sherwin.price(a)niksoft.com> > Date: Mon, Oct 17, 2011 at 1:04 AM > Subject: Intel Z68 - GA-Z68MX-UD2H-B3 mainboard from Gigabyte > To: flashrom(a)flashrom.org > > > Intel Z68 - GA-Z68MX-UD2H-B3 mainboard from Gigabyte > > Award BIOS > Hello Sherwin, Thanks for your report! I have marked the chipset as tested and will commit that later together with other small changes. There are two revisions of your board: 1.0: http://www.gigabyte.com/fileupload/product/2/3854/4279_big.jpg and 1.3: http://www.gigabyte.com/fileupload/product/2/3974/4929_big.jpg They look almost identical and are probably indistinguishable from each other for flashrom, but for the record I'd like to know which one you got? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

NVIDIA MCP78S
by Loose Cannon 18 Oct '11

18 Oct '11

ASUS M3N78-VM

1 0

Re: [flashrom] Atmel AT49F002NT-90PC - Erase OK - Write FAIL
by Stefan Tauner 18 Oct '11

18 Oct '11

On Mon, 17 Oct 2011 19:25:47 -0200 Marcos Felipe Rasia de Mello <marcosfrm(a)gmail.com> wrote: > Tested using hot swap in this board > http://www.flashrom.org/pipermail/flashrom/2011-September/007986.html > already reported. > > Erase works (I compared the chip content before and after), but the > write process fails. I can easily test if you need, because I have a > backup BIOS chip. > hi and thanks for your report! to me it looks like erase is also failing. your -VE log shows: > Erasing and writing flash chip... Trying erase function 0... 0x000000-0x01ffff:E, 0x020000-0x037fff:E, 0x038000-0x039fff:E, 0x03a000-0x03bfff:EERASE FAILED at 0x0003a705! Expected=0xff, Read=0xfd, failed byte count from 0x0003a000-0x0003bfff: 0x39 > ERASE FAILED! > Reading current flash chip contents... done. Looking for another erase function. > Trying erase function 1... 0x000000-0x03ffff:EERASE FAILED at 0x0003a737! Expected=0xff, Read=0xfe, failed byte count from 0x00000000-0x0003ffff: 0x1b > ERASE FAILED! > Looking for another erase function. > No usable erase functions left. > FAILED! then writing will fail too of course... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] AMIC A290021T-70 - Erase/Write OK
by Stefan Tauner 18 Oct '11

18 Oct '11

On Mon, 17 Oct 2011 19:11:54 -0200 Marcos Felipe Rasia de Mello <marcosfrm(a)gmail.com> wrote: > Tested using hot swap in this board > http://www.flashrom.org/pipermail/flashrom/2011-September/007986.html > already reported. > > Marcos Hello Marcos, Thanks for your report! I have marked the flash chip as fully tested and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Macronix MX29F002NTPC-12 - Erase/Write OK
by Stefan Tauner 18 Oct '11

18 Oct '11

On Mon, 17 Oct 2011 19:06:22 -0200 Marcos Felipe Rasia de Mello <marcosfrm(a)gmail.com> wrote: > Tested using hot swap in this board > http://www.flashrom.org/pipermail/flashrom/2011-September/007986.html > already reported. > > Marcos Hello Marcos, Thanks for your report! I have marked the flash chip as fully tested and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] Fwd: Intel Z68 - GA-Z68MX-UD2H-B3 mainboard from Gigabyte
by Bernd Blaauw 17 Oct '11

17 Oct '11

Op 17-10-2011 7:45, Sherwin Price schreef: > after write and verified. Your log claims "No operations were specified." rather than being first who can write modern Intel chipsets/firmware. I thought flashrom by now would echo the commandline it was invoked with, but apparently not. > Intel Z68 - GA-Z68MX-UD2H-B3 mainboard from Gigabyte > > Award BIOS

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