flashrom

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9164 discussions

Re: [flashrom] flashrom -V
by Idwer Vollering 11 Jan '12

11 Jan '12

2012/1/11 Vince S <vince06fr(a)gmail.com>: > Hello > The output of flashrom -V : > > > flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci > 3.1.7, GCC 4.6.1, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 736M loops per > second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1000 us, 10000 myus > = 10004 us, 4 myus = 5 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Acer" > DMI string system-product-name: "Aspire T180" > DMI string system-version: "R01-A2" > DMI string baseboard-manufacturer: "Acer" > DMI string baseboard-product-name: "EM61SM/EM61PM " > DMI string baseboard-version: " " > DMI string chassis-type: "Desktop" > Found ITE Super I/O, ID 0x8726 on port 0x2e > Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... This chipset is not really supported yet. > Guesswork... > ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 > Flash bus type is LPC > Found SMBus device 10de:03eb at 00:01:1 > MCP SPI BAR is at 0x00000000 > MCP SPI is not used. > Please send the output of "flashrom -V" to flashrom(a)flashrom.org with > your board name: flashrom -V as the subject to help us finish support for > your > chipset. Thanks. > OK. > This chipset supports the following protocols: LPC. > Super I/O ID 0x8726 is not on the list of flash capable controllers. > Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50, > id1 is normal flash content > Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50, > id1 is normal flash content > Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50, > id1 is normal flash content > Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Found SST flash chip "SST49LF040B" (512 kB, LPC) at physical address > 0xfff80000. > Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing > information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 > 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash > content > > Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is > normal flash content, id2 is normal flash content > Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is > normal flash content, id2 is normal flash content > Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 > 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2 > 0x50, id1 is normal flash content > === > This flash part has status UNTESTED for operations: WRITE > The test status of this chip may have been updated in the latest development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above > operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, -Vr, > -Vw, -VE), and mention which mainboard or programmer you tested. > Please mention your board in the subject line. Thanks for your help! > > No operations were specified. > Restoring PCI config space for 00:01:0 reg 0x6d > Restoring PCI config space for 00:01:0 reg 0x90 > Restoring PCI config space for 00:01:0 reg 0x8c > Restoring PCI config space for 00:01:0 reg 0x88 > > > ======================================== > > Here the output of flashrom -VE : > > flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci > 3.1.7, GCC 4.6.1, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 729M loops per > second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 990 us, 10000 myus = > 9955 us, 4 myus = 5 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Acer" > DMI string system-product-name: "Aspire T180" > DMI string system-version: "R01-A2" > DMI string baseboard-manufacturer: "Acer" > DMI string baseboard-product-name: "EM61SM/EM61PM " > DMI string baseboard-version: " " > DMI string chassis-type: "Desktop" > Found ITE Super I/O, ID 0x8726 on port 0x2e > Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... This chipset is not really supported yet. > Guesswork... > ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 > Flash bus type is LPC > Found SMBus device 10de:03eb at 00:01:1 > MCP SPI BAR is at 0x00000000 > MCP SPI is not used. > Please send the output of "flashrom -V" to flashrom(a)flashrom.org with > your board name: flashrom -V as the subject to help us finish support for > your > chipset. Thanks. > OK. > This chipset supports the following protocols: LPC. > Super I/O ID 0x8726 is not on the list of flash capable controllers. > Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50, > id1 is normal flash content > Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50, > id1 is normal flash content > Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50, > id1 is normal flash content > Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Found SST flash chip "SST49LF040B" (512 kB, LPC) at physical address > 0xfff80000. > Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing > information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 > 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash > content > > Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is > normal flash content, id2 is normal flash content > Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is > normal flash content, id2 is normal flash content > Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 > 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2 > 0x50, id1 is normal flash content > === > This flash part has status UNTESTED for operations: WRITE > The test status of this chip may have been updated in the latest development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above > operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, -Vr, > -Vw, -VE), and mention which mainboard or programmer you tested. > Please mention your board in the subject line. Thanks for your help! > Erasing and writing flash chip... Trying erase function 0... > 0x000000-0x000fff:E, 0x001000-0x001fff:E, 0x002000-0x002fff:E, > 0x003000-0x003fff:E, 0x004000-0x004fff:E, 0x005000-0x005fff:E, > 0x006000-0x006fff:E, 0x007000-0x007fff:E, 0x008000-0x008fff:E, > 0x009000-0x009fff:E, 0x00a000-0x00afff:E, 0x00b000-0x00bfff:E, > 0x00c000-0x00cfff:E, 0x00d000-0x00dfff:E, 0x00e000-0x00efff:E, > 0x00f000-0x00ffff:E, 0x010000-0x010fff:E, 0x011000-0x011fff:E, > 0x012000-0x012fff:E, 0x013000-0x013fff:E, 0x014000-0x014fff:E, > 0x015000-0x015fff:E, 0x016000-0x016fff:E, 0x017000-0x017fff:E, > 0x018000-0x018fff:E, 0x019000-0x019fff:E, 0x01a000-0x01afff:E, > 0x01b000-0x01bfff:E, 0x01c000-0x01cfff:E, 0x01d000-0x01dfff:E, > 0x01e000-0x01efff:E, 0x01f000-0x01ffff:E, 0x020000-0x020fff:E, > 0x021000-0x021fff:E, 0x022000-0x022fff:E, 0x023000-0x023fff:E, > 0x024000-0x024fff:E, 0x025000-0x025fff:E, 0x026000-0x026fff:E, > 0x027000-0x027fff:E, 0x028000-0x028fff:E, 0x029000-0x029fff:E, > 0x02a000-0x02afff:E, 0x02b000-0x02bfff:E, 0x02c000-0x02cfff:E, > 0x02d000-0x02dfff:E, 0x02e000-0x02efff:E, 0x02f000-0x02ffff:E, > 0x030000-0x030fff:E, 0x031000-0x031fff:E, 0x032000-0x032fff:E, > 0x033000-0x033fff:E, 0x034000-0x034fff:E, 0x035000-0x035fff:E, > 0x036000-0x036fff:E, 0x037000-0x037fff:E, 0x038000-0x038fff:E, > 0x039000-0x039fff:E, 0x03a000-0x03afff:E, 0x03b000-0x03bfff:E, > 0x03c000-0x03cfff:E, 0x03d000-0x03dfff:E, 0x03e000-0x03efff:E, > 0x03f000-0x03ffff:E, 0x040000-0x040fff:E, 0x041000-0x041fff:E, > 0x042000-0x042fff:E, 0x043000-0x043fff:E, 0x044000-0x044fff:E, > 0x045000-0x045fff:E, 0x046000-0x046fff:E, 0x047000-0x047fff:E, > 0x048000-0x048fff:E, 0x049000-0x049fff:E, 0x04a000-0x04afff:E, > 0x04b000-0x04bfff:E, 0x04c000-0x04cfff:E, 0x04d000-0x04dfff:E, > 0x04e000-0x04efff:E, 0x04f000-0x04ffff:E, 0x050000-0x050fff:E, > 0x051000-0x051fff:E, 0x052000-0x052fff:E, 0x053000-0x053fff:E, > 0x054000-0x054fff:E, 0x055000-0x055fff:E, 0x056000-0x056fff:E, > 0x057000-0x057fff:E, 0x058000-0x058fff:E, 0x059000-0x059fff:E, > 0x05a000-0x05afff:E, 0x05b000-0x05bfff:E, 0x05c000-0x05cfff:E, > 0x05d000-0x05dfff:E, 0x05e000-0x05efff:E, 0x05f000-0x05ffff:E, > 0x060000-0x060fff:E, 0x061000-0x061fff:E, 0x062000-0x062fff:E, > 0x063000-0x063fff:E, 0x064000-0x064fff:E, 0x065000-0x065fff:E, > 0x066000-0x066fff:E, 0x067000-0x067fff:E, 0x068000-0x068fff:E, > 0x069000-0x069fff:E, 0x06a000-0x06afff:E, 0x06b000-0x06bfff:E, > 0x06c000-0x06cfff:E, 0x06d000-0x06dfff:E, 0x06e000-0x06efff:E, > 0x06f000-0x06ffff:E, 0x070000-0x070fff:E, 0x071000-0x071fff:E, > 0x072000-0x072fff:E, 0x073000-0x073fff:E, 0x074000-0x074fff:E, > 0x075000-0x075fff:E, 0x076000-0x076fff:E, 0x077000-0x077fff:E, > 0x078000-0x078fff:E, 0x079000-0x079fff:E, 0x07a000-0x07afff:E, > 0x07b000-0x07bfff:E, 0x07c000-0x07cfff:E, 0x07d000-0x07dfff:E, > 0x07e000-0x07efff:E, 0x07f000-0x07ffff:E > Erase/write done. The chip is now erased, it doesn't contain BIOS/(U)EFI software anymore. > > Restoring PCI config space for 00:01:0 reg 0x6d > Restoring PCI config space for 00:01:0 reg 0x90 > Restoring PCI config space for 00:01:0 reg 0x8c > Restoring PCI config space for 00:01:0 reg 0x88 > > > =================================================== > > If you want the output of another command, please ask me > I finally flash my bios with a windows live disk so i don't want to take > anyu risk but i want help Please do not reboot as your machine may have to be sent in for repair. Unless you have made a backup readout file, we will supply a link for the right BIOS rom. > > > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom

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Re: [flashrom] flashrom -V
by Stefan Tauner 11 Jan '12

11 Jan '12

On Fri, 6 Jan 2012 14:12:18 +0100 Vince S <vince06fr(a)gmail.com> wrote: > probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal > flash content, id2 is normal flash content > Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 > is normal flash content, id2 is normal flash content > Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 > is normal flash content, id2 is normal flash content > Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 > 0xff, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Found SST flash chip "SST49LF040B" (512 kB, LPC). > No operations were specified. > Restoring PCI config space for 00:01:0 reg 0x6d > Restoring PCI config space for 00:01:0 reg 0x90 > Restoring PCI config space for 00:01:0 reg 0x8c > Restoring PCI config space for 00:01:0 reg 0x88 > > > Thanks for your work hey there! thanks for your slightly mangled report ;) could you please resend the whole thing if it is still available to you, thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1484 - trunk
by repository service 10 Jan '12

10 Jan '12

Author: hailfinger Date: Wed Jan 11 03:10:11 2012 New Revision: 1484 URL: http://flashrom.org/trac/flashrom/changeset/1484 Log: Postpone layout file reading Layout file reading should happen after option parsing like all other file accesses. Guard against multiple --layout parameters. Followup fix for r1483: Remove -m short option from getopt. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/cli_classic.c Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Wed Jan 4 01:48:27 2012 (r1483) +++ trunk/cli_classic.c Wed Jan 11 03:10:11 2012 (r1484) @@ -177,7 +177,7 @@ enum programmer prog = PROGRAMMER_INVALID; int ret = 0; - static const char optstring[] = "r:Rw:v:nVEfc:m:l:i:p:Lzh"; + static const char optstring[] = "r:Rw:v:nVEfc:l:i:p:Lzh"; static const struct option long_options[] = { {"read", 1, NULL, 'r'}, {"write", 1, NULL, 'w'}, @@ -198,6 +198,7 @@ }; char *filename = NULL; + char *layoutfile = NULL; char *tempstr = NULL; char *pparam = NULL; @@ -273,9 +274,12 @@ force = 1; break; case 'l': - tempstr = strdup(optarg); - if (read_romlayout(tempstr)) + if (layoutfile) { + fprintf(stderr, "Error: --layout specified " + "more than once. Aborting.\n"); cli_classic_abort_usage(); + } + layoutfile = strdup(optarg); break; case 'i': tempstr = strdup(optarg); @@ -373,9 +377,6 @@ cli_classic_abort_usage(); } - if (process_include_args()) - cli_classic_abort_usage(); - /* FIXME: Print the actions flashrom will take. */ if (list_supported) { @@ -390,6 +391,11 @@ } #endif + if (layoutfile && read_romlayout(layoutfile)) + cli_classic_abort_usage(); + if (process_include_args()) + cli_classic_abort_usage(); + /* Does a chip with the requested name exist in the flashchips array? */ if (chip_to_probe) { for (flash = flashchips; flash && flash->name; flash++)

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Re: [flashrom] I lost my backup image and now my pc doesn't start...!
by Stefan Tauner 10 Jan '12

10 Jan '12

On Tue, 10 Jan 2012 07:54:04 +0200 İlhan Kahraman <ilhan805(a)gmail.com> wrote: > Hello, > I think, I exaggerated things a little bit, due to excitement of my > inoperative mother board. The fan of cpu is working. I noticed that the > fans are working, in my latter flashing attempts, which I tried later than > I e-mailed you. The problem is that it is rotating in a very low constant > rpm. hi again, hm... doesnt the fan spin up fully at power-on first and is then throttled down afterwards (by software)? this is usually done because not all fans have the same start up voltage. some start at 6V or even less, others need more than 10V (even if they continue spinning at lower levels after getting to speed once). this shouldnt be different even for 4-pin fans i think... > I am sorry about that misleading e-mail :( > if I am not bothering you, would I continue to share my adventure with you? > is the aim of this mailing group, that? well as long as it is related to flashrom, it is right. not sure if everyone subscribed to the list (>200 ppl) is interested in personal recovery stories though :) if you find a solution for your problem that might be interesting for others too, i'd love to hear it! good luck -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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ASRock AM2NF6G-VSTA (Nvidia MCP61): `flashrom -Vr` (r1483)
by Paul Menzel 10 Jan '12

10 Jan '12

Dear Flashrom folks, I tested the ASRock AM2NF6G-VSTA with an Nvidia MCP61 chipset. The output says, that the chipset is not fully supported so please tell me what I have to consider when testing writing. $ flashrom -V -r am2nf6g-vsta.bin […] DMI string system-manufacturer: "To Be Filled By O.E.M." DMI string system-product-name: "To Be Filled By O.E.M." DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: " " DMI string baseboard-product-name: "AM2NF6G-VSTA" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0x40000000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. The following protocols are supported: LPC. […] Reading seems to work. The difference between the read image to the downloaded file (1.20) from the ASRock [2] is minimal according to `bsdiff`. 00000000 42 53 44 49 46 46 34 30 42 00 00 00 00 00 00 00 2D 00 00 00 00 00 00 00 00 00 08 00 BSDIFF40B.......-........... 0000001C 00 00 00 00 42 5A 68 39 31 41 59 26 53 59 59 02 DA 4C 00 00 0E EC 41 71 38 00 20 01 ....BZh91AY&SYY..L....Aq8. . 00000038 00 40 00 40 20 01 00 20 00 31 00 D0 00 C5 32 19 36 A2 B1 39 12 48 15 EA BC D8 B4 74 .@.@ .. .1....2.6..9.H.....t 00000054 E8 C2 6F E2 EE 48 A7 0A 12 0B 20 5B 49 80 42 5A 68 39 31 41 59 26 53 59 35 50 66 AE ..o..H.... [I.BZh91AY&SY5Pf. 00000070 00 04 04 40 00 C4 00 00 08 20 00 30 CC 05 29 A6 10 0D 88 80 78 BB 92 29 C2 84 81 AA ...@..... .0..).....x..).... 0000008C 83 35 70 42 5A 68 39 17 72 45 38 50 90 00 00 00 00 .5pBZh9.rE8P..... Please find all log files attached. Thanks, Paul [1] http://www.asrock.com/MB/overview.asp?Model=AM2NF6G-VSTA [2] http://www.asrock.com/mb/download.asp?Model=AM2NF6G-VSTA&o=BIOS

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[PATCH] add support for SFDP (JESD216)
by Stefan Tauner 10 Jan '12

10 Jan '12

Similar to ICH Hardware Sequencing this uses a generic struct flashchip element in flashchips.c with dummy values and a special probe function that fills the obtained values into that generic struct. Documentation used: http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) W25Q32BV data sheet Revision F (2011-04-01) EN25QH16 data sheet Revision F (2011-06-01) todo: - handle programmers which have a problem with the dummy bytes needed - move the code from spi25.c to its own file - rephrase the 'default' message of get_erasefn_from_opcode so that it becomes universally usable? Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 1 + flash.h | 2 + flashchips.c | 24 ++++ flashchips.h | 1 + flashrom.c | 28 +++++- spi.h | 5 + spi25.c | 355 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 415 insertions(+), 1 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index a1d0cd9..bbc403f 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -28,6 +28,7 @@ #include "flash.h" /* for chipaddr and flashctx */ /* spi.c, should probably be in spi_chip.c */ +int probe_spi_sfdp(struct flashctx *flash); int probe_spi_rdid(struct flashctx *flash); int probe_spi_rdid4(struct flashctx *flash); int probe_spi_rems(struct flashctx *flash); diff --git a/flash.h b/flash.h index e51b6d4..6bcae71 100644 --- a/flash.h +++ b/flash.h @@ -174,6 +174,8 @@ struct flashctx { struct registered_programmer *pgm; }; +typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + #define TEST_UNTESTED 0 #define TEST_OK_PROBE (1 << 0) diff --git a/flashchips.c b/flashchips.c index ca1c57f..f0fde20 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8872,6 +8872,30 @@ const struct flashchip flashchips[] = { .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, + + { + .vendor = "Unknown", + .name = "SFDP device", + .bustype = BUS_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = SFDP_DEVICE_ID, + /* We present our own "report this" text hence we do not + * want the default "This flash part has status UNTESTED..." + * text to be printed. */ + .tested = TEST_OK_PREW, + .probe = probe_spi_sfdp, + .read = spi_chip_read, + /* FIXME: some vendor extensions define this */ + .voltage = {}, + /* Everything below will be set by the probing function. */ + .page_size = 0, + .write = NULL, + .total_size = 0, + .feature_bits = 0, + .block_erasers = {}, + .unlock = NULL, + .printlock = NULL, + }, { .vendor = "Programmer", diff --git a/flashchips.h b/flashchips.h index 03efb86..1f2a8ca 100644 --- a/flashchips.h +++ b/flashchips.h @@ -36,6 +36,7 @@ #define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */ #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ +#define SFDP_DEVICE_ID 0xfffe #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define ALLIANCE_AS29F002B 0x34 diff --git a/flashrom.c b/flashrom.c index f1a6165..38998dd 100644 --- a/flashrom.c +++ b/flashrom.c @@ -986,7 +986,33 @@ int probe_flash(struct registered_programmer *pgm, int startchip, * probe_flash() is the first one and thus no chip has been * found before. */ - if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) + if (startchip == 0 && fill_flash->model_id == SFDP_DEVICE_ID) { + msg_cinfo("===\n" + "SFDP has autodetected a flash chip which is " + "not natively supported by flashrom yet.\n"); + if (count_usable_erasers(fill_flash) == 0) + msg_cinfo("The standard operations read and " + "verify should work, but to support " + "erase, write and all other " + "possible features"); + else + msg_cinfo("All standard operations (read, " + "verify, erase and write) should " + "work, but to support all possible " + "features"); + + msg_cinfo(" we need to add them manually.\nYou " + "can help us by mailing us the output of " + "the following command to flashrom@flashrom." + "org: \n'flashrom -VV [plus the " + "-p/--programmer parameter (if needed)]" + "'\nThanks for your help!\n" + "===\n"); + } + + if (startchip == 0 || + ((fill_flash->model_id != GENERIC_DEVICE_ID) && + (fill_flash->model_id != SFDP_DEVICE_ID))) break; notfound: diff --git a/spi.h b/spi.h index b908603..5f07eae 100644 --- a/spi.h +++ b/spi.h @@ -40,6 +40,11 @@ #define JEDEC_REMS_OUTSIZE 0x04 #define JEDEC_REMS_INSIZE 0x02 +/* Read Serial Flash Discoverable Parameters (SFDP) */ +#define JEDEC_SFDP 0x5a +#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */ +/* JEDEC_SFDP_INSIZE : any length */ + /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 diff --git a/spi25.c b/spi25.c index 3ce7f08..07c716a 100644 --- a/spi25.c +++ b/spi25.c @@ -23,6 +23,7 @@ */ #include <string.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -115,6 +116,360 @@ int spi_write_disable(struct flashctx *flash) return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); } +static int spi_sfdp_wrapper(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) +{ + int i, ret; + const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { + JEDEC_SFDP, + (address >> 16) & 0xff, + (address >> 8) & 0xff, + (address >> 0) & 0xff, + 0 + }; + msg_cspew("spi_sfdp_wrapper: addr=0x%x, len=%d, data:\n", address, len); + ret = spi_send_command(flash, sizeof(cmd), len, cmd, buf); + for (i = 0; i < len; i++) + msg_cspew(" 0x%02x", buf[i]); + msg_cspew("\n"); + return ret; +} + +/* FIXME: eventually something similar like this but more generic should be + * available to split up spi commands. use that then instead */ +static int spi_sfdp(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) +{ + /* FIXME: this is wrong. */ + int maxstep = 8; + int ret = 0; + while (len > 0) { + int step = min(len, maxstep); + ret = spi_sfdp_wrapper(flash, address, buf, step); + if (ret) + return ret; + address += step; + buf += step; + len -= step; + } + return ret; +} + +struct sfdp_tbl_hdr { + uint8_t id; + uint8_t v_minor; + uint8_t v_major; + uint8_t len; + uint32_t ptp; /* 24b pointer */ +}; + +static int (*get_erasefn_from_opcode(uint8_t opcode)) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen) +{ + switch(opcode){ + case 0x00: + case 0xff: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x20: + return &spi_block_erase_20; + break; + case 0x52: + return &spi_block_erase_52; + break; + case 0x60: + return &spi_block_erase_60; + break; + case 0xc7: + return &spi_block_erase_c7; + break; + case 0xd7: + return &spi_block_erase_d7; + break; + case 0xd8: + return &spi_block_erase_d8; + default: + msg_cinfo("%s: unknown opcode (0x%02x) in SFDP table. " + "Please report this at " + "flashrom(a)flashrom.org\n", + __func__, opcode); + return NULL; + } +} + +static int sfdp_fill_flash(struct flashctx *f, uint8_t *buf, uint16_t len) +{ + uint32_t tmp32; + uint8_t tmp8; + uint32_t total_size; /* in bytes */ + uint32_t bsize; + uint8_t opcode_4k = 0xFF; + int dw, j; + int (*erasefn) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); + + + msg_cdbg2("Parsing JEDEC SFDP parameter table...\n"); + if (len == 9 * 4) { + msg_cerr("%s: len out of spec\n", __func__); + return 1; + } + + /* 1. double word */ + dw = 0; + tmp32 = buf[(4 * dw) + 0]; + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; + + tmp8 = (tmp32 >> 17) & 0x3; + switch (tmp8) { + case 0x0: + msg_cdbg2(" 3-Byte only addressing.\n"); + break; + case 0x1: + msg_cdbg2(" 3-Byte (and optionally 4-Byte) addressing.\n"); + break; + case 0x2: + msg_cdbg(" 4-Byte only addressing not supported.\n"); + return 1; + default: + msg_cdbg(" Required addressing mode (0x%x) not supported.\n", + tmp8); + return 1; + } + + msg_cdbg2(" Writes to the status register have "); + if (tmp32 & (1 << 3)) { + f->unlock = spi_disable_blockprotect; + msg_cdbg2("to be enabled with "); + if (tmp32 & (1 << 4)) { + f->feature_bits = FEATURE_WRSR_WREN; + msg_cdbg2("WREN (0x06).\n"); + } else { + f->feature_bits = FEATURE_WRSR_EWSR; + msg_cdbg2("EWSR (0x50).\n"); + } + } else + msg_cdbg2("not to be especially enabled.\n"); + + msg_cdbg2(" Write granularity is "); + if (tmp32 & (1 << 2)) { + msg_cdbg2(" at least 64 B.\n"); + f->page_size = 64; + f->write = spi_chip_write_256; + } else { + msg_cdbg2(" 1 B only.\n"); + f->page_size = 256; /* ? */ + f->write = spi_chip_write_1; + } + + if ((tmp32 & 0x3) == 0x1) { + opcode_4k = (tmp32 >> 8) & 0xFF; /* will be dealt with later */ + } + + /* 2. double word */ + dw = 1; + tmp32 = buf[(4 * dw) + 0]; + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; + + if (tmp32 & (1 << 31)) { + msg_cdbg(" Flash chip size >= 4 Gb/500 MB not supported.\n"); + return 1; + } + total_size = (tmp32 & 0x7FFFFFFF) / 8; + f->total_size = total_size / 1024; + msg_cdbg2(" Flash chip size is %d kB.\n", f->total_size); + + dw = 8; + for(j = 0; j < 4; j++) { + /* 8 double words from the start + 2 words for every eraser */ + tmp32 = buf[(4 * dw) + (2 * j)]; + if (tmp32 == 0) { + msg_cdbg2(" Block eraser %d is unused.\n", j); + continue; + } + if (tmp32 >= 31) { + msg_cdbg2(" Block size of eraser %d (2^%d) is too big." + "\n", j, tmp32); + continue; + } + bsize = 1 << (tmp32); /* bsize = 2 ^ field */ + + tmp8 = buf[(4 * dw) + (2 * j) + 1]; + erasefn = get_erasefn_from_opcode(tmp8); + if (erasefn == NULL) + continue; + f->block_erasers[j].block_erase = erasefn; + f->block_erasers[j].eraseblocks[0].size = bsize; + f->block_erasers[j].eraseblocks[0].count = total_size/bsize; + msg_cdbg2(" Block eraser %d: %d x %d B with opcode 0x%02x\n", + j, total_size/bsize, bsize, tmp8); + /* If there is a valid 4k value in the last double words, + * we override the value from double word 1. */ + if (bsize == 4 * 1024) + opcode_4k = 0xFF; + } + if (opcode_4k != 0xFF && + ((erasefn = get_erasefn_from_opcode(opcode_4k)) != NULL)) { + for (j = 0; j < NUM_ERASEFUNCTIONS; j++) { + struct block_eraser eraser = f->block_erasers[j]; + if (eraser.eraseblocks[0].size != 0) + continue; + eraser.block_erase = erasefn; + eraser.eraseblocks[0].size = 4 * 1024; + eraser.eraseblocks[0].count = total_size/bsize; + msg_cdbg2(" Block eraser %d: %d x %d B with opcode " + "0x%02x\n", j, total_size/bsize, bsize, + opcode_4k); + break; + } + msg_cinfo("%s: Not enough space to store another eraser (j=%d)." + " Please report this at flashrom(a)flashrom.org\n", + __func__, j); + } + return 0; +} + +static int sfdp_fetch_pt(struct flashctx *flash, uint32_t addr, uint8_t *buf, uint16_t len) +{ + uint16_t i; + if (spi_sfdp(flash, addr, buf, len)) { + msg_cerr("Receiving SFDP parameter table failed.\n"); + return 1; + } + msg_cspew(" Parameter table contents:\n"); + for(i = 0; i < len; i++) { + if ((i % 8) == 0) { + msg_cspew(" 0x%03x: ", i); + } + msg_cspew(" 0x%02x", buf[i]); + if ((i % 8) == 7) { + msg_cspew("\n"); + continue; + } + if ((i % 8) == 3) { + msg_cspew(" "); + continue; + } + } + msg_cspew("\n"); + return 0; +} + +int probe_spi_sfdp(struct flashctx *flash) +{ + int ret = 0; + uint8_t buf[8]; + uint16_t tmp16; + uint32_t tmp32; + uint8_t nph; + /* need to limit the table loop by comparing i to uint8_t nph hence: */ + uint16_t i; + struct sfdp_tbl_hdr *hdrs; + uint8_t *hbuf; + uint8_t *tbuf; + + if (spi_sfdp(flash, 0x00, buf, 4)) { + msg_cerr("Receiving SFDP signature failed.\n"); + return 0; + } + tmp32 = buf[0]; + tmp32 |= ((unsigned int)buf[1]) << 8; + tmp32 |= ((unsigned int)buf[2]) << 16; + tmp32 |= ((unsigned int)buf[3]) << 24; + + msg_cdbg2("SFDP signature = 0x%08x (should be 0x50444653)\n", tmp32); + if (tmp32 != 0x50444653) { + msg_cdbg("No SFDP signature found.\n"); + return 0; + } + if (spi_sfdp(flash, 0x04, buf, 3)) { + msg_cerr("Receiving SFDP revision and number of parameter " + "headers (NPH) failed. "); + return 0; + } + msg_cdbg2("SFDP revision = %d.%d\n", buf[1], buf[0]); + nph = buf[3]; + msg_cdbg2("SFDP number of parameter headers (NPH) = %d (+ 1 mandatory)" + "\n", nph); + + /* Fetch all parameter headers, even if we don't use them all (yet). */ + hbuf = malloc(sizeof(struct sfdp_tbl_hdr) * (nph + 1)); + hdrs = malloc((nph + 1) * 8); + if (hbuf == NULL || hdrs == NULL ) { + msg_gerr("Out of memory!\n"); + exit(1); /* FIXME: shutdown gracefully */ + } + if (spi_sfdp(flash, 0x08, hbuf, (nph + 1) * 8)) { + msg_cerr("Receiving SFDP parameter table headers failed.\n"); + goto cleanup_hdrs; + } + + i = 0; + do{ + hdrs[i].id = hbuf[(8 * i) + 0]; + hdrs[i].v_minor = hbuf[(8 * i) + 1]; + hdrs[i].v_major = hbuf[(8 * i) + 2]; + hdrs[i].len = hbuf[(8 * i) + 3]; + hdrs[i].ptp = hbuf[(8 * i) + 4]; + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; + msg_cdbg2("SFDP parameter table header %d/%d:\n", i, nph); + msg_cdbg2(" ID 0x%02x, version %d.%d\n", hdrs[i].id, + hdrs[i].v_major, hdrs[i].v_minor); + tmp16 = hdrs[i].len * 4; + tmp32 = hdrs[i].ptp; + msg_cdbg2(" Length %d B, Parameter Table Pointer 0x%06x\n", + tmp16, tmp32); + + if (tmp16 + tmp32 > UINT16_MAX) { + msg_cerr("SFDP Parameter Table %d supposedly " + "overflows addressable SFDP area. This most\n" + "probably indicates a corrupt SFDP parameter " + "table header. Aborting SFDP probe!\n", i); + ret = 0; + goto cleanup_hdrs; + } + + tbuf = malloc(tmp16); + if (tbuf == NULL) { + msg_gerr("Out of memory!\n"); + exit(1); /* FIXME: shutdown gracefully */ + } + if (sfdp_fetch_pt(flash, tmp32, tbuf, tmp16)){ + msg_cerr("Fetching SFDP parameter table %d failed.\n", + i); + free(tbuf); + break; + } + if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ + if (hdrs[i].id != 0) + msg_cdbg("ID of the mandatory JEDEC SFDP " + "parameter table is not 0 as demanded " + "by JESD216 (warning only).\n"); + + if (hdrs[i].len != (9 * 4)) { + msg_cdbg("Length of the mandatory JEDEC SFDP " + "parameter table is not 24 B as " + "demanded by JESD216.\n"); + if (hdrs[i].len == (4 * 4)) + msg_cdbg("It seems like it is the " + "preliminary Intel version of " + "SFDP, which we don't support." + "\n"); + } else if (sfdp_fill_flash(flash, tbuf, tmp16) == 0) + ret = 1; + } + + free(tbuf); + i++; + } while(i <= nph); + +cleanup_hdrs: + free(hdrs); + free(hbuf); + return ret; +} + static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) { unsigned char readarr[4]; -- 1.7.1

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[PATCH 0/1] SFDP 2.2
by Stefan Tauner 10 Jan '12

10 Jan '12

just a few minor changes: - added a wrapper around the spi sends that aids debugging now and extending later - better error handling: previous version had a possible infinite loop. also, we now abort on particularly fishy data. - added a typedef for erase functions. sadly it can not be used in struct flashchip/ctx due to circular dependencies Stefan Tauner (1): add support for SFDP (JESD216) chipdrivers.h | 1 + flash.h | 2 + flashchips.c | 24 ++++ flashchips.h | 1 + flashrom.c | 28 +++++- spi.h | 5 + spi25.c | 355 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 415 insertions(+), 1 deletions(-)

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Re: [flashrom] Help: unable to upgrade bios
by David Hendricks 10 Jan '12

10 Jan '12

On Mon, Jan 9, 2012 at 3:20 AM, Raghuramchary Jallipalli < Raghuramchary.Jallipalli(a)lntinfotech.com> wrote: > Thanks David.**** > > As you said, the reason for not programming is due to wrong op.atomic > configuration. Is there any way to set these properly? > It should be set automatically. Carl-Daniel clarified on IRC that the "atomic" cycle flag will always be 0 at the stage they are printed. Sorry for the confusion! I recommend adding a debug print to ich9_run_opcode() to see what the "atomic" flag ends up being: Index: ichspi.c =================================================================== --- ichspi.c (revision 1483) +++ ichspi.c (working copy) @@ -908,6 +908,7 @@ This means the timeout must be sufficient for chip erase of slow high-capacity chips. */ + msg_pdbg("opcode: 0x%02x, spi_type: %u, atomic: %u\n", op.opcode, op.spi_type, op.atomic); switch (op.atomic) { case 2: /* Select second preop. */ Then run "flashrom -V -p internal:this_is_not_a_laptop -r foo.bin" and make sure that the sector erase opcode (0x20) and byte program opcode (0x02) show either "1" or "2" for op.atomic. This will help us to prove whether or not this is the problem you are encountering. **** > > Yes jumper selects the ROM at a time. > Okay. I do not think Flashrom is confused about the flash part, then. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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ASUS M2V-MX SE: Can Winbond flash chip W39V040B (512 kB, LPC) be used?
by Paul Menzel 10 Jan '12

10 Jan '12

Dear Flashrom folks, I got two spare boards with socketed flash chips and hope they can be used also for the ASUS M2V-MX SE which is supported by coreboot [1]. One board is the ASRock AM2NF6G-VSTA with a Winbond flash chip W39V040B (512 kB, LPC) [3]. Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xda, id2 0x54 Found Winbond flash chip "W39V040B" (512 kB, LPC). This output says LPC but the shipped flash chip in the ASUS M2V-MX SE seems to be SPI [2]. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "AMIC A25L40P" (512 KB, SPI) at physical address 0xfff80000. In my board there is the Macronix flash chip MX25L4005 (512 kB, SPI). $ sudo ./flashrom flashrom v0.9.4-r1483 on Linux 3.1.0-1-amd64 (x86_64), built with libpci 3.1.8, GCC 4.6.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "VIA VT8237S". Enabling flash write... Mapping VT8237S MMIO registers at 0xfed02000, unaligned size 0x70. OK. Found Macronix flash chip "MX25L4005" (512 kB, SPI) at physical address 0xfff80000. No operations were specified. So the vendor flash chip is SPI but it says the chipset also supports LPC. Is such a socket universal so that I can use the LPC flash chip Winbond W39V040B? Thanks, Paul [1] http://www.asus.com/Product.aspx?P_ID=rO7Bu9kq3D25tXHl&content=specificatio… [2] http://www.coreboot.org/ASUS_M2V-MX_SE [3] http://www.flashrom.org/pipermail/flashrom/2012-January/008512.html

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Re: [flashrom] I lost my backup image and now my pc doesn't start...!
by Stefan Tauner 09 Jan '12

09 Jan '12

On Sun, 8 Jan 2012 16:33:54 +0200 İlhan Kahraman <ilhan805(a)gmail.com> wrote: > It has not respond anything after that, not even any fan has cycled... hello İlhan, your whole story sounds to me a bit like if the hardware has broken coincidentally at the same moment as you wrote to the flash chip. Not starting the fans at power-up is a quite uncommon symptom because normally this is not handled by the host software. if i understood your mails correctly you have re-used the rest of the hardware with the new board and everything works? IMHO the only things that could make the fans not spin are: - broken power supply and/or connections - broken mainboard (voltage regulators, traces, capacitors etc) - shorts by lost screws etc. - broken/dusted or unconnected fan :) i guess this wont help you much, but besides the steps you tried already, i dont know anything either, sorry. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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