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Kombi aus Leder und Holz
by Die Office Einrichter 10 Aug '21

10 Aug '21

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Quotation Request
by Natalia Chernenko | Supply Chain Analyst 10 Aug '21

10 Aug '21

Good day, I tried calling your offline line yesterday, and earlier today, but couldn't get through. Please can you kindly check our attached request for an urgent quote of your products. We are a bit behind schedule on our delivery time and would appreciate it if you can treat this quotation request with priority. Hoping to hear from you soon. Kind regards, Natalia Natalia Chernenko | Supply Chain Analyst Lasante Vital SA 1st Km Markopoulou-Kalyvion , Kalivia ,Attica GR 19010 Greece , tel : +30 290 451 111 Fax: +30 229ewr0 61 443

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More detailed tests with the JTAG-lock-pick Tiny 2
by Denis 'GNUtoo' Carikli 03 Aug '21

03 Aug '21

Hi, I've tried to make the Distortec JTAG-lock-pick Tiny 2[1][2] work with flashrom and for some reason it always read the same thing. Back in April there was also a thread about it[0], but not much details were shared about the setup, so since I tried things, I also took the occasion to try to share them here. The JTAG-lock-pick Tiny 2 connector is similar to the one of the Olimex ARM-USB-TINY that is described in the wiki[3]. Even if the connector is the same, there are some differences between both hardware designs: - On the JTAG-lock-pick Tiny 2, VREF and VTARGET are connected together according to its schematics that are in its manual[4]. - Users are supposed to connect a reference voltage to any of these two pins (VREF and VTARGET). - The pins 17 and 19 are not connected (NC) at all. - The JTAG-lock-pick Tiny 2 uses an FTD232HL chip (among with other chips like a CPLD and some chips to isolate the target device from it). I've made the following patch to try to use it: diff --git a/ft2232_spi.c b/ft2232_spi.c index e32d7f81..d986e0a2 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -38,6 +38,7 @@ #define FTDI_FT2232H_PID 0x6010 #define FTDI_FT4232H_PID 0x6011 #define FTDI_FT232H_PID 0x6014 +#define DISTORTEC_JTAG_LOCK_PICK_TINY_2_PID 0x8220 #define TIAO_TUMPA_PID 0x8a98 #define TIAO_TUMPA_LITE_PID 0x8a99 #define AMONTEC_JTAGKEY_PID 0xCFF8 @@ -66,6 +67,7 @@ static const struct dev_entry devs_ft2232spi[] = { {FTDI_VID, TIAO_TUMPA_PID, OK, "TIAO", "USB Multi-Protocol Adapter"}, {FTDI_VID, TIAO_TUMPA_LITE_PID, OK, "TIAO", "USB Multi-Protocol Adapter Lite"}, {FTDI_VID, AMONTEC_JTAGKEY_PID, OK, "Amontec", "JTAGkey"}, + {FTDI_VID, DISTORTEC_JTAG_LOCK_PICK_TINY_2_PID, OK, "Distortec", "JTAG-lock-pick"}, {GOEPEL_VID, GOEPEL_PICOTAP_PID, OK, "GOEPEL", "PicoTAP"}, {GOOGLE_VID, GOOGLE_SERVO_PID, OK, "Google", "Servo"}, {GOOGLE_VID, GOOGLE_SERVO_V2_PID0, OK, "Google", "Servo V2 Legacy"}, @@ -350,6 +352,13 @@ static int ft2232_spi_init(void) ft2232_vid = GOEPEL_VID; ft2232_type = GOEPEL_PICOTAP_PID; channel_count = 2; + } else if (!strcasecmp(arg, "JTAG-lock-pick")) { + ft2232_type = DISTORTEC_JTAG_LOCK_PICK_TINY_2_PID; + /* It contains an FTD232HL chip. Its datasheet has + * "FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE + * UART/FIFO IC" + */ + channel_count = 1; } else if (!strcasecmp(arg, "tumpa")) { /* Interface A is SPI1, B is SPI2. */ ft2232_type = TIAO_TUMPA_PID; I've connected it in the same way described in the wiki for the Olimex ARM-USB-TINY[3], with wires that are about 10 centimeters, and I've provided 3.3v on VREF/VTARGET. When doing that flashrom always reads 0xff: > ./flashrom -p ft2232_spi:type=JTAG-lock-pick,divisor=131072 --verbose > [...] > Probing for Sanyo unknown Sanyo SPI chip, 0 kB: RDID byte 0 > parity violation. compare_id: id1 0xff, id2 0xffff > Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: RDID > byte 0 parity violation. compare_id: id1 0xff, id2 0xffff > Probing for Generic Variable Size SPI chip, 64 kB: Probing for Generic > unknown SPI chip (RDID), 0 kB: RDID byte 0 parity violation. > compare_id: id1 0xff, id2 0xffff > Probing for Generic unknown SPI chip (REMS), 0 kB: compare_id: > id1 0xff, id2 0xff > No EEPROM/flash device found. > Note: flashrom can never write if the flash chip isn't found > automatically. > Releasing I/Os If instead I remove the power source, flashrom always reads zeros (0x00) instead of ones (0xff). If I go to about 1volt, flashrom still reads 0xff. That device is also supported by openocd and there I managed to use it to reprogram a microcontroller through SWD. With the same connection, on an openmoko debug board (connecting the 3.3v source to VTARGET), I get the following result: > ./flashrom -p ft2232_spi:type=openmoko,divisor=131072 --verbose > Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: > compare_id: id1 0xef, id2 0x4017 > Probing for Generic Variable Size SPI chip, 64 kB: > Probing for Generic unknown SPI chip (RDID), 0 kB: > compare_id: id1 0xef, id2 0x4017 > Probing for Generic unknown SPI chip (REMS), 0 kB: > compare_id: id1 0xef, id2 0x16 > Found Winbond flash chip "W25Q64.V" (8192 kB, SPI). > This chip may contain one-time programmable memory. flashrom cannot > read and may never be able to write it, hence it may not be able to > completely clone the contents of this chip (see man page for > details). > No operations were specified. > Releasing I/Os So something is probably wrong somewhere. Note that in the distribution I use (Parabola i686), the FT232H support seems to be supported in libftdi as when running make in the flashrom source directory I have: > Checking for FTDI support... found. > Checking for FT232H support in libftdi... found. I wonder if there is some easy way to make the JTAG-lock-pick Tiny 2 work, as it is quite small and it also does JTAG and SWD, and it'd probably be more reliable than the Arduino that I use at 3.3v (which also needs a 3.3v power source to run at 3.3v). References: ----------- [0]https://www.mail-archive.com/flashrom@flashrom.org/msg14801.html [1]https://distortec.com/jtag-lock-pick-tiny-2/ [2]https://shop.sysmocom.de/products/jtag-lock-pick-tiny-2 [3]https://www.flashrom.org/FT2232SPI_Programmer#Olimex_ARM-USB-TINY.2F-H_an… [4]https://distortec.com/download/70/ [5]https://ftdichip.com/products/ft232hl/ [6]https://ftdichip.com/wp-content/uploads/2020/07/DS_FT232H.pdf [7]https://www.mail-archive.com/flashrom@flashrom.org/msg14801.html Denis.

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Intel Gemini Lake
by michael harris 02 Aug '21

02 Aug '21

Warning: unexpected second chipset match: "Intel Gemini Lake" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line.Found Winbond flash chip "W25Q128.W" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000 im trying to change write protect it won't let me because it found second chip set sorry if i sound stupid but i bought acerspin311 chromebook because i thought it would be easy enough to get up and running i can't even get a vm to work because of kvm Reguards Nick

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SMM BIOS protection Enabled!
by Munduru Avinash (Europe - iDEAS-ER&D) 28 Jul '21

28 Jul '21

HI, I am working on Intel Denverton c3558 processor and bootloader I am using is Coreboot. For this flashrom utility support is not given. But some how I added this utility. When I tried running this utility. I am getting the following output. ******************************************************************************************************************************** root@CMM2:/mnt# flashrom -p internal -w coreboot-working.rom flashrom v1.2 on Linux 4.19.198-cmm2 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Cannot open file stream for /dev/mtd0 coreboot table found at 0x7f76f000. Found chipset "Intel Denverton". Enabling flash write... Warning: BIOS region SMM protection is enabled! Warning: Setting Bios Control at 0xdc from 0xab to 0x89 failed. New value is 0xab. SPI Configuration is locked down. PR0: Warning: 0x00000000-0x00000fff is read-only. PR1: Warning: 0x00000000-0x00000fff is read-only. PR2: Warning: 0x00000000-0x00000fff is read-only. PR3: Warning: 0x00000000-0x00000fff is read-only. PR4: Warning: 0x00000000-0x00000fff is read-only. At least some flash regions are write protected. For write operations, you should use a flash layout and include only writable regions. See manpage for more details. Enabling hardware sequencing because some important opcode is locked. OK. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Reading old flash chip contents... Transaction error between offset 0x00ccb000 and 0x00ccb03f (= 0x00ccb000 + 63)! FAILED. root@CMM2:/mnt# The Flash chip I am having is N25Q128..3E but it is recognizing as Opaque flash chip. Could you please suggest a solution for this. Regards, Avinash. Sensitivity: Internal & Restricted 'The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments. WARNING: Computer viruses can be transmitted via email. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email. www.wipro.com'

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Unknown SPI Chip for CH341A
by Georg Urff 28 Jul '21

28 Jul '21

Hello, the following Chip is not working with latest verion of flashrom on Ubuntu and CH341A: Issi IS25WP080 DNLE Found Generic flash chip "unkown SPI chip (RDID)" (0kb, SPI) on ch341a_spi This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE Cheers Georg Urff -- Diese E-Mail wurde von Avast Antivirus-Software auf Viren geprüft. https://www.avast.com/antivirus

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Full UEFI firmware install error on AKEMI
by David Horner 27 Jul '21

27 Jul '21

I received the following errors when attempting to install full UEFI firmware. The statements about rebooting conflict with each other too. The first says that a reboot can be done, the second says do not reboot in CAPS. I believe I followed the instructions correctly, all of the checks matched the instructions. Thank you in advance for help with what to do next. Please note that I am not including the many lines that preceded the error lines below. Dave ** Device: Lenovo Ideapad Flex 5 Chromebook (AKEMI) ** Platform: Intel CometLake ** Fw Type: Stock ChromeOS w/RW_LEGACY ** Fw Ver: Google_Akemi.12672.375.0 (12/16/2020) ** Fw WP: Disabled ==================================================== HSFC used for block erasing: HSFC: FGO=1, HSFC=3, WET=0, FDBC=63, SME=0 Transaction error between offset 0x00ad0000 and 0x00ad0fff (= 0x00ad0000 + 4095)! HSFS: FDONE=1, FCERR=1, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=0, FDOPSS=1, FDV=1, FLOCKDN=1 HSFC: FGO=0, HSFC=3, WET=0, FDBC=63, SME=0 ERASE_FAILED FAILED! Uh oh. Erase/write failed. Checking if anything changed. Reading current flash chip contents... 000000-0xffffff:R Reading 16777216 bytes starting at 0x000000. ignoring error when reading 0x0-0xffffff done. Good, writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. FAILED Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. An error occurred flashing the Full ROM firmware. DO NOT REBOOT! Press [Enter] to return to the main menu.

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flashrom -p internal does not work on HP 8200 SFF Elite
by karmo 24 Jul '21

24 Jul '21

Hi Please take a look at the error log. PC is running HP BIOS J01_0233.bin, ME cleaned, HAP bit Set (me_cleaner.py). Chipset: Intel Q67. BIOS Chip is Macronix MX25L6406E. BB and FDO Jumpers are both set on the Mainboard. Can you help me, please? Thank you very much... A. P.

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all 1's - parity violation - No EEPROM/flash device found - compare_id: id1 0xff, id2 0xffff for *every* device tested
by James Feeney 17 Jul '21

17 Jul '21

Where to look for a cause? I have an only partially booting coreboot firmware image on a Geminilake Chromebook, apparently with a bad payload, but the flash device is obviously being read on boot, as can be seen on the AP console. Short version: Chromebook boot can read the flash device, but flashrom, through SuzyQable, only reads all "1's". Have a sparkfun SuzyQable connected to an Arch Linux box, and to the Chromebook. Have the desired result after running on the Cr50 console: > ccd reset factory > ccd testlab enable > ccd open Previously running flashrom from the stock ChromeOS would give 'Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D"'. I have flashrom from both: git clone https://chromium.googlesource.com/chromiumos/third_party/flashrom WARNERROR=no CONFIG_MEC1308=no CONFIG_ENE_LPC=no make and git clone https://chromium.googlesource.com/chromiumos/platform/standalone-hdctools flashrom install These appear to both act exactly the same. Then: sudo ./flashrom -V -p raiden_debug_spi:target=AP results in "No EEPROM/flash device found", where: $ sudo ./flashrom -V -p raiden_debug_spi:target=AP |sed -n 's/.*$compare.*$/\1/p'|sort|uniq compare_id: id1 0xff, id2 0xff compare_id: id1 0xff, id2 0xffff From running flashrom, the Cr50 console says: [10398.332186 enable_spi_pinmux: AP] [10398.445490 usb_spi_board_disable] [10399.512358 AP UART on] [10399.514036 CCD state: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX] [10399.728811 deferred_tpm_rst_isr] [10399.730025 AP on] [10399.730757 tpm_reset_request(0, 0)] [10399.731775 tpm_reset_now(0)] [10399.735335 tpm_init] tpm_manufactured: manufactured [10399.737601 tpm_reset_now: done] [10402.488852 PinWeaver: Loading Tree!] [10402.511275 PinWeaver: Loaded Tree. restart_count = 88] [10402.513121 Skipping commit] [10402.738718 Committing NVMEM changes.] This causes the Chromebook to boot, so then: [10408.218302 power button pressed] [10408.355704 tpm_rst_asserted] [10409.356714 AP off] [10418.538157 AP UART off] [10418.540362 CCD state: UARTEC+TX I2C SPI USBEC+TX] I don't know whether or not there should be a report of "usb_spi_board_enable" being called, but it is conspicuously not seen. If I understand, it appears as if flashrom reads and caches the flash device ID, but is just seeing all "1's". So - where is the problem? ... the flash device? the "pinmux" accessing the flash? the SPI channel? the USB channel? the Cr50? the raiden_debug_spi driver? some Cr50 configuration variable? some nasty hardware problem? I did run-across this odd thread: https://groups.google.com/a/chromium.org/g/chromium-os-discuss/c/yFevUZz9aac where running flashrom first gives "No EEPROM/flash device found", but subsequently reports, in that case, "Found Winbond flash chip "W25Q256JV_M" (32768 kB, SPI) on raiden_debug_spi." But, the reason for the different consecutive responses from flashrom were not explored there. Any thoughts about why the boot process can read the flash device, while flashrom only reads "1's" for the device ID? I did try running flashrom while specifying the device and forcing a read, but again, it just sees all "1's". Thanks James

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Flashrom asked me to do this
by havsfrun＠topchan.eu 17 Jul '21

17 Jul '21

flashrom v1.2 on Linux 5.13.1-1-default (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found SST flash chip "SST25VF016B" (2048 kB, SPI) on ch341a_spi. Reading old flash chip contents... done. Erasing and writing flash chip... FAILED at 0x00000000! Expected=0xff, Found=0x4e, failed byte count from 0x00000000-0x00000fff: 0xfb8 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000003! Expected=0xff, Found=0x7f, failed byte count from 0x00000000-0x00007fff: 0x1e76 ERASE FAILED! Reading current flash chip contents... cb_in: error: LIBUSB_TRANSFER_TIMED_OUT ch341a_spi_spi_send_command: Failed to read 4100 bytes libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 Can't read anymore! Aborting. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Apparently at least some data has changed. Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks!

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