flashrom

flashrom@flashrom.org

8 participants
9164 discussions

Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger 09 Feb '12

09 Feb '12

Hi Mike, On 23.02.2010 05:45, Spangler, Mike T wrote: > I can probe with a continuity tester, but would need to know specific > pin locations to try. Do you have any generic info on doing this? Yes (well, I'd have to write up something), but the solution mentioned by Michael is way easier, so I'll wait until Michael has diagnosed the GPIO settings from the flashrom run on factory BIOS. Regards, Carl-Daniel -- "I do consider assignment statements and pointer variables to be among computer science's most valuable treasures." -- Donald E. Knuth

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Re: [flashrom] FAILED : mcp61sm -am
by Stefan Tauner 09 Feb '12

09 Feb '12

On Thu, 9 Feb 2012 14:03:01 +0100 Vince S <vince06fr(a)gmail.com> wrote: > 0x07f000-0x07ffff:E hm. this last log was with the old, already erased (and partially reprogrammed) chip, right? this is even more astonishing, because the E indicates that flashrom has read that sector and found not yet erased data (i.e. bytes != 0xff), else it would just have skipped it afaics. something is really fishy here, the other guys need to look into it. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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FAILED: AXIOMTEK PICO821 REV:A2-RC
by Recovery.se 09 Feb '12

09 Feb '12

Hello I'm very pleased with flashrom! Hovever we have a problem erasing. I can work around it by running erase (flashrom -E) sevral times and then flash with (flashrom -w <rom>). When I run errase the falure posision moves forward .. "ERASE FAILED at 0x00030000!" "ERASE FAILED at 0x00040000!" "ERASE FAILED at 0x000ef000!" ... Regards Eric Eriksson Recovery.se

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Re: [flashrom] r1394: Acer Aspire E380: FAILED : mcp61sm -am
by Paul Menzel 09 Feb '12

09 Feb '12

Dear Vince, Am Donnerstag, den 09.02.2012, 14:03 +0100 schrieb Vince S: > This is curious because it is always possible to clear the bios : > > vince@Bob:~$ sudo flashrom -VE > flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci > 3.1.7, GCC 4.6.1, little endian > flashrom is free software, get the source code at http://www.flashrom.org I did not follow the thread closely, but is that version not too old? Maybe try the latest revision from the Subversion repository? […] Thanks, Paul

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Re: [flashrom] FAILED : mcp61sm -am
by Stefan Tauner 09 Feb '12

09 Feb '12

On Thu, 9 Feb 2012 08:25:51 +0100 Vince S <vince06fr(a)gmail.com> wrote: > Hi so the output of my attempt to flash is > > sudo flashrom -V -w '/home/vince/Téléchargements/BIOS_R01-C0/61AO615.BIN' > > flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci > 3.1.7, GCC 4.6.1, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 736M loops per > second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1007 us, 10000 myus > = 10003 us, 4 myus = 5 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Acer" > DMI string system-product-name: "Aspire E380" > DMI string system-version: "R01-A2" > DMI string baseboard-manufacturer: "Acer" > DMI string baseboard-product-name: "EM61SM/EM61PM " > DMI string baseboard-version: " " > DMI string chassis-type: "Desktop" > Found ITE Super I/O, ID 0x8726 on port 0x2e > Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... This chipset is not really supported yet. > Guesswork... > ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 > Flash bus type is LPC > Found SMBus device 10de:03eb at 00:01:1 > MCP SPI BAR is at 0xfec80000 > Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI > enabled. > Please send the output of "flashrom -V" to flashrom(a)flashrom.org with > your board name: flashrom -V as the subject to help us finish support for > your > chipset. Thanks. > OK. > This chipset supports the following protocols: LPC. > Super I/O ID 0x8726 is not on the list of flash capable controllers. > Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Found SST flash chip "SST49LF040B" (512 kB, LPC) at physical address > 0xfff80000. > […] > === > This flash part has status UNTESTED for operations: WRITE > The test status of this chip may have been updated in the latest development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above > operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, -Vr, > -Vw, -VE), and mention which mainboard or programmer you tested. > Please mention your board in the subject line. Thanks for your help! > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Trying erase function 0... > 0x000000-0x000fff:W, 0x001000-0x001fff:S, 0x002000-0x002fff:S, > 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, > 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, > 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, > 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, > 0x00f000-0x00ffff:S, 0x010000-0x010fff:W, 0x011000-0x011fff:W, > 0x012000-0x012fff:W, 0x013000-0x013fff:W, 0x014000-0x014fff:W, > 0x015000-0x015fff:W, 0x016000-0x016fff:W, 0x017000-0x017fff:W, > 0x018000-0x018fff:W, 0x019000-0x019fff:W, 0x01a000-0x01afff:W, > 0x01b000-0x01bfff:W, 0x01c000-0x01cfff:W, 0x01d000-0x01dfff:W, > 0x01e000-0x01efff:W, 0x01f000-0x01ffff:W, 0x020000-0x020fff:W, > 0x021000-0x021fff:W, 0x022000-0x022fff:W, 0x023000-0x023fff:W, > 0x024000-0x024fff:W, 0x025000-0x025fff:W, 0x026000-0x026fff:W, > 0x027000-0x027fff:W, 0x028000-0x028fff:W, 0x029000-0x029fff:W, > 0x02a000-0x02afff:W, 0x02b000-0x02bfff:W, 0x02c000-0x02cfff:W, > 0x02d000-0x02dfff:W, 0x02e000-0x02efff:W, 0x02f000-0x02ffff:W, > 0x030000-0x030fff:W, 0x031000-0x031fff:W, 0x032000-0x032fff:W, > 0x033000-0x033fff:W, 0x034000-0x034fff:W, 0x035000-0x035fff:W, > 0x036000-0x036fff:W, 0x037000-0x037fff:W, 0x038000-0x038fff:W, > 0x039000-0x039fff:W, 0x03a000-0x03afff:W, 0x03b000-0x03bfff:W, > 0x03c000-0x03cfff:W, 0x03d000-0x03dfff:W, 0x03e000-0x03efff:W, > 0x03f000-0x03ffff:W, 0x040000-0x040fff:W, 0x041000-0x041fff:W, > 0x042000-0x042fff:W, 0x043000-0x043fff:W, 0x044000-0x044fff:W, > 0x045000-0x045fff:W, 0x046000-0x046fff:W, 0x047000-0x047fff:W, > 0x048000-0x048fff:W, 0x049000-0x049fff:W, 0x04a000-0x04afff:W, > 0x04b000-0x04bfff:W, 0x04c000-0x04cfff:W, 0x04d000-0x04dfff:W, > 0x04e000-0x04efff:W, 0x04f000-0x04ffff:W, 0x050000-0x050fff:W, > 0x051000-0x051fff:W, 0x052000-0x052fff:W, 0x053000-0x053fff:W, > 0x054000-0x054fff:W, 0x055000-0x055fff:W, 0x056000-0x056fff:S, > 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, > 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, > 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, > 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, > 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, > 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, > 0x069000-0x069fff:S, 0x06a000-0x06afff:W, 0x06b000-0x06bfff:W, > 0x06c000-0x06cfff:W, 0x06d000-0x06dfff:W, 0x06e000-0x06efff:W, > 0x06f000-0x06ffff:W, 0x070000-0x070fff:W writing sector at 0x7f28ed976000 > failed! > Reading current flash chip contents... done. Looking for another erase > function. > Trying erase function 1... 0x000000-0x00ffff:S, 0x010000-0x01ffff:S, > 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, > 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:W writing > sector at 0x7f28ed976000 failed! > Looking for another erase function. > No usable erase functions left. > FAILED! > Uh oh. Erase/write failed. Checking if anything changed. > Your flash chip is in an unknown state. > Get help on IRC at irc.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! > ------------------------------------------------------------------------------- > DO NOT REBOOT OR POWEROFF! > Restoring PCI config space for 00:01:0 reg 0x6d > Restoring PCI config space for 00:01:0 reg 0x90 > Restoring PCI config space for 00:01:0 reg 0x8c > Restoring PCI config space for 00:01:0 reg 0x88 that's interesting. it always fails at the same address (0x070000). this is where the boot block protection of that chip begins. the boot block protection is enabled by setting a pin to low and can not be disabled directly by software. usually the pin is connected to a general output pin of the southbridge (or another chip) on the mainboard and can be controlled by that. adding support for this requires some reverse engineering of various difficulty. the interesting question is something different: why were we able to erase that block a month ago... can you confirm that the two chips you are using are the same model? > > what can i do?? since you have a replacement chip, you could just throw the old one away... i would really like to know what happened though. maybe my colleagues can shed some light onto this... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom@ mailing list at Gmane (news:gmane.linux.bios.flashrom)
by Ivan Shmakov 08 Feb '12

08 Feb '12

Apparently, the flashrom@ mailing list traffic isn't properly forwarded to Gmane [1]. Indeed, it seems that all the messages archived there were propagated through one or more of the other Gmane-ized lists instead. Could the forwarding please be fixed? Also, it'd make sense to import the whole mailing list archive to Gmane (check, e. g., [2].) For this, however, one needs access to the Mailman's internal archives, as the downloadable mbox'es at [3] are stripped of much of the relevant information, including, in particular, MIME headers (effectively rendering anything non-ASCII there unreadable) and MIME parts. TIA. [1] http://dir.gmane.org/gmane.linux.bios.flashrom [2] http://gmane.org/import.php [3] http://www.flashrom.org/pipermail/flashrom/ -- FSF associate member #7257

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Re: [flashrom] FAILED : mcp61sm -am
by Vince S 08 Feb '12

08 Feb '12

Hi so the output of my attempt to flash is sudo flashrom -V -w '/home/vince/Téléchargements/BIOS_R01-C0/61AO615.BIN' flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 736M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1007 us, 10000 myus = 10003 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Acer" DMI string system-product-name: "Aspire E380" DMI string system-version: "R01-A2" DMI string baseboard-manufacturer: "Acer" DMI string baseboard-product-name: "EM61SM/EM61PM " DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8726 on port 0x2e Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xfec80000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Super I/O ID 0x8726 is not on the list of flash capable controllers. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Found SST flash chip "SST49LF040B" (512 kB, LPC) at physical address 0xfff80000. Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:W, 0x001000-0x001fff:S, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:W, 0x011000-0x011fff:W, 0x012000-0x012fff:W, 0x013000-0x013fff:W, 0x014000-0x014fff:W, 0x015000-0x015fff:W, 0x016000-0x016fff:W, 0x017000-0x017fff:W, 0x018000-0x018fff:W, 0x019000-0x019fff:W, 0x01a000-0x01afff:W, 0x01b000-0x01bfff:W, 0x01c000-0x01cfff:W, 0x01d000-0x01dfff:W, 0x01e000-0x01efff:W, 0x01f000-0x01ffff:W, 0x020000-0x020fff:W, 0x021000-0x021fff:W, 0x022000-0x022fff:W, 0x023000-0x023fff:W, 0x024000-0x024fff:W, 0x025000-0x025fff:W, 0x026000-0x026fff:W, 0x027000-0x027fff:W, 0x028000-0x028fff:W, 0x029000-0x029fff:W, 0x02a000-0x02afff:W, 0x02b000-0x02bfff:W, 0x02c000-0x02cfff:W, 0x02d000-0x02dfff:W, 0x02e000-0x02efff:W, 0x02f000-0x02ffff:W, 0x030000-0x030fff:W, 0x031000-0x031fff:W, 0x032000-0x032fff:W, 0x033000-0x033fff:W, 0x034000-0x034fff:W, 0x035000-0x035fff:W, 0x036000-0x036fff:W, 0x037000-0x037fff:W, 0x038000-0x038fff:W, 0x039000-0x039fff:W, 0x03a000-0x03afff:W, 0x03b000-0x03bfff:W, 0x03c000-0x03cfff:W, 0x03d000-0x03dfff:W, 0x03e000-0x03efff:W, 0x03f000-0x03ffff:W, 0x040000-0x040fff:W, 0x041000-0x041fff:W, 0x042000-0x042fff:W, 0x043000-0x043fff:W, 0x044000-0x044fff:W, 0x045000-0x045fff:W, 0x046000-0x046fff:W, 0x047000-0x047fff:W, 0x048000-0x048fff:W, 0x049000-0x049fff:W, 0x04a000-0x04afff:W, 0x04b000-0x04bfff:W, 0x04c000-0x04cfff:W, 0x04d000-0x04dfff:W, 0x04e000-0x04efff:W, 0x04f000-0x04ffff:W, 0x050000-0x050fff:W, 0x051000-0x051fff:W, 0x052000-0x052fff:W, 0x053000-0x053fff:W, 0x054000-0x054fff:W, 0x055000-0x055fff:W, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:W, 0x06b000-0x06bfff:W, 0x06c000-0x06cfff:W, 0x06d000-0x06dfff:W, 0x06e000-0x06efff:W, 0x06f000-0x06ffff:W, 0x070000-0x070fff:W writing sector at 0x7f28ed976000 failed! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:S, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:W writing sector at 0x7f28ed976000 failed! Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88 what can i do??

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Re: [flashrom] [PATCH] dummy programmer: blacklist SPI commands
by Carl-Daniel Hailfinger 08 Feb '12

08 Feb '12

Am 08.02.2012 01:49 schrieb David Hendricks: > Acked-by: David Hendricks <dhendrix(a)google.com> Thanks, committed in r1490. Do we want to add a selftest script or "make selftest" target in the Makefile which compares known good output of a complicated write (maybe even including layout) to a reference output shipped with flashrom? That might be useful for distributors and/or as pre-checkin test of invasive changes. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1490 - trunk
by repository service 08 Feb '12

08 Feb '12

Author: hailfinger Date: Thu Feb 9 00:28:54 2012 New Revision: 1490 URL: http://flashrom.org/trac/flashrom/changeset/1490 Log: SPI command black-/ignorelisting for the flash chip emulator in the dummy programmer Usage: flashrom -p dummy:spi_blacklist=commandlist flashrom -p dummy:spi_ignorelist=commandlist If commandlist is 0302, flashrom will refuse (blacklist) or ignore (ignorelist) command 0x03 (READ) and command 0x02 (WRITE). The commandlist can be up to 512 bytes (256 commands) long. Specifying flash chip emulation is a good idea to get useful results. Very useful for testing corner cases if you don't own a locked down Intel chipset and want to simulate such a thing. Example usage: dd if=/dev/zeros bs=1024k count=4 of=dummy_simulator.rom dd if=/dev/urandom bs=1024k count=4 of=randomimage.rom flashrom -p dummy:emulate=SST25VF032B,image=dummy_simulator.rom,\ spi_blacklist=20,spi_ignorelist=52 -w randomimage.rom -V Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/dummyflasher.c trunk/flashrom.8 Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Tue Feb 7 22:29:48 2012 (r1489) +++ trunk/dummyflasher.c Thu Feb 9 00:28:54 2012 (r1490) @@ -19,6 +19,8 @@ #include <string.h> #include <stdlib.h> +#include <stdio.h> +#include <ctype.h> #include "flash.h" #include "chipdrivers.h" #include "programmer.h" @@ -55,6 +57,10 @@ static unsigned int emu_jedec_be_d8_size = 0; static unsigned int emu_jedec_ce_60_size = 0; static unsigned int emu_jedec_ce_c7_size = 0; +unsigned char spi_blacklist[256]; +unsigned char spi_ignorelist[256]; +int spi_blacklist_size = 0; +int spi_ignorelist_size = 0; #endif #endif @@ -126,6 +132,7 @@ { char *bustext = NULL; char *tmp = NULL; + int i; #if EMULATE_CHIP struct stat image_stat; #endif @@ -170,6 +177,68 @@ } } + tmp = extract_programmer_param("spi_blacklist"); + if (tmp) { + i = strlen(tmp); + if (!strncmp(tmp, "0x", 2)) { + i -= 2; + memmove(tmp, tmp + 2, i + 1); + } + if ((i > 512) || (i % 2)) { + msg_perr("Invalid SPI command blacklist length\n"); + free(tmp); + return 1; + } + spi_blacklist_size = i / 2; + for (i = 0; i < spi_blacklist_size * 2; i++) { + if (!isxdigit((unsigned char)tmp[i])) { + msg_perr("Invalid char \"%c\" in SPI command " + "blacklist\n", tmp[i]); + free(tmp); + return 1; + } + } + for (i = 0; i < spi_blacklist_size; i++) { + sscanf(tmp + i * 2, "%2hhx", &spi_blacklist[i]); + } + msg_pdbg("SPI blacklist is "); + for (i = 0; i < spi_blacklist_size; i++) + msg_pdbg("%02x ", spi_blacklist[i]); + msg_pdbg(", size %i\n", spi_blacklist_size); + } + free(tmp); + + tmp = extract_programmer_param("spi_ignorelist"); + if (tmp) { + i = strlen(tmp); + if (!strncmp(tmp, "0x", 2)) { + i -= 2; + memmove(tmp, tmp + 2, i + 1); + } + if ((i > 512) || (i % 2)) { + msg_perr("Invalid SPI command ignorelist length\n"); + free(tmp); + return 1; + } + spi_ignorelist_size = i / 2; + for (i = 0; i < spi_ignorelist_size * 2; i++) { + if (!isxdigit((unsigned char)tmp[i])) { + msg_perr("Invalid char \"%c\" in SPI command " + "ignorelist\n", tmp[i]); + free(tmp); + return 1; + } + } + for (i = 0; i < spi_ignorelist_size; i++) { + sscanf(tmp + i * 2, "%2hhx", &spi_ignorelist[i]); + } + msg_pdbg("SPI ignorelist is "); + for (i = 0; i < spi_ignorelist_size; i++) + msg_pdbg("%02x ", spi_ignorelist[i]); + msg_pdbg(", size %i\n", spi_ignorelist_size); + } + free(tmp); + #if EMULATE_CHIP tmp = extract_programmer_param("emulate"); if (!tmp) { @@ -348,7 +417,7 @@ const unsigned char *writearr, unsigned char *readarr) { - unsigned int offs; + unsigned int offs, i; static int unsigned aai_offs; static int aai_active = 0; @@ -356,7 +425,24 @@ msg_perr("No command sent to the chip!\n"); return 1; } - /* TODO: Implement command blacklists here. */ + /* spi_blacklist has precedence before spi_ignorelist. */ + for (i = 0; i < spi_blacklist_size; i++) { + if (writearr[0] == spi_blacklist[i]) { + msg_pdbg("Refusing blacklisted SPI command 0x%02x\n", + spi_blacklist[i]); + return SPI_INVALID_OPCODE; + } + } + for (i = 0; i < spi_ignorelist_size; i++) { + if (writearr[0] == spi_ignorelist[i]) { + msg_cdbg("Ignoring ignorelisted SPI command 0x%02x\n", + spi_ignorelist[i]); + /* Return success because the command does not fail, + * it is simply ignored. + */ + return 0; + } + } switch (writearr[0]) { case JEDEC_RES: if (emu_chip != EMULATE_ST_M25P10_RES) @@ -563,7 +649,7 @@ case EMULATE_SST_SST25VF032B: if (emulate_spi_chip_response(writecnt, readcnt, writearr, readarr)) { - msg_perr("Invalid command sent to flash chip!\n"); + msg_pdbg("Invalid command sent to flash chip!\n"); return 1; } break; Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Tue Feb 7 22:29:48 2012 (r1489) +++ trunk/flashrom.8 Thu Feb 9 00:28:54 2012 (r1490) @@ -421,6 +421,28 @@ Example: .sp .B " flashrom -p dummy:emulate=M25P10.RES,spi_write_256_chunksize=5" +.sp +To simulate a programmer which refuses to send certain SPI commands to the +flash chip, you can specify a blacklist of SPI commands with the +.sp +.B " flashrom -p dummy:spi_blacklist=commandlist" +.sp +syntax where commandlist is a list of two-digit hexadecimal representations of +SPI commands. If commandlist is e.g. 0302, flashrom will behave as if the SPI +controller refuses to run command 0x03 (READ) and command 0x02 (WRITE). +commandlist may be up to 512 characters (256 commands) long. +Implementation note: flashrom will detect an error during command execution. +.sp +To simulate a flash chip which ignores (doesn't support) certain SPI commands, +you can specify an ignorelist of SPI commands with the +.sp +.B " flashrom -p dummy:spi_ignorelist=commandlist" +.sp +syntax where commandlist is a list of two-digit hexadecimal representations of +SPI commands. If commandlist is e.g. 0302, the emulated flash chip will ignore +command 0x03 (READ) and command 0x02 (WRITE). commandlist may be up to 512 +characters (256 commands) long. +Implementation note: flashrom won't detect an error during command execution. .TP .BR "nic3com" , " nicrealtek" , " nicsmc1211" , " nicnatsemi" , " nicintel\ " , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\

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Re: [flashrom] FAILED : mcp61sm -am
by Stefan Tauner 08 Feb '12

08 Feb '12

On Wed, 8 Feb 2012 20:47:13 +0100 Vince S <vince06fr(a)gmail.com> wrote: > can i restore my bios from my linux session or do i have to reboot (i have > another bios with i can reboot) to flash it from a freedos live usb? *if* you are talking about the acer you reported last month and *if* i understood your question correctly, *then* you should be able to write the flash chip with flashrom in your linux session. your previous log confirmed at least that erasing works. writing will almost always work if erase works. if you read out the good contents with -r, install the bad chip, write the previously read good content with -w, the two chips should be identical. please ask further questions if something is not clear. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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