flashrom

flashrom@flashrom.org

9164 discussions

Re: [flashrom] Flashrom on stock X60(s)
by Stefan Tauner 25 Jul '12

25 Jul '12

On Tue, 10 Jul 2012 19:24:21 +0200 Tomasz Ostaszewski <tomasz.ostaszewski(a)interia.pl> wrote: > Hi all. > I want to flash on of my X60s with a coreboot using flashrom. I did > search the flashrom list archive, and I found the "FAILED: MX25L1605 > on Thinkpad X60s" (http://bit.ly/NetLop) and related "Lenovo T60 Type > 8743-GZU - RAM Support? 3Gb or 4Gb" (http://bit.ly/Mfhi1W) threads. > Despite what the heading says, those threads do treat about a > successful flashing of a stock X60s with flahshrom utility. There is > is almost a complete descripton of what to do, and what to use. > However, for me there's one piece of the puzzle missing - the patch. > Peter writes: > > "[..]You need the flashrom source, a small patch, and my bucts utility > from http://git.stuge.se/?p=bucts.git" > > The flashrom is readily available from SVN, the bucts from git, but > what are the patches and where to get them from? > And, if worst comes to the worst and I brick my X60s, would I be able > to resurrect it using a programmer and a SOIC-8 clip > (http://bit.ly/Nj8Sdx)? Or rather (de)soldering would be necessary? the patch(es) and bucts are needed because the chipset is locked down by the vendor bios so much that vanilla flashrom can not cope with it (and modifying it so that it does is neither worth it nor trivial). please ask the coreboot guys about the details of the procedure. afaik desoldering is not necessary but an external programmer. if you already know the complete procedure please ask for a coreboot wiki account and create an article about it. it is recurring regularly here and on the coreboot ml (and obviously no one cares to document it fully). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

EN25QH16 (2MiB) READ/PROBE success
by andrew＠ncrmnt.org 25 Jul '12

25 Jul '12

Hello, Just reporting a chip marked as UNTESTED as working. Checked: Probe, Read. Write untested, read produced good bootable results. Used buspirate_spi programmer. Log attached. Regards, Andrew.

2 1

Re: [flashrom] annotate Numonyx/Micron N25Q064
by Stefan Tauner 25 Jul '12

25 Jul '12

On Tue, 24 Jul 2012 15:17:02 -0700 David Hendricks <dhendrix(a)google.com> wrote: > This adds the following: > - missing feature_bits to indicate WREN required before WRSR and the > presence of OTP bytes > - a comment mentioning SFDP support > - voltage range > > Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Thanks for that! i'll commit it in my tested_stuff branch (soon-ish). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

annotate Numonyx/Micron N25Q064
by David Hendricks 25 Jul '12

25 Jul '12

This adds the following: - missing feature_bits to indicate WREN required before WRSR and the presence of OTP bytes - a comment mentioning SFDP support - voltage range Signed-off-by: David Hendricks <dhendrix(a)google.com> Index: flashchips.c =================================================================== --- flashchips.c (revision 1553) +++ flashchips.c (working copy) @@ -5431,6 +5431,9 @@ .model_id = ST_N25Q064, .total_size = 8192, .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5450,6 +5453,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

1 0

Re: [flashrom] [PATCH] Intel QM77
by Stefan Tauner 24 Jul '12

24 Jul '12

On Tue, 24 Jul 2012 10:19:29 +0200 "Wagner, Helge (GE Germany)" <Helge.Wagner(a)ge.com> wrote: > Hi all, > > Please find attached our changes for the QM77 chipset. I looked at the > datasheet to be sure that the strap names (SPI, PCI, LPC) are the same > as on the series 5 and 6 chipsets. > > Signed-off-by: Helge Wagner <Helge.Wagner(a)ge.com> Thanks for your patch, committed in r1553 without a code change. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[commit] r1553 - trunk
by repository service 24 Jul '12

24 Jul '12

Author: stefanct Date: Tue Jul 24 18:33:55 2012 New Revision: 1553 URL: http://flashrom.org/trac/flashrom/changeset/1553 Log: Intel 7 Series fixes (addition of QM77, fixed straps printing). I looked at the datasheet to be sure that the strap names (SPI, PCI, LPC) are the same as on the series 5 and 6 chipsets. Signed-off-by: Helge Wagner <Helge.Wagner(a)ge.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Jul 22 14:01:43 2012 (r1552) +++ trunk/chipset_enable.c Tue Jul 24 18:33:55 2012 (r1553) @@ -526,7 +526,7 @@ static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" }; static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; - static const char *const straps_names_pch56[] = { "LPC", "reserved", "PCI", "SPI" }; + static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; switch (ich_generation) { @@ -546,7 +546,8 @@ break; case CHIPSET_5_SERIES_IBEX_PEAK: case CHIPSET_6_SERIES_COUGAR_POINT: - straps_names = straps_names_pch56; + case CHIPSET_7_SERIES_PANTHER_POINT: + straps_names = straps_names_pch567; break; default: msg_gerr("%s: unknown ICH generation. Please report!\n", @@ -1298,6 +1299,7 @@ {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7}, {0x8086, 0x1e49, NT, "Intel", "B75", enable_flash_pch7}, {0x8086, 0x1e4a, NT, "Intel", "H77", enable_flash_pch7}, + {0x8086, 0x1e55, OK, "Intel", "QM77", enable_flash_pch7}, {0x8086, 0x1e57, NT, "Intel", "HM77", enable_flash_pch7}, {0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7}, {0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7},

1 0

Re: [flashrom] Which hardware do you want supported?
by Andrew Goodbody 24 Jul '12

24 Jul '12

On 22/07/12 00:13, Vitali Druzhinin wrote: > Hello! > > Did not find my motherboards in supported hardware list, but found chipsets. > > I would like to flash the following: > > ASUS M3A-H/HDMI (SB7x0/SB8x0/SB9x0 1002:439d) > Elitegroup NFORCE6M-A2 (MCP61 10de:03e0) > > How safe is to try flash Coreboot on these MoBo? What information do you > need else? > > BR, > Vitali Not safe at all. Flashrom may well work if the boards do not require board specific enables but coreboot requires a specific port to each motherboard in question. So you are very likely to end up with a motherboard that will not boot. If you want to do the coreboot ports then the coreboot mailing list will be the place to get the help you need. Andrew

2 1

[PATCH] Intel QM77
by Wagner, Helge (GE Germany) 24 Jul '12

24 Jul '12

Hi all, Please find attached our changes for the QM77 chipset. I looked at the datasheet to be sure that the strap names (SPI, PCI, LPC) are the same as on the series 5 and 6 chipsets. Signed-off-by: Helge Wagner <Helge.Wagner(a)ge.com> Best Regards, Helge Wagner

1 0

Re: [flashrom] [PATCH] Fix VIA VX*** support.
by Wagner, Helge (GE Germany) 24 Jul '12

24 Jul '12

Hello Stefan, your patch looks good. I tried it on my VX900 system and found it fully working. Logs attached. Regards, Helge

1 0

[PATCH] Fix VIA VX*** support.
by Stefan Tauner 24 Jul '12

24 Jul '12

Helge Wagner's patch that added VIA VX900 chipset support made me look closer at the datasheets which led to some concise documentation about newer VIA chipsets: http://flashrom.org/VIA Based on that this patch adds full support for VX800/VX820, VX855/VX875 and VX900, including SPI and LPC. VT8237S was not changed (SPI support only) because there is no public datasheet and it is not clear how to distinguish between LPC and SPI strapping and investigations in (NDAed) documents have not brought up anything conclusively. enable_flash_vt823x could probably be enhanced too due to various ignored LPC options of the chipset. Signed-off-by: Helge Wagner <Helge.Wagner(a)ge.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------- ichspi.c | 9 +++---- programmer.h | 2 +- 3 files changed, 73 insertions(+), 17 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index bde2e12..a977d68 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -6,6 +6,7 @@ * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger * Copyright (C) 2009 Kontron Modular Computers GmbH + * Copyright (C) 2011, 2012 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -508,12 +509,6 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) return ret; } -static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) -{ - /* Do we really need no write enable? */ - return via_init_spi(dev); -} - static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) { @@ -680,7 +675,7 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name) return -1; } - if (dev->device_id == 0x3227) { /* VT8237R */ + if (dev->device_id == 0x3227) { /* VT8237 */ /* All memory cycles, not just ROM ones, go to LPC. */ val = pci_read_byte(dev, 0x59); val &= ~0x80; @@ -690,6 +685,69 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name) return 0; } +static int enable_flash_vt_vx(struct pci_dev *dev, const char *name) +{ + struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353); + if (south_north == NULL) { + msg_perr("Could not find South-North Module Interface Control device!\n"); + return -1; + } + + msg_pdbg("Strapped to "); + if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) { + msg_pdbg("LPC.\n"); + return enable_flash_vt823x(dev, name); + } + msg_pdbg("SPI.\n"); + + uint32_t mmio_base; + void *mmio_base_physmapped; + uint32_t spi_cntl; + #define SPI_CNTL_LEN 0x08 + uint32_t spi0_mm_base = 0; + switch(dev->device_id) { + case 0x8353: /* VX800/VX820 */ + spi0_mm_base = pci_read_long(dev, 0xbc) << 8; + break; + case 0x8409: /* VX855/VX875 */ + case 0x8410: /* VX900 */ + mmio_base = pci_read_long(dev, 0xbc) << 8; + mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN); + if (mmio_base_physmapped == ERROR_PTR) { + physunmap(mmio_base_physmapped, SPI_CNTL_LEN); + return ERROR_FATAL; + } + + /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */ + spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00; + if ((spi_cntl & 0x01) == 0) { + msg_pdbg ("SPI Bus0 disabled!\n"); + physunmap(mmio_base_physmapped, SPI_CNTL_LEN); + return ERROR_FATAL; + } + /* Offset 1-3 has SPI Bus Memory Map Base Address: */ + spi0_mm_base = spi_cntl & 0xFFFFFF00; + + /* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */ + spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04; + if ((spi_cntl & 0x01) == 1) + msg_pdbg2("SPI Bus1 is enabled too.\n"); + + physunmap(mmio_base_physmapped, SPI_CNTL_LEN); + break; + default: + msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id); + return ERROR_FATAL; + } + + return via_init_spi(dev, spi0_mm_base); +} + +static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) +{ + return via_init_spi(dev, pci_read_long(dev, 0xbc) << 8); +} + static int enable_flash_cs5530(struct pci_dev *dev, const char *name) { uint8_t reg8; @@ -1262,7 +1320,7 @@ const struct penable chipset_enables[] = { {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_amd8111}, - {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x}, + {0x1106, 0x3074, OK, "VIA", "VT8233/VT8237R", enable_flash_vt823x}, {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x}, @@ -1270,8 +1328,9 @@ const struct penable chipset_enables[] = { {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, - {0x1106, 0x8353, OK, "VIA", "VX800/VX820", enable_flash_vt8237s_spi}, - {0x1106, 0x8409, OK, "VIA", "VX855/VX875", enable_flash_vt823x}, + {0x1106, 0x8353, NT, "VIA", "VX800/VX820", enable_flash_vt_vx}, + {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt_vx}, + {0x1106, 0x8410, NT, "VIA", "VX900", enable_flash_vt_vx}, {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, diff --git a/ichspi.c b/ichspi.c index 792d35d..fb87459 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1844,17 +1844,14 @@ static const struct spi_programmer spi_programmer_via = { .write_aai = default_spi_write_aai, }; -int via_init_spi(struct pci_dev *dev) +int via_init_spi(struct pci_dev *dev, uint32_t mmio_base) { - uint32_t mmio_base; int i; - mmio_base = (pci_read_long(dev, 0xbc)) << 8; msg_pdbg("MMIO base at = 0x%x\n", mmio_base); - ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); + ich_spibar = physmap("VIA SPI MMIO registers", mmio_base, 0x70); + /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */ - /* Not sure if it speaks all these bus protocols. */ - internal_buses_supported = BUS_LPC | BUS_FWH; ich_generation = CHIPSET_ICH7; register_spi_programmer(&spi_programmer_via); diff --git a/programmer.h b/programmer.h index f511c71..cfdc677 100644 --- a/programmer.h +++ b/programmer.h @@ -561,7 +561,7 @@ enum ich_chipset { extern uint32_t ichspi_bbar; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, enum ich_chipset ich_generation); -int via_init_spi(struct pci_dev *dev); +int via_init_spi(struct pci_dev *dev, uint32_t mmio_base); /* it85spi.c */ int it85xx_spi_init(struct superio s); -- Kind regards, Stefan Tauner

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

flashrom