flashrom

flashrom@flashrom.org

9164 discussions

flashrom ignores layout file?
by Ross Amans 04 Mar '13

04 Mar '13

I can run flashrom under linux for read, but not yet write. Sandy Bridge / Patsburg C602 When I attempt to use a layout file, it likes it, but ignores it. No complaints, but instead of doing the 4 MB bios, it does the whole flash (8MB). command line: ./flashrom -r fll-19-w-bios.bin -c W25Q64 -p internal:laptop=this_is_not_a_laptop -i bios -l layout.flash -o fl-bios.log layout.flash: 00000000:0000ffff desc 00010000:003fffff me 00400000:007fffff bios fl-bios.log: flashrom v0.9.6.1-r1653 on Linux 3.7.5-201.fc18.x86_64 (x86_64) flashrom was built with libpci 3.1.10, GCC 4.7.2 20121109 (Red Hat 4.7.2-8), little endian Command line (12 args): ./flashroml -r fll-19-w-bios.bin -c W25Q64 -p internal:laptop=this_is_not_a_laptop -i bios -l layout.flash -o fl-bios.log romlayout 00000000 - 0000ffff named desc romlayout 00010000 - 003fffff named me romlayout 00400000 - 007fffff named bios Using region: "bios". Calibrating delay loop... OS timer resolution is 1 usecs, 1781M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 1004 us, 10000 myus = 9992 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "To be filled by O.E.M." DMI string system-product-name: "To be filled by O.E.M." DMI string system-version: "To be filled by O.E.M." DMI string baseboard-manufacturer: "To be filled by O.E.M." DMI string baseboard-product-name: "To be filled by O.E.M." DMI string baseboard-version: "To be filled by O.E.M." DMI string chassis-type: "Desktop" Found chipset "Intel X79" with PCI ID 8086:1d41. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0xc20: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0xd8, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x90, read w/ addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x9f, read w/o addr, none op[7]: 0xc7, write w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x007fffc0 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x000f0000 FREG0: Flash Descriptor region (0x00000000-0x0000ffff) is read-write. 0x58: 0x07ff0400 FREG1: BIOS region (0x00400000-0x007fffff) is read-write. 0x5C: 0x03ff0010 FREG2: Management Engine region (0x00010000-0x003fffff) is read-write. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf87f10 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00002005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210020 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 0 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x00100024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 20 MHz Write and Erase Clock Freq.: 20 MHz Fast Read is supported. Fast Read Clock Frequency: 20 MHz No forbidden opcodes. === Region Section === FLREG0 0x000f0000 FLREG1 0x07ff0400 FLREG2 0x03ff0010 FLREG3 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x0000ffff Region 1 (BIOS ) 0x00400000 - 0x007fffff Region 2 (ME ) 0x00010000 - 0x003fffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0xffff0000 FLMSTR2 0xffff0000 FLMSTR3 0xffff0118 --- Details --- Descr. BIOS ME GbE Platf. BIOS rw rw rw rw rw ME rw rw rw rw rw GbE rw rw rw rw rw SPI Read Configuration: prefetching enabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Found Winbond flash chip "W25Q64" (8192 kB, SPI) at physical address 0xff800000. Chip status register is 0x00. This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Block protection is disabled. Reading flash... done. Restoring MMIO space at 0x7f6ced1e68a0 Restoring MMIO space at 0x7f6ced1e689c Restoring MMIO space at 0x7f6ced1e6898 Restoring MMIO space at 0x7f6ced1e6896 Restoring MMIO space at 0x7f6ced1e6894 Restoring PCI config space for 00:1f:0 reg 0xdc -- Ross Amans Systems Engineer Newisys div of Sanmina 5385 Mark Dabling blvd Colorado Springs, CO 80918 719-884-8714 (work) 719-287-4446 (cell) CONFIDENTIALITY This e-mail message and any attachments thereto, is intended only for use by the addressee(s) named herein and may contain legally privileged and/or confidential information. If you are not the intended recipient of this e-mail message, you are hereby notified that any dissemination, distribution or copying of this e-mail message, and any attachments thereto, is strictly prohibited. If you have received this e-mail message in error, please immediately notify the sender and permanently delete the original and any copies of this email and any prints thereof. ABSENT AN EXPRESS STATEMENT TO THE CONTRARY HEREINABOVE, THIS E-MAIL IS NOT INTENDED AS A SUBSTITUTE FOR A WRITING. Notwithstanding the Uniform Electronic Transactions Act or the applicability of any other law of similar substance and effect, absent an express statement to the contrary hereinabove, this e-mail message its contents, and any attachments hereto are not intended to represent an offer or acceptance to enter into a contract and are not otherwise intended to bind the sender, Sanmina Corporation (or any of its subsidiaries), or any other person or entity.

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M29W512B write operation verified on 3C905C/TX
by Lu Xie 04 Mar '13

04 Mar '13

Hi, Thanks for the wonderful tool. The verification is attached as requested. Lu

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Re: [flashrom] Rayer_SPI and xilinx buffered dlc5 cable
by Kyösti Mälkki 04 Mar '13

04 Mar '13

On Tue, 2013-02-26 at 11:55 +1100, Andrew Tarabaras wrote: > Hi, > > Just a heads up that the rayer_spi module wont work with a buffered xilinx > DLC cable. There is a pull down buffer in the MISO ( Data In ) line which > is enabled when pin 6 of the parallel port is pulled low. > > I dont have time to be submitting patches, fix it or not I dont mind. > Thanks. So this is for the "Xilinx DLC-5" with following schematic? http://dev.ivanov.eu/uploads/images/dlc5/dlc5_schematic3.png There is another pending rayer_spi patch, I'll handle both. Regards, Kyösti

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Assist in the development of SPI protocol.
by Сергей Бараненков 04 Mar '13

04 Mar '13

Hello, please help in the development of the protocol SPI, I would like to implement a simple program to program MX25L3205. In this case, it is possible to program it with the Raspberry Pi, but you just want to understand. If you are not hard to help in your endeavors, if not difficult to specify where you can read and see the source code. I work in the Borland C + + 6.0. Thanks again -- Sincerely Sergey Baranenkov Engineer Grade 1 Interregional Center of ICT in the Bank of Russia (Central Bank)

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Re: [flashrom] [coreboot] IMC on persimmon (was: Flashrom erase failure)
by Racine, Michel 04 Mar '13

04 Mar '13

Hello Wolfgang, I cannot do the commit to flashrom.org; I'm not a contributor, just a user. However, if you have a patch file I could apply it to the code on my system, and rebuild flashrom. That would get me out of the problem I have, and be able to reboot. Cheers, Michel. -----Original Message----- From: Wolfgang Kamp - datakamp [mailto:wmkamp@datakamp.de] Sent: Monday, March 04, 2013 1:43 AM To: flashrom(a)flashrom.org Cc: Stefan Tauner; Racine, Michel Subject: AW: [coreboot] IMC on persimmon (was: Flashrom erase failure) Hi, recently I had the same problems to get Flashrom working on an embedded platform with AMD G-series processor similar to Persimmon. I did all the patches to get Flashrom working but actually I'm not able to commit to flashrom.org. If there is interest I would send the necessary files to someone who can do that for me. Regards, Wolfgang -----Ursprüngliche Nachricht----- Von: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] Im Auftrag von Stefan Tauner Gesendet: Freitag, 1. März 2013 22:04 An: Racine, Michel Cc: flashrom(a)flashrom.org; coreboot(a)coreboot.org Betreff: [coreboot] IMC on persimmon (was: Flashrom erase failure) On Fri, 1 Mar 2013 20:48:48 +0000 "Racine, Michel" <michel.racine(a)hp.com> wrote: > Thank you for the quick reply. > > I have upgraded flashrom. I did a verify, and flashrom indicated a difference. I tried to re-flash coreboot, but I think I'm missing something: > > root@debian:~/flashrom/flashrom-0.9.6.1# ./flashrom -p internal -w > ~/coreboot.rom flashrom v0.9.6.1-r1564 on Linux 2.6.32-5-686 (i686) > flashrom is free software, get the source code at > http://www.flashrom.org > > Calibrating delay loop... OK. > coreboot table found at 0xc717d000. > Found chipset "AMD SB7x0/SB8x0/SB9x0". Enabling flash write... The SB700 IMC is active and may interfere with SPI commands. Disabling write. > OK. > Found SST flash chip "SST25VF032B" (4096 kB, SPI) at physical address 0xffc00000. > Write/erase is not working yet on your programmer in its current configuration. > Aborting > > > Thoughts? I have added the coreboot mailing list because I ham not familiar with the board or chipset and I am quite certain someone there knows how to handle this correctly. The new version of flashrom detects that the embedded controller on the board (IMC) accesses the SPI bus concurrently with flashrom. We disable writes for safety reasons in that case (your old version did not...). Apparently there is no way to force writing other than changing the source code (sb600.c). I don't think that is wisely though... Apart from repeating the warning to *NOT* reboot/reset/shutdown the machine (unless you have a known-working external flash programmer), I can not help you further ATM. > -----Original Message----- > From: Stefan Tauner [mailto:stefan.tauner@student.tuwien.ac.at] > Sent: Friday, March 01, 2013 12:09 PM > To: Racine, Michel > Cc: flashrom(a)flashrom.org > Subject: Re: [flashrom] Flashrom erase failure > > On Fri, 1 Mar 2013 17:19:46 +0000 > "Racine, Michel" <michel.racine(a)hp.com> wrote: > > > Greetings, > > > > I have an AMD Persimmon dev board. I built coreboot and flashed it successfully; the board was operational. > > I have attempted to flash the original rom (obtained before flashing coreboot with flashrom -r). > > When I attempted to flash the original rom, I get the output below. > > > > Hi, > > you are trying to write the original image while running coreboot, right? > > You are using a very old version of flashrom. Please verify that the content of the flash is untouched (by using the -v option with the image you have written successfully last). If it was modified try to rewrite that image. If that still does not work, please report back, else update and retry. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [flashrom] patch Dynamic list Multiple chips
by Stefan Tauner 04 Mar '13

04 Mar '13

On Sat, 2 Mar 2013 09:42:51 +0400 Николай Николаев <evrinoma(a)gmail.com> wrote: > hi 8) > Can you please resend the patch without the superfluous comments? > > yes of course i will send him at next week > i want to improve them to add in structure dynamic list a pointer to header > flashes and i want to write function sort by voltage > Ok, thanks! Please split those changes into multiple patches and don't send one single patch then. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Added chipsets
by Stefan Tauner 04 Mar '13

04 Mar '13

Hi, I took a closer look at your patch. It contains a lot of white space errors. Please make sure that this won't happen again. Checking data sheets to review such patches is no fun, dealing with other's white space errors is even worse ;) Some additions of chips are non-functional yet... e.g. there is no support for more than 24 bits in addresses, but some chips require that. Also, please do not send patches as base64 encoded attachments. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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IMC on persimmon (was: Flashrom erase failure)
by Stefan Tauner 04 Mar '13

04 Mar '13

On Fri, 1 Mar 2013 20:48:48 +0000 "Racine, Michel" <michel.racine(a)hp.com> wrote: > Thank you for the quick reply. > > I have upgraded flashrom. I did a verify, and flashrom indicated a difference. I tried to re-flash coreboot, but I think I'm missing something: > > root@debian:~/flashrom/flashrom-0.9.6.1# ./flashrom -p internal -w ~/coreboot.rom > flashrom v0.9.6.1-r1564 on Linux 2.6.32-5-686 (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > coreboot table found at 0xc717d000. > Found chipset "AMD SB7x0/SB8x0/SB9x0". Enabling flash write... The SB700 IMC is active and may interfere with SPI commands. Disabling write. > OK. > Found SST flash chip "SST25VF032B" (4096 kB, SPI) at physical address 0xffc00000. > Write/erase is not working yet on your programmer in its current configuration. > Aborting > > > Thoughts? I have added the coreboot mailing list because I ham not familiar with the board or chipset and I am quite certain someone there knows how to handle this correctly. The new version of flashrom detects that the embedded controller on the board (IMC) accesses the SPI bus concurrently with flashrom. We disable writes for safety reasons in that case (your old version did not...). Apparently there is no way to force writing other than changing the source code (sb600.c). I don't think that is wisely though... Apart from repeating the warning to *NOT* reboot/reset/shutdown the machine (unless you have a known-working external flash programmer), I can not help you further ATM. > -----Original Message----- > From: Stefan Tauner [mailto:stefan.tauner@student.tuwien.ac.at] > Sent: Friday, March 01, 2013 12:09 PM > To: Racine, Michel > Cc: flashrom(a)flashrom.org > Subject: Re: [flashrom] Flashrom erase failure > > On Fri, 1 Mar 2013 17:19:46 +0000 > "Racine, Michel" <michel.racine(a)hp.com> wrote: > > > Greetings, > > > > I have an AMD Persimmon dev board. I built coreboot and flashed it successfully; the board was operational. > > I have attempted to flash the original rom (obtained before flashing coreboot with flashrom -r). > > When I attempted to flash the original rom, I get the output below. > > > > Hi, > > you are trying to write the original image while running coreboot, right? > > You are using a very old version of flashrom. Please verify that the content of the flash is untouched (by using the -v option with the image you have written successfully last). If it was modified try to rewrite that image. If that still does not work, please report back, else update and retry. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1653 - trunk
by repository service 03 Mar '13

03 Mar '13

Author: stefanct Date: Mon Mar 4 02:41:56 2013 New Revision: 1653 URL: http://flashrom.org/trac/flashrom/changeset/1653 Log: Add (untested) board enable for ASUS P4PE-X/TE. REed by roxfan and Michael Karcher, patch by Stefan Tauner. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Mar 4 02:20:28 2013 (r1652) +++ trunk/board_enable.c Mon Mar 4 02:41:56 2013 (r1653) @@ -2351,6 +2351,7 @@ {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80a5, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-VM$", NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-X$", NULL, NULL, P3, "ASUS", "P4P800-X", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80b2, 0x8086, 0x24c3, 0x1043, 0x8089, "^P4PE-X/TE$",NULL, NULL, P3, "ASUS", "P4PE-X/TE", 0, NT, intel_ich_gpio21_raise}, {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Mar 4 02:20:28 2013 (r1652) +++ trunk/print.c Mon Mar 4 02:41:56 2013 (r1653) @@ -638,6 +638,7 @@ B("ASUS", "P4P800-E Deluxe", OK, "http://www.asus.com/Motherboards/Intel_Socket_478/P4P800E_Deluxe/", NULL), B("ASUS", "P4P800-VM", OK, "http://www.asus.com/Motherboards/Intel_Socket_478/P4P800VM/", NULL), B("ASUS", "P4P800-X", OK, "http://www.asus.com/Motherboards/Intel_Socket_478/P4P800X/", NULL), + B("ASUS", "P4PE-X/TE", NT, "http://www.asus.com/999/html/events/mb/socket478/p4pe-x-te/overview.htm", NULL), B("ASUS", "P4S533-X", OK, NULL, NULL), B("ASUS", "P4S800-MX", OK, "http://www.asus.com/Motherboards/Intel_Socket_478/P4S800MX/", NULL), B("ASUS", "P4SC-E", OK, NULL, "Part of ASUS Terminator P4 533 barebone system"),

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[PATCH] Add M25P20-old
by Kyösti Mälkki 03 Mar '13

03 Mar '13

This older revision (?) of M25P20 chip was not detected correctly. Similar case was with M25P40 detection. I have misplaced my narrow SOIC-8 adapter and cannot reproduce the test logs at the moment. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- flashchips.c | 27 +++++++++++++++++++++++++++ flashchips.h | 1 + 2 files changed, 28 insertions(+) diff --git a/flashchips.c b/flashchips.c index d4ab1be..7321e6c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8327,6 +8327,33 @@ const struct flashchip flashchips[] = { }, { + .vendor = "ST", + .name = "M25P20-old", + .bustype = BUS_SPI, + .manufacture_id = 0, /* Not used. */ + .model_id = ST_M25P20_RES, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_res1, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { .vendor = "ST", /* Numonyx */ .name = "M25P40", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 1a0696f..c4c72ba 100644 --- a/flashchips.h +++ b/flashchips.h @@ -572,6 +572,7 @@ #define ST_M25P10A 0x2011 #define ST_M25P10_RES 0x10 /* Same code as M25P05. */ #define ST_M25P20 0x2012 +#define ST_M25P20_RES 0x11 #define ST_M25P40 0x2013 #define ST_M25P40_RES 0x12 #define ST_M25P80 0x2014 -- 1.8.1.1

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