flashrom

flashrom@flashrom.org

5 participants
9154 discussions

Flashrom Dev Meeting summary info
by Anastasia Klimchuk 18 May '22

18 May '22

Hello People, I wanted to summarise the information on the time of Dev meeting. At some point there was an idea to alternate times, but then we discovered that we got really lucky and there is one time which everyone agrees on. That was an open question at the last meeting, to confirm the time with those US folks who were not present. Since no one was replying to the mailing list, I reached out to folks and confirmed the time is fine. —------------- SUMMARY —------------- #1 Between November and March (inclusive) time of meeting: Wednesday 21:00-22:00 UTC+0 also known as Wednesday 13.00-14.00 Pacific Standard Time UTC-8 Wednesday 22.00-23.00 Central European Time UTC+1 Thursday 8.00-9.00am Australian Eastern Daylight Time UTC+11 #2 Between April and September (inclusive) time of meeting: Thursday 6.00-7.00am UTC+0 also known as Wednesday 11pm-midnight Pacific Daylight Time UTC-7 Thursday 8.00-9.00am Central European Summer Time UTC+2 Thursday 16.00-17.00 Australian Eastern Standard Time UTC+10 #3 Note that in the last week of March and 4 weeks of October there will be no meetings, because daylight saving time changes are happening on different dates in different locations, and setting up meeting time becomes too complicated. Once the regularity is stable, I will add info about Dev meeting on the Contacts page. Meanwhile: —---- FAQ —---- #1 When is the next meeting? Look into the meeting notes document <https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZkADzQSH6WF…>. The top entry, on the first page, with the date in the future, and empty list of attendees - is the next meeting. #2 How to join the meeting? Look into the meeting notes document <https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZkADzQSH6WF…>. On the top it says “to join, click the link”, click the link. #3 Where is that document? Meeting notes document is linked to the Home page of flashrom.org, Developers menu at the bottom of the page. #4 Do I need an invitation to join the meeting? No, just join. -- Anastasia.

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Is anyone interested in OTP support patchset?
by Sergii Dmytruk 17 May '22

17 May '22

Hello, Some time ago I've revived an old patchset by Hatim Kanchwala and extended it with support for more devices and unit tests. It wasn't reviewed for a while and now that reviewing makes sense (changes it's based on were accepted) it's not really needed for 3mdeb's project anymore... The question is whether there is a need for it? If there is interest and wiliness to test it (wasn't tested on hardware), pursuing review still makes sense. Someone can even take over the patches and I'll become a reviewer and help along the way. If OTP isn't needed at the moment, the patchset will be abandoned at least until some project which requires OTP in flashrom or until someone else will pick it up. The first change of the series is (no topic yet) https://review.coreboot.org/c/flashrom/+/59402 To give you an idea of the amount of work it might take to upstream: Makefile | 2 chipdrivers.h | 5 cli_classic.c | 243 dummyflasher.c | 351 flash.h | 6 flashchips.c | 61 flashrom.8.tmpl | 81 libflashrom.h | 18 meson.build | 2 otp.c | 490 otp.h | 91 otp_layouts.c | 210 spi.h | 40 spi25.c | 89 spi25_statusreg.c | 90 tests/chip_otp.c | 470 tests/meson.build | 1 tests/tests.c | 14 tests/tests.h | 12 19 files changed, 2186 insertions(+), 90 deletions(-) Conflicts with current master for a couple of month, should be easy to fix (I'll do that if someone else will take over). I also have a bash script to test new CLI options via dummyflasher. Best regards, Sergii

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Release preparations
by Nico Huber 17 May '22

17 May '22

Hi folks, people often ask me about a potential next release and what is holding me back. Long story short, I knew about some bad things in our master branch that make a release impossible and I was very much afraid that there could be more that I don't know about. I've been scrolling through the commit log from v1.1 (the last release I was involved) to today's master. Some of the things I found are simple like something missing for a flash chip entry. But most of it are things I'd rather not have on a release branch. And the list turned out to be much longer than I expected. OTOH, I didn't find issues of the worst kind I expected. Not sure how to go on from here. As this is a lot to do, I suggest that we freeze the master branch for everything that is neither a fix nor on the list (or a similar case that I missed). I noted sometimes that we could just drop the code from a release branch. If we'd decide to do that, we'd also need a plan how to stop the rot on the master branch. Below are my raw notes, I don't have the time to write things up nicely. I noted the commit hash where things began, but tried to take the cur- rent state into account. For instance, when it's about a new programmer driver, I was looking at the file, not the initial patch. Cheers, Nico Recommended clean-ups and investigations before v1.3 ==================================================== * cb973683 Added partial meson support which confuses package main- tainers. Should we remove it from or disable CLI building on release branches? * 71b706f5 Adds some libflashrom APIs with questionable design, buggy implementation and no visible user. Would be easiest to drop and add back when somebody needs it. Open comment. Partially fixed up. * 86fc9cf7 Open comment. Partially fixed up. * 05c629be Looks incomplete, flash would be fully erased with programmers that lack native 4BA command support. * ad08aef6 Undocumented programmer. disable? drop from realease branch? * 703de983 Added `spireadmode` param to sb600spi. (How) does it work? * 13a2ef6c Added `lspcon_i2c_spi`. Too generic name: LSPCon is a concept but driver seems to be about a specific vendor/chip. No pro- bing just starts to write to hardcoded addresses. WP code contains magic numbers, board specific? Implements `spi_ master` but contains hard-coded SPI opcodes. Not documented? disable? drop from release branch? * d97f87b0 Added `realtek_mst_i2c_spi`. No probing, starts by toggling a GPIO. Are GPIO settings board specific? Timeout checks seem to have regressed since original commit. Not documented? Changes clock settings, is this board specific? Implements `spi_master` with special cases in an opcode LUT, doesn't bail out on unknown codes. Falls back on unaligned reads/ writes, were these paths tested? Fixups suggest that the original code wasn't properly tested, was it by now? disable? drop from release branch? * be4682dc Might miss some block erasers. * f82dd300 Might miss some block erasers. * a2dc4f7f It seems `clear_spi_id_cache()` is never called. Probably, should be before probing. * 3149822c Added variable size in `dummy_programmer`. Didn't look at it right now, but I remember it caused a lot of trouble. Probably not fully fixed up yet. * cb9f3cd0 Possible division by zero. * ca2e3bce Fixed some libpci usage. IIRC, there are many more similar cases that might need a fix now that libpci is more strict. * 0386aa17 sb600spi refactoring. Looks like it dropped an error message from many error paths. * f745d0e6, adbae0e2 Added infrastructure for S25F chips. Code style looks a bit outdated. Probably needs upstream review. * 8fa792fb Added chips with oddities and w/o reasoning, e.g: .total_size = 16384, /* This is just half the size.... */ Complete patch needs review. * 855d6b6f Added Ryzen support to sb600spi. API violations. Stalled other cleanup work. Soft bricks machines with >16MiB flash. Patches on Gerrit. drop from release branch? * 32f4cb4f Looks like copy-pasta from Winbond chips. Might miss some block erasers. Missing 4BA_WRITE is probably wrong. * 45d50a10 Added support code for per-region file arguments. Review was interrupted, IIRC. Rebase was borked shortly before merge. Work never finished. * d4063bf3 Missed to update the manpage. Literal `-` shouldn't be in `<>`. * ce983bcc Missed to update the manpage. Filters only spaces when converting region names to file names. * 51e1d0e4 Still selects the wrong chipset, IIRC. * e98b2d11 Review never really started. See comments on Gerrit. Backport candidates =================== * 4ca575dc usbdev: Only match requested USB devices * 8bbb7648 spi95: Check for success before using send_command's returned data * b07c53d7 spi25: Debug flashrom crash when Write Protect is ON Looks like this covers up a general problem with flash-chip entries. Why would we know how to disable block protection if we don't know how to report it? Should probably be added to self checks. * 51261541 it87spi.c: Prevent use-after-free bug * da0825f0 chipset_enable.c: check return value from rphysmap() call * 705212da chipset_enable.c: Validate physmap() return rcrb value * b76d2810 dediprog: Fix segmentation fault on no device found * 1a21cc70 helpers.c: Fix undefined behavior in strndup() * a2f2f3f5 linux_mtd: Disable buffering on the mtd device * ab623c65 jlink_spi: Reduce transfer size * Many fixes in dummy_flasher, not sure if they were applicable earlier. * aedfb7eb flashrom.8: add missing entry for `--flash-contents` * 89c73b5a linux_mtd: check ioctl() return value properly

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Updating Intel idaville BIOS failed.
by Jackie Tang 17 May '22

17 May '22

Hi Team, Excuse me, I am currently working on the BIOS of the Intel idaville platform, and the BIOS chip used is a 64M WINBOND W25Q512JVFIQ. After the machine boots into CentOS, I use the command "flashrom -w BIOS.ROM -p linux-spi" and it will return "No spi device given", and the BIOS update fails. May I ask what method can be used to solve this problem or update the BIOS with flashrom in the OS successfully, or how can I successfully mount the flash? Waiting for your reply. Best Regards, Celestica Technology Consultancy (Shanghai) Co.,Ltd Jackie

1 0

Gatekeeping, ACLs and Review Rules
by Nico Huber 16 May '22

16 May '22

Dear fellow flashrom developers, I've been reflecting lately about written and unwritten rules around our review process and our related privileges on Gerrit. I couldn't identify anything that works well, or let's say well enough. So it might be time we discuss some things and make changes :) Before the dawn of our Git repository and using Gerrit as a review plat- form, we had a Subversion repository. With very few people, usually one or two I think, that had write access. So practically we had gatekeepers that watched over the code. Eventually, they became a bottleneck so we widened that a little when starting the work on Gerrit. Today, I often catch myself falling back into such a gatekeeper mode. Which is futile anyway because I'm not the only one who can write to the repository. But I still wonder why this happens and if it's necessary. I guess first everyone needs to understand how we imagined things with Gerrit and how it looks like today. As mentioned above we set up a group "flashrom developers" which has exclusive write access to the reposi- tory. The idea was to only have people in this group who are long-term (I was thinking about years) contributors to flashrom, know each other from real-time communication (IRC) and trust each other. For the review right "+2", we used the "Reviewers" group from coreboot. IIRC, I pushed for the latter. I was hoping to grow the communities a little together that seemed to have gone separate ways in the years before. After all, a lot of coreboot developers use flashrom in their everyday work. Combined with the "flashrom developers" group it shouldn't have been an issue that people with little flashrom knowledge would review. Since the original setup (about 2017) things went on rather uncon- trolled. I think the gist of it is that people didn't expect that flashrom would need/have different rules compared to coreboot. At some point somebody whom I only knew from their work on coreboot sud- denly merged patches for flashrom. And I guess people pushing patches today pretty much expect that there is nothing more to be done once they see the first +2. No matter if the reviewer knows anything about flashrom. When reviewers disagree then, it can become frustrating for everyone. So currently, I lean towards aligning our process more with that of coreboot. The big difference seems to be that at coreboot merging patches, i.e. hitting the "Submit" button, is more or less considered an administrative task unrelated to one's opinion on the code. While for us it was supposed to replace the gatekeeping. Changing this would imply that we need our own group of reviewers. With this, a +2 would become both rarer and stronger. If this idea meets some consent, I would propose to copy the "flashrom developers" group for a start. And when we identify somebody over time who shows in-depth knowledge about at least a part of flashrom and good self-judgement if they are experienced enough for a +2, we could add them. Right now, some candidates come to mind already, Peter, Nikolai, and Thomas. The "flashrom developers" group also grants the privilege to block "-2" a change. I have very conflicting feelings about this. On one hand, this is a tool that is only ever necessary when people in said group can't trust each other. On the other, that seems to be the status quo already. Maybe we should have another group on top for this? This time really only for trusted, established, long-term contributors? Or maybe for those who maintain the codebase beyond what they are paid for? There is one related idea for a rule that crossed my mind: How about we forbid blocking reverts that fix a regression and apply cleanly (i.e. without needing to revert anything else in advance). Also, let them pass after review without waiting 24 hours. At least for myself this would reduce a lot pressure to fall back to gatekeeping if I knew I could keep things safe and sound without discussion. For maintainers, the patches that are already merged matter the most, cause the most work. This should also be the case for contributors, but alas many don't see it like this and don't help to fix things after a patch is merged. Easing reverts would push the hard work back to the people who break things. Looks a bit longer than what I intended to write, as usual when one starts writing ;) If we come to a conclusion wrt. Gerrit privileges, we could also discuss more rules for each role. While I'm not a fan of too many rules and would rather keep things to common sense, these things depend much on the people we add to the respective groups. I hope it's not too much to digest at once ;) Cheers, Nico

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Questions regarding Easy project and GSoC
by Aarya Chaumal 16 May '22

16 May '22

Hello there, I hope you are well today when you receive this email. I am Aarya Chaumal, a Computer Engineering student at the College of Engineering Pune, India. While going through organizations for this year's Google's Summer of Code I came across your organization, Flashrom. I am a part of onboard computers subsystem at my college's satellite initiative. Through this, I have closely worked on Atmel SAM E70 XPLAINED board. Also, I have strong knowledge about C/C++ and assembly language. From your list of GSoC project ideas, I liked the idea of “Remove global state from flashrom” and "Optimize Erase-Function Selection", although I am not quite sure which one is more suitable for me. Can you guide me through this? As mentioned in your Contributor commitments and requirements, I started to do one of the easy projects - Add new flash chip definitions. For this, I read the relevant datasheets, one from the unlisted chips and another of a listed one (for reference) but still, I am not getting the information about some fields for the structure in the datasheet, namely the feature_bits, probe_timing. Also, do I have to write the probe, read, write and erase functions for the chip separately? Also, how do I test if my code is working as I don't have relevant hardware with me? Can you help me with this? Also what resources should I use to learn more about it? Thank you for looking into this for me. Sincerely, Aarya Chaumal

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flash intel network adapter
by Denis 16 May '22

16 May '22

Hello. Do you have any plans to add support for 8086:1583 - Intel Ethernet Converged Network Adapter XL710-QDA2 ? After an unsuccessful firmware... BootUtil writes "Cannot initialize adapter". No standard ways to make rollback :((( It would be great to flash with your utility. Thanks in advance

1 0

how to enable the internal programmer
by Selva Harris 16 May '22

16 May '22

Hi, I have an Intel Apollo lake board. I want to read the SPI chip. When I run 'flashrom -p internal', this is the message I get: flashrom v1.2-735-gb728f4b on Linux 4.5.5-300.fc24.x86_64 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Error: Unknown programmer "internal". Valid choices are: dummy, serprog, buspirate_spi, rayer_spi, pony_spi, linux_mtd, linux_spi. Please run "flashrom --help" for usage info. Thanks in advance, Selva

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[PATCH] Add voltage data for chips
by Chinmay Lonkar 11 May '22

11 May '22

From: ChinmayLonkar <chinmay20220(a)gmail.com> This patch adds voltage data for following chips: * Intel 28F002BC/BL/BV/BX-T * Intel 28F004B5/BE/BV/BX-B * Intel 28F004B5/BE/BV/BX-T * Intel 28F008S3/S5/SC * Intel 28F400BV/BX/CE/CV-B * Intel 28F400BV/BX/CE/CV-T * Micron/Numonyx/ST M25P40-old * SyncMOS/MoselVitelic {F,S,V}29C51002T * Winbond W29C010(M)/W29C011A/W29EE011/W29EE012 * Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old Change-Id: I42bc546e03a899086c034c026231955088a7d400 Signed-off-by: Chinmay Lonkar <chinmay20220(a)gmail.com> --- flashchips.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/flashchips.c b/flashchips.c index d155b24..f9cb0cd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8112,6 +8112,7 @@ const struct flashchip flashchips[] = { }, .write = write_82802ab, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -8139,6 +8140,7 @@ const struct flashchip flashchips[] = { }, .write = write_82802ab, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -8166,6 +8168,7 @@ const struct flashchip flashchips[] = { }, .write = write_82802ab, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -8189,6 +8192,7 @@ const struct flashchip flashchips[] = { .unlock = unlock_28f004s5, .write = write_82802ab, .read = read_memmapped, + .voltage = {2700, 3300}, }, { @@ -8217,6 +8221,7 @@ const struct flashchip flashchips[] = { }, .write = write_82802ab, .read = read_memmapped, + .voltage = {2700, 3600}, }, { @@ -8245,6 +8250,7 @@ const struct flashchip flashchips[] = { }, .write = write_82802ab, .read = read_memmapped, + .voltage = {2700, 3600}, }, { @@ -10521,6 +10527,7 @@ const struct flashchip flashchips[] = { .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2300, 3600}, }, { @@ -16884,6 +16891,7 @@ const struct flashchip flashchips[] = { }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {4500, 5500} }, { @@ -16910,6 +16918,7 @@ const struct flashchip flashchips[] = { }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {4500, 5500} }, { @@ -18607,6 +18616,7 @@ const struct flashchip flashchips[] = { }, .write = write_jedec, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -18630,6 +18640,7 @@ const struct flashchip flashchips[] = { }, .write = write_jedec, .read = read_memmapped, + .voltage = {4500, 5500}, }, { -- 2.25.1

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Flashrom sp_stream_buffer_op() API issue
by Chinmay Lonkar 07 May '22

07 May '22

Hi, I'm trying to fix the build errors of flashrom and came across an API error "Argument with 'nonnull' attribute passed null" which occurred in memcpy() function called inside sp_stream_buffer_op() in file serprog.c. We are passing the third argument of sp_stream_buffer_op() as NULL which gets passed on to the second argument of memcpy() and it expects that argument to be nonnull. Can anybody please provide me with the info and docs for knowing exactly what sp_stream_buffer_op() function does? Also, should we report an error when the third argument passed in the sp_stream_buffer_op() is NULL? Thank You! Regards, Chinmay Lonkar

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