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FAILED
by Joseph Smith 06 Aug '13

06 Aug '13

Samsung 550 chromebook

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P4R8L - Asus Pundit R - READ OK (looks like) ERASE FAILED
by Gianluigi Tiesi 05 Aug '13

05 Aug '13

I've got a barebone pc from asus: http://www.asus.com/Barebone_PCs/PunditR/ read flash looks ok perhaps dumps are a bit different I've attached both from flashrom, original from asus in roms.tar.xz other files: info.tar.xz => lspci/lsusb/dmesg/dmidecode read.log.xz => flashrom -r write.log.xz => flashrom -w Hope it helps Regards -- Gianluigi Tiesi <sherpya(a)netfarm.it> EDP Project Leade Netfarm S.r.l. - http://www.netfarm.it/ Free Software: http://oss.netfarm.it/ Q: Because it reverses the logical flow of conversation. A: Why is putting a reply at the top of the message frowned upon? A non-text attachment roms.tar.xz has been stripped. It is available at http://paste.flashrom.org/view.php?id=1709

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Re: [flashrom] Intel DQ45CB - flashrom -V - ouput
by Stefan Tauner 05 Aug '13

05 Aug '13

Hello Kurtis, thanks for your report! The main problem is the locked ME region as seen in the log. For more details please see http://flashrom.org/ME I have added the board to our list of (un)supported boards (with an appropriate note) and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Detect AMD Yangtze (found in Kabini and Tamesh).
by Stefan Tauner 04 Aug '13

04 Aug '13

The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) but the SPI interface does. Bail out in case we detect Yangtze and add infrastructure to distinguish other families too for further refactorings. Also, add ASRock IMB-A180 to the laptop whitelist. Tested on ASRock IMB-A180 with and w/o USE_YANGTZE_HEURISTICS. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- board_enable.c | 2 ++ chipset_enable.c | 2 +- sb600spi.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 65 insertions(+), 3 deletions(-) diff --git a/board_enable.c b/board_enable.c index d60f9cb..074cabb 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2234,6 +2234,7 @@ static int it8718f_gpio63_raise(void) /* * Suited for all boards with ambiguous DMI chassis information, which should be * whitelisted because they are known to work: + * - ASRock IMB-A180(-H) * - Intel D945GCNL * - MSC Q7 Tunnel Creek Module (Q7-TCTC) */ @@ -2322,6 +2323,7 @@ const struct board_match board_matches[] = { {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise}, {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg}, {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise}, + {0x1022, 0x1536, 0x1849, 0x1536, 0x1022, 0x780e, 0x1849, 0x780e, "^Kabini CRB$", NULL, NULL, P2, "ASRock", "IMB-A180(-H)", 0, OK, p2_not_a_laptop}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, diff --git a/chipset_enable.c b/chipset_enable.c index e1a74ae..6c5e34b 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1304,7 +1304,7 @@ const struct penable chipset_enables[] = { {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, - {0x1022, 0x780e, OK, "AMD", "Hudson", enable_flash_sb600}, + {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, diff --git a/sb600spi.c b/sb600spi.c index 74106c2..168e910 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -44,6 +44,59 @@ */ static uint8_t *sb600_spibar = NULL; +enum amd_chipset { + CHIPSET_AMD_UNKNOWN, + CHIPSET_SB6XX, + CHIPSET_SB7XX, /* SP5100 too */ + CHIPSET_SB89XX, /* Hudson-1 too */ + CHIPSET_HUDSON234, + CHIPSET_YANGTZE, +}; +static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; + +static void determine_generation(struct pci_dev *dev) +{ + amd_gen = CHIPSET_AMD_UNKNOWN; + msg_pdbg2("Trying to determine the generation of the SPI interface.\n"); + if (dev->device_id == 0x780e) { + /* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) + * although they use different SPI interfaces. */ +#ifdef USE_YANGTZE_HEURISTICS + /* This heuristic accesses the SPI interface MMIO BAR at locations beyond those supported by + * Hudson in the hope of getting 0xff readback on older chipsets and non-0xff readback on + * Yangtze (and newer, compatible chipsets). */ + int i; + msg_pdbg("Checking for AMD Yangtze (Kabini/Temash) or later... "); + for (i = 0x20; i <= 0x4f; i++) { + if (mmio_readb(sb600_spibar + i) != 0xff) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("found.\n"); + return; + } + } + msg_pdbg("not found. Assuming Hudson.\n"); + amd_gen = CHIPSET_HUDSON234; +#else + struct pci_dev *smbus_dev = pci_dev_find(0x1022, 0x780B); + if (smbus_dev == NULL) { + msg_pdbg("No SMBus device with ID 1022:780B found.\n"); + return; + } + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev >= 0x11 && rev <= 0x15) { + amd_gen = CHIPSET_HUDSON234; + msg_pdbg("Hudson-2/3/4 detected.\n"); + } else if (rev >= 0x39 && rev <= 0x3A) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("Yangtze detected.\n"); + } else { + msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!.\n", rev); + } +#endif + } +} static void reset_internal_fifo_pointer(void) { @@ -281,6 +334,14 @@ int sb600_probe_spi(struct pci_dev *dev) */ sb600_spibar += tmp & 0xfff; + determine_generation(dev); + + if (amd_gen == CHIPSET_YANGTZE) { + msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" + "Please try a newer version of flashrom.\n"); + return ERROR_NONFATAL; + } + tmp = pci_read_long(dev, 0xa0); msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, @@ -312,9 +373,8 @@ int sb600_probe_spi(struct pci_dev *dev) /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); - if (!smbus_dev) { - smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD Hudson */ + smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD FCH */ if (!smbus_dev) { msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); return ERROR_NONFATAL; -- Kind regards, Stefan Tauner

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[PATCH] Detect AMD Yangtze (found in Kabini and Tamesh).
by Stefan Tauner 03 Aug '13

03 Aug '13

The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) but the SPI interface does. Bail out in case we detect Yangtze and add infrastructure to distinguish other families too for further refactorings. Also, add ASRock IMB-A180 to the laptop whitelist. Tested on ASRock IMB-A180 with and w/o USE_YANGTZE_HEURISTIC. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- board_enable.c | 3 +++ chipset_enable.c | 2 +- sb600spi.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 68 insertions(+), 1 deletion(-) diff --git a/board_enable.c b/board_enable.c index a565c15..074cabb 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2234,6 +2234,8 @@ static int it8718f_gpio63_raise(void) /* * Suited for all boards with ambiguous DMI chassis information, which should be * whitelisted because they are known to work: + * - ASRock IMB-A180(-H) + * - Intel D945GCNL * - MSC Q7 Tunnel Creek Module (Q7-TCTC) */ static int p2_not_a_laptop(void) @@ -2321,6 +2323,7 @@ const struct board_match board_matches[] = { {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise}, {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg}, {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise}, + {0x1022, 0x1536, 0x1849, 0x1536, 0x1022, 0x780e, 0x1849, 0x780e, "^Kabini CRB$", NULL, NULL, P2, "ASRock", "IMB-A180(-H)", 0, OK, p2_not_a_laptop}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, diff --git a/chipset_enable.c b/chipset_enable.c index b52a5b4..2706be4 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1304,7 +1304,7 @@ const struct penable chipset_enables[] = { {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, - {0x1022, 0x780e, OK, "AMD", "Hudson", enable_flash_sb600}, + {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, diff --git a/sb600spi.c b/sb600spi.c index e76c04a..ec70ffc 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -44,6 +44,62 @@ */ static uint8_t *sb600_spibar = NULL; +enum amd_chipset { + CHIPSET_AMD_UNKNOWN, + CHIPSET_SB6XX, + CHIPSET_SB7XX, /* SP5100 too */ + CHIPSET_SB89XX, /* Hudson-1 too */ + CHIPSET_HUDSON234, + CHIPSET_YANGTZE, +}; +static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; + +static void determine_generation(struct pci_dev *dev) +{ + amd_gen = CHIPSET_AMD_UNKNOWN; + msg_pdbg2("Trying to determine the generation of the SPI interface.\n"); + if (dev->device_id == 0x780e) { + /* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) + * although they use different SPI interfaces. */ +#ifdef USE_YANGTZE_HEURISTIC + /* This heuristic accesses the SPI interface MMIO BAR at locations beyond those supported by + * Hudson in the hope of getting 0xff readback on older chipsets and non-0xff readback on + * Yangtze (and newer, compatible chipsets). */ + int i; + msg_pdbg("Checking for AMD Yangtze (Kabini/Temash) or later... "); + for (i = 0x20; i <= 0x4f; i++) { + if (mmio_readb(sb600_spibar + i) != 0xff) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("found.\n"); + return; + } + } + msg_pdbg("not found. Assuming Hudson.\n"); + amd_gen = CHIPSET_HUDSON234; +#else + struct pci_dev *smbus_dev = pci_dev_find(0x1022, 0x780B); + if (smbus_dev == NULL) { + msg_pdbg("No SMBus device with ID 1022:780B found.\n"); + return; + } + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev >= 0x11 && rev <= 0x15) { + amd_gen = CHIPSET_HUDSON234; + msg_pdbg("Hudson-2/3/4 detected.\n"); + } else if (rev >= 0x39 && rev <= 0x3A) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("Yangtze detected.\n"); + } else { + msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!.\n", rev); + } +#endif + } else + msg_perr("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n", + __func__, dev->vendor_id, dev->device_id); +} + static void reset_internal_fifo_pointer(void) { @@ -281,6 +337,14 @@ int sb600_probe_spi(struct pci_dev *dev) */ sb600_spibar += tmp & 0xfff; + determine_generation(dev); + + if (amd_gen == CHIPSET_YANGTZE) { + msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" + "Please try a newer version of flashrom.\n"); + return ERROR_NONFATAL; + } + tmp = pci_read_long(dev, 0xa0); msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, -- Kind regards, Stefan Tauner

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Intel DQ45CB - flashrom -V - ouput
by Kurtis W 03 Aug '13

03 Aug '13

flashrom v0.9.5.2-r1517 on Linux 3.2.0-51-generic-pae (i686), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2994M loops per second, 10 myus = 10 us, 100 myus = 101 us, 1000 myus = 999 us, 10000 myus = 10007 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "" DMI string system-product-name: "" DMI string system-version: "000" DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "DQ45CB" DMI string baseboard-version: "AAE30148-303" DMI string chassis-type: "Desktop" Found chipset "Intel ICH10DO" with PCI ID 8086:3a14. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2 Root Complex Register Block address = 0xfed1c000 GCS = 0x1465: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00001a1b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x03ff0280 FREG1: BIOS region (0x00280000-0x003fffff) is read-write. 0x5C: 0x02770003 FREG2: WARNING: Management Engine region (0x00003000-0x00277fff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. 0x64: 0x027f0278 FREG4: Platform Data region (0x00278000-0x0027ffff) is read-write. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0x004240 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00000000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) SPI Read Configuration: prefetching disabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Chip status register is 00 Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x30, id2 0xeb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Found Winbond flash chip "W25Q32" (4096 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). No operations were specified. Restoring MMIO space at 0xb77618a0 Restoring PCI config space for 00:1f:0 reg 0xdc

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flashrom -V Dell XPS L702X
by Don Alexander 01 Aug '13

01 Aug '13

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 - -- CUT -- flashrom -V flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.2, little endian Command line (1 args): flashrom -V Calibrating delay loop... OS timer resolution is 1 usecs, 3017M loops per second, 10 myus = 10 us, 100 myus = 115 us, 1000 myus = 992 us, 10000 myus = 9922 us, 4 myus = 13 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Dell Inc. " DMI string system-product-name: "Dell System XPS L702X" DMI string system-version: "Not Specified" DMI string baseboard-manufacturer: "Dell Inc. " DMI string baseboard-product-name: "03RG89" DMI string baseboard-version: "FAB1" DMI string chassis-type: "Portable" Laptop detected via DMI. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found ITE EC, ID 0x8518,Rev 0x02 on port 0x4e. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. - -- CUT -- - -- == Don Alexander It's a tough job, but some mug has to do it... RooSoft Ltd -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iEYEARECAAYFAlH6Y+4ACgkQuipFNInZ6etJJgCeOwunO2DdppKh3RbSExvBZXem 9BUAniT+UHsGKRlGXNKO3jaie2nYb8mD =C01L -----END PGP SIGNATURE-----

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Re: [flashrom] A quick hack to support AMD Family 16h SOC
by Carl-Daniel Hailfinger 31 Jul '13

31 Jul '13

Am 30.07.2013 23:22 schrieb Wei Hu: > On Tue, Jul 30, 2013 at 1:59 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> This patch should work at normal speed and use the correct FIFO pointer >> registers on Kabini. >> The code is not exactly pretty, but functional and should (in theory) >> need no functional changes before commit. >> >> Please check if read/write works at the expected speed. -VV is >> sufficient this time. > > Reading the 4MB flash took 18 seconds, whereas writing took almost 3 > minutes. Is it normal? On another system with Intel PCH writes were > way faster. There's another FIFO register at offset 0x80 in the new > Kabini interface, which can hopefully speed up things, but the > description is quite dense. > > I'm attaching two -VV logs, one from reading and the other from writing. Thanks! This means my code works well. The following timings are straight from the W25Q32BV datasheet. They may be completely unrealistic. Typical erase time for that chip is around 30 seconds for a sectorwise chip erase (without overhead). The typical write time for that chip (using 5-byte chunks due to the short FIFO for SB600) would be around 600 seconds. Typical write time for that chip with the long Kabini FIFO would be 45 seconds. Add initial read time, sectorwise chip erase time, erase-verify time (full chip read), write time, write-verify time (full chip read) and the write time suddenly looks pretty reasonable. Most important for me was to get the FIFO pointers right for Kabini. Speed issues can be dealt with after the flashrom 0.9.7 release (right now I'm just trying to fix things). That said, the datasheet is rather unclear about the effect of UseSpi100=1, and I'd like to set it to 0. By the way, the data which enabled me to fix the FIFO stuff for Kabini (because the datasheets have room for improvement) is here: http://paste.flashrom.org/view.php?id=1718 Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] A quick hack to support AMD Family 16h SOC
by Carl-Daniel Hailfinger 31 Jul '13

31 Jul '13

Am 30.07.2013 20:55 schrieb Wei Hu: > Attached is a log from flashrom -VVV -p internal -o /tmp/flashrom.log. > Please let me know what else you want to collect. Thanks! > On Sun, Jul 28, 2013 at 3:38 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> Am 26.07.2013 23:31 schrieb Stefan Tauner: >>> On Fri, 26 Jul 2013 12:28:48 -0700 >>> Wei Hu <wei(a)aristanetworks.com> wrote: >>>> On Fri, Jul 26, 2013 at 12:18 AM, Carl-Daniel Hailfinger >>>> <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >>>>>> I'll give you modified patch a test tomorrow. >>>>> Please note that I expect problems with my patch. Not all of the FIFO >>>>> management has been changed, and this might be the cause of error >>>>> messages. Updated patch with more debugging at the end of this mail. >>>> After changing the device ID to match 0x780e, your patch works for >>>> both reading and writing. Writing is extremely slow though. I feel >>>> like on this new FCH we should ditch the SB600 interface and >>>> investigate the new programming interface. My current patch is more >>>> like a band aid workaround. >>> I plan to do that but for now it would be better than nothing, *but* >>> this will break Hudson-2... I talked to Martin Roth from sage and he >>> confirmed that although AMD changed PCI IDs with Hudson-1 the >>> interface did only really change with Kabini/Temash. >>> >>> That explains also why Hudson-2 worked fine previously: >>> http://marc.info/?l=flashrom&m=131853263731000 >>> Wang Qing Pei has tested his Hudson patch too probably before sending >>> it to us but I don't know which system he used exactly. >>> >>> I'll try to get the Hudson-2 datasheets, but ATM I don't have them. >>> We need a way to distinguish Kabini from the rest... since it is a SoC, >>> we could match the pci ids of the root complex >>> (00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 16h >>> Processor Root Complex [1022:1536] in my case), but we would need to >>> maintain that for future models... Martin told me that they just read >>> if the new registers are (non-)0xff and infer from that if they need to >>> use the new interface. >> New patch. Better heuristic (Martin's variant) for Kabini, more debug >> prints. >> The big challenge is to check whether this breaks Hudson variants before >> Kabini. >> >> Please get some -VVV logs for a simple probe. Thanks! >> # flashrom -o logfile.txt -VVV >> >> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> This patch should work at normal speed and use the correct FIFO pointer registers on Kabini. The code is not exactly pretty, but functional and should (in theory) need no functional changes before commit. Please check if read/write works at the expected speed. -VV is sufficient this time. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-kabini/sb600spi.c =================================================================== --- flashrom-kabini/sb600spi.c (Revision 1704) +++ flashrom-kabini/sb600spi.c (Arbeitskopie) @@ -4,7 +4,7 @@ * Copyright (C) 2008 Wang Qingpei <Qingpei.Wang(a)amd.com> * Copyright (C) 2008 Joe Bao <Zheng.Bao(a)amd.com> * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010, 2013 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -45,6 +45,8 @@ static uint8_t *sb600_spibar = NULL; +static int kabini_method = 0; + static void reset_internal_fifo_pointer(void) { mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); @@ -54,33 +56,67 @@ msg_pspew("reset\n"); } -static int compare_internal_fifo_pointer(uint8_t want) +static int check_internal_fifo_pointer(uint8_t have, uint8_t want) { + if (have != want) { + msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash chip.\n"); + return 1; + } + msg_pspew("AMD SPI FIFO pointer is %d, wanted %d\n", have, want); + return 0; +} + +static int compare_internal_kabini_fifo_write_pointer(uint8_t want) +{ uint8_t tmp; + tmp = mmio_readb(sb600_spibar + 0x4d) & 0x7f; + return check_internal_fifo_pointer(tmp, want); +} + +static int compare_internal_kabini_fifo_read_pointer(uint8_t want) +{ + uint8_t tmp; + + tmp = mmio_readb(sb600_spibar + 0x4e) & 0x7f; + return check_internal_fifo_pointer(tmp, want); +} + +static int compare_internal_sb600_fifo_pointer(uint8_t want) +{ + uint8_t tmp; + tmp = mmio_readb(sb600_spibar + 0xd) & 0x07; want &= 0x7; - if (want != tmp) { - msg_perr("FIFO pointer corruption! Pointer is %d, wanted %d\n", tmp, want); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); - return 1; - } else { - msg_pspew("SB600 FIFO pointer is %d, wanted %d\n", tmp, want); - return 0; - } + return check_internal_fifo_pointer(tmp, want); } +#if 0 static int reset_compare_internal_fifo_pointer(uint8_t want) { int ret; +#if 0 + if (kabini_method) { + uint8_t tmp1; + mmio_writeb(7, sb600_spibar + 0x1e); + tmp = mmio_readb(sb600_spibar + 0x1f); + msg_pspew("Kabini SPIDataFifoPtr %d/%d, ", tmp, want); + tmp = mmio_readb(sb600_spibar + 0xd) & 0x07; + msg_pspew("FifoPtr %d/%d, ", tmp, want & 0x07); + tmp = mmio_readb(sb600_spibar + 0x4d) & 0x7f; + tmp1 = mmio_readb(sb600_spibar + 0x4e) & 0x7f; + msg_pspew("FifoWrPtr/FifoRdPtr %d/%d\n", tmp, tmp1); + } +#endif + ret = compare_internal_fifo_pointer(want); reset_internal_fifo_pointer(); return ret; } +#endif static void execute_command(void) { @@ -99,7 +135,7 @@ /* First byte is cmd which can not being sent through FIFO. */ unsigned char cmd = *writearr++; unsigned int readoffby1; - unsigned char readwrite; + unsigned char readwrite = 0; writecnt--; @@ -118,15 +154,21 @@ return SPI_INVALID_LENGTH; } - /* This is a workaround for a bug in SB600 and SB700. If we only send - * an opcode and no additional data/address, the SPI controller will - * read one byte too few from the chip. Basically, the last byte of - * the chip response is discarded and will not end up in the FIFO. - * It is unclear if the CS# line is set high too early as well. - */ - readoffby1 = (writecnt) ? 0 : 1; - readwrite = (readcnt + readoffby1) << 4 | (writecnt); - mmio_writeb(readwrite, sb600_spibar + 1); + if (kabini_method) { + /* Use the extended TxByteCount and RxByteCount register. */ + mmio_writeb(writecnt, sb600_spibar + 0x48); + mmio_writeb(readcnt, sb600_spibar + 0x4b); + } else { + /* This is a workaround for a bug in SB600 and SB700. If we only send + * an opcode and no additional data/address, the SPI controller will + * read one byte too few from the chip. Basically, the last byte of + * the chip response is discarded and will not end up in the FIFO. + * It is unclear if the CS# line is set high too early as well. + */ + readoffby1 = (writecnt) ? 0 : 1; + readwrite = (readcnt + readoffby1) << 4 | (writecnt); + mmio_writeb(readwrite, sb600_spibar + 1); + } mmio_writeb(cmd, sb600_spibar + 0); /* Before we use the FIFO, reset it first. */ @@ -139,16 +181,29 @@ mmio_writeb(*writearr, sb600_spibar + 0xC); } msg_pspew("\n"); + if (kabini_method) { + if (compare_internal_kabini_fifo_write_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } else { + if (compare_internal_sb600_fifo_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } /* * We should send the data by sequence, which means we need to reset * the FIFO pointer to the first byte we want to send. */ - if (reset_compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; + reset_internal_fifo_pointer(); msg_pspew("Executing: \n"); execute_command(); + if (kabini_method) { + if (compare_internal_kabini_fifo_write_pointer(writecnt + readcnt)) + return SPI_PROGRAMMER_ERROR; + } else { + if (compare_internal_sb600_fifo_pointer(writecnt + readcnt)) + return SPI_PROGRAMMER_ERROR; + } /* * After the command executed, we should find out the index of the @@ -161,8 +216,7 @@ * the opcode, the FIFO already stores the response from the chip. * Usually, the chip will respond with 0x00 or 0xff. */ - if (reset_compare_internal_fifo_pointer(writecnt + readcnt)) - return SPI_PROGRAMMER_ERROR; + reset_internal_fifo_pointer(); /* Skip the bytes we sent. */ msg_pspew("Skipping: "); @@ -171,27 +225,53 @@ msg_pspew("[%02x]", cmd); } msg_pspew("\n"); - if (compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; + if (kabini_method) { + if (compare_internal_kabini_fifo_read_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } else { + if (compare_internal_sb600_fifo_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } + msg_pspew("Reading: "); for (count = 0; count < readcnt; count++, readarr++) { *readarr = mmio_readb(sb600_spibar + 0xC); msg_pspew("[%02x]", *readarr); } msg_pspew("\n"); - if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) - return SPI_PROGRAMMER_ERROR; - if (mmio_readb(sb600_spibar + 1) != readwrite) { - msg_perr("Unexpected change in SB600 read/write count!\n"); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); - return SPI_PROGRAMMER_ERROR; + if (kabini_method) { + if (compare_internal_kabini_fifo_read_pointer(writecnt + readcnt)) + return SPI_PROGRAMMER_ERROR; + } else { + if (compare_internal_sb600_fifo_pointer(writecnt + readcnt)) + return SPI_PROGRAMMER_ERROR; } + reset_internal_fifo_pointer(); + if (kabini_method) { + uint8_t tmp_wc = mmio_readb(sb600_spibar + 0x48); + uint8_t tmp_rc = mmio_readb(sb600_spibar + 0x4b); + if ((tmp_rc != readcnt) || (tmp_wc != writecnt)) { + msg_perr("Unexpected change in Kabini read/write count: %i/%i instead of %i/%i!\n", + tmp_rc, tmp_wc, readcnt, writecnt); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash " + "chip.\n"); + return SPI_PROGRAMMER_ERROR; + } + } else { + uint8_t tmp_rw = mmio_readb(sb600_spibar + 1); + if (tmp_rw != readwrite) { + msg_perr("Unexpected change in SB600 read/write count: %i instead of %i!\n", tmp_rw, + readwrite); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash " + "chip.\n"); + return SPI_PROGRAMMER_ERROR; + } + } return 0; } @@ -245,8 +325,8 @@ uint32_t tmp; uint8_t reg; bool amd_imc_force = false; - static const char *const speed_names[4] = { - "66/reserved", "33", "22", "16.5" + static const char *const speed_names[8] = { + "66 MHz", "33 MHz", "22 MHz", "16.6 MHz", "100 MHz", "Reserved", "Reserved", "800 kHz" }; char *arg = extract_programmer_param("amd_imc_force"); @@ -281,6 +361,30 @@ */ sb600_spibar += tmp & 0xfff; + /* AMD Kabini has a different SPI interface. */ + kabini_method = 0; + if (dev->device_id == 0x780e) { + /* The PCI ID of the LPC bridge doesn't change between Hudson-2 and Kabini (Hudson-3) although + * they use different SPI interfaces. ID 0x780e is common for all Hudson variants. This + * heuristic accesses the SPI interface MMIO BAR at locations beyond those supported by + * Hudson-2 and earlier in the hope of getting 0xff readback on older chipsets and non-0xff + * readback on Kabini and newer chipsets. + */ + int i; + msg_pdbg("Checking for AMD Kabini or later... "); + for (i = 0x20; i <= 0x4f; i++) { + if (mmio_readb(sb600_spibar + i) != 0xff) { + kabini_method = 1; + break; + } + } + if (kabini_method) + msg_pdbg("using AMD Kabini SPI access method.\n"); + else + msg_pdbg("not found.\n"); + } + + /* FIXME: Check all accesses below for Kabini incompatibilities. */ tmp = pci_read_long(dev, 0xa0); msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, @@ -300,15 +404,28 @@ * SB700 or later, reads and writes will be corrupted. Abort in this * case. Make sure to avoid this check on SB600. */ - msg_pdbg("(0x%08" PRIx32 ") fastReadEnable=%u, SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + msg_pdbg("(0x%08" PRIx32 ") SpiReadMode/FastReadEnable=%i, SpiArbEnable=%i, SpiAccessMacRomEn=%i, " "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", - tmp, (tmp >> 18) & 0x1, + "SpiBridgeDisable=%i, SpiClkGate/DropOneClkOnRd=%i\n", + tmp, ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1), (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); - tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; - msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); + if (kabini_method) { + tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; + msg_pdbg("UseSpi100 is %i (%s)\n", tmp, tmp ? "unsupported" : "OK"); + tmp = mmio_readw(sb600_spibar + 0x22); + msg_pdbg("TpmSpeedNew is %s\n", speed_names[tmp & 0xf]); + tmp >>= 4; + msg_pdbg("AltSpeedNew is %s\n", speed_names[tmp & 0xf]); + tmp >>= 4; + msg_pdbg("FastSpeedNew is %s\n", speed_names[tmp & 0xf]); + tmp >>= 4; + msg_pdbg("NormSpeedNew is %s\n", speed_names[tmp & 0xf]); + } else { + tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; + msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); + } /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); -- http://www.hailfinger.org/

2 1

MSI H87-G43 flash success :)
by Marek Zakrzewski 30 Jul '13

30 Jul '13

flashrom v0.9.6.1-r1564 on Linux 2.6.18-348.12.1.el5 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel Lynx Point". This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... enable_flash_ich_dc_spi: unknown ICH generation. Please report! WARNING: SPI Configuration Lockdown activated. Enabling hardware sequencing because some important opcode is locked. OK. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) at physical address 0x0. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. flashrom v0.9.6.1-r1564 on Linux 2.6.18-348.12.1.el5 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.1.2 20080704 (Red Hat 4.1.2-54), little endian Command line (2 args): flashrom -V --programmer=internal Calibrating delay loop... OS timer resolution is 1 usecs, 3365M loops per second, 10 myus = 10 us, 100 myus = 106 us, 1000 myus = 1014 us, 10000 myus = 10006 us, 4 myus = 6 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "MSI" DMI string system-product-name: "MS-7816" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "MSI" DMI string baseboard-product-name: "H87-G43 (MS-7816)" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "Intel Lynx Point" with PCI ID 8086:8c4a. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... enable_flash_ich_dc_spi: unknown ICH generation. Please report! 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 Root Complex Register Block address = 0xfed1c000 GCS = 0xc65: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (unknown) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xf008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x08: 0x00ffffc0 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x0fff0a00 FREG1: BIOS region (0x00a00000-0x00ffffff) is read-write. 0x5C: 0x09ff0001 FREG2: Management Engine region (0x00001000-0x009fffff) is read-write. 0x90: 0xc0 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xfc4010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=4 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05203b02 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x80802025 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002025 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x50444653 (FPB) Enabling hardware sequencing because some important opcode is locked. SPI Read Configuration: prefetching enabled, caching enabled, OK. The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip with a density of 16384 kB. The flash address space (0x000000 - 0x9acfff) is divided at address 0x653000 in two partitions. The first partition ranges from 0x000000 to 0x652fff. In that range are 1619 erase blocks with 4096 B each. The second partition ranges from 0x653000 to 0x9acfff. In that range are 2477 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x00, id2 0x03, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x2d, id2 0xbd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x2d, id2 0xbd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific). No operations were specified. Restoring MMIO space at 0x2b92ee7ee8a0 Restoring PCI config space for 00:1f:0 reg 0xdc

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