flashrom

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9163 discussions

Re: [flashrom] flashrom for ECS A785GM-M7
by Stefan Tauner 24 Aug '13

24 Aug '13

On Sat, 24 Aug 2013 16:22:11 +0300 Beeblebrox <zaphod(a)berentweb.com> wrote: > works when using > *gmake* USE_GCC=any Right. Sorry, I am not really familiar with freebsd's ways of things and forgot about this :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] flashrom for ECS A785GM-M7
by Stefan Tauner 24 Aug '13

24 Aug '13

On Sat, 24 Aug 2013 15:12:08 +0300 Beeblebrox <zaphod(a)berentweb.com> wrote: > Hello. > It seems the flash controller on my mobo does not support flashing. > "Super I/O ID 0x8726 is not on the list of flash capable controllers" > Product page: > www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=1089 > Output of flashrom -V -p internal attached. > Regards. Hi there, that line in the log indicates that we have found a chip type that is often used to act as flash controller but which is either unsupported yet or does not have that functionality at all. This is no problem though since your flash is attached differently, namely directly to the SB710 chipset and that should work without a problem. I have changed the verbosity of the message so that it does not show up in "normal" verbose logs and does no longer confuse users. In any case you should be able to use flashrom to read and write the flash chip of that board unless there are other problems. If you are familiar with git and compiling I would very much appreciate if you could test a patch set for improved AMD support. The patches can be found on github. The following commands should grab them, compile them, run flashrom and create a log file named amd-probe.log (hopefully :) which I would like you to send us back. git clone https://github.com/stefanct/flashrom.git cd flashrom git checkout origin/amd -b amd make ./flashrom -p internal -o amd-probe.log -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] flashrom for ECS A785GM-M7
by Beeblebrox 24 Aug '13

24 Aug '13

works when using *gmake* USE_GCC=any On Sat, Aug 24, 2013 at 4:18 PM, Beeblebrox <zaphod(a)berentweb.com> wrote: > On Sat, Aug 24, 2013 at 4:02 PM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > >> On Sat, 24 Aug 2013 15:12:08 +0300 >> Beeblebrox <zaphod(a)berentweb.com> wrote: >> >> > Hello. >> > It seems the flash controller on my mobo does not support flashing. >> > "Super I/O ID 0x8726 is not on the list of flash capable controllers" >> > Product page: >> > www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=1089 >> > Output of flashrom -V -p internal attached. >> > Regards. >> >> Hi there, >> >> that line in the log indicates that we have found a chip type that is >> often used to act as flash controller but which is either unsupported >> yet or does not have that functionality at all. This is no problem >> though since your flash is attached differently, namely directly to the >> SB710 chipset and that should work without a problem. I have changed >> the verbosity of the message so that it does not show up in "normal" >> verbose logs and does no longer confuse users. In any case you should >> be able to use flashrom to read and write the flash chip of that board >> unless there are other problems. >> >> If you are familiar with git and compiling I would very much appreciate >> if you could test a patch set for improved AMD support. >> The patches can be found on github. The following commands should grab >> them, compile them, run flashrom and create a log file named >> amd-probe.log (hopefully :) which I would like you to send us back. >> >> git clone https://github.com/stefanct/flashrom.git >> cd flashrom >> git checkout origin/amd -b amd >> make >> ./flashrom -p internal -o amd-probe.log >> > > > Hi - System: FreeBSD_9.2_stable_amd64 > HAVE INSTALLED: > gmake-3.82_1 GNU version of 'make' utility > libpci-3.2.0 PCI configuration space I/O made easy > libpciaccess-0.13.2 Generic PCI access library > > In flashrom folder, # make => > "Makefile", line 59: Missing dependency operator > "Makefile", line 61: Need an operator > "Makefile", line 68: Missing dependency operator > "Makefile", line 71: Need an operator > "Makefile", line 72: Missing dependency operator > "Makefile", line 74: Need an operator > Error expanding embedded variable. > > All these are "ifeq" commands, paired to endif. > Compilers available: clang 3.3, gcc 4.6, gcc 4.2 > make USE_GCC=any gives same result > > Regards. >

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Re: [flashrom] [PATCH] IT87: Add ability to select between chips on GIGABYTE DualBIOS boards.
by Stefan Tauner 24 Aug '13

24 Aug '13

On Sat, 10 Aug 2013 17:55:55 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Thanks to Vadim Girlin for finding out how to do that > The patent describing the overall implementation of DualBIOS can be found > here: http://www.google.com/patents/US6892323 > This is known to work on GA-MA770-UD3, GA-B75M-D3V, GA-B75N and > GA-H61M-S1 (only M_BIOS is populated). > > Signed-off-by: Vadim Girlin <vadimgirlin(a)gmail.com> > Signed-off-by: Damien Zammit <damien(a)zamaudio.com> > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Tested-by: Damien Zammit <damien(a)zamaudio.com> > Tested-by: Anton Kochkov <anton.kochkov(a)gmail.com> Self-acked and committed in r1720. Thanks everyone! Please report back if you notice any problems with yet untested (GIGABYTE) boards, thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1720 - trunk
by repository service 24 Aug '13

24 Aug '13

Author: stefanct Date: Sat Aug 24 14:18:17 2013 New Revision: 1720 URL: http://flashrom.org/trac/flashrom/changeset/1720 Log: IT87: Add ability to select between chips on GIGABYTE DualBIOS boards. Thanks to Vadim Girlin for finding out how to do that. This is known to work on GA-MA770-UD3, GA-B75M-D3V, GA-B75N and GA-H61M-S1 (only M_BIOS is populated). Signed-off-by: Vadim Girlin <vadimgirlin(a)gmail.com> Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Tested-by: Damien Zammit <damien(a)zamaudio.com> Tested-by: Anton Kochkov <anton.kochkov(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashrom.8 trunk/internal.c trunk/it87spi.c Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Sat Aug 24 04:10:18 2013 (r1719) +++ trunk/flashrom.8 Sat Aug 24 14:18:17 2013 (r1720) @@ -315,6 +315,19 @@ .TP .B ITE IT87 Super I/O .sp +If your mainboard is manufactured by GIGABYTE and supports DualBIOS it is very likely that it uses an +ITE IT87 series Super I/O to switch between the two flash chips. Only one of them can be accessed at a time +and you can manually select which one to use with the +.sp +.B " flashrom \-p internal:dualbiosindex=chip" +.sp +syntax where +.B chip +is the index of the chip to use (0 = main, 1 = backup). You can check which one is currently selected by +leaving out the +.B chip +parameter. +.sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, flashrom should autodetect that configuration. If you want to set the I/O base port of the IT87 series SPI controller manually instead of Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Sat Aug 24 04:10:18 2013 (r1719) +++ trunk/internal.c Sat Aug 24 14:18:17 2013 (r1720) @@ -331,9 +331,8 @@ return ret; #if defined(__i386__) || defined(__x86_64__) - /* Probe unconditionally for IT87* LPC->SPI translation and for - * IT87* Parallel write enable. - */ + /* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and + * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ init_superio_ite(); #endif Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Sat Aug 24 04:10:18 2013 (r1719) +++ trunk/it87spi.c Sat Aug 24 14:18:17 2013 (r1720) @@ -27,6 +27,7 @@ #include <string.h> #include <stdlib.h> +#include <errno.h> #include "flash.h" #include "chipdrivers.h" #include "programmer.h" @@ -36,7 +37,7 @@ #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e -uint16_t it8716f_flashport = 0; +static uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ static int fast_spi = 1; @@ -124,10 +125,40 @@ static uint16_t it87spi_probe(uint16_t port) { uint8_t tmp = 0; - char *portpos = NULL; uint16_t flashport = 0; enter_conf_mode_ite(port); + + char *param = extract_programmer_param("dualbiosindex"); + if (param != NULL) { + sio_write(port, 0x07, 0x07); /* Select GPIO LDN */ + tmp = sio_read(port, 0xEF); + if (*param == '\0') { /* Print current setting only. */ + free(param); + } else { + char *dualbiosindex_suffix; + errno = 0; + long chip_index = strtol(param, &dualbiosindex_suffix, 0); + free(param); + if (errno != 0 || *dualbiosindex_suffix != '\0' || chip_index < 0 || chip_index > 1) { + msg_perr("DualBIOS: Invalid chip index requested - choose 0 or 1.\n"); + exit_conf_mode_ite(port); + return 1; + } + if (chip_index != (tmp & 1)) { + msg_pdbg("DualBIOS: Previous chip index: %d\n", tmp & 1); + sio_write(port, 0xEF, (tmp & 0xFE) | chip_index); + tmp = sio_read(port, 0xEF); + if ((tmp & 1) != chip_index) { + msg_perr("DualBIOS: Chip selection failed.\n"); + exit_conf_mode_ite(port); + return 1; + } + } + } + msg_pinfo("DualBIOS: Selected chip: %d\n", tmp & 1); + } + /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; /* Check if LPC->SPI translation is active. */ @@ -163,11 +194,11 @@ flashport |= sio_read(port, 0x65); msg_pdbg("Serial flash port 0x%04x\n", flashport); /* Non-default port requested? */ - portpos = extract_programmer_param("it87spiport"); - if (portpos) { + param = extract_programmer_param("it87spiport"); + if (param) { char *endptr = NULL; unsigned long forced_flashport; - forced_flashport = strtoul(portpos, &endptr, 0); + forced_flashport = strtoul(param, &endptr, 0); /* Port 0, port >0x1000, unaligned ports and garbage strings * are rejected. */ @@ -180,7 +211,8 @@ msg_perr("Error: it87spiport specified, but no valid " "port specified.\nPort must be a multiple of " "0x8 and lie between 0x100 and 0xff8.\n"); - free(portpos); + exit_conf_mode_ite(port); + free(param); return 1; } else { flashport = (uint16_t)forced_flashport; @@ -190,7 +222,7 @@ sio_write(port, 0x65, (flashport & 0xff)); } } - free(portpos); + free(param); exit_conf_mode_ite(port); it8716f_flashport = flashport; if (internal_buses_supported & BUS_SPI) @@ -228,6 +260,7 @@ case 0x8716: case 0x8718: case 0x8720: + case 0x8728: ret |= it87spi_probe(superios[i].port); break; default:

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flashrom for ECS A785GM-M7
by Beeblebrox 24 Aug '13

24 Aug '13

Hello. It seems the flash controller on my mobo does not support flashing. "Super I/O ID 0x8726 is not on the list of flash capable controllers" Product page: www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=1089 Output of flashrom -V -p internal attached. Regards.

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Re: [flashrom] [PATCH 7/7] Get rid of sp_die().
by Stefan Tauner 24 Aug '13

24 Aug '13

On Wed, 10 Jul 2013 21:21:11 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > - Export msg_perr_strerror() > - Add return values to sp_flush_stream(), sp_pass_writen(), > sp_execute_opbuf(), sp_execute_opbuf_noflush(), > sp_check_opbuf_usage(), sp_do_read_n(). > - Use those return values to propagate errors instead of exiting. > In some places this has to wait for core API changes (error handling for > chip_readb, chip_readn, chip_write) hence comments are added instead. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Slightly refined, self-acked and committed in r1719. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1719 - trunk
by repository service 24 Aug '13

24 Aug '13

Author: stefanct Date: Sat Aug 24 04:10:18 2013 New Revision: 1719 URL: http://flashrom.org/trac/flashrom/changeset/1719 Log: Get rid of sp_die(). - Add return values to sp_flush_stream(), sp_pass_writen(), sp_execute_opbuf(), sp_execute_opbuf_noflush(), sp_check_opbuf_usage(), sp_do_read_n(). - Use those return values to propagate errors instead of exiting. In some places this has to wait for core API changes (error handling for chip_readb, chip_readn, chip_write) hence comments are added instead. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/programmer.h trunk/serial.c trunk/serprog.c Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Aug 24 01:29:23 2013 (r1718) +++ trunk/programmer.h Sat Aug 24 04:10:18 2013 (r1719) @@ -661,7 +661,6 @@ void sp_flush_incoming(void); fdtype sp_openserport(char *dev, unsigned int baud); int serialport_config(fdtype fd, unsigned int baud); -void __attribute__((noreturn)) sp_die(char *msg); extern fdtype sp_fd; /* expose serialport_shutdown as it's currently used by buspirate */ int serialport_shutdown(void *data); Modified: trunk/serial.c ============================================================================== --- trunk/serial.c Sat Aug 24 01:29:23 2013 (r1718) +++ trunk/serial.c Sat Aug 24 04:10:18 2013 (r1719) @@ -41,12 +41,6 @@ fdtype sp_fd = SER_INV_FD; -void __attribute__((noreturn)) sp_die(char *msg) -{ - perror(msg); - exit(1); -} - #ifdef _WIN32 struct baudentry { DWORD flag; Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Sat Aug 24 01:29:23 2013 (r1718) +++ trunk/serprog.c Sat Aug 24 04:10:18 2013 (r1719) @@ -237,43 +237,58 @@ return 0; } -static void sp_flush_stream(void) +static int sp_flush_stream(void) { if (sp_streamed_transmit_ops) do { unsigned char c; if (serialport_read(&c, 1) != 0) { - sp_die("Error: cannot read from device (flushing stream)"); + msg_perr("Error: cannot read from device (flushing stream)"); + return 1; } if (c == S_NAK) { msg_perr("Error: NAK to a stream buffer operation\n"); - exit(1); + return 1; } if (c != S_ACK) { msg_perr("Error: Invalid reply 0x%02X from device\n", c); - exit(1); + return 1; } } while (--sp_streamed_transmit_ops); sp_streamed_transmit_ops = 0; sp_streamed_transmit_bytes = 0; + return 0; } -static int sp_stream_buffer_op(uint8_t cmd, uint32_t parmlen, uint8_t * parms) +static int sp_stream_buffer_op(uint8_t cmd, uint32_t parmlen, uint8_t *parms) { uint8_t *sp; if (sp_automatic_cmdcheck(cmd)) return 1; + sp = malloc(1 + parmlen); - if (!sp) sp_die("Error: cannot malloc command buffer"); + if (!sp) { + msg_perr("Error: cannot malloc command buffer\n"); + return 1; + } sp[0] = cmd; memcpy(&(sp[1]), parms, parmlen); - if (sp_streamed_transmit_bytes >= (1 + parmlen + sp_device_serbuf_size)) - sp_flush_stream(); - if (serialport_write(sp, 1 + parmlen) != 0) - sp_die("Error: cannot write command"); - free(sp); + + if (sp_streamed_transmit_bytes >= (1 + parmlen + sp_device_serbuf_size)) { + if (sp_flush_stream() != 0) { + free(sp); + return 1; + } + } + if (serialport_write(sp, 1 + parmlen) != 0) { + msg_perr("Error: cannot write command\n"); + free(sp); + return 1; + } sp_streamed_transmit_ops += 1; sp_streamed_transmit_bytes += 1 + parmlen; + + free(sp); return 0; } @@ -656,16 +671,16 @@ return 0; } -/* Move an in flashrom buffer existing write-n operation to * - * the on-device operation buffer. */ -static void sp_pass_writen(void) +/* Move an in flashrom buffer existing write-n operation to the on-device operation buffer. */ +static int sp_pass_writen(void) { unsigned char header[7]; - msg_pspew(MSGHEADER "Passing write-n bytes=%d addr=0x%x\n", - sp_write_n_bytes, sp_write_n_addr); - if (sp_streamed_transmit_bytes >= - (7 + sp_write_n_bytes + sp_device_serbuf_size)) - sp_flush_stream(); + msg_pspew(MSGHEADER "Passing write-n bytes=%d addr=0x%x\n", sp_write_n_bytes, sp_write_n_addr); + if (sp_streamed_transmit_bytes >= (7 + sp_write_n_bytes + sp_device_serbuf_size)) { + if (sp_flush_stream() != 0) { + return 1; + } + } /* In case it's just a single byte send it as a single write. */ if (sp_write_n_bytes == 1) { sp_write_n_bytes = 0; @@ -673,9 +688,10 @@ header[1] = (sp_write_n_addr >> 8) & 0xFF; header[2] = (sp_write_n_addr >> 16) & 0xFF; header[3] = sp_write_n_buf[0]; - sp_stream_buffer_op(S_CMD_O_WRITEB, 4, header); + if (sp_stream_buffer_op(S_CMD_O_WRITEB, 4, header) != 0) + return 1; sp_opbuf_usage += 5; - return; + return 0; } header[0] = S_CMD_O_WRITEN; header[1] = (sp_write_n_bytes >> 0) & 0xFF; @@ -684,39 +700,55 @@ header[4] = (sp_write_n_addr >> 0) & 0xFF; header[5] = (sp_write_n_addr >> 8) & 0xFF; header[6] = (sp_write_n_addr >> 16) & 0xFF; - if (serialport_write(header, 7) != 0) - sp_die("Error: cannot write write-n command\n"); - if (serialport_write(sp_write_n_buf, sp_write_n_bytes) != 0) - sp_die("Error: cannot write write-n data"); + if (serialport_write(header, 7) != 0) { + msg_perr(MSGHEADER "Error: cannot write write-n command\n"); + return 1; + } + if (serialport_write(sp_write_n_buf, sp_write_n_bytes) != 0) { + msg_perr(MSGHEADER "Error: cannot write write-n data"); + return 1; + } sp_streamed_transmit_bytes += 7 + sp_write_n_bytes; sp_streamed_transmit_ops += 1; sp_opbuf_usage += 7 + sp_write_n_bytes; sp_write_n_bytes = 0; sp_prev_was_write = 0; + return 0; } -static void sp_execute_opbuf_noflush(void) +static int sp_execute_opbuf_noflush(void) { - if ((sp_max_write_n) && (sp_write_n_bytes)) - sp_pass_writen(); - sp_stream_buffer_op(S_CMD_O_EXEC, 0, NULL); - msg_pspew(MSGHEADER "Executed operation buffer of %d bytes\n", - sp_opbuf_usage); + if ((sp_max_write_n) && (sp_write_n_bytes)) { + if (sp_pass_writen() != 0) { + msg_perr("Error: could not transfer write buffer\n"); + return 1; + } + } + if (sp_stream_buffer_op(S_CMD_O_EXEC, 0, NULL) != 0) { + msg_perr("Error: could not execute command buffer\n"); + return 1; + } + msg_pspew(MSGHEADER "Executed operation buffer of %d bytes\n", sp_opbuf_usage); sp_opbuf_usage = 0; sp_prev_was_write = 0; - return; + return 0; } -static void sp_execute_opbuf(void) +static int sp_execute_opbuf(void) { - sp_execute_opbuf_noflush(); - sp_flush_stream(); + if (sp_execute_opbuf_noflush() != 0) + return 1; + if (sp_flush_stream() != 0) + return 1; + + return 0; } static int serprog_shutdown(void *data) { if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) - sp_execute_opbuf(); + if (sp_execute_opbuf() != 0) + msg_pwarn("Could not flush command buffer.\n"); if (sp_check_commandavail(S_CMD_S_PIN_STATE)) { uint8_t dis = 0; if (sp_docommand(S_CMD_S_PIN_STATE, 1, &dis, 0, NULL) == 0) @@ -731,14 +763,15 @@ return 0; } -static void sp_check_opbuf_usage(int bytes_to_be_added) +static int sp_check_opbuf_usage(int bytes_to_be_added) { if (sp_device_opbuf_size <= (sp_opbuf_usage + bytes_to_be_added)) { - sp_execute_opbuf(); - /* If this happens in the mid of an page load the page load * - * will probably fail. */ - msg_pdbg(MSGHEADER "Warning: executed operation buffer due to size reasons\n"); + /* If this happens in the middle of a page load the page load will probably fail. */ + msg_pwarn(MSGHEADER "Warning: executed operation buffer due to size reasons\n"); + if (sp_execute_opbuf() != 0) + return 1; } + return 0; } static void serprog_chip_writeb(const struct flashctx *flash, uint8_t val, @@ -768,7 +801,7 @@ writeb_parm[1] = (addr >> 8) & 0xFF; writeb_parm[2] = (addr >> 16) & 0xFF; writeb_parm[3] = val; - sp_stream_buffer_op(S_CMD_O_WRITEB, 4, writeb_parm); + sp_stream_buffer_op(S_CMD_O_WRITEB, 4, writeb_parm); // FIXME: return error sp_opbuf_usage += 5; } } @@ -785,16 +818,16 @@ buf[0] = ((addr >> 0) & 0xFF); buf[1] = ((addr >> 8) & 0xFF); buf[2] = ((addr >> 16) & 0xFF); - sp_stream_buffer_op(S_CMD_R_BYTE, 3, buf); - sp_flush_stream(); + sp_stream_buffer_op(S_CMD_R_BYTE, 3, buf); // FIXME: return error + sp_flush_stream(); // FIXME: return error if (serialport_read(&c, 1) != 0) - sp_die("readb byteread"); + msg_perr(MSGHEADER "readb byteread"); // FIXME: return error msg_pspew("%s addr=0x%" PRIxPTR " returning 0x%02X\n", __func__, addr, c); return c; } /* Local version that really does the job, doesn't care of max_read_n. */ -static void sp_do_read_n(uint8_t * buf, const chipaddr addr, size_t len) +static int sp_do_read_n(uint8_t * buf, const chipaddr addr, size_t len) { unsigned char sbuf[6]; msg_pspew("%s: addr=0x%" PRIxPTR " len=%zu\n", __func__, addr, len); @@ -808,10 +841,13 @@ sbuf[4] = ((len >> 8) & 0xFF); sbuf[5] = ((len >> 16) & 0xFF); sp_stream_buffer_op(S_CMD_R_NBYTES, 6, sbuf); - sp_flush_stream(); - if (serialport_read(buf, len) != 0) - sp_die("Error: cannot read read-n data"); - return; + if (sp_flush_stream() != 0) + return 1; + if (serialport_read(buf, len) != 0) { + msg_perr(MSGHEADER "Error: cannot read read-n data"); + return 1; + } + return 0; } /* The externally called version that makes sure that max_read_n is obeyed. */ @@ -821,12 +857,12 @@ size_t lenm = len; chipaddr addrm = addr; while ((sp_max_read_n != 0) && (lenm > sp_max_read_n)) { - sp_do_read_n(&(buf[addrm-addr]), addrm, sp_max_read_n); + sp_do_read_n(&(buf[addrm-addr]), addrm, sp_max_read_n); // FIXME: return error addrm += sp_max_read_n; lenm -= sp_max_read_n; } if (lenm) - sp_do_read_n(&(buf[addrm-addr]), addrm, lenm); + sp_do_read_n(&(buf[addrm-addr]), addrm, lenm); // FIXME: return error } void serprog_delay(int usecs) @@ -858,11 +894,18 @@ unsigned char *parmbuf; int ret; msg_pspew("%s, writecnt=%i, readcnt=%i\n", __func__, writecnt, readcnt); - if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) - sp_execute_opbuf(); + if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) { + if (sp_execute_opbuf() != 0) { + msg_perr("Error: could not execute command buffer before sending SPI commands.\n"); + return 1; + } + } + parmbuf = malloc(writecnt + 6); - if (!parmbuf) - sp_die("Error: cannot malloc SPI send param buffer"); + if (!parmbuf) { + msg_perr("Error: could not allocate SPI send param buffer.\n"); + return 1; + } parmbuf[0] = (writecnt >> 0) & 0xFF; parmbuf[1] = (writecnt >> 8) & 0xFF; parmbuf[2] = (writecnt >> 16) & 0xFF;

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[commit] r1718 - trunk
by repository service 24 Aug '13

24 Aug '13

Author: stefanct Date: Sat Aug 24 01:29:23 2013 New Revision: 1718 URL: http://flashrom.org/trac/flashrom/changeset/1718 Log: Add additional error handling to pcidev_readbar() callers. This is mostly a leftover of Niklas' "remove exit call from pcidev_init" patch. While not explicitly necessary detecting errors early is usually a good idea. Signed-off-by: Niklas Söderlund <niso(a)kth.se> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/atahpt.c trunk/drkaiser.c trunk/gfxnvidia.c trunk/nic3com.c trunk/nicintel.c trunk/nicintel_spi.c trunk/nicnatsemi.c trunk/nicrealtek.c trunk/ogp_spi.c trunk/pcidev.c trunk/satamv.c trunk/satasii.c Modified: trunk/atahpt.c ============================================================================== --- trunk/atahpt.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/atahpt.c Sat Aug 24 01:29:23 2013 (r1718) @@ -69,6 +69,8 @@ return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4); + if (!io_base_addr) + return 1; /* Enable flash access. */ reg32 = pci_read_long(dev, REG_FLASH_ACCESS); Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/drkaiser.c Sat Aug 24 01:29:23 2013 (r1718) @@ -69,6 +69,8 @@ return 1; addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); + if (!addr) + return 1; /* Write magic register to enable flash write. */ rpci_write_word(dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE); Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/gfxnvidia.c Sat Aug 24 01:29:23 2013 (r1718) @@ -90,6 +90,9 @@ return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/nic3com.c Sat Aug 24 01:29:23 2013 (r1718) @@ -96,6 +96,8 @@ return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; id = dev->device_id; Modified: trunk/nicintel.c ============================================================================== --- trunk/nicintel.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/nicintel.c Sat Aug 24 01:29:23 2013 (r1718) @@ -76,12 +76,17 @@ return 1; addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); + if (!addr) + return 1; + nicintel_bar = rphysmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); if (nicintel_bar == ERROR_PTR) return 1; addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); - /* FIXME: This is not an aligned mapping. Use 4k? */ + if (!addr) + return 1; + nicintel_control_bar = rphysmap("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE); if (nicintel_control_bar == ERROR_PTR) return 1; Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/nicintel_spi.c Sat Aug 24 01:29:23 2013 (r1718) @@ -173,6 +173,9 @@ return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, Modified: trunk/nicnatsemi.c ============================================================================== --- trunk/nicnatsemi.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/nicnatsemi.c Sat Aug 24 01:29:23 2013 (r1718) @@ -64,6 +64,8 @@ return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 * in another. My NIC has MA16 connected to A16 on the boot ROM socket Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/nicrealtek.c Sat Aug 24 01:29:23 2013 (r1718) @@ -69,6 +69,8 @@ return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; /* Beware, this ignores the vendor ID! */ switch (dev->device_id) { Modified: trunk/ogp_spi.c ============================================================================== --- trunk/ogp_spi.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/ogp_spi.c Sat Aug 24 01:29:23 2013 (r1718) @@ -131,6 +131,9 @@ return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + ogp_spibar = rphysmap("OGP registers", io_base_addr, 4096); if (ogp_spibar == ERROR_PTR) return 1; Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/pcidev.c Sat Aug 24 01:29:23 2013 (r1718) @@ -94,7 +94,7 @@ supported_cycles = pci_read_word(dev, PCI_COMMAND); - msg_pdbg("Requested BAR is "); + msg_pdbg("Requested BAR is of type "); switch (bartype) { case TYPE_MEMBAR: msg_pdbg("MEM"); Modified: trunk/satamv.c ============================================================================== --- trunk/satamv.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/satamv.c Sat Aug 24 01:29:23 2013 (r1718) @@ -88,6 +88,9 @@ return 1; addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!addr) + return 1; + mv_bar = rphysmap("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) return 1; @@ -136,6 +139,9 @@ /* Get I/O BAR location. */ tmp = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); + if (!addr) + return 1; + /* Truncate to reachable range. * FIXME: Check if the I/O BAR is actually reachable. * This is an arch specific check. Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Fri Aug 23 23:51:32 2013 (r1717) +++ trunk/satasii.c Sat Aug 24 01:29:23 2013 (r1718) @@ -85,9 +85,13 @@ if ((id == 0x3132) || (id == 0x3124)) { addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!addr) + return 1; reg_offset = 0x70; } else { addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5); + if (!addr) + return 1; reg_offset = 0x50; }

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Re: [flashrom] [PATCH 2/2] Introduce serialport_config().
by Stefan Tauner 23 Aug '13

23 Aug '13

On Sat, 1 Jun 2013 02:40:59 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > This allows to easily reconfigure a serial port as needed in > the Bus Pirate speedup. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Self-acked and committed in r1717. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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