flashrom

flashrom@flashrom.org

7 participants
9163 discussions

[PATCH 0/4] layout patches 3.0 (first half)
by Stefan Tauner 12 Sep '13

12 Sep '13

This set is only the infrastructural base on which the patches that make layout handling work in other modes than writing rely on. Stefan Tauner (4): layout: Add a method to cleanup layout data structures. layout: Add -i <image>[:<file>] support. util: add script for converting legacy layout files to format 2. layout: Better file parsing. cli_classic.c | 3 +- flash.h | 1 + flashrom.8.tmpl | 79 ++++--- flashrom.c | 8 +- layout.c | 456 ++++++++++++++++++++++++++++++++++------ util/convert_layout_v1_to_v2.sh | 71 +++++++ 6 files changed, 524 insertions(+), 94 deletions(-) create mode 100755 util/convert_layout_v1_to_v2.sh -- Kind regards, Stefan Tauner

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Genius G540 programmer - anyone looked into supporting it?
by Corey Osgood 12 Sep '13

12 Sep '13

I've bought a Genius G540 programmer, it's a very cheap (~$60 USD on ebay) USB programmer that supports a ton of eproms and flash chips, with reasonable flashing speed, but only with Windows software. I have tried contacting the (chinese) manufacturer for documentation, but got no response. There does exist a sourceforge project, g540tool ( http://sourceforge.net/projects/g540tool/), that supports 4 flash chips, and of those 2 are parallel EPROMs, 1 is LPC flash and 1 is SPI. The downside is that with a current ubuntu install, with libusb installed, it doesn't compile, and the code is very poorly documented. I'm wondering if anyone has looked into supporting this programmer under flashrom, or else if someone with more USB and flashrom experience could take a look at the g540tool code and give me some pointers on where to start. g540tool also has an odd license that I'm not sure how would mesh with GPL. Thanks, Corey

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flashrom upgrade
by it＠sca-uk.com 12 Sep '13

12 Sep '13

Super I/O ID 0x8712 is not on the list of flash capable controllers. The following protocols are supported: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Unknown SFDP-capable chip, 0 kB: No SFDP signature found. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 Found Macronix flash chip "MX25L8005" (1024 kB, SPI). No operations were specified.

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Re: [flashrom] [PATCH] BSD refinements.
by Stefan Tauner 12 Sep '13

12 Sep '13

On Tue, 3 Sep 2013 01:25:17 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Make it easier to compile flashrom under NetBSD and DragonFlyBSD: > - Use /usr/pkg/ as prefix for includes and linking > - Use pciutils as include path for the right(tm) libpci > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> After some wrestling with the sed script to parse subversion's date output which was tested by Idwer quite a few times, I have committed a refined version of this patch in r1742. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 1/6] sbxxx: Add detection for the remaining AMD chipset families.
by Stefan Tauner 12 Sep '13

12 Sep '13

On Tue, 10 Sep 2013 09:31:13 +0200 (CEST) "Carl-Daniel U. Hailfinger" <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > [Sorry for breaking the threading. This is meant to be a reply to > http://patchwork.coreboot.org/patch/4016/ ] > Stefan Tauner wrote on 2013-08-14 17:35:13 > > > > On Wed, 14 Aug 2013 08:42:15 +0200 > > Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > > > > Am 10.08.2013 03:45 schrieb Stefan Tauner: > > > > Also, correct prettyprinting of the registers of the various families, > > > > and abort if SpiAccessMacRomEn or SpiHostAccessRomEn prohibit full access. > > > > > > > > Tested reading/writing on ASRock IMB-A180, and chipset detection on > > > > one of each affected generation by Chris Goodrich from Sage. > > > > > > > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > > > > --- > > > > sb600spi.c | 133 ++++++++++++++++++++++++++++++++++++++++++++++++------------- > > > > 1 file changed, 106 insertions(+), 27 deletions(-) > > > > > > > > diff --git a/sb600spi.c b/sb600spi.c > > > > index cb7c4ac..c9be44c 100644 > > > > --- a/sb600spi.c > > > > +++ b/sb600spi.c > > > > @@ -57,7 +57,28 @@ static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; > > > > static void determine_generation(struct pci_dev *dev) > > > > { > > > > amd_gen = CHIPSET_AMD_UNKNOWN; > > > > - if (dev->device_id == 0x780e) { > > > > + msg_pdbg2("Trying to determine the generation of the SPI interface... "); > > > > + if (dev->device_id == 0x438d) { > > > > + amd_gen = CHIPSET_SB6XX; > > > > + msg_pdbg("SB6xx detected.\n"); > > > > + } else if (dev->device_id == 0x439d) { > > > > + struct pci_dev *smbus_dev = pci_dev_find(0x1002, 0x4385); > > > > > > Why do we search twice for this SMBus device, once inside > > > sb600_probe_spi and once here? Can't we just pass the smbus device as > > > second parameter to determine_generation? > > > > Yes we could and I thought about this too but came to the conclusion > > that it is not worth it. Do you think otherwise? > > I'd really like to limit the number of times we search for PCI devices. > On some machines with lots of PCI devices that can take a lot of time. I have no idea how you come to that conclusion. This uses 0 bus accesses AFAICS because libpci caches that information, but even if we would have to rescan all devices on the bus it would be rather negligible: it does only apply to very few users and I am not sure if any of them would notice it. It might not be pretty theoretically, but I don't anticipate any problems in reality at all. What do you think is the worst case latency added? A few ms? > That said, I also think such refactoring can be done in a later > iteration, and it is also possible to have the generation detection as > first command inside the AMD SBx00 SPI probe function, and let it set > a static struct *smbus_dev. Your choice when/how to deal with it. > > Anyway, most/all of the code above was committed in r1706, so this is > mostly an after-the-fact review. ATM we do only look for the smbus device twice on hudson 2+ and yangtze. With the rebased version of this patch it will be done for all amd chipsets since sb7xx: > > > > + if (smbus_dev == NULL) > > > > + return; > > > > + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); > > > > + if (rev >= 0x39 && rev <= 0x3D) { > > > > + amd_gen = CHIPSET_SB7XX; > > > > + msg_pdbg("SB7xx/SP5100 detected.\n"); > > > > + } else if (rev >= 0x40 && rev <= 0x42) { > > > > + amd_gen = CHIPSET_SB89XX; > > > > + msg_pdbg("SB8xx/SB9xx/Hudson-1 detected.\n"); > > > > + } else { > > > > + msg_pwarn("SB device found but SMBus revision 0x%02x does not match known values.\n" > > > > + "Assuming SB8xx/SB9xx/Hudson-1. Please send a log to flashrom(a)flashrom.org\n", > > > > + rev); > > > > + amd_gen = CHIPSET_SB89XX; > > > > > > We could error out here as well. The next release is a few weeks away > > > anyway. > > > > No regressions if we can easily avoid them please (I'll break enough > > stuff unintentionally, rest assured :) > > It is fairly safe to assume that the code path for sb89xx/hudson will > > work on such devices if they exist, maybe with some wrong prints if it > > is sb7xx but nothing we worried about until I provided a solution for > > it in most cases :) > > I'm not convinced that this would likely introduce a regression. For all > we know, AMD might use higher SMBus device PCI revision IDs for respins > of older chipsets, and there we really want to error out instead of having > flashrom deal with bogus errors. This does only affect pre-hudson2 chipsets. All of them work fine with the existing code for pre-hudson2 chipsets as far as most users are concerned. With my changes applied it would print an additional warning (the one above) and maybe print some verbose messages about registers that do not exist. The latter has been the case since we had sb7xx support and I can't remember anyone complaining (or sending a fix for it). Therefore, I don't see any beneficial effects of bailing out here other than getting notified about different IDs more probably. > > > > - tmp = pci_read_byte(dev, 0xbb); > > > > - /* FIXME: Set bit 3,6,7 if not already set. > > > > - * Set bit 5, otherwise SPI accesses are pointless in LPC mode. > > > > - * See doc 42413 AMD SB700/710/750 RPR. > > > > + /* Chipset support matrix for SPI Base_Addr (LPC PCI reg 0xa0) > > > > + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze > > > > + * 3 rsvd <- <- ? <- ? RouteTpm2Spi > > > > + * 2 rsvd AbortEnable rsvd ? <- ? <- > > > > + * 1 rsvd SpiRomEnable <- ? <- ? <- > > > > + * 0 rsvd AltSpiCSEnable<1> rsvd ? <- ? <- > > > > > > Maybe it's just me, but I have trouble parsing that table. Let's talk > > > about bit 2: What you mean is clear for 6xx (rsvd), 7xx (abortenable), > > > 8xx (abortenable). I'm assuming that this bit is not described for 9xx > > > and hudson1, but why is the hudson2+ entry "?" instead of "<-" ? Or do > > > the "?" entries for 9xx and hudson2+ have a different meaning? > > > > Actually it is the <- that changes meaning, if you will, and the ? are > > not just "we dont know", as one obviously would to infer. > > The ? marks values where we do not have a datasheet, but which we > > assume to be identical to the previous generations. So maybe we should > > use "<-?" instead? Other suggestions are very welcomed. > > Now it should also be clear what the <- after a ? means: we have a > > datasheet and it indicates the same values as the generation *before* > > the question marks before it. I used this mainly for myself but I would > > still like to include it in some form. > > Let me try to phrase this in a way I can understand: > +++++++++++++ > How to read this table: > "nd" means we have no datasheet for this chipset generation. > "ni" means the datasheet for this generation doesn't have any relevant info. > "<-" means the bit/register meaning is identical to the next non-ni/non-nd > chipset to the left. > If a "nd" chipset is between two chipsets with identical meaning, we assume > the meaning didn't change twice in between, i.e. the meaning is unchanged > for the "nd" chipset. This is a tried and (so far) valid assumption. > +++++++++++++ > Your "?" would turn into "nd". > > That said, keeping your symbols is also an option. My phrasing for that > scenario would be: > +++++++++++++ > How to read this table: > "?" means we have no datasheet for this chipset generation or the datasheet > doesn't have any relevant info. > "<-" means the bit/register meaning is identical to the next non-"?" > chipset to the left. "<-" thus never refers to a "?". > If a "?" chipset is between two chipsets with identical meaning, we assume > the meaning didn't change twice in between, i.e. the meaning is unchanged > for the "?" chipset. This is a tried and (so far) valid assumption. > +++++++++++++ I have added an explanation to the source. > > > > + * > > > > + * <1> It is unknown if that was ever working. On later chipsets the CS config is at memmapped 0x1D. > > > > > > Heh. Let's find someone with DualBIOS on a SB7xx board. But seriously, > > > I'd assume this works if it's still in the current revision of the > > > register reference guide. > > > > The problem is (IIRC) that it is not too well defined (who would have > > thought that!) but maybe I am confusing it with Fast Speed. > > AFAICS the meaning is well defined, except that vendors apparently didn't > use it on the boards we know. A simple test would be to set that bit and > check if SPI probe still returns anything. If yes, there are either two > flash chips or my understanding of that bit is wrong. If it is well defined you can surely tell me which pin SPI_CS2# is connected to? Oh actually you can. It is H21 == SPI_CS2#/IMC_GPIO2. My skepticism was rooted in the phrase "When this bit is set, SPI_CS# is routed to a different pin (TBD)" of the RRG. The sb710 databook does actually specify which pin it is... > […] > > > > > */ > > > > - msg_pdbg("(0x%08" PRIx32 ") fastReadEnable=%u, SpiArbEnable=%i, SpiAccessMacRomEn=%i, " > > > > - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " > > > > - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", > > > > - tmp, (tmp >> 18) & 0x1, > > > > - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, > > > > - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, > > > > - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); > > > > + tmp = mmio_readl(sb600_spibar + 0x00); > > > > + msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); > > > > + > > > > + msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i", > > > > + (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7); > > > > + > > > > + if (amd_gen != CHIPSET_YANGTZE) > > > > + msg_pdbg(", SpiBridgeDisable=%i", (tmp >> 27) & 0x1); > > > > + > > > > + switch (amd_gen) { > > > > + case CHIPSET_SB7XX: > > > > + msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1); > > > > > > Should we check that bit and set it to 0? I haven't yet been able to > > > find a good explanation of what it does, but it seems to be a trick to > > > allow normal read commands at higher speed. I could be mistaken, though. > > > > I would refrain from changing it if we don't really know what it does > > (and we probably will never do so...). I have read the description a > > few times... and it does not make a lot of sense to me. > > Maybe our friends at AMD/Sage can explain this? One would have to ask them ;) > > > > + case CHIPSET_SB89XX: > > > > + case CHIPSET_HUDSON234: > > > > + msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1); > > > > + default: break; > > > > + } > > > > + msg_pdbg("\n"); > > > > + > > > > + if (((tmp >> 22) & 0x1) == 0 || ((tmp >> 23) & 0x1) == 0) { > > > > + msg_perr("ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access.\n"); > > > > + return ERROR_NONFATAL; > > > > + } > > > > + > > > > tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; > > > > msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); > > > > > > AFAICS this speed handling stuff is changing in a later patch, correct? > > > > Exactly because this is a good breaking point to avoid a monster > > patch ;) > > > > Thanks for the review! Apart from the ? explanation and the fatal > > error, I think this can go in soon? > > Yes, looks fine otherwise. Could you please forward-port this patch > and repost it? I just want to make sure I didn't overlook anything > serious. > Otherwise, this is (with the ? explanation and the fatal error) > > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> repost follows later. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 3

Re: [flashrom] [PATCH 1/2] sbxxx: Add detection for the remaining AMD chipset families.
by Carl-Daniel Hailfinger 12 Sep '13

12 Sep '13

Am 12.09.2013 17:18 schrieb Stefan Tauner: > Also, correct prettyprinting of the registers of the various families, > and abort if SpiAccessMacRomEn or SpiHostAccessRomEn prohibit full access. > > Tested reading/writing on ASRock IMB-A180, and chipset detection on > one of each affected generation by Chris Goodrich from Sage. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Thanks! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1742 - in trunk: . util
by repository service 12 Sep '13

12 Sep '13

Author: stefanct Date: Thu Sep 12 17:48:39 2013 New Revision: 1742 URL: http://flashrom.org/trac/flashrom/changeset/1742 Log: BSD refinements. Make it easier to compile flashrom under NetBSD and DragonFlyBSD: - Use /usr/pkg/ as prefix for includes and linking - Use pciutils as include path for the right(tm) libpci Also, fix date handling in getrevision.sh to work with the various formats for invoking 'date'. This also uses svn's info --xml output instead of the regular one. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Tested-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/Makefile trunk/README trunk/hwaccess.h trunk/util/getrevision.sh Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Sep 12 17:48:35 2013 (r1741) +++ trunk/Makefile Thu Sep 12 17:48:39 2013 (r1742) @@ -98,6 +98,16 @@ LDFLAGS += -L/usr/local/lib endif +ifeq ($(TARGET_OS), NetBSD) +CPPFLAGS += -I/usr/pkg/include +LDFLAGS += -L/usr/pkg/lib +endif + +ifeq ($(TARGET_OS), DragonFlyBSD) +CPPFLAGS += -I/usr/pkg/include +LDFLAGS += -L/usr/pkg/lib +endif + ifeq ($(TARGET_OS), DOS) EXEC_SUFFIX := .exe CPPFLAGS += -I$(DOSLIBS_BASE)/libgetopt @@ -743,7 +753,11 @@ define LIBPCI_TEST /* Avoid a failing test due to libpci header symbol shadowing breakage */ #define index shadow_workaround_index +#if !defined __NetBSD__ && !defined __DragonFly__ #include <pci/pci.h> +#else +#include <pciutils/pci.h> +#endif struct pci_access *pacc; int main(int argc, char **argv) { Modified: trunk/README ============================================================================== --- trunk/README Thu Sep 12 17:48:35 2013 (r1741) +++ trunk/README Thu Sep 12 17:48:39 2013 (r1742) @@ -80,11 +80,9 @@ gmake LDFLAGS="-L$pathtolibpci" CC="gcc -I$pathtopciheaders" CFLAGS=-O2 -To compile on NetBSD or DragonFly BSD, use: +To compile on NetBSD or DragonFly BSD (with pciutils, libftdi, libusb installed in /usr/pkg/), use: - ln -s /usr/pkg/include/pciutils pci - gmake CPPFLAGS="-I. -I/usr/pkg/include" \ - LDFLAGS="-L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib" + gmake To compile on OpenBSD, use: Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Thu Sep 12 17:48:35 2013 (r1741) +++ trunk/hwaccess.h Thu Sep 12 17:48:39 2013 (r1742) @@ -37,7 +37,13 @@ * or as builtin. */ #define index shadow_workaround_index + +#if !defined (__NetBSD__) && !defined (__DragonFly__) #include <pci/pci.h> +#else +#include <pciutils/pci.h> +#endif + #undef index #endif Modified: trunk/util/getrevision.sh ============================================================================== --- trunk/util/getrevision.sh Thu Sep 12 17:48:35 2013 (r1741) +++ trunk/util/getrevision.sh Thu Sep 12 17:48:39 2013 (r1742) @@ -110,15 +110,33 @@ timestamp() { local t + # date syntaxes are manifold: + # gnu date [-d input]... [+FORMAT] + # netbsd date [-ajnu] [-d date] [-r seconds] [+format] [[[[[[CC]yy]mm]dd]HH]MM[.SS]] + # freebsd date [-jnu] [-d dst] [-r seconds] [-f fmt date | [[[[[cc]yy]mm]dd]HH]MM[.ss]] [+format] [...] + # dragonflybsd date [-jnu] [-d dst] [-r seconds] [-f fmt date | [[[[[cc]yy]mm]dd]HH]MM[.ss]] [+format] [...] + # openbsd date [-aju] [-d dst] [-r seconds] [+format] [[[[[[cc]yy]mm]dd]HH]MM[.SS]] [...] if svn_is_file_tracked "$2" ; then if svn_has_local_changes "$2"; then t=$(date -u "$1") else - # No local changes, get date of the last log record. - local last_commit_date="$(svn info "$2" | \ - grep '^Last Changed Date:' | \ - awk '{print $4" "$5" "$6}')" - t=$(date -d "${last_commit_date}" -u "$1") + # No local changes, get date of the last log record. Subversion provides that in + # ISO 8601 format when using the --xml switch. The sed call extracts that ignoring any + # fractional parts started by a comma or a dot. + local last_commit_date="$(svn info --xml "$2"| \ + sed -n -e 's/<date>$[^,\.]*$$[\.,].*$*Z<\/date>/\1Z/p')" + + case $(uname) in + # Most BSD dates do not support parsing date values from user input with -d but all of + # them support parsing the syntax with [[[[[[cc]yy]mm]dd]HH]MM[.ss]]. We have to + # transform the ISO8601 date first though. + NetBSD|OpenBSD|DragonFly|FreeBSD) + last_commit_date="$(echo ${last_commit_date} | \ + sed -n -e 's/$....$-$..$-$..$T$..$:$..$:$..$Z/\1\2\3\4\5\.\6/p')" + t=$(date -u -j "${last_commit_date}" "$1" 2>/dev/null);; + *) + t=$(date -u -d "${last_commit_date}" "$1" 2>/dev/null);; + esac fi elif git_is_file_tracked "$2" ; then # are there local changes? @@ -126,12 +144,22 @@ t=$(date -u "${1}") else # No local changes, get date of the last commit - t=$(date -d "$(git log --pretty=format:"%cD" -1 -- "$2")" -u "$1") + case $(uname) in + # Most BSD dates do not support parsing date values from user input with -d but all of + # them support parsing epoch seconds with -r. Thanks to git we can easily use that: + NetBSD|OpenBSD|DragonFly|FreeBSD) + t=$(date -u -r "$(git log --pretty=format:%ct -1 -- $2)" "$1" 2>/dev/null);; + *) + t=$(date -d "$(git log --pretty=format:%cD -1 -- $2)" -u "$1" 2>/dev/null);; + esac fi else t=$(date -u "$1") fi + if [ -z "$t" ]; then + echo "Warning: Could not determine timestamp." 2>/dev/null + fi echo "${t}" }

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[commit] r1741 - trunk
by repository service 12 Sep '13

12 Sep '13

Author: stefanct Date: Thu Sep 12 17:48:35 2013 New Revision: 1741 URL: http://flashrom.org/trac/flashrom/changeset/1741 Log: sbxxx: Add detection for the remaining AMD chipset families. Also, correct prettyprinting of the registers of the various families, and abort if SpiAccessMacRomEn or SpiHostAccessRomEn prohibit full access. Tested reading/writing on ASRock IMB-A180, and chipset detection on one of each affected generation by Chris Goodrich from Sage. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/sb600spi.c Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Thu Sep 12 16:04:31 2013 (r1740) +++ trunk/sb600spi.c Thu Sep 12 17:48:35 2013 (r1741) @@ -57,7 +57,28 @@ static void determine_generation(struct pci_dev *dev) { amd_gen = CHIPSET_AMD_UNKNOWN; - if (dev->device_id == 0x780e) { + msg_pdbg2("Trying to determine the generation of the SPI interface... "); + if (dev->device_id == 0x438d) { + amd_gen = CHIPSET_SB6XX; + msg_pdbg("SB6xx detected.\n"); + } else if (dev->device_id == 0x439d) { + struct pci_dev *smbus_dev = pci_dev_find(0x1002, 0x4385); + if (smbus_dev == NULL) + return; + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev >= 0x39 && rev <= 0x3D) { + amd_gen = CHIPSET_SB7XX; + msg_pdbg("SB7xx/SP5100 detected.\n"); + } else if (rev >= 0x40 && rev <= 0x42) { + amd_gen = CHIPSET_SB89XX; + msg_pdbg("SB8xx/SB9xx/Hudson-1 detected.\n"); + } else { + msg_pwarn("SB device found but SMBus revision 0x%02x does not match known values.\n" + "Assuming SB8xx/SB9xx/Hudson-1. Please send a log to flashrom(a)flashrom.org\n", + rev); + amd_gen = CHIPSET_SB89XX; + } + } else if (dev->device_id == 0x780e) { /* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) * although they use different SPI interfaces. */ #ifdef USE_YANGTZE_HEURISTICS @@ -94,7 +115,11 @@ "the output of lspci -nnvx, thanks!.\n", rev); } #endif - } + } else + msg_pwarn("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!\n", + __func__, dev->vendor_id, dev->device_id); } static void reset_internal_fifo_pointer(void) @@ -250,7 +275,7 @@ static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) { /* Handle IMC everywhere but sb600 which does not have one. */ - if (dev->device_id == 0x438d) + if (amd_gen == CHIPSET_SB6XX) return 0; /* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at @@ -336,6 +361,10 @@ sb600_spibar += tmp & 0xfff; determine_generation(dev); + if (amd_gen == CHIPSET_AMD_UNKNOWN) { + msg_perr("Could not determine chipset generation."); + return ERROR_NONFATAL; + } if (amd_gen == CHIPSET_YANGTZE) { msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" @@ -343,35 +372,89 @@ return ERROR_NONFATAL; } - tmp = pci_read_long(dev, 0xa0); - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, - (tmp & 0x4) >> 2); - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); - - tmp = pci_read_byte(dev, 0xbb); - /* FIXME: Set bit 3,6,7 if not already set. - * Set bit 5, otherwise SPI accesses are pointless in LPC mode. - * See doc 42413 AMD SB700/710/750 RPR. + /* How to read the following table and similar ones in this file: + * "?" means we have no datasheet for this chipset generation or it doesn't have any relevant info. + * "<-" means the bit/register meaning is identical to the next non-"?" chipset to the left. "<-" thus + * never refers to another "?". + * If a "?" chipset is between two chipsets with identical meaning, we assume the meaning didn't change + * twice in between, i.e. the meaning is unchanged for the "?" chipset. Usually we assume that + * succeeding hardware supports the same functionality as its predecessor unless proven different by + * tests or documentation, hence "?" will often be implemented equally to "<-". + * + * Chipset support matrix for SPI Base_Addr (LPC PCI reg 0xa0) + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze + * 3 rsvd <- <- ? <- ? RouteTpm2Spi + * 2 rsvd AbortEnable rsvd ? <- ? <- + * 1 rsvd SpiRomEnable <- ? <- ? <- + * 0 rsvd AltSpiCSEnable rsvd ? <- ? <- */ - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", - tmp & 0x1, (tmp & 0x20) >> 5); - tmp = mmio_readl(sb600_spibar); - /* FIXME: If SpiAccessMacRomEn or SpiHostAccessRomEn are zero on - * SB700 or later, reads and writes will be corrupted. Abort in this - * case. Make sure to avoid this check on SB600. + if (amd_gen >= CHIPSET_SB7XX) { + tmp = pci_read_long(dev, 0xa0); + msg_pdbg("SpiRomEnable=%i", (tmp >> 1) & 0x1); + if (amd_gen == CHIPSET_SB7XX) + msg_pdbg(", AltSpiCSEnable=%i, AbortEnable=%i", tmp & 0x1, (tmp >> 2) & 0x1); + + tmp = pci_read_byte(dev, 0xba); + msg_pdbg(", PrefetchEnSPIFromIMC=%i", (tmp & 0x4) >> 2); + + tmp = pci_read_byte(dev, 0xbb); + /* FIXME: Set bit 3,6,7 if not already set. + * Set bit 5, otherwise SPI accesses are pointless in LPC mode. + * See doc 42413 AMD SB700/710/750 RPR. + */ + if (amd_gen == CHIPSET_SB7XX) + msg_pdbg(", SpiOpEnInLpcMode=%i", (tmp >> 5) & 0x1); + msg_pdbg(", PrefetchEnSPIFromHost=%i\n", tmp & 0x1); + } + + /* Chipset support matrix for SPI_Cntrl0 (spibar + 0x0) + * See the chipset support matrix for SPI Base_Addr above for an explanation of the symbols used. + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze + * 17 rsvd <- <- ? <- ? <- + * 18 rsvd <- fastReadEnable<1> ? <- ? SpiReadMode[0] + * 19 SpiArbEnable <- <- ? <- ? <- + * 20 (FifoPtrClr) <- <- ? <- ? <- + * 21 (FifoPtrInc) <- <- ? <- ? IllegalAccess + * 22 SpiAccessMacRomEn <- <- ? <- ? <- + * 23 SpiHostAccessRomEn <- <- ? <- ? <- + * 24:26 ArbWaitCount <- <- ? <- ? <- + * 27 SpiBridgeDisable <- <- ? <- ? rsvd + * 28 rsvd DropOneClkOnRd = SPIClkGate ? <- ? <- + * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] + * 31 rsvd <- SpiBusy ? <- ? <- */ - msg_pdbg("(0x%08" PRIx32 ") fastReadEnable=%u, SpiArbEnable=%i, SpiAccessMacRomEn=%i, " - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", - tmp, (tmp >> 18) & 0x1, - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); + tmp = mmio_readl(sb600_spibar + 0x00); + msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); + + msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i", + (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7); + + if (amd_gen != CHIPSET_YANGTZE) + msg_pdbg(", SpiBridgeDisable=%i", (tmp >> 27) & 0x1); + + switch (amd_gen) { + case CHIPSET_SB7XX: + msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1); + case CHIPSET_SB89XX: + case CHIPSET_HUDSON234: + msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1); + default: break; + } + msg_pdbg("\n"); + + if (((tmp >> 22) & 0x1) == 0 || ((tmp >> 23) & 0x1) == 0) { + msg_perr("ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access.\n"); + return ERROR_NONFATAL; + } + tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); + if (amd_gen >= CHIPSET_SB89XX) { + tmp = mmio_readb(sb600_spibar + 0x1D); + msg_pdbg("Using SPI_CS%d\n", tmp & 0x3); + } + /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); if (!smbus_dev) {

1 0

[PATCH 2/2] sbxxx: Set SPI clock to 16.5 MHz and disable fast reads.
by Stefan Tauner 12 Sep '13

12 Sep '13

Do not rely on broken firmware to set up the SPI configuration correctly. Some boards fail with flashrom because the firmware chose too high speeds for the alternate SPI mode which flashrom uses. Temporarily change the clock to the lowest common value of 16.5 MHz. Also, disable fast reads just to be safe. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- sb600spi.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 63 insertions(+), 8 deletions(-) diff --git a/sb600spi.c b/sb600spi.c index febeabb..91268c0 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -272,6 +272,62 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, return 0; } +struct spispeed { + const char *const name; + const int8_t speed; +}; + +static const struct spispeed spispeeds[] = { + { "66 MHz", 0x00 }, + { "33 MHz", 0x01 }, + { "22 MHz", 0x02 }, + { "16.5 MHz", 0x03 }, +}; + +static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) +{ + bool success = false; + uint8_t speed = spispeed->speed; + + msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed); + if (amd_gen != CHIPSET_YANGTZE) { + rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd); + success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3)); + } + + if (!success) { + msg_perr("Setting SPI clock failed.\n"); + return 1; + } + return 0; +} + +static int handle_speed(struct pci_dev *dev) +{ + uint32_t tmp; + int8_t spispeed_idx = 3; /* Default to 16.5 MHz */ + + /* See the chipset support matrix for SPI Base_Addr below for an explanation of the symbols used. + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze + * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] + * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] + */ + if (amd_gen != CHIPSET_YANGTZE) { + if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { + bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1; + msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis"); + if (fast_read) { + msg_pdbg("Disabling them temporarily.\n"); + rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18), + sb600_spibar + 0x00); + } + } + tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; + msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); + } + return set_speed(dev, &spispeeds[spispeed_idx]); +} + static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) { /* Handle IMC everywhere but sb600 which does not have one. */ @@ -322,9 +378,6 @@ int sb600_probe_spi(struct pci_dev *dev) uint32_t tmp; uint8_t reg; bool amd_imc_force = false; - static const char *const speed_names[4] = { - "66/reserved", "33", "22", "16.5" - }; char *arg = extract_programmer_param("amd_imc_force"); if (arg && !strcmp(arg, "yes")) { @@ -411,7 +464,7 @@ int sb600_probe_spi(struct pci_dev *dev) * See the chipset support matrix for SPI Base_Addr above for an explanation of the symbols used. * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze * 17 rsvd <- <- ? <- ? <- - * 18 rsvd <- fastReadEnable<1> ? <- ? SpiReadMode[0] + * 18 rsvd <- fastReadEnable<1> ? <- ? SpiReadMode[0]<1> * 19 SpiArbEnable <- <- ? <- ? <- * 20 (FifoPtrClr) <- <- ? <- ? <- * 21 (FifoPtrInc) <- <- ? <- ? IllegalAccess @@ -420,8 +473,10 @@ int sb600_probe_spi(struct pci_dev *dev) * 24:26 ArbWaitCount <- <- ? <- ? <- * 27 SpiBridgeDisable <- <- ? <- ? rsvd * 28 rsvd DropOneClkOnRd = SPIClkGate ? <- ? <- - * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] + * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1]<1> * 31 rsvd <- SpiBusy ? <- ? <- + * + * <1> see handle_speed */ tmp = mmio_readl(sb600_spibar + 0x00); msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); @@ -447,9 +502,6 @@ int sb600_probe_spi(struct pci_dev *dev) return ERROR_NONFATAL; } - tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; - msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); - if (amd_gen >= CHIPSET_SB89XX) { tmp = mmio_readb(sb600_spibar + 0x1D); msg_pdbg("Using SPI_CS%d\n", tmp & 0x3); @@ -494,6 +546,9 @@ int sb600_probe_spi(struct pci_dev *dev) return 0; } + if (handle_speed(dev) != 0) + return ERROR_FATAL; + if (sb600_handle_imc(dev, amd_imc_force) != 0) return ERROR_FATAL; -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH] Makefile: Warn if user tries to compile for libpayload w/o crossgcc.
by Stefan Tauner 12 Sep '13

12 Sep '13

On Thu, 29 Aug 2013 03:05:46 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > While flashrom is not as picky on compilers as coreboot, there is still a > high probablilty of breakage when one combines libpayload and distribution > compilers. Print a warning if we detect that to give the daring user a hint how > to resolve the explosions potentially following below it. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> r1740 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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