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[commit] r1749 - trunk
by repository service 15 Sep '13

15 Sep '13

Author: stefanct Date: Sun Sep 15 16:01:06 2013 New Revision: 1749 URL: http://flashrom.org/trac/flashrom/changeset/1749 Log: layout: Add a method to cleanup layout data structures. Add layout_cleanup() to layout.c and hook it up in cli_classic.c. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/cli_classic.c trunk/flash.h trunk/layout.c Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Sun Sep 15 01:37:01 2013 (r1748) +++ trunk/cli_classic.c Sun Sep 15 16:01:06 2013 (r1749) @@ -221,8 +221,6 @@ free(tempstr); cli_classic_abort_usage(); } - /* FIXME: A pointer to the image name is saved in a static array (of size MAX_ROMLAYOUT) - * by register_include_arg() and needs to be freed after processing them. */ break; case 'L': if (++operation_specified > 1) { @@ -527,6 +525,7 @@ for (i = 0; i < chipcount; i++) free(flashes[i].chip); + layout_cleanup(); free(filename); free(layoutfile); free(pparam); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Sep 15 01:37:01 2013 (r1748) +++ trunk/flash.h Sun Sep 15 16:01:06 2013 (r1749) @@ -320,6 +320,7 @@ int process_include_args(void); int read_romlayout(char *name); int handle_romentries(const struct flashctx *flash, uint8_t *oldcontents, uint8_t *newcontents); +void layout_cleanup(void); /* spi.c */ struct spi_command { Modified: trunk/layout.c ============================================================================== --- trunk/layout.c Sun Sep 15 01:37:01 2013 (r1748) +++ trunk/layout.c Sun Sep 15 16:01:06 2013 (r1749) @@ -3,6 +3,7 @@ * * Copyright (C) 2005-2008 coresystems GmbH * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) + * Copyright (C) 2011-2013 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -189,6 +190,21 @@ return 0; } +void layout_cleanup(void) +{ + int i; + for (i = 0; i < num_include_args; i++) { + free(include_args[i]); + include_args[i] = NULL; + } + num_include_args = 0; + + for (i = 0; i < num_rom_entries; i++) { + rom_entries[i].included = 0; + } + num_rom_entries = 0; +} + romentry_t *get_next_included_romentry(unsigned int start) { int i;

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[PATCH] Combine enable_flash_ich_4e() and enable_flash_ich_dc().
by Stefan Tauner 15 Sep '13

15 Sep '13

Putting parameters into function names is not where they belong. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 76 ++++++++++++++++++++++++-------------------------------- programmer.h | 3 ++- 2 files changed, 34 insertions(+), 45 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index c85db73..00070bd 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -314,15 +314,6 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, uint8_t bios_ return 0; } -static int enable_flash_ich0(struct pci_dev *dev, const char *name) -{ - internal_buses_supported = BUS_FWH; - /* FIXME: Make this use enable_flash_ich_4e() too and add IDSEL support. Unlike later chipsets, - * ICH and ICH-0 do only support mapping of the top-most 4MB and therefore do only feature - * FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */ - return enable_flash_ich(dev, name, 0x4e); -} - static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) { uint32_t fwh_conf; @@ -342,6 +333,10 @@ static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name, en fwh_sel2 = 0xee; fwh_dec_en_lo = 0xf0; fwh_dec_en_hi = 0xe3; + } else if (ich_generation == CHIPSET_ICH) { + /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB + * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */ + return 0; } else { msg_perr("Error: FWH decode setting not implemented.\n"); return ERROR_FATAL; @@ -448,7 +443,8 @@ idsel_garbage_out: return 0; } -static int enable_flash_ich_4e(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) +static int enable_flash_ich_fwh(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation, + uint8_t bios_cntl) { int err; @@ -456,48 +452,41 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name, enum ich_c if ((err = enable_flash_ich_fwh_decode(dev, name, ich_generation)) != 0) return err; + /* If we're called by enable_flash_ich_spi, it will override + * internal_buses_supported anyway. + */ internal_buses_supported = BUS_FWH; - return enable_flash_ich(dev, name, 0x4e); + return enable_flash_ich(dev, name, bios_cntl); +} + +static int enable_flash_ich0(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_fwh(dev, name, CHIPSET_ICH, 0x4e); } static int enable_flash_ich2(struct pci_dev *dev, const char *name) { - return enable_flash_ich_4e(dev, name, CHIPSET_ICH2); + return enable_flash_ich_fwh(dev, name, CHIPSET_ICH2, 0x4e); } static int enable_flash_ich3(struct pci_dev *dev, const char *name) { - return enable_flash_ich_4e(dev, name, CHIPSET_ICH3); + return enable_flash_ich_fwh(dev, name, CHIPSET_ICH3, 0x4e); } static int enable_flash_ich4(struct pci_dev *dev, const char *name) { - return enable_flash_ich_4e(dev, name, CHIPSET_ICH4); + return enable_flash_ich_fwh(dev, name, CHIPSET_ICH4, 0x4e); } static int enable_flash_ich5(struct pci_dev *dev, const char *name) { - return enable_flash_ich_4e(dev, name, CHIPSET_ICH5); -} - -static int enable_flash_ich_dc(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) -{ - int err; - - /* Configure FWH IDSEL decoder maps. */ - if ((err = enable_flash_ich_fwh_decode(dev, name, ich_generation)) != 0) - return err; - - /* If we're called by enable_flash_ich_dc_spi, it will override - * internal_buses_supported anyway. - */ - internal_buses_supported = BUS_FWH; - return enable_flash_ich(dev, name, 0xdc); + return enable_flash_ich_fwh(dev, name, CHIPSET_ICH5, 0x4e); } static int enable_flash_ich6(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc(dev, name, CHIPSET_ICH6); + return enable_flash_ich_fwh(dev, name, CHIPSET_ICH6, 0xdc); } static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) @@ -565,8 +554,7 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) return ret; } -static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, - enum ich_chipset ich_generation) +static int enable_flash_ich_spi(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) { int ret, ret_spi; uint8_t bbs, buc; @@ -619,7 +607,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, } /* Enable Flash Writes */ - ret = enable_flash_ich_dc(dev, name, ich_generation); + ret = enable_flash_ich_fwh(dev, name, ich_generation, 0xdc); if (ret == ERROR_FATAL) return ret; @@ -683,58 +671,58 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, static int enable_flash_ich7(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH7); + return enable_flash_ich_spi(dev, name, CHIPSET_ICH7); } static int enable_flash_ich8(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH8); + return enable_flash_ich_spi(dev, name, CHIPSET_ICH8); } static int enable_flash_ich9(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH9); + return enable_flash_ich_spi(dev, name, CHIPSET_ICH9); } static int enable_flash_ich10(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH10); + return enable_flash_ich_spi(dev, name, CHIPSET_ICH10); } /* Ibex Peak aka. 5 series & 3400 series */ static int enable_flash_pch5(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_5_SERIES_IBEX_PEAK); + return enable_flash_ich_spi(dev, name, CHIPSET_5_SERIES_IBEX_PEAK); } /* Cougar Point aka. 6 series & c200 series */ static int enable_flash_pch6(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_6_SERIES_COUGAR_POINT); + return enable_flash_ich_spi(dev, name, CHIPSET_6_SERIES_COUGAR_POINT); } /* Panther Point aka. 7 series */ static int enable_flash_pch7(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_7_SERIES_PANTHER_POINT); + return enable_flash_ich_spi(dev, name, CHIPSET_7_SERIES_PANTHER_POINT); } /* Lynx Point aka. 8 series */ static int enable_flash_pch8(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_LYNX_POINT); + return enable_flash_ich_spi(dev, name, CHIPSET_8_SERIES_LYNX_POINT); } /* Lynx Point aka. 8 series low-power */ static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_LYNX_POINT_LP); + return enable_flash_ich_spi(dev, name, CHIPSET_8_SERIES_LYNX_POINT_LP); } /* Wellsburg (for Haswell-EP Xeons) */ static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_WELLSBURG); + return enable_flash_ich_spi(dev, name, CHIPSET_8_SERIES_WELLSBURG); } static int via_no_byte_merge(struct pci_dev *dev, const char *name) diff --git a/programmer.h b/programmer.h index ef96c9e..187390d 100644 --- a/programmer.h +++ b/programmer.h @@ -557,7 +557,8 @@ int register_spi_programmer(const struct spi_programmer *programmer); /* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */ enum ich_chipset { CHIPSET_ICH_UNKNOWN, - CHIPSET_ICH2 = 2, + CHIPSET_ICH = 1, + CHIPSET_ICH2, CHIPSET_ICH3, CHIPSET_ICH4, CHIPSET_ICH5, -- Kind regards, Stefan Tauner

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Large FWH support
by Kyösti Mälkki 15 Sep '13

15 Sep '13

Hi I came across two problems using 2 MiB FWH flash on two different boards with old ICH4 and ICH6 chipsets: First, ICH3/4/5 do not implement fwh_idsel= parameter. If vendor bios had the default map of 1 MiB, it did not even detect 2 MiB flash chips. For this I have patches prepared already. Before: (idsel_failure.txt) Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xbf, id2 0x5c Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content After: (idsel_ok.txt) Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xbf, id2 0x5c Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xbf, id2 0x5c Found SST flash chip "SST49LF016C" (2048 kB, FWH) at physical address 0xffe00000. Second, a board with ICH6 had all except one 512 kiB range of flash disabled by vendor bios and it would not detect 1MiB and 2MiB flash chips. NOTE: the board actually had 512kiB flash for these logs, but you can see where ther problem is. Before: (decode-disabled.txt) 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode disabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled ... Maximum FWH chip size: 0x80000 bytes ... Probing for SST SST49LF008C, 1024 kB: Chip size 1024 kB is bigger than supported size 512 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content I used the following as a work-around for ICH6, but this should be derived from fwh_idsel= parameter: $ setpci -s 0:1f.0 0xd8.W=0xf0c0 After: (decode-enabled.txt) 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled Maximum FWH chip size: 0x200000 bytes Regards, Kyösti Mälkki

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[commit] r1748 - trunk
by repository service 15 Sep '13

15 Sep '13

Author: stefanct Date: Sun Sep 15 01:37:01 2013 New Revision: 1748 URL: http://flashrom.org/trac/flashrom/changeset/1748 Log: Enable fwh_idsel parameter for C-ICH and ICH2/3/4/5 chipsets. Register locations are different from ICH6, but otherwise appear to have identical bit specifications and defaults. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c trunk/flashrom.8.tmpl Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Sep 15 01:36:57 2013 (r1747) +++ trunk/chipset_enable.c Sun Sep 15 01:37:01 2013 (r1748) @@ -323,7 +323,7 @@ return enable_flash_ich(dev, name, 0x4e); } -static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name) +static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) { uint32_t fwh_conf; uint8_t fwh_sel1, fwh_sel2, fwh_dec_en_lo, fwh_dec_en_hi; @@ -332,11 +332,20 @@ int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; int contiguous = 1; - /* Register map from ICH6 onwards. */ - fwh_sel1 = 0xd0; - fwh_sel2 = 0xd4; - fwh_dec_en_lo = 0xd8; - fwh_dec_en_hi = 0xd9; + if (ich_generation >= CHIPSET_ICH6) { + fwh_sel1 = 0xd0; + fwh_sel2 = 0xd4; + fwh_dec_en_lo = 0xd8; + fwh_dec_en_hi = 0xd9; + } else if (ich_generation >= CHIPSET_ICH2) { + fwh_sel1 = 0xe8; + fwh_sel2 = 0xee; + fwh_dec_en_lo = 0xf0; + fwh_dec_en_hi = 0xe3; + } else { + msg_perr("Error: FWH decode setting not implemented.\n"); + return ERROR_FATAL; + } idsel = extract_programmer_param("fwh_idsel"); if (idsel && strlen(idsel)) { @@ -441,11 +450,12 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) { - /* - * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and - * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and - * FB_DEC_EN2. - */ + int err; + + /* Configure FWH IDSEL decoder maps. */ + if ((err = enable_flash_ich_fwh_decode(dev, name, ich_generation)) != 0) + return err; + internal_buses_supported = BUS_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -475,7 +485,7 @@ int err; /* Configure FWH IDSEL decoder maps. */ - if ((err = enable_flash_ich_fwh_decode(dev, name)) != 0) + if ((err = enable_flash_ich_fwh_decode(dev, name, ich_generation)) != 0) return err; /* If we're called by enable_flash_ich_dc_spi, it will override Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sun Sep 15 01:36:57 2013 (r1747) +++ trunk/flashrom.8.tmpl Sun Sep 15 01:37:01 2013 (r1748) @@ -397,7 +397,7 @@ probably bring it into an inconsistent and unbootable state and we will not provide any support in such a case. .sp -If you have an Intel chipset with an ICH6 or later southbridge and if you want +If you have an Intel chipset with an ICH2 or later southbridge and if you want to set specific IDSEL values for a non-default flash chip or an embedded controller (EC), you can use the .sp

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[commit] r1747 - trunk
by repository service 15 Sep '13

15 Sep '13

Author: stefanct Date: Sun Sep 15 01:36:57 2013 New Revision: 1747 URL: http://flashrom.org/trac/flashrom/changeset/1747 Log: Use ich_generation parameter in enable functions prior to ICH7. Follow the style used from ICH7 onwards to pass ich_generation parameter to lower-level functions on older ICH chipsets too. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c trunk/programmer.h Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Sep 15 01:36:53 2013 (r1746) +++ trunk/chipset_enable.c Sun Sep 15 01:36:57 2013 (r1747) @@ -314,14 +314,12 @@ return 0; } -static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) +static int enable_flash_ich0(struct pci_dev *dev, const char *name) { - /* - * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and - * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and - * FB_DEC_EN2. - */ internal_buses_supported = BUS_FWH; + /* FIXME: Make this use enable_flash_ich_4e() too and add IDSEL support. Unlike later chipsets, + * ICH and ICH-0 do only support mapping of the top-most 4MB and therefore do only feature + * FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */ return enable_flash_ich(dev, name, 0x4e); } @@ -441,7 +439,38 @@ return 0; } -static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) +static int enable_flash_ich_4e(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) +{ + /* + * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and + * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and + * FB_DEC_EN2. + */ + internal_buses_supported = BUS_FWH; + return enable_flash_ich(dev, name, 0x4e); +} + +static int enable_flash_ich2(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_4e(dev, name, CHIPSET_ICH2); +} + +static int enable_flash_ich3(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_4e(dev, name, CHIPSET_ICH3); +} + +static int enable_flash_ich4(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_4e(dev, name, CHIPSET_ICH4); +} + +static int enable_flash_ich5(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_4e(dev, name, CHIPSET_ICH5); +} + +static int enable_flash_ich_dc(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) { int err; @@ -456,6 +485,11 @@ return enable_flash_ich(dev, name, 0xdc); } +static int enable_flash_ich6(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_dc(dev, name, CHIPSET_ICH6); +} + static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) { uint16_t old, new; @@ -575,7 +609,7 @@ } /* Enable Flash Writes */ - ret = enable_flash_ich_dc(dev, name); + ret = enable_flash_ich_dc(dev, name, ich_generation); if (ret == ERROR_FATAL) return ret; @@ -1495,21 +1529,21 @@ {0x8086, 0x1e5f, NT, "Intel", "NM70", enable_flash_pch7}, {0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7}, {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, - {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, - {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, - {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, - {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e}, - {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich_4e}, - {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e}, - {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e}, - {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e}, - {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e}, - {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e}, - {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e}, - {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc}, - {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich_dc}, - {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc}, + {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, + {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0}, + {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2}, + {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2}, + {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2}, + {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich3}, + {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich3}, + {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich4}, + {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich4}, + {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich5}, + {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich5}, + {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6}, + {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich6}, + {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6}, + {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6}, {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sun Sep 15 01:36:53 2013 (r1746) +++ trunk/programmer.h Sun Sep 15 01:36:57 2013 (r1747) @@ -554,10 +554,15 @@ int default_spi_write_aai(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int register_spi_programmer(const struct spi_programmer *programmer); -/* The following enum is needed by ich_descriptor_tool and ich* code. */ +/* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */ enum ich_chipset { CHIPSET_ICH_UNKNOWN, - CHIPSET_ICH7 = 7, + CHIPSET_ICH2 = 2, + CHIPSET_ICH3, + CHIPSET_ICH4, + CHIPSET_ICH5, + CHIPSET_ICH6, + CHIPSET_ICH7, CHIPSET_ICH8, CHIPSET_ICH9, CHIPSET_ICH10,

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[commit] r1746 - trunk
by repository service 15 Sep '13

15 Sep '13

Author: stefanct Date: Sun Sep 15 01:36:53 2013 New Revision: 1746 URL: http://flashrom.org/trac/flashrom/changeset/1746 Log: Introduce enable_flash_ich_fwh_decode(). ICH2 (and C-ICH)/3/4/5 also have FWH_SEL1/2 registers but at different addresses. In preparation for implementing fwh_idsel parsing for older ICH chipsets extract the parameter handling and add variables for the offsets. While FWH_DEC_EN1 is a 16bit register for ICH6, it is two separate 8bit registers on ICH5 and earlier. Implement all accesses with two byte instructions instead, to prepare for extended support. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sat Sep 14 11:02:27 2013 (r1745) +++ trunk/chipset_enable.c Sun Sep 15 01:36:53 2013 (r1746) @@ -325,14 +325,21 @@ return enable_flash_ich(dev, name, 0x4e); } -static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) +static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name) { uint32_t fwh_conf; + uint8_t fwh_sel1, fwh_sel2, fwh_dec_en_lo, fwh_dec_en_hi; int i, tmp; char *idsel = NULL; int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; int contiguous = 1; + /* Register map from ICH6 onwards. */ + fwh_sel1 = 0xd0; + fwh_sel2 = 0xd4; + fwh_dec_en_lo = 0xd8; + fwh_dec_en_hi = 0xd9; + idsel = extract_programmer_param("fwh_idsel"); if (idsel && strlen(idsel)) { uint64_t fwh_idsel_old, fwh_idsel; @@ -349,14 +356,14 @@ "unused bits set.\n"); goto idsel_garbage_out; } - fwh_idsel_old = pci_read_long(dev, 0xd0); + fwh_idsel_old = pci_read_long(dev, fwh_sel1); fwh_idsel_old <<= 16; - fwh_idsel_old |= pci_read_word(dev, 0xd4); + fwh_idsel_old |= pci_read_word(dev, fwh_sel2); msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to " "0x%012" PRIx64 " for top 16 MB.", fwh_idsel_old, fwh_idsel); - rpci_write_long(dev, 0xd0, (fwh_idsel >> 16) & 0xffffffff); - rpci_write_word(dev, 0xd4, fwh_idsel & 0xffff); + rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); + rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); /* FIXME: Decode settings are not changed. */ } else if (idsel) { msg_perr("Error: fwh_idsel= specified, but no value given.\n"); @@ -372,7 +379,7 @@ * have to be adjusted. */ /* FWH_SEL1 */ - fwh_conf = pci_read_long(dev, 0xd0); + fwh_conf = pci_read_long(dev, fwh_sel1); for (i = 7; i >= 0; i--) { tmp = (fwh_conf >> (i * 4)) & 0xf; msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", @@ -386,7 +393,7 @@ } } /* FWH_SEL2 */ - fwh_conf = pci_read_word(dev, 0xd4); + fwh_conf = pci_read_word(dev, fwh_sel2); for (i = 3; i >= 0; i--) { tmp = (fwh_conf >> (i * 4)) & 0xf; msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", @@ -401,7 +408,9 @@ } contiguous = 1; /* FWH_DEC_EN1 */ - fwh_conf = pci_read_word(dev, 0xd8); + fwh_conf = pci_read_byte(dev, fwh_dec_en_hi); + fwh_conf <<= 8; + fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo); for (i = 7; i >= 0; i--) { tmp = (fwh_conf >> (i + 0x8)) & 0x1; msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", @@ -429,6 +438,17 @@ max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); + return 0; +} + +static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) +{ + int err; + + /* Configure FWH IDSEL decoder maps. */ + if ((err = enable_flash_ich_fwh_decode(dev, name)) != 0) + return err; + /* If we're called by enable_flash_ich_dc_spi, it will override * internal_buses_supported anyway. */

1 0

[PATCH] CONFIG_DEFAULT setting
by Carl-Daniel Hailfinger 14 Sep '13

14 Sep '13

Allow easy disabling of all programmers except selected ones by setting CONFIG_DEFAULT=no. Setting CONFIG_DEFAULT=yes has no effect. Usage example: # make CONFIG_DUMMY=yes CONFIG_NIC3COM=yes CONFIG_DEFAULT=no This will disable all programmers except dummy and nic3com. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-Makefile_config_default/Makefile =================================================================== --- flashrom-Makefile_config_default/Makefile (Revision 1623) +++ flashrom-Makefile_config_default/Makefile (Arbeitskopie) @@ -52,6 +52,10 @@ # Compilation will fail for unspecified values. CONFIG_DEFAULT_PROGRAMMER ?= PROGRAMMER_INVALID +# This parameter picks the default setting for CONFIG_ variables of programmers not specified explicitly +# on the command line. +CONFIG_DEFAULT ?= yes + # If your compiler spits out excessive warnings, run make WARNERROR=no # You shouldn't have to change this flag. WARNERROR ?= yes @@ -322,65 +326,65 @@ SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' # Always enable internal/onboard support for now. -CONFIG_INTERNAL ?= yes +CONFIG_INTERNAL ?= $(CONFIG_DEFAULT) # Always enable serprog for now. Needs to be disabled on Windows. -CONFIG_SERPROG ?= yes +CONFIG_SERPROG ?= $(CONFIG_DEFAULT) # RayeR SPIPGM hardware support -CONFIG_RAYER_SPI ?= yes +CONFIG_RAYER_SPI ?= $(CONFIG_DEFAULT) # PonyProg2000 SPI hardware support -CONFIG_PONY_SPI ?= yes +CONFIG_PONY_SPI ?= $(CONFIG_DEFAULT) # Always enable 3Com NICs for now. -CONFIG_NIC3COM ?= yes +CONFIG_NIC3COM ?= $(CONFIG_DEFAULT) # Enable NVIDIA graphics cards. Note: write and erase do not work properly. -CONFIG_GFXNVIDIA ?= yes +CONFIG_GFXNVIDIA ?= $(CONFIG_DEFAULT) # Always enable SiI SATA controllers for now. -CONFIG_SATASII ?= yes +CONFIG_SATASII ?= $(CONFIG_DEFAULT) # Highpoint (HPT) ATA/RAID controller support. # IMPORTANT: This code is not yet working! CONFIG_ATAHPT ?= no # Always enable FT2232 SPI dongles for now. -CONFIG_FT2232_SPI ?= yes +CONFIG_FT2232_SPI ?= $(CONFIG_DEFAULT) # Always enable dummy tracing for now. -CONFIG_DUMMY ?= yes +CONFIG_DUMMY ?= $(CONFIG_DEFAULT) # Always enable Dr. Kaiser for now. -CONFIG_DRKAISER ?= yes +CONFIG_DRKAISER ?= $(CONFIG_DEFAULT) # Always enable Realtek NICs for now. -CONFIG_NICREALTEK ?= yes +CONFIG_NICREALTEK ?= $(CONFIG_DEFAULT) # Disable National Semiconductor NICs until support is complete and tested. CONFIG_NICNATSEMI ?= no # Always enable Intel NICs for now. -CONFIG_NICINTEL ?= yes +CONFIG_NICINTEL ?= $(CONFIG_DEFAULT) # Always enable SPI on Intel NICs for now. -CONFIG_NICINTEL_SPI ?= yes +CONFIG_NICINTEL_SPI ?= $(CONFIG_DEFAULT) # Always enable SPI on OGP cards for now. -CONFIG_OGP_SPI ?= yes +CONFIG_OGP_SPI ?= $(CONFIG_DEFAULT) # Always enable Bus Pirate SPI for now. -CONFIG_BUSPIRATE_SPI ?= yes +CONFIG_BUSPIRATE_SPI ?= $(CONFIG_DEFAULT) # Disable Dediprog SF100 until support is complete and tested. CONFIG_DEDIPROG ?= no # Always enable Marvell SATA controllers for now. -CONFIG_SATAMV ?= yes +CONFIG_SATAMV ?= $(CONFIG_DEFAULT) # Enable Linux spidev interface by default. We disable it on non-Linux targets. -CONFIG_LINUX_SPI ?= yes +CONFIG_LINUX_SPI ?= $(CONFIG_DEFAULT) # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no -- http://www.hailfinger.org/

2 2

[PATCH] Remove exit call from physmap_common
by Niklas Söderlund 14 Sep '13

14 Sep '13

Only call path where exit is reached is from physmap(). Callers of physmap() that where not prepared to handle the ERROR_PTR return value have been handled. Signed-off-by: Niklas Söderlund <niso(a)kth.se> --- chipset_enable.c | 6 ++++++ drkaiser.c | 2 ++ gfxnvidia.c | 2 ++ ichspi.c | 2 ++ it85spi.c | 2 ++ mcp6x_spi.c | 2 ++ nicintel_spi.c | 2 ++ ogp_spi.c | 2 ++ physmap.c | 12 +++--------- satasii.c | 2 ++ sb600spi.c | 2 ++ 11 files changed, 27 insertions(+), 9 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index fa79511..b1738ea 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -494,6 +494,8 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); + if (rcrb == ERROR_PTR) + return ERROR_FATAL; /* Test Boot BIOS Strap Status */ bnt = mmio_readl(rcrb + 0x3410); @@ -565,6 +567,8 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); + if (rcrb == ERROR_PTR) + return ERROR_FATAL; gcs = mmio_readl(rcrb + 0x3410); msg_pdbg("GCS = 0x%x: ", gcs); @@ -1235,6 +1239,8 @@ static int get_flashbase_sc520(struct pci_dev *dev, const char *name) /* 1. Map MMCR */ mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize()); + if (mmcr == ERROR_PTR) + return -1; /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for * BOOTCS region (PARx[31:29] = 100b)e diff --git a/drkaiser.c b/drkaiser.c index 83b8b3d..71981e8 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -82,6 +82,8 @@ int drkaiser_init(void) /* Map 128kB flash memory window. */ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", addr, DRKAISER_MEMMAP_SIZE); + if (drkaiser_bar == ERROR_PTR) + return 1; if (register_shutdown(drkaiser_shutdown, NULL)) return 1; diff --git a/gfxnvidia.c b/gfxnvidia.c index 9232677..9600675 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -102,6 +102,8 @@ int gfxnvidia_init(void) msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); + if (nvidia_bar == ERROR_PTR) + return 1; /* Must be done before rpci calls. */ if (register_shutdown(gfxnvidia_shutdown, NULL)) diff --git a/ichspi.c b/ichspi.c index bbe2b06..f6b77ad 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1836,6 +1836,8 @@ int via_init_spi(struct pci_dev *dev, uint32_t mmio_base) int i; ich_spibar = physmap("VIA SPI MMIO registers", mmio_base, 0x70); + if (ich_spibar == ERROR_PTR) + return ERROR_FATAL; /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */ /* Not sure if it speaks all these bus protocols. */ diff --git a/it85spi.c b/it85spi.c index 0b074eb..e15a287 100644 --- a/it85spi.c +++ b/it85spi.c @@ -262,6 +262,8 @@ static int it85xx_spi_common_init(struct superio s) * Major TODO here, and it will be a lot of work. */ base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); + if (base == ERROR_PTR) + return 1; msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ diff --git a/mcp6x_spi.c b/mcp6x_spi.c index ac40557..438e661 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -149,6 +149,8 @@ int mcp6x_spi_init(int want_spi) } /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */ mcp6x_spibar = physmap("NVIDIA MCP6x SPI", mcp6x_spibaraddr, 0x544); + if (mcp6x_spibar == ERROR_PTR) + return 1; #if 0 /* FIXME: Run the physunmap in a shutdown function. */ diff --git a/nicintel_spi.c b/nicintel_spi.c index 72b470b..6dc40f5 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -178,6 +178,8 @@ int nicintel_spi_init(void) nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); + if (nicintel_spibar == ERROR_PTR) + return 1; /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, * but other bits with side effects as well. Those other bits must be diff --git a/ogp_spi.c b/ogp_spi.c index 9b596bf..b3963c2 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -138,6 +138,8 @@ int ogp_spi_init(void) return 1; ogp_spibar = physmap("OGP registers", io_base_addr, 4096); + if (ogp_spibar == ERROR_PTR) + return 1; if (register_shutdown(ogp_spi_shutdown, NULL)) return 1; diff --git a/physmap.c b/physmap.c index adce315..35dcfb8 100644 --- a/physmap.c +++ b/physmap.c @@ -211,13 +211,11 @@ void physunmap(void *virt_addr, size_t len) } #endif -#define PHYSMAP_NOFAIL 0 -#define PHYSMAP_MAYFAIL 1 #define PHYSMAP_RW 0 #define PHYSMAP_RO 1 static void *physmap_common(const char *descr, unsigned long phys_addr, - size_t len, int mayfail, int readonly) + size_t len, int readonly) { void *virt_addr; @@ -261,8 +259,6 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, "and reboot, or reboot into\n" "single user mode.\n"); #endif - if (!mayfail) - exit(3); } return virt_addr; @@ -270,14 +266,12 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, void *physmap(const char *descr, unsigned long phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, - PHYSMAP_RW); + return physmap_common(descr, phys_addr, len, PHYSMAP_RW); } void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, - PHYSMAP_RO); + return physmap_common(descr, phys_addr, len, PHYSMAP_RO); } #if defined(__i386__) || defined(__x86_64__) diff --git a/satasii.c b/satasii.c index 838fff4..9f9bb7f 100644 --- a/satasii.c +++ b/satasii.c @@ -97,6 +97,8 @@ int satasii_init(void) } sii_bar = physmap("SATA SiI registers", addr, SATASII_MEMMAP_SIZE) + reg_offset; + if (sii_bar == ERROR_PTR) + return 1; /* Check if ROM cycle are OK. */ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) diff --git a/sb600spi.c b/sb600spi.c index fe60aa9..a4ca20b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -226,6 +226,8 @@ int sb600_probe_spi(struct pci_dev *dev) /* Physical memory has to be mapped at page (4k) boundaries. */ sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + if (sb600_spibar == ERROR_PTR) + return ERROR_FATAL; /* The low bits of the SPI base address are used as offset into * the mapped page. */ -- 1.7.12.4

2 1

[commit] r1745 - trunk
by repository service 14 Sep '13

14 Sep '13

Author: stefanct Date: Sat Sep 14 11:02:27 2013 New Revision: 1745 URL: http://flashrom.org/trac/flashrom/changeset/1745 Log: Remove exit call and mayfail parameter from physmap_common(). The only call path where exit was reached was from physmap functions. Callers of physmap() et al. which were not prepared to handle ERROR_PTR return values have been adjusted. physmap_try_ro() has been renamed to physmap_ro() and physmap_common() slightly refactored due to the now removed *FAIL parameters. Signed-off-by: Niklas Söderlund <niso(a)kth.se> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/cbtable.c trunk/chipset_enable.c trunk/dmi.c trunk/nicintel_spi.c trunk/physmap.c trunk/programmer.h trunk/sb600spi.c Modified: trunk/cbtable.c ============================================================================== --- trunk/cbtable.c Fri Sep 13 21:19:25 2013 (r1744) +++ trunk/cbtable.c Sat Sep 14 11:02:27 2013 (r1745) @@ -261,7 +261,7 @@ #else start = 0x0; #endif - table_area = physmap_try_ro("low megabyte", start, BYTES_TO_MAP - start); + table_area = physmap_ro("low megabyte", start, BYTES_TO_MAP - start); if (ERROR_PTR == table_area) { msg_perr("Failed getting access to coreboot low tables.\n"); return -1; @@ -277,7 +277,7 @@ start = forward->forward; start &= ~(getpagesize() - 1); physunmap(table_area, BYTES_TO_MAP); - table_area = physmap_try_ro("high tables", start, BYTES_TO_MAP); + table_area = physmap_ro("high tables", start, BYTES_TO_MAP); if (ERROR_PTR == table_area) { msg_perr("Failed getting access to coreboot high tables.\n"); return -1; Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Sep 13 21:19:25 2013 (r1744) +++ trunk/chipset_enable.c Sat Sep 14 11:02:27 2013 (r1745) @@ -482,7 +482,7 @@ /* Map RCBA to virtual memory */ rcrb = rphysmap("ICH RCRB", tmp, 0x4000); if (rcrb == ERROR_PTR) - return 1; + return ERROR_FATAL; /* Test Boot BIOS Strap Status */ bnt = mmio_readl(rcrb + 0x3410); @@ -566,7 +566,7 @@ /* Map RCBA to virtual memory */ rcrb = rphysmap("ICH RCRB", tmp, 0x4000); if (rcrb == ERROR_PTR) - return 1; + return ERROR_FATAL; gcs = mmio_readl(rcrb + 0x3410); msg_pdbg("GCS = 0x%x: ", gcs); @@ -1289,6 +1289,8 @@ /* 1. Map MMCR */ mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize()); + if (mmcr == ERROR_PTR) + return ERROR_FATAL; /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for * BOOTCS region (PARx[31:29] = 100b)e Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Fri Sep 13 21:19:25 2013 (r1744) +++ trunk/dmi.c Sat Sep 14 11:02:27 2013 (r1745) @@ -250,8 +250,8 @@ * - EFI's configuration table contains a pointer to the SMBIOS table. On linux it can be obtained from * sysfs. EFI's SMBIOS GUID is: {0xeb9d2d31,0x2d88,0x11d3,0x9a,0x16,0x0,0x90,0x27,0x3f,0xc1,0x4d} * - Scanning physical memory address range 0x000F0000h to 0x000FFFFF for the anchor-string(s). */ - dmi_mem = physmap_try_ro("DMI", 0xF0000, 0x10000); - if (dmi_mem == NULL) + dmi_mem = physmap_ro("DMI", 0xF0000, 0x10000); + if (dmi_mem == ERROR_PTR) return ret; for (fp = 0; fp <= 0xFFF0; fp += 16) { Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Fri Sep 13 21:19:25 2013 (r1744) +++ trunk/nicintel_spi.c Sat Sep 14 11:02:27 2013 (r1745) @@ -177,6 +177,9 @@ return 1; nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); + if (nicintel_spibar == ERROR_PTR) + return 1; + /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, * but other bits with side effects as well. Those other bits must be Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Fri Sep 13 21:19:25 2013 (r1744) +++ trunk/physmap.c Sat Sep 14 11:02:27 2013 (r1745) @@ -203,8 +203,6 @@ } #endif -#define PHYSM_NOFAIL 0 -#define PHYSM_MAYFAIL 1 #define PHYSM_RW 0 #define PHYSM_RO 1 #define PHYSM_NOCLEANUP 0 @@ -249,8 +247,8 @@ return 0; } -static void *physmap_common(const char *descr, uintptr_t phys_addr, size_t len, bool mayfail, - bool readonly, bool autocleanup, bool round) +static void *physmap_common(const char *descr, uintptr_t phys_addr, size_t len, bool readonly, bool autocleanup, + bool round) { void *virt_addr; uintptr_t offset = 0; @@ -287,53 +285,47 @@ "and reboot, or reboot into\n" "single user mode.\n"); #endif - if (mayfail) - return ERROR_PTR; - else - exit(3); + return ERROR_PTR; } if (autocleanup) { struct undo_physmap_data *d = malloc(sizeof(struct undo_physmap_data)); if (d == NULL) { msg_perr("%s: Out of memory!\n", __func__); - goto unmap_out; + physunmap(virt_addr, len); + return ERROR_PTR; } d->virt_addr = virt_addr; d->len = len; if (register_shutdown(undo_physmap, d) != 0) { msg_perr("%s: Could not register shutdown function!\n", __func__); - goto unmap_out; + physunmap(virt_addr, len); + return ERROR_PTR; } } return virt_addr + offset; -unmap_out: - physunmap(virt_addr, len); - if (!mayfail) - exit(3); - return ERROR_PTR; } void *physmap(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSM_NOFAIL, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_EXACT); + return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_EXACT); } void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSM_NOFAIL, PHYSM_RW, PHYSM_CLEANUP, PHYSM_ROUND); + return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_CLEANUP, PHYSM_ROUND); } void *physmap_round(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSM_NOFAIL, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_ROUND); + return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_ROUND); } -void *physmap_try_ro(const char *descr, uintptr_t phys_addr, size_t len) +void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSM_MAYFAIL, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_EXACT); + return physmap_common(descr, phys_addr, len, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_EXACT); } /* MSR abstraction implementations for Linux, OpenBSD, FreeBSD/Dragonfly, OSX, libpayload Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Fri Sep 13 21:19:25 2013 (r1744) +++ trunk/programmer.h Sat Sep 14 11:02:27 2013 (r1745) @@ -278,7 +278,7 @@ void *physmap(const char *descr, uintptr_t phys_addr, size_t len); void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len); void *physmap_round(const char *descr, uintptr_t phys_addr, size_t len); -void *physmap_try_ro(const char *descr, uintptr_t phys_addr, size_t len); +void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); #if CONFIG_INTERNAL == 1 int setup_cpu_msr(int cpu); Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Fri Sep 13 21:19:25 2013 (r1744) +++ trunk/sb600spi.c Sat Sep 14 11:02:27 2013 (r1745) @@ -353,7 +353,7 @@ /* Physical memory has to be mapped at page (4k) boundaries. */ sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); if (sb600_spibar == ERROR_PTR) - return 1; + return ERROR_FATAL; /* The low bits of the SPI base address are used as offset into * the mapped page.

1 0

[PATCH] Remove exit call from sys_physmap_*
by Niklas Söderlund 13 Sep '13

13 Sep '13

All callers are prepared to handle error if ERROR_PTR is returned. Signed-off-by: Niklas Söderlund <niso(a)kth.se> --- physmap.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/physmap.c b/physmap.c index 5aa9874..adce315 100644 --- a/physmap.c +++ b/physmap.c @@ -173,12 +173,11 @@ static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) /* Open the memory device UNCACHED. Important for MMIO. */ if (-1 == (fd_mem = open(MEM_DEV, O_RDWR | O_SYNC))) { perror("Critical error: open(" MEM_DEV ")"); - exit(2); + return ERROR_PTR; } } - virt_addr = mmap(NULL, len, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t)phys_addr); + virt_addr = mmap(NULL, len, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t)phys_addr); return MAP_FAILED == virt_addr ? ERROR_PTR : virt_addr; } @@ -192,14 +191,12 @@ static void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) if (-1 == fd_mem_cached) { /* Open the memory device CACHED. */ if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) { - msg_perr("Critical error: open(" MEM_DEV "): %s", - strerror(errno)); - exit(2); + msg_perr("Critical error: open(" MEM_DEV "): %s", strerror(errno)); + return ERROR_PTR; } } - virt_addr = mmap(NULL, len, PROT_READ, MAP_SHARED, - fd_mem_cached, (off_t)phys_addr); + virt_addr = mmap(NULL, len, PROT_READ, MAP_SHARED, fd_mem_cached, (off_t)phys_addr); return MAP_FAILED == virt_addr ? ERROR_PTR : virt_addr; } @@ -209,7 +206,7 @@ void physunmap(void *virt_addr, size_t len) msg_pspew("Not unmapping zero size at %p\n", virt_addr); return; } - + munmap(virt_addr, len); } #endif -- 1.7.12.3

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