flashrom

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9161 discussions

flash failed on Chromebook C7
by Ralph Embedded 01 May '15

01 May '15

Howdy, I just tried to flash a Chromebook C7. I was using the script at: https://johnlewis.ie/getnflash_johnlewis_rom.sh I got 4 errors Reading current flash chip contents... spi_block_erase_52 failed during command execution at address 0x0 Reading current flash chip contents... spi_block_erase_d8 failed during command execution at address 0x0 Reading current flash chip contents... spi_chip_erase_60 failed during command execution Reading current flash chip contents... spi_chip_erase_c7 failed during command execution do not reboot under any circumstance, it also says. What should I do? I am currently in IRC as Ralph Thank you

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Gigabyte Ga-k8ns
by nicolae788 . 30 Apr '15

30 Apr '15

Hello, i want to inform you that Gigabyte Ga-k8ns was successfully flashed with the "boardenable=force". This is the 754 socket for AMD processors. The board has a non-existent jumper location were it's possible to solder a bridge to disable protection, but it works with the above option. I noticed that it identified this board as a 939 Pro version but it's not. However everything went smooth. Alex

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Re: [flashrom] Advice on problem with libusb/buffer size
by Stefan Tauner 29 Apr '15

29 Apr '15

On Wed, 29 Apr 2015 21:20:48 +0100 Steven Honeyman <stevenhoneyman(a)gmail.com> wrote: > I'm adding support (OK, *trying* to add support...) for a USB > programmer in flashrom. I've had it working without error, but at an > incredibly slow rate due to a tiny 128 byte chunk size, which is all I > can get it to work with. > > This (USB driver development) is new to me so I expected to hit a few > problems and learn along the way... but I'm at a point where I don't > know where the problem is and could use a push in the right direction. > > A linux+libusb1.0 program already exists, which is using async bulk > transfer and 8192 byte chunks. The closed source Windows driver reads > in the same way but 4096 byte chunks. > As far as I know, the legacy libusb 0.1 does not support async so I > can't just copy/paste code here. I don't think you should implement it for libusb 0.1 at all... we will switch to 1.0 sooner or later anyway and it is certainly not worth it to waste time on 0.1 if there is code for 1.0 already. See also Kyösti's attempt to port dediprog to libusb 1.0: http://patchwork.coreboot.org/patch/3905/ I don't have time to look into your current problem in detail. #libusb on freenode or their mailing list might be more helpful if you still want to continue. Showing some code might also help ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Advice on problem with libusb/buffer size
by Steven Honeyman 29 Apr '15

29 Apr '15

I'm adding support (OK, *trying* to add support...) for a USB programmer in flashrom. I've had it working without error, but at an incredibly slow rate due to a tiny 128 byte chunk size, which is all I can get it to work with. This (USB driver development) is new to me so I expected to hit a few problems and learn along the way... but I'm at a point where I don't know where the problem is and could use a push in the right direction. A linux+libusb1.0 program already exists, which is using async bulk transfer and 8192 byte chunks. The closed source Windows driver reads in the same way but 4096 byte chunks. As far as I know, the legacy libusb 0.1 does not support async so I can't just copy/paste code here. The error occurs at 160 bytes, which happens to be the same number that is returned as "URB length" in a "-ENOENT" packet immediately following the read request - probably not a coincidence. Here's a small example of what's going on in a printf-heavy version (the "ff ff ff ff" is expected at the start of each chunk): begin loop len=4178502, max_payload=7901 usb write (out) (8192 bytes) [read #00] (32 bytes): ff ff ff ff c0 44 46 c2 ... [read #01] (32 bytes): 57 c0 c0 9d 8f 00 f0 ... [read #02] (32 bytes): 00 04 bd 17 0f 41 00 ... [read #03] (32 bytes): 9f ff ef 2f ff 00 04 7f ... [read #04] (32 bytes): ERROR ret=-110 end loop begin loop len=4170601, max_payload=7901 usb write (out) (8192 bytes) [read #00] (32 bytes): ff ff ff ff 00 00 00 00 ... [read #01] (32 bytes): 00 00 00 00 00 ... [read #02] (32 bytes): c3 00 00 80 00 00 00 ... [read #03] (32 bytes): 20 c0 80 00 1a 40 ... [read #04] (32 bytes): ERROR ret=-110 end loop My current thoughts are: - I'm doing this completely wrong for legacy libusb - I haven't found the secret "enable large read buffers" command to send the device - Something in flashrom is changing how this should work - Something really simple like a value out by 1, although that wouldn't explain why it works up until the 5th read of each block I'm not after being spoonfed - but if anyone can give a hint as to where I should be looking or what I may have done wrong that'd help! Thanks, Steven

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SST49LF004B: On motherboard Intel Desktop board D915GLVG/D915PLDT 03 not recognise flash chip, not read
by Александр Трубицын 29 Apr '15

29 Apr '15

-- with best regards, Alexander V.Trubitsyn

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Not able to update firmware with flashrom
by Caleb Bartholomew 28 Apr '15

28 Apr '15

Can’t update BIOS with flashrom. BIOS chip is W25Q64FV - Source: Visual confirmation Thanks, Caleb Bartholomew Manager, Software Engineering caleb.bartholomew(a)xi3.com <mailto:caleb.bartholomew@xi3.com> Xi3 Corporation 299 S. Main, Suite 1300 Salt Lake City, UT 84111 t: (801) 478-3848 f: (801) 478-3765 web: www.xi3.com <http://www.xi3.com/>

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Flashing libreboot on x200 using a Shikra
by matcor＠riseup.net 28 Apr '15

28 Apr '15

Hi, I'm trying to flash libreboot to my x200 using a Shikra. When it gets to the "Erasing and writing flash chip" part, it seems to hang, but top shows that flashrom is still using a lot of the CPU. I left it for over 3 hours and it doesn't get any further than my logfile below. Would anyone be able to shed some light as to what might be going on here? Thanks. command: flashrom -p ft2232_spi:type=232H -c "MX25L6405D" -w x200_8mb_usqwerty_vesafb.rom -V 2>&1 | tee logfile output: flashrom v0.9.8-r1889 on Linux 3.17.4-301.fc21.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.3.0, GCC 4.9.2 20150212 (Red Hat 4.9.2-6), little endian Command line (7 args): flashrom -p ft2232_spi:type=232H -c MX25L6405D -w x200_8mb_usqwerty_vesafb.rom -V Calibrating delay loop... OS timer resolution is 1 usecs, 1491M loops per second, 10 myus = 10 us, 100 myus = 119 us, 1000 myus = 1019 us, 10000 myus = 10100 us, 4 myus = 4 us, OK. Initializing ft2232_spi programmer Using device type FTDI FT232H channel A. Disable divide-by-5 front stage Set clock divisor MPSSE clock: 60.000000 MHz, divisor: 2, SPI clock: 30.000000 MHz No loopback of TDI/DO TDO/DI Set data bits The following protocols are supported: SPI. Probing for Macronix MX25L6405D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Found Macronix flash chip "MX25L6405D" (8192 kB, SPI) on ft2232_spi. Chip status register is 0xff. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is set Chip status register: Bit 6 is set Chip status register: Block Protect 3 (BP3) is set Chip status register: Block Protect 2 (BP2) is set Chip status register: Block Protect 1 (BP1) is set Chip status register: Block Protect 0 (BP0) is set Chip status register: Write Enable Latch (WEL) is set Chip status register: Write In Progress (WIP/BUSY) is set This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Some block protection in effect, disabling... Need to disable the register lock first... Error: WIP bit after WRSR never cleared spi_write_status_register failed. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:E

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Re: [flashrom] Help
by Stefan Tauner 28 Apr '15

28 Apr '15

On Sun, 26 Apr 2015 21:28:29 -0700 Khoirul Anam <uoen.ka(a)gmail.com> wrote: > I have die computer. My view is there problem at mobo (jetway > MI5-G41SGMD3-LF). How can I flashrom on it while the computer doesnt reach > bios mode ?. Please help me Hi, you need an external programmer (or another mainboard) to write the flash chip if the respective mainboard does no longer boot (nor provide any other means of recovery). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Help
by Khoirul Anam 27 Apr '15

27 Apr '15

I have die computer. My view is there problem at mobo (jetway MI5-G41SGMD3-LF). How can I flashrom on it while the computer doesnt reach bios mode ?. Please help me

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W25X40: Asrock G31M-GS rev. G/A 2.04 successfully reflash from BIOS P1.80 05/20/2011 to BIOS P1.90 05/16/2012
by Александр Трубицын 21 Apr '15

21 Apr '15

Hi! I successfully reflash Asrock G31M-GS rev G/A2.04 motherboard from BIOS P1.80 05/20/2011 to BIOS P1.90 05/16/2012 with your tool. Thank you! -- With best regards, Alexander Trubitsyn

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