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[commit] r1845 - in trunk: . util/ich_descriptors_tool
by repository service 20 Aug '14

20 Aug '14

Author: stefanct Date: Wed Aug 20 17:39:38 2014 New Revision: 1845 URL: http://flashrom.org/trac/flashrom/changeset/1845 Log: Add support for Intel Wildcat Point PCH. The Wildcat Point PCH can be paired with Broadwell or Haswell. This patch was essentially backported from ChromiumOS commit 9bd2af8. Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipset_enable.c trunk/ich_descriptors.c trunk/ich_descriptors.h trunk/programmer.h trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Aug 20 17:39:32 2014 (r1844) +++ trunk/chipset_enable.c Wed Aug 20 17:39:38 2014 (r1845) @@ -594,7 +594,7 @@ static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" }; static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; - static const char *const straps_names_pch8_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; + static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; @@ -623,8 +623,9 @@ straps_names = straps_names_pch567; break; case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_9_SERIES_WILDCAT_POINT: case CHIPSET_BAYTRAIL: - straps_names = straps_names_pch8_baytrail; + straps_names = straps_names_pch89_baytrail; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: straps_names = straps_names_pch8_lp; @@ -776,6 +777,12 @@ return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); } +/* Wildcat Point */ +static int enable_flash_pch9(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); +} + /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. * @@ -1759,6 +1766,14 @@ {0x8086, 0x8d5d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, {0x8086, 0x8d5e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, {0x8086, 0x8d5f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9}, + {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9}, + {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9}, + {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9}, + {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9}, + {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9}, + {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9}, + {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9}, #endif {0}, }; Modified: trunk/ich_descriptors.c ============================================================================== --- trunk/ich_descriptors.c Wed Aug 20 17:39:32 2014 (r1844) +++ trunk/ich_descriptors.c Wed Aug 20 17:39:38 2014 (r1845) @@ -141,7 +141,8 @@ case CHIPSET_8_SERIES_LYNX_POINT: case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: - case CHIPSET_8_SERIES_WELLSBURG: { + case CHIPSET_8_SERIES_WELLSBURG: + case CHIPSET_9_SERIES_WILDCAT_POINT: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.new.comp1_density; @@ -184,6 +185,7 @@ case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: + case CHIPSET_9_SERIES_WILDCAT_POINT: return freq_str[value]; case CHIPSET_ICH_UNKNOWN: default: @@ -825,6 +827,7 @@ case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: + case CHIPSET_9_SERIES_WILDCAT_POINT: if (idx == 0) { size_enc = desc->component.new.comp1_density; } else { Modified: trunk/ich_descriptors.h ============================================================================== --- trunk/ich_descriptors.h Wed Aug 20 17:39:32 2014 (r1844) +++ trunk/ich_descriptors.h Wed Aug 20 17:39:38 2014 (r1845) @@ -117,7 +117,7 @@ * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? */ struct { - uint32_t :17, + uint32_t :17, freq_read :3, fastread :1, freq_fastread :3, Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed Aug 20 17:39:32 2014 (r1844) +++ trunk/programmer.h Wed Aug 20 17:39:38 2014 (r1845) @@ -603,6 +603,7 @@ CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */ CHIPSET_8_SERIES_LYNX_POINT_LP, CHIPSET_8_SERIES_WELLSBURG, + CHIPSET_9_SERIES_WILDCAT_POINT, }; /* ichspi.c */ Modified: trunk/util/ich_descriptors_tool/ich_descriptors_tool.c ============================================================================== --- trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Wed Aug 20 17:39:32 2014 (r1844) +++ trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Wed Aug 20 17:39:38 2014 (r1845) @@ -123,6 +123,7 @@ "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" "\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" +"\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -205,6 +206,9 @@ cs = CHIPSET_8_SERIES_LYNX_POINT; else if ((strcmp(csn, "silvermont") == 0)) cs = CHIPSET_BAYTRAIL; + else if ((strcmp(csn, "9") == 0) || + (strcmp(csn, "wildcat") == 0)) + cs = CHIPSET_9_SERIES_WILDCAT_POINT; } ret = read_ich_descriptors_from_dump(buf, len, &desc);

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[commit] r1844 - in trunk: . util/ich_descriptors_tool
by repository service 20 Aug '14

20 Aug '14

Author: stefanct Date: Wed Aug 20 17:39:32 2014 New Revision: 1844 URL: http://flashrom.org/trac/flashrom/changeset/1844 Log: Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton. The core of this patch to support Bay Trail originally came from the Chromiumos flashrom repo and was modified by Sage to support the Rangeley/Avoton parts as well. Because that was not complicated enough already Stefan Tauner refactored and refined everything. Bay Trail seems to be the first Atom SoC able to support hwseq. No SPI Programming Guide could be obtained so it is handled similarly to Lynx Point which seems to be its nearest relative. Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Tested-by: Marc Jones <marcj303(a)gmail.com> Tested-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Tested-by: Thomas Reardon <thomas_reardon(a)hotmail.com> Tested-by: Wen Wang <wen.wang(a)adiengineering.com> Acked-By: Marc Jones <marcj303(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipset_enable.c trunk/ich_descriptors.c trunk/ichspi.c trunk/programmer.h trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Aug 20 17:39:19 2014 (r1843) +++ trunk/chipset_enable.c Wed Aug 20 17:39:32 2014 (r1844) @@ -260,9 +260,13 @@ return 0; } -/* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom +/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space + * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'. + * + * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */ -static int enable_flash_ich_bios_cntl(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr, + struct pci_dev *dev, uint8_t bios_cntl) { uint8_t old, new, wanted; @@ -273,8 +277,8 @@ case CHIPSET_ICH: case CHIPSET_ICH2345: break; - /* Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to what - * other SPI-capable chipsets have at DCh. + /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to + * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register. * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it * mentions that the prefetching and caching does only happen for direct memory reads. * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the @@ -285,9 +289,13 @@ old = pci_read_byte(dev, bios_cntl + 1); msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); break; + case CHIPSET_BAYTRAIL: case CHIPSET_ICH7: default: /* Future version might behave the same */ - old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3; + if (ich_generation == CHIPSET_BAYTRAIL) + old = (mmio_readl(addr) >> 2) & 0x3; + else + old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3; msg_pdbg("SPI Read Configuration: "); if (old == 3) msg_pdbg("invalid prefetching/caching settings, "); @@ -297,7 +305,11 @@ (old & 0x1) ? "dis" : "en"); } - wanted = old = pci_read_byte(dev, bios_cntl); + if (ich_generation == CHIPSET_BAYTRAIL) + wanted = old = mmio_readl(addr); + else + wanted = old = pci_read_byte(dev, bios_cntl); + /* * Quote from the 6 Series datasheet (Document Number: 324645-004): * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP) @@ -327,8 +339,13 @@ /* Only write the register if it's necessary */ if (wanted != old) { - rpci_write_byte(dev, bios_cntl, wanted); - new = pci_read_byte(dev, bios_cntl); + if (ich_generation == CHIPSET_BAYTRAIL) { + rmmio_writel(wanted, addr); + new = mmio_readl(addr); + } else { + rpci_write_byte(dev, bios_cntl, wanted); + new = pci_read_byte(dev, bios_cntl); + } } else new = old; @@ -349,10 +366,22 @@ return 0; } +static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation, + uint8_t bios_cntl) +{ + return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl); +} + +static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr) +{ + return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0); +} + static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation) { uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */ bool implemented = 0; + void *ilb = NULL; /* Only for Baytrail */ switch (ich_generation) { case CHIPSET_ICH: /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB @@ -373,6 +402,19 @@ case CHIPSET_CENTERTON: /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */ break; + case CHIPSET_BAYTRAIL: { + uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */ + if (ilb_base == 0) { + msg_perr("Error: Invalid ILB_BASE_ADDRESS\n"); + return ERROR_FATAL; + } + ilb = rphysmap("BYT IBASE", ilb_base, 512); + fwh_sel1 = 0x18; + fwh_dec_en_lo = 0xd8; + fwh_dec_en_hi = 0xd9; + implemented = 1; + break; + } case CHIPSET_ICH6: case CHIPSET_ICH7: default: /* Future version might behave the same */ @@ -397,17 +439,27 @@ msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n"); goto idsel_garbage_out; } - if (fwh_idsel & 0xffff000000000000ULL) { + uint64_t fwh_mask = 0xffffffff; + if (fwh_sel2 > 0) + fwh_mask |= (0xffffULL << 32); + if (fwh_idsel & ~fwh_mask) { msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n"); goto idsel_garbage_out; } - uint64_t fwh_idsel_old = pci_read_long(dev, fwh_sel1); - fwh_idsel_old <<= 16; - fwh_idsel_old |= pci_read_word(dev, fwh_sel2); + uint64_t fwh_idsel_old; + if (ich_generation == CHIPSET_BAYTRAIL) { + fwh_idsel_old = mmio_readl(ilb + fwh_sel1); + rmmio_writel(fwh_idsel, ilb + fwh_sel1); + } else { + fwh_idsel_old = pci_read_long(dev, fwh_sel1) << 16; + rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); + if (fwh_sel2 > 0) { + fwh_idsel_old |= pci_read_word(dev, fwh_sel2); + rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); + } + } msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n", fwh_idsel_old, fwh_idsel); - rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); - rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); /* FIXME: Decode settings are not changed. */ } else if (idsel) { msg_perr("Error: fwh_idsel= specified, but no value given.\n"); @@ -429,7 +481,12 @@ */ int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; bool contiguous = 1; - uint32_t fwh_conf = pci_read_long(dev, fwh_sel1); + uint32_t fwh_conf; + if (ich_generation == CHIPSET_BAYTRAIL) + fwh_conf = mmio_readl(ilb + fwh_sel1); + else + fwh_conf = pci_read_long(dev, fwh_sel1); + int i; /* FWH_SEL1 */ for (i = 7; i >= 0; i--) { @@ -444,18 +501,20 @@ contiguous = 0; } } - /* FWH_SEL2 */ - fwh_conf = pci_read_word(dev, fwh_sel2); - for (i = 3; i >= 0; i--) { - int tmp = (fwh_conf >> (i * 4)) & 0xf; - msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", - (0xff4 + i) * 0x100000, - (0xff0 + i) * 0x100000, - tmp); - if ((tmp == 0) && contiguous) { - max_decode_fwh_idsel = (8 - i) * 0x100000; - } else { - contiguous = 0; + if (fwh_sel2 > 0) { + /* FWH_SEL2 */ + fwh_conf = pci_read_word(dev, fwh_sel2); + for (i = 3; i >= 0; i--) { + int tmp = (fwh_conf >> (i * 4)) & 0xf; + msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", + (0xff4 + i) * 0x100000, + (0xff0 + i) * 0x100000, + tmp); + if ((tmp == 0) && contiguous) { + max_decode_fwh_idsel = (8 - i) * 0x100000; + } else { + contiguous = 0; + } } } contiguous = 1; @@ -502,7 +561,7 @@ return err; internal_buses_supported = BUS_FWH; - return enable_flash_ich_bios_cntl(dev, ich_generation, bios_cntl); + return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl); } static int enable_flash_ich0(struct pci_dev *dev, const char *name) @@ -525,14 +584,17 @@ return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8); } -static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +static void enable_flash_ich_handle_gcs(struct pci_dev *dev, enum ich_chipset ich_generation, uint32_t gcs, bool top_swap) { + msg_pdbg("GCS = 0x%x: ", gcs); + msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); + static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" }; static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" }; static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; - static const char *const straps_names_pch8[] = { "LPC", "reserved", "reserved", "SPI" }; + static const char *const straps_names_pch8_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; @@ -561,7 +623,8 @@ straps_names = straps_names_pch567; break; case CHIPSET_8_SERIES_LYNX_POINT: - straps_names = straps_names_pch8; + case CHIPSET_BAYTRAIL: + straps_names = straps_names_pch8_baytrail; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: straps_names = straps_names_pch8_lp; @@ -576,40 +639,40 @@ break; } - /* Get physical address of Root Complex Register Block */ - uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; - msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra); - - /* Map RCBA to virtual memory */ - void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); - if (rcrb == ERROR_PTR) - return ERROR_FATAL; - - uint32_t gcs = mmio_readl(rcrb + 0x3410); - msg_pdbg("GCS = 0x%x: ", gcs); - msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); - uint8_t bbs; switch (ich_generation) { case CHIPSET_TUNNEL_CREEK: bbs = (gcs >> 1) & 0x1; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: - case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet - /* Lynx Point LP uses a single bit for GCS */ + /* Lynx Point LP uses a single bit for BBS */ bbs = (gcs >> 10) & 0x1; break; default: - /* Older chipsets use two bits for GCS */ + /* Other chipsets use two bits for BBS */ bbs = (gcs >> 10) & 0x3; break; } msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); - if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) { - uint8_t buc = mmio_readb(rcrb + 0x3414); - msg_pdbg("Top Swap: %s\n", (buc & 1) ? "enabled (A16(+) inverted)" : "not enabled"); - } + /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */ + if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) + msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled"); +} + +static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +{ + + /* Get physical address of Root Complex Register Block */ + uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; + msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra); + + /* Map RCBA to virtual memory */ + void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); + if (rcrb == ERROR_PTR) + return ERROR_FATAL; + + enable_flash_ich_handle_gcs(dev, ich_generation, mmio_readl(rcrb + 0x3410), mmio_readb(rcrb + 0x3414)); /* Handle FWH-related parameters and initialization */ int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl); @@ -619,6 +682,7 @@ /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */ uint16_t spibar_offset; switch (ich_generation) { + case CHIPSET_BAYTRAIL: case CHIPSET_ICH_UNKNOWN: return ERROR_FATAL; case CHIPSET_ICH7: @@ -712,6 +776,57 @@ return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); } +/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. + * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. + * + * Differences include: + * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB. + * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410). + * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414). + * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800). + * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC). + */ +static int enable_flash_silvermont(struct pci_dev *dev, const char *name) +{ + enum ich_chipset ich_generation = CHIPSET_BAYTRAIL; + + /* Get physical address of Root Complex Register Block */ + uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00; + msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba); + + /* Handle GCS (in RCRB) */ + void *rcrb = physmap("BYT RCRB", rcba, 4); + uint32_t gcs = mmio_readl(rcrb + 0); + enable_flash_ich_handle_gcs(dev, ich_generation, gcs, gcs & 0x2); + physunmap(rcrb, 4); + + /* Handle fwh_idsel parameter */ + int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation); + if (ret_fwh == ERROR_FATAL) + return ret_fwh; + + internal_buses_supported = BUS_FWH; + + /* Get physical address of SPI Base Address and map it */ + uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; + msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); + void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ + + /* Enable Flash Writes. + * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). + */ + enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC); + + int ret_spi = ich_init_spi(dev, spibar, ich_generation); + if (ret_spi == ERROR_FATAL) + return ret_spi; + + if (ret_fwh || ret_spi) + return ERROR_NONFATAL; + + return 0; +} + static int via_no_byte_merge(struct pci_dev *dev, const char *name) { uint8_t val; @@ -1471,6 +1586,10 @@ {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, + {0x8086, 0x0f1c, NT, "Intel", "Bay Trail", enable_flash_silvermont}, + {0x8086, 0x0f1d, NT, "Intel", "Bay Trail", enable_flash_silvermont}, + {0x8086, 0x0f1e, NT, "Intel", "Bay Trail", enable_flash_silvermont}, + {0x8086, 0x0f1f, NT, "Intel", "Bay Trail", enable_flash_silvermont}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, {0x8086, 0x1c44, DEP, "Intel", "Z68", enable_flash_pch6}, @@ -1505,7 +1624,11 @@ {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7}, {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7}, {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7}, - {0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7}, + {0x8086, 0x1f38, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7}, {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0}, @@ -1567,7 +1690,7 @@ {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, - {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_tunnelcreek}, + {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek}, {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8}, {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8}, Modified: trunk/ich_descriptors.c ============================================================================== --- trunk/ich_descriptors.c Wed Aug 20 17:39:19 2014 (r1843) +++ trunk/ich_descriptors.c Wed Aug 20 17:39:32 2014 (r1844) @@ -139,6 +139,7 @@ return size_str[size_enc]; } case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: { uint8_t size_enc; @@ -180,6 +181,7 @@ case CHIPSET_6_SERIES_COUGAR_POINT: case CHIPSET_7_SERIES_PANTHER_POINT: case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: return freq_str[value]; @@ -820,6 +822,7 @@ size_max = 5; break; case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: if (idx == 0) { Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed Aug 20 17:39:19 2014 (r1843) +++ trunk/ichspi.c Wed Aug 20 17:39:32 2014 (r1844) @@ -612,7 +612,8 @@ bbar_off = 0x50; break; case CHIPSET_ICH8: - msg_perr("BBAR offset is unknown on ICH8!\n"); + case CHIPSET_BAYTRAIL: + msg_pdbg("BBAR offset is unknown!\n"); return; case CHIPSET_ICH9: default: /* Future version might behave the same */ @@ -1739,9 +1740,12 @@ msg_pdbg("VSCC: "); prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); } else { - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); + if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) { + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + ich_set_bbar(0); + } if (desc_valid) { tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); @@ -1757,10 +1761,8 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); } - ich_set_bbar(0); } - msg_pdbg("\n"); if (desc_valid) { if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(ich_gen, &desc); Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed Aug 20 17:39:19 2014 (r1843) +++ trunk/programmer.h Wed Aug 20 17:39:32 2014 (r1844) @@ -600,6 +600,7 @@ CHIPSET_6_SERIES_COUGAR_POINT, CHIPSET_7_SERIES_PANTHER_POINT, CHIPSET_8_SERIES_LYNX_POINT, + CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */ CHIPSET_8_SERIES_LYNX_POINT_LP, CHIPSET_8_SERIES_WELLSBURG, }; Modified: trunk/util/ich_descriptors_tool/ich_descriptors_tool.c ============================================================================== --- trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Wed Aug 20 17:39:19 2014 (r1843) +++ trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Wed Aug 20 17:39:32 2014 (r1844) @@ -118,6 +118,7 @@ "\t- \"ich8\",\n" "\t- \"ich9\",\n" "\t- \"ich10\",\n" +"\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" @@ -202,6 +203,8 @@ else if ((strcmp(csn, "8") == 0) || (strcmp(csn, "lynx") == 0)) cs = CHIPSET_8_SERIES_LYNX_POINT; + else if ((strcmp(csn, "silvermont") == 0)) + cs = CHIPSET_BAYTRAIL; } ret = read_ich_descriptors_from_dump(buf, len, &desc);

1 0

[commit] r1843 - in trunk: . util/ich_descriptors_tool
by repository service 20 Aug '14

20 Aug '14

Author: stefanct Date: Wed Aug 20 17:39:19 2014 New Revision: 1843 URL: http://flashrom.org/trac/flashrom/changeset/1843 Log: Refine Flash Component descriptor handling. Possible values as well as encodings have changed in newer chipsets as follows. - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all operations - Since Cougar Point the chipsets support dual output fast reads (encoded in bit 30). - Flash component density encoding has changed from 3 to 4 bits with Lynx Point, currently allowing for up to 64 MB chips. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/ich_descriptors.c trunk/ich_descriptors.h trunk/ichspi.c trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Modified: trunk/ich_descriptors.c ============================================================================== --- trunk/ich_descriptors.c Fri Aug 15 19:17:59 2014 (r1842) +++ trunk/ich_descriptors.c Wed Aug 20 17:39:19 2014 (r1843) @@ -45,14 +45,16 @@ #define min(a, b) (a < b) ? a : b #endif -void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl) { print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF); print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF); print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF); - print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF); - print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); + print(verbosity, "EO=0x%x", (reg_val & VSCC_EO) >> VSCC_EO_OFF); + if (print_vcl) + print(verbosity, ", VCL=%d", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); + print(verbosity, "\n"); } #define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) @@ -64,7 +66,7 @@ void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) { prettyprint_ich_descriptor_content(&desc->content); - prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_component(cs, desc); prettyprint_ich_descriptor_region(desc); prettyprint_ich_descriptor_master(&desc->master); #ifdef ICH_DESCRIPTORS_FROM_DUMP @@ -98,28 +100,97 @@ msg_pdbg2("\n"); } -void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) +static const char *pprint_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx) +{ + if (idx > 1) { + msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); + return NULL; + } + + if (desc->content.NC == 0 && idx > 0) + return "unused"; + + static const char * const size_str[] = { + "512 kB", /* 0000 */ + "1 MB", /* 0001 */ + "2 MB", /* 0010 */ + "4 MB", /* 0011 */ + "8 MB", /* 0100 */ + "16 MB", /* 0101 */ /* Maximum up to Lynx Point (excl.) */ + "32 MB", /* 0110 */ + "64 MB", /* 0111 */ + }; + + switch (cs) { + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: + case CHIPSET_7_SERIES_PANTHER_POINT: { + uint8_t size_enc; + if (idx == 0) { + size_enc = desc->component.old.comp1_density; + } else { + size_enc = desc->component.old.comp2_density; + } + if (size_enc > 5) + return "reserved"; + return size_str[size_enc]; + } + case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_WELLSBURG: { + uint8_t size_enc; + if (idx == 0) { + size_enc = desc->component.new.comp1_density; + } else { + size_enc = desc->component.new.comp2_density; + } + if (size_enc > 7) + return "reserved"; + return size_str[size_enc]; + } + case CHIPSET_ICH_UNKNOWN: + default: + return "unknown"; + } +} + +static const char *pprint_freq(enum ich_chipset cs, uint8_t value) { static const char * const freq_str[8] = { "20 MHz", /* 000 */ "33 MHz", /* 001 */ "reserved", /* 010 */ "reserved", /* 011 */ - "50 MHz", /* 100 */ + "50 MHz", /* 100 */ /* New since Ibex Peak */ "reserved", /* 101 */ "reserved", /* 110 */ "reserved" /* 111 */ }; - static const char * const size_str[8] = { - "512 kB", /* 000 */ - " 1 MB", /* 001 */ - " 2 MB", /* 010 */ - " 4 MB", /* 011 */ - " 8 MB", /* 100 */ - " 16 MB", /* 101 */ - "reserved", /* 110 */ - "reserved", /* 111 */ - }; + + switch (cs) { + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: + if (value > 1) + return "reserved"; + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: + case CHIPSET_7_SERIES_PANTHER_POINT: + case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_WELLSBURG: + return freq_str[value]; + case CHIPSET_ICH_UNKNOWN: + default: + return "unknown"; + } +} + +void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc) +{ msg_pdbg2("=== Component Section ===\n"); msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); @@ -127,24 +198,21 @@ msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); - msg_pdbg2("Component 1 density: %s\n", - size_str[desc->component.comp1_density]); + msg_pdbg2("Component 1 density: %s\n", pprint_density(cs, desc, 0)); if (desc->content.NC) - msg_pdbg2("Component 2 density: %s\n", - size_str[desc->component.comp2_density]); + msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1)); else msg_pdbg2("Component 2 is not used.\n"); - msg_pdbg2("Read Clock Frequency: %s\n", - freq_str[desc->component.freq_read]); - msg_pdbg2("Read ID and Status Clock Freq.: %s\n", - freq_str[desc->component.freq_read_id]); - msg_pdbg2("Write and Erase Clock Freq.: %s\n", - freq_str[desc->component.freq_write]); - msg_pdbg2("Fast Read is %ssupported.\n", - desc->component.fastread ? "" : "not "); - if (desc->component.fastread) + msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.common.freq_read)); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_read_id)); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_write)); + msg_pdbg2("Fast Read is %ssupported.\n", desc->component.common.fastread ? "" : "not "); + if (desc->component.common.fastread) msg_pdbg2("Fast Read Clock Frequency: %s\n", - freq_str[desc->component.freq_fastread]); + pprint_freq(cs, desc->component.common.freq_fastread)); + if (cs > CHIPSET_6_SERIES_COUGAR_POINT) + msg_pdbg2("Dual Output Fast Read Support: %sabled\n", + desc->component.new.dual_output ? "dis" : "en"); if (desc->component.FLILL == 0) msg_pdbg2("No forbidden opcodes.\n"); else { @@ -273,7 +341,7 @@ msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1); off *= 4; - switch(conf){ + switch (conf){ case 0: msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off); break; @@ -630,7 +698,7 @@ msg_pdbg2(" "); /* indention */ prettyprint_rdid(jid); msg_pdbg2(" "); /* indention */ - prettyprint_ich_reg_vscc(vscc, 0); + prettyprint_ich_reg_vscc(vscc, 0, false); } msg_pdbg2("\n"); } @@ -723,29 +791,57 @@ #else /* ICH_DESCRIPTORS_FROM_DUMP */ /** Returns the integer representation of the component density with index -idx in bytes or 0 if a correct size can not be determined. */ -int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx) +\em idx in bytes or -1 if the correct size can not be determined. */ +int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx) { + if (idx > 1) { + msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); + return -1; + } + + if (desc->content.NC == 0 && idx > 0) + return 0; + uint8_t size_enc; - - switch(idx) { - case 0: - size_enc = desc->component.comp1_density; - break; - case 1: - if (desc->content.NC == 0) - return 0; - size_enc = desc->component.comp2_density; + uint8_t size_max; + + switch (cs) { + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: + case CHIPSET_7_SERIES_PANTHER_POINT: + if (idx == 0) { + size_enc = desc->component.old.comp1_density; + } else { + size_enc = desc->component.old.comp2_density; + } + size_max = 5; + break; + case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_WELLSBURG: + if (idx == 0) { + size_enc = desc->component.new.comp1_density; + } else { + size_enc = desc->component.new.comp2_density; + } + size_max = 7; break; + case CHIPSET_ICH_UNKNOWN: default: - msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); - return 0; + msg_pwarn("Density encoding is unknown on this chipset.\n"); + return -1; } - if (size_enc > 5) { - msg_perr("Density of ICH SPI component with index %d is invalid. Encoded density is 0x%x.\n", - idx, size_enc); - return 0; + + if (size_enc > size_max) { + msg_perr("Density of ICH SPI component with index %d is invalid." + "Encoded density is 0x%x while maximum allowed is 0x%x.\n", + idx, size_enc, size_max); + return -1; } + return (1 << (19 + size_enc)); } Modified: trunk/ich_descriptors.h ============================================================================== --- trunk/ich_descriptors.h Fri Aug 15 19:17:59 2014 (r1842) +++ trunk/ich_descriptors.h Wed Aug 20 17:39:19 2014 (r1843) @@ -64,7 +64,7 @@ #define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) #define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) -void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl); struct ich_desc_content { uint32_t FLVALSIG; /* 0x00 */ @@ -102,17 +102,44 @@ struct ich_desc_component { union { /* 0x00 */ uint32_t FLCOMP; /* Flash Components Register */ + /* FLCOMP encoding on various generations: + * + * Chipset/Generation max_speed dual_output density + * [MHz] bits max. bits + * ICH8: 33 N/A 5 0:2, 3:5 + * ICH9: 33 N/A 5 0:2, 3:5 + * ICH10: 33 N/A 5 0:2, 3:5 + * Ibex Peak/5: 50 N/A 5 0:2, 3:5 + * Cougar Point/6: 50 30 5 0:2, 3:5 + * Patsburg: 50 30 5 0:2, 3:5 + * Panther Point/7 50 30 5 0:2, 3:5 + * Lynx Point/8: 50 30 7 0:3, 4:7 + * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? + */ struct { - uint32_t comp1_density :3, - comp2_density :3, - :11, + uint32_t :17, freq_read :3, fastread :1, freq_fastread :3, freq_write :3, freq_read_id :3, :2; - }; + } common; + struct { + uint32_t comp1_density :3, + comp2_density :3, + :11, + :13, + :2; + } old; + struct { + uint32_t comp1_density :4, /* new since Lynx Point/8 */ + comp2_density :4, + :9, + :13, + dual_output :1, /* new since Cougar Point/6 */ + :1; + } new; }; union { /* 0x04 */ uint32_t FLILL; /* Flash Invalid Instructions Register */ @@ -555,7 +582,7 @@ void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc); void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); -void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc); void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); @@ -568,7 +595,7 @@ #else /* ICH_DESCRIPTORS_FROM_DUMP */ int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); -int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx); +int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx); #endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* __ICH_DESCRIPTORS_H__ */ Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Aug 15 19:17:59 2014 (r1842) +++ trunk/ichspi.c Wed Aug 20 17:39:19 2014 (r1843) @@ -1737,7 +1737,7 @@ tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); } else { ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", @@ -1747,12 +1747,12 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); msg_pdbg("LVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); msg_pdbg("UVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, false); tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); @@ -1762,10 +1762,9 @@ msg_pdbg("\n"); if (desc_valid) { - if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == - ICH_RET_OK) - prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, - &desc); + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) + prettyprint_ich_descriptors(ich_gen, &desc); + /* If the descriptor is valid and indicates multiple * flash devices we need to use hwseq to be able to * access the second flash device. @@ -1791,8 +1790,21 @@ "valid. Aborting.\n"); return ERROR_FATAL; } - hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); - hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); + + int tmpi = getFCBA_component_density(ich_generation, &desc, 0); + if (tmpi < 0) { + msg_perr("Could not determine density of flash component %d.\n", 0); + return ERROR_FATAL; + } + hwseq_data.size_comp0 = tmpi; + + tmpi = getFCBA_component_density(ich_generation, &desc, 1); + if (tmpi < 0) { + msg_perr("Could not determine density of flash component %d.\n", 1); + return ERROR_FATAL; + } + hwseq_data.size_comp1 = tmpi; + register_opaque_master(&opaque_master_ich_hwseq); } else { register_spi_master(&spi_master_ich9); Modified: trunk/util/ich_descriptors_tool/ich_descriptors_tool.c ============================================================================== --- trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Fri Aug 15 19:17:59 2014 (r1842) +++ trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Wed Aug 20 17:39:19 2014 (r1843) @@ -113,7 +113,7 @@ "where <image file name> points to an image of the contents of the SPI flash.\n" "In case the image is really in descriptor mode %s\n" "will pretty print some of the contained information.\n" -"To also print the data stored in the descriptor strap you have to indicate\n" +"To also print the data stored in the descriptor straps you have to indicate\n" "the chipset series with the '-c' parameter and one of the possible arguments:\n" "\t- \"ich8\",\n" "\t- \"ich9\",\n" @@ -121,6 +121,7 @@ "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -198,6 +199,9 @@ else if ((strcmp(csn, "7") == 0) || (strcmp(csn, "panther") == 0)) cs = CHIPSET_7_SERIES_PANTHER_POINT; + else if ((strcmp(csn, "8") == 0) || + (strcmp(csn, "lynx") == 0)) + cs = CHIPSET_8_SERIES_LYNX_POINT; } ret = read_ich_descriptors_from_dump(buf, len, &desc);

1 0

Re: [flashrom] [PATCH 3/3] Refine physical address mapping of flash chips.
by Carl-Daniel Hailfinger 20 Aug '14

20 Aug '14

Am 08.08.2014 16:25 schrieb Stefan Tauner: > Previously we did map the physical memory corresponding to all chips, > even for SPI chips where it is completely unnecessary because we do > not use it in any SPI-capable programmer. Ahem. it87spi.c: it8716f_spi_chip_read() and it8716f_spi_page_program() uses that. > Also, the mapping was never undone before the program exited. > Mapping of additional flash registers was done within probing methods > instead of centrally. This patch changes the behaviour: In current HEAD, the mapping of registers only happens on successful probe. With this patch, it happens unconditionally (depending only on whether the chip supports it, not on whether the programmer supports it) before probe. If you really want to change that, it should be mentioned in the changelog. > Besides all of that, this patch also adds proper error handling for > mapping-related operations. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Sorry, no ack yet. > 82802ab.c | 2 -- > flash.h | 1 - > flashrom.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++---------------- > jedec.c | 6 ----- > 4 files changed, 63 insertions(+), 30 deletions(-) > > diff --git a/82802ab.c b/82802ab.c > index 70c6af0..5d015ba 100644 > --- a/82802ab.c > +++ b/82802ab.c > @@ -83,8 +83,6 @@ int probe_82802ab(struct flashctx *flash) > if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id) > return 0; > > - if (flash->chip->feature_bits & FEATURE_REGISTERMAP) > - map_flash_registers(flash); > > return 1; > } > diff --git a/flash.h b/flash.h > index 82a8b74..998696c 100644 > --- a/flash.h > +++ b/flash.h > @@ -252,7 +252,6 @@ void tolower_string(char *str); > /* flashrom.c */ > extern const char flashrom_version[]; > extern const char *chip_to_probe; > -void map_flash_registers(struct flashctx *flash); > int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); > int erase_flash(struct flashctx *flash); > int probe_flash(struct registered_master *mst, int startchip, struct flashctx *fill_flash, int force); > diff --git a/flashrom.c b/flashrom.c > index 0ff6b63..72bf157 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -528,12 +528,23 @@ void programmer_delay(unsigned int usecs) > programmer_table[programmer].delay(usecs); > } > > -void map_flash_registers(struct flashctx *flash) > +static int map_flash_registers(struct flashctx *flash) Can you leave that one untouched, please? It's code I dare not change because even I have no idea where (if at all) registers would be mapped for chips on masters mapping the chip to nonstandard locations. If you have access to Loongson and Elan SC520 datasheets, you're welcome to check and fix this. Until then, the known broken and documented broken code is IMHO better than speculative code that looks like it could work but was never checked against datasheets or hardware. > { > size_t size = flash->chip->total_size * 1024; > /* Flash registers live 4 MByte below the flash. */ > - /* FIXME: This is incorrect for nonstandard flashbase. */ > - flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); > + uintptr_t base = (flashbase != 0) ? flashbase : (0xffffffff - size + 1); > + if (base < 0x400000) { > + msg_perr("Base address is too low to map flash registers."); > + return 1; > + } > + base -= 0x400000; > + void *addr = programmer_map_flash_region("flash chip registers", base, size); > + if (addr == ERROR_PTR) { > + msg_perr("Could not map flash chip registers.\n"); > + return 1; > + } > + flash->virtual_registers = (chipaddr)addr; > + return 0; > } > > int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, > @@ -1052,12 +1063,49 @@ unsigned int count_max_decode_exceedings(struct flashctx *flash) > return limitexceeded; > } > > +void unmap_flash(struct flashctx *flash) > +{ > + if (flash->chip->bustype & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) { > + if (flash->virtual_memory != 0) { > + programmer_unmap_flash_region((void *)flash->virtual_memory, > + flash->chip->total_size * 1024); > + flash->virtual_memory = 0; > + } > + > + if (flash->chip->feature_bits & FEATURE_REGISTERMAP && flash->virtual_registers != 0) { > + programmer_unmap_flash_region((void *)flash->virtual_registers, > + flash->chip->total_size * 1024); > + flash->virtual_registers = 0; > + } > + } > +} > + > +int map_flash(struct flashctx *flash) > +{ > + const unsigned long size = flash->chip->total_size; > + if (flash->chip->bustype & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) { > + uintptr_t base = flashbase ? flashbase : (0xffffffff - size + 1); > + void *addr = programmer_map_flash_region("flash chip", base, size); > + if (addr == ERROR_PTR) { > + msg_perr("Could not map flash chip registers.\n"); > + return 1; > + } > + flash->virtual_memory = (chipaddr)addr; > + > + if (flash->chip->feature_bits & FEATURE_REGISTERMAP) { > + if (map_flash_registers(flash) != 0) { > + unmap_flash(flash); > + return 1; > + } > + } > + } AFAICS this will segfault (NULL pointer dereference) on chips of 4 MBit and less on IT87 SPI. > + > + return 0; > +} > + > int probe_flash(struct registered_master *mst, int startchip, struct flashctx *flash, int force) > { > const struct flashchip *chip; > - unsigned long base = 0; > - char location[64]; > - uint32_t size; > enum chipbustype buses_common; > char *tmp; > > @@ -1082,9 +1130,8 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f > memcpy(flash->chip, chip, sizeof(struct flashchip)); > flash->mst = mst; > > - size = chip->total_size * 1024; > - base = flashbase ? flashbase : (0xffffffff - size + 1); > - flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); > + if (map_flash(flash) != 0) > + return -1; > > /* We handle a forced match like a real match, we just avoid probing. Note that probe_flash() > * is only called with force=1 after normal probing failed. > @@ -1133,8 +1180,7 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f > break; > /* Not the first flash chip detected on this bus, and it's just a generic match. Ignore it. */ > notfound: > - programmer_unmap_flash_region((void *)flash->virtual_memory, size); > - flash->virtual_memory = (chipaddr)NULL; > + unmap_flash(flash); > free(flash->chip); > flash->chip = NULL; > } > @@ -1142,16 +1188,9 @@ notfound: > if (!flash->chip) > return -1; > > -#if CONFIG_INTERNAL == 1 > - if (programmer_table[programmer].map_flash_region == physmap) > - snprintf(location, sizeof(location), "at physical address 0x%lx", base); > - else > -#endif > - snprintf(location, sizeof(location), "on %s", programmer_table[programmer].name); > - That info should not have disappeared, and we may soon have to extend it for funny constellations like two chips in a programmer (EC flash and chipset flash for laptops). > tmp = flashbuses_to_text(flash->chip->bustype); > - msg_cinfo("%s %s flash chip \"%s\" (%d kB, %s) %s.\n", force ? "Assuming" : "Found", > - flash->chip->vendor, flash->chip->name, flash->chip->total_size, tmp, location); > + msg_cinfo("%s %s flash chip \"%s\" (%d kB, %s).\n", force ? "Assuming" : "Found", > + flash->chip->vendor, flash->chip->name, flash->chip->total_size, tmp); > free(tmp); > > /* Flash registers will not be mapped if the chip was forced. Lock info > @@ -1872,7 +1911,8 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, > flash->chip->unlock(flash); > > if (read_it) { > - return read_flash_to_file(flash, filename); > + ret = read_flash_to_file(flash, filename); > + goto unmap; > } > > oldcontents = malloc(size); > @@ -1991,5 +2031,7 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, > out: > free(oldcontents); > free(newcontents); > +unmap: > + unmap_flash(flash); > return ret; > } > diff --git a/jedec.c b/jedec.c > index 358b850..1345b89 100644 > --- a/jedec.c > +++ b/jedec.c > @@ -166,9 +166,6 @@ int probe_jedec_29gl(struct flashctx *flash) > if (man_id != chip->manufacture_id || dev_id != chip->model_id) > return 0; > > - if (chip->feature_bits & FEATURE_REGISTERMAP) > - map_flash_registers(flash); > - > return 1; > } > > @@ -287,9 +284,6 @@ static int probe_jedec_common(struct flashctx *flash, unsigned int mask) > if (largeid1 != chip->manufacture_id || largeid2 != chip->model_id) > return 0; > > - if (chip->feature_bits & FEATURE_REGISTERMAP) > - map_flash_registers(flash); > - > return 1; > } > Regards, Carl-Daniel

2 4

Thinkpad X60s bug report
by Ted 19 Aug '14

19 Aug '14

>>>x60s@TedX60s:~/Downloads/libreboot_bin/flashrom$ sudo ./flashrom_lenovobios_sst -p internal -r factory.bin flashrom v0.9.7-unknown on Linux 3.2.0-60-generic (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel ICH7M". Enabling flash write... WARNING: SPI Configuration Lockdown activated. OK. Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically.

2 1

Re: [flashrom] Macronix MX25L12835FMI-10G, bus pirate and flashrom support
by Stefan Tauner 19 Aug '14

19 Aug '14

On Tue, 19 Aug 2014 14:43:09 +0200 Marli LI <marco.li.li.marco(a)gmail.com> wrote: > My output now is: > >> Found Macronix flash chip "MX25L12805(D)" (16384 kB, SPI). > >> This chip may contain one-time programmable memory. flashrom cannot read > >> and may never be able to write it, hence it may not be able to completely > >> clone the contents of this chip (see man page for details). > > I think I can now proceed w/ dumping the chip, right? Yes, even erase and write should work fine. The chips do not only share the same ID but also the most important opcodes. I am not expecting more trouble. > Can't flashrom somehow distinguish the different Macronix chips? The > label of mine should be MX25L12835FMI-10g . > If someone has an idea if such an improvement is possible, I would be > happy to test/analyze. With the current infrastructure it can't distinguish them. Improvements are on the way but even with them it might not be exactly trivial to accomplish that. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] Macronix MX25L12835FMI-10G, bus pirate and flashrom support
by Stefan Tauner 19 Aug '14

19 Aug '14

On Mon, 18 Aug 2014 17:38:04 +0200 Marli LI <marco.li.li.marco(a)gmail.com> wrote: > Hello all, > > I need some help to get this chip MX25L12835FMI-10G manufactured by > Macronix to work w/ flashrom. > > I already asked for help on #flashrom IRC channel, but I was referred > to ask on this mailing list. > In fact, before I connected everything I asked on IRC if this chip is > "already" supported, and someone from IRC did double-check it and said > that the other MX25L128 chip model that IS supported is very similar > and identifies itself w/ same code/id (he got this info from > spreadsheet that I've linked below). > > So here is my output of flashrom (I've tried both the svn version and > the one shipped with ubuntu packages w/ identical results): > http://paste.flashrom.org/view.php?id=2658 > > > The chip's datasheet should be this one: > http://www.macronix.com/Lists/Datasheet/Attachments/1587/MX25L12835F,%203V,… > On page 7 you can see the pin-out. The chip type I have has 16 (= 8x2) > pins. There are several NC labels in the pin-out therefore I didn't > connect those. > > For the rest of the connections I followed this site: > http://flashrom.org/Bus_Pirate (because I use a bus pirate w/ > hardware version 3.6 ). > The chip itself is directly attached to a pomona 5252 (SOIC-16) test clip. > > What follows are some pics of my setup + chip. > > Any hints and help would be very much appreciated because I am kind of stuck. > > Ps. Today I discovered something interesting in the spreadsheet; the > 10 (from -10g suffix) stands for 10: 104MHz . Do I need to set > spispeed to a higher level b/c of this? > > Thx again > > - - - IMAGES - - - > > Macronix MX25L12835FMI-10G chip (16 pins): http://postimg.org/image/y7ykedq6r/ > Pomona soic-16 test clip 5252 : http://postimg.org/image/gqru9oum7/ > Bus pirate hw version 3.6 : http://postimg.org/image/80a7zp0ub/ > Test clip + chip, direction (where point is): > http://postimg.org/image/koc4h655d/ > Chip attached: http://postimg.org/image/4ywrbnnst/ As discussed on IRC, this is probably caused by bad connections or not enough power supplied to the chip. The frequency stated for flash chip is a maximum and slower programmers work fine (most mainboards do not use more than ~50 MHz either). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Re: [flashrom] FAILED: HP ChromeBook 14 (Falco)
by Stefan Tauner 19 Aug '14

19 Aug '14

On Mon, 18 Aug 2014 19:35:18 +0200 "Maria Roth" <rothm(a)mail.com> wrote: > Hi, > > I got that while using J. Lewis script to flash an HP Chromebook 14 (Falco) (without screw). > > flashrom v0.9.4 : 14ce0cf : Oct 09 2013 22:16:28 UTC on Linux 3.15.10-200.fc20.x86_64 (x86_64), built with libpci 3.1.10, GCC 4.7.x-google 20130114 (prerelease), little endian Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0 Verifying flash... VERIFY FAILED at 0x00000062! Expected=0xff, Read=0x0b, failed byte count from 0x00000000-0x007fffff: 0x4 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! FAILED > > Can you help ? > > Thanks, > R. As discussed on IRC, and merely in the hope it might help someone in the future: if you see exactly this message (esp. the 0x4 after the range of memory addresses and the 0x0...62 after VERIFY FAILED) then you are safe. It is caused by a difference between the original flash contents and the image John Lewis is providing at his website (https://johnlewis.ie). The difference is in a copy-protected region that is not essential for the rest of the image and both versions are OK - they just can't be changed without an external programmer and that's why one gets the warning when using flashrom with the internal programmer. You have to nag John to get this fixed/changed, but it is in this form only a cosmetic nuisance. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

FAILED: HP ChromeBook 14 (Falco)
by Maria Roth 18 Aug '14

18 Aug '14

1 0

Macronix MX25L12835FMI-10G, bus pirate and flashrom support
by Marli LI 18 Aug '14

18 Aug '14

Hello all, I need some help to get this chip MX25L12835FMI-10G manufactured by Macronix to work w/ flashrom. I already asked for help on #flashrom IRC channel, but I was referred to ask on this mailing list. In fact, before I connected everything I asked on IRC if this chip is "already" supported, and someone from IRC did double-check it and said that the other MX25L128 chip model that IS supported is very similar and identifies itself w/ same code/id (he got this info from spreadsheet that I've linked below). So here is my output of flashrom (I've tried both the svn version and the one shipped with ubuntu packages w/ identical results): http://paste.flashrom.org/view.php?id=2658 The chip's datasheet should be this one: http://www.macronix.com/Lists/Datasheet/Attachments/1587/MX25L12835F,%203V,… On page 7 you can see the pin-out. The chip type I have has 16 (= 8x2) pins. There are several NC labels in the pin-out therefore I didn't connect those. For the rest of the connections I followed this site: http://flashrom.org/Bus_Pirate (because I use a bus pirate w/ hardware version 3.6 ). The chip itself is directly attached to a pomona 5252 (SOIC-16) test clip. What follows are some pics of my setup + chip. Any hints and help would be very much appreciated because I am kind of stuck. Ps. Today I discovered something interesting in the spreadsheet; the 10 (from -10g suffix) stands for 10: 104MHz . Do I need to set spispeed to a higher level b/c of this? Thx again - - - IMAGES - - - Macronix MX25L12835FMI-10G chip (16 pins): http://postimg.org/image/y7ykedq6r/ Pomona soic-16 test clip 5252 : http://postimg.org/image/gqru9oum7/ Bus pirate hw version 3.6 : http://postimg.org/image/80a7zp0ub/ Test clip + chip, direction (where point is): http://postimg.org/image/koc4h655d/ Chip attached: http://postimg.org/image/4ywrbnnst/

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[PATCH] Bus Pirate UART speedup
by Bernie Innocenti 18 Aug '14

18 Aug '14

I'm reposting this patch sent by Stefan Tauner in April, after rebasing it onto flashrom's svn trunk. Compared to the original, there's just one change: the original patch did set the host uart speed back to 115200 (which is a no-op). So I changed the baudrate to 2000000 (2Mbit), making the code agree with the description. I tested the patched flashrom with a Buspirate v3 running the 6.2beta firmware. While I didn't make any accurate measurements, I'd guesstimate a 10x speedup with my 8MB SPI flash. WOAH! --- original description follows ---- Increase PIC/FT232 UART speed to 2 Mbaud (instead of 115200 baud) in firmware 5.5 and newer. Given that UART speed is the biggest bottleneck for Bus Pirate communication (right now 90% of the read time is caused by slow BP<->host communication), this patch is absolutely needed to get any decent speed out of the Bus Pirate. WARNING: This patch may hang flashrom or corrupt data for any non-v3 Bus Pirate model. I haven't tested such models, and it might work without problems. Who knows. We would have to find someone with a v2 (or earlier) Bus Pirate and a firmware version >=v5.5 to test this. For Bus Pirate model v4 this patch may be completely superfluous. Anyway, activating fast UART only for some models is probably the way to go. We already have code to determine the hardware model in the init function, this just needs to be stored in some variable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- buspirate_spi.c | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/buspirate_spi.c b/buspirate_spi.c index d2ebc75..57da63a 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -178,7 +178,10 @@ static int buspirate_spi_shutdown(void *data) } /* Reset Bus Pirate (return to user terminal) */ bp_commbuf[0] = 0x0f; - ret = buspirate_sendrecv(bp_commbuf, 1, 0); + if ((ret = buspirate_sendrecv(bp_commbuf, 1, 0))) + goto out_shutdown; + if ((ret = serialport_config(sp_fd, 115200))) + goto out_shutdown; out_shutdown: /* Shut down serial port communication */ @@ -365,6 +368,45 @@ int buspirate_spi_init(void) spi_programmer_buspirate.command = buspirate_spi_send_command_v1; } + /* Increase PIC/FT232 UART speed to 2 Mbaud (instead of 115200 baud) in firmware 5.5 and newer. + * Although this is already possible in firmware 5.2, fast UART in combination with the old SPI + * command set causes hangs for bigger transactions. This is caused by a UART buffer overrun + * in the PIC, and all firmware versions up to (hopefully not including) 6.2 are affected. + */ + if (BP_FWVERSION(fw_version_major, fw_version_minor) >= BP_FWVERSION(5, 5)) { + // FIXME: Do this only for USB-based Bus Pirates... unless you're sure the UART can handle more. + int cmdlen; + /* Request setting the UART baud rate. */ + cmdlen = snprintf((char *)bp_commbuf, DEFAULT_BUFSIZE, "b\n"); + if ((ret = buspirate_sendrecv(bp_commbuf, cmdlen, 0))) + return ret; + if ((ret = buspirate_wait_for_string(bp_commbuf, ">"))) + return ret; + /* Request setting the UART clock divisor manually. */ + cmdlen = snprintf((char *)bp_commbuf, DEFAULT_BUFSIZE, "10\n"); + if ((ret = buspirate_sendrecv(bp_commbuf, cmdlen, 0))) + return ret; + if ((ret = buspirate_wait_for_string(bp_commbuf, ">"))) + return ret; + /* Set the UART clock divisor. New clock is 4000000/(divisor+1). */ + cmdlen = snprintf((char *)bp_commbuf, DEFAULT_BUFSIZE, "%i\n", 1); + if ((ret = buspirate_sendrecv(bp_commbuf, cmdlen, 0))) + return ret; + sleep(1); + if (serialport_config(sp_fd, 2000000) != 0) + return 1; + bp_commbuf[0] = ' '; + if ((ret = buspirate_sendrecv(bp_commbuf, 1, 0))) + return ret; + if ((ret = buspirate_wait_for_string(bp_commbuf, "HiZ>"))) + return ret; + msg_pdbg("Using fast 2 Mbaud for Bus Pirate <-> host communication.\n"); + } else { + msg_pinfo("Bus Pirate firmware 5.4 and older does not support fast Bus Pirate <-> host " + "communication. Limiting UART speed to 115200 Baud.\n"); + msg_pinfo("It is recommended to upgrade to firmware 6.2 or newer.\n"); + } + /* Workaround for broken speed settings in firmware 6.1 and older. */ if (BP_FWVERSION(fw_version_major, fw_version_minor) < BP_FWVERSION(6, 2)) if (spispeed > 0x4) { -- _ // Bernie Innocenti \X/ http://codewiz.org

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Re: [flashrom] [PATCH 2/3] Refine handling chips that exceed maximum programmer sizes.
by Carl-Daniel Hailfinger 15 Aug '14

15 Aug '14

Am 08.08.2014 16:25 schrieb Stefan Tauner: > - Change check_max_decode() to return the number of (common) busses > where the flash chip exceeds the supported size of the programmer. > - Refine its signature to use a flashctx pointer only. > - Move CLI-related bits to cli_classic.c. > - Rename check_max_decode() to count_max_decode_exceedings() to > better reflect what it (now) really does. > - Refine the messages printed by the caller to better integrate with the new > setup, and simplify them. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> I like it. One small comment below. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > diff --git a/flashrom.c b/flashrom.c > index eeed90b..0ff6b63 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1079,9 +1073,6 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f > continue; > } > > - size = chip->total_size * 1024; > - check_max_decode(buses_common, size); > - > /* Start filling in the dynamic data. */ > flash->chip = calloc(1, sizeof(struct flashchip)); > if (!flash->chip) { > @@ -1091,6 +1082,7 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f > memcpy(flash->chip, chip, sizeof(struct flashchip)); > flash->mst = mst; > > + size = chip->total_size * 1024; At this point, it might be better to use "flash->chip->total_size * 1024" given that flash->chip is now valid (it wasn't valid at the old location). > base = flashbase ? flashbase : (0xffffffff - size + 1); > flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); > Regards, Carl-Daniel

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[commit] r1842 - trunk
by repository service 15 Aug '14

15 Aug '14

Author: stefanct Date: Fri Aug 15 19:17:59 2014 New Revision: 1842 URL: http://flashrom.org/trac/flashrom/changeset/1842 Log: Refine handling chips that exceed maximum programmer sizes. - Change check_max_decode() to return the number of (common) busses where the flash chip exceeds the supported size of the programmer. - Refine its signature to use a flashctx pointer only. - Move CLI-related bits to cli_classic.c. - Rename check_max_decode() to count_max_decode_exceedings() to better reflect what it (now) really does. - Refine the messages printed by the caller to better integrate with the new setup, and simplify them. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/cli_classic.c trunk/flashrom.c trunk/programmer.h Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Sat Aug 9 01:52:33 2014 (r1841) +++ trunk/cli_classic.c Fri Aug 15 19:17:59 2014 (r1842) @@ -91,7 +91,6 @@ int main(int argc, char *argv[]) { - unsigned long size; /* Probe for up to three flash chips. */ const struct flashchip *chip = NULL; struct flashctx flashes[6] = {{0}}; @@ -501,9 +500,18 @@ print_chip_support_status(fill_flash->chip); - size = fill_flash->chip->total_size * 1024; - if (check_max_decode(fill_flash->mst->buses_supported & fill_flash->chip->bustype, size) && (!force)) { - msg_cerr("Chip is too big for this programmer (-V gives details). Use --force to override.\n"); + unsigned int limitexceeded = count_max_decode_exceedings(fill_flash); + if (limitexceeded > 0 && !force) { + enum chipbustype commonbuses = fill_flash->mst->buses_supported & fill_flash->chip->bustype; + + /* Sometimes chip and programmer have more than one bus in common, + * and the limit is not exceeded on all buses. Tell the user. */ + if ((bitcount(commonbuses) > limitexceeded)) { + msg_pdbg("There is at least one interface available which could support the size of\n" + "the selected flash chip.\n"); + } + msg_cerr("This flash chip is too big for this programmer (--verbose/-V gives details).\n" + "Use --force/-f to override at your own risk.\n"); ret = 1; goto out_shutdown; } Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Aug 9 01:52:33 2014 (r1841) +++ trunk/flashrom.c Fri Aug 15 19:17:59 2014 (r1842) @@ -1009,9 +1009,13 @@ return 0; } -int check_max_decode(enum chipbustype buses, uint32_t size) +/* Returns the number of busses commonly supported by the current programmer and flash chip where the latter + * can not be completely accessed due to size/address limits of the programmer. */ +unsigned int count_max_decode_exceedings(const struct flashctx *flash) { - int limitexceeded = 0; + unsigned int limitexceeded = 0; + uint32_t size = flash->chip->total_size * 1024; + enum chipbustype buses = flash->mst->buses_supported & flash->chip->bustype; if ((buses & BUS_PARALLEL) && (max_rom_decode.parallel < size)) { limitexceeded++; @@ -1045,17 +1049,7 @@ "probe/read/erase/write may fail. ", size / 1024, max_rom_decode.spi / 1024, "SPI"); } - if (!limitexceeded) - return 0; - /* Sometimes chip and programmer have more than one bus in common, - * and the limit is not exceeded on all buses. Tell the user. - */ - if (bitcount(buses) > limitexceeded) - /* FIXME: This message is designed towards CLI users. */ - msg_pdbg("There is at least one common chip/programmer " - "interface which can support a chip of this size. " - "You can try --force at your own risk.\n"); - return 1; + return limitexceeded; } int probe_flash(struct registered_master *mst, int startchip, struct flashctx *flash, int force) @@ -1079,9 +1073,6 @@ continue; } - size = chip->total_size * 1024; - check_max_decode(buses_common, size); - /* Start filling in the dynamic data. */ flash->chip = calloc(1, sizeof(struct flashchip)); if (!flash->chip) { @@ -1091,6 +1082,7 @@ memcpy(flash->chip, chip, sizeof(struct flashchip)); flash->mst = mst; + size = flash->chip->total_size * 1024; base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Aug 9 01:52:33 2014 (r1841) +++ trunk/programmer.h Fri Aug 15 19:17:59 2014 (r1842) @@ -513,7 +513,7 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -int check_max_decode(enum chipbustype buses, uint32_t size); +unsigned int count_max_decode_exceedings(const struct flashctx *flash); char *extract_programmer_param(const char *param_name); /* spi.c */

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Re: [flashrom] Chips requiring 12 volts on VPP for erase and write
by Stefan Tauner 15 Aug '14

15 Aug '14

On Thu, 14 Aug 2014 16:35:16 +0200 Daniele Forsi <dforsi(a)gmail.com> wrote: > Hello, > > I have an Intel P28F001 flash memory which flashrom knows as > INTEL_28F001T and lists with .tested = TEST_OK_PR > > I can confirm that reading works with -p internal but erasing and > writing don't work because according to its datasheet it needs 12 > volts on VPP (min 11.4 max 12.6) > > should this fact about 12V VPP recorded somewhere? > > the same for the B variant (which I haven't got) Yes, definitely. flashrom does not handle that yet explicitly. Maybe there are some board enables that enable that on single boards, I dont know... but there is nothing chip-specific AFAIK. I'd suggest a new feature flag for that, what do you think Carl-Daniel? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 1/3] Refine Flash Component descriptor handling.
by Stefan Tauner 14 Aug '14

14 Aug '14

On Tue, 12 Aug 2014 17:01:42 -0600 Marc Jones <marcj303(a)gmail.com> wrote: > I tested this branch on CC2: https://github.com/stefanct/flashrom/tree/intel > > See attached logs. > > > Flashrom views both chips as a single flash space. Yes, because the Intel chipsets do not allow the chip select pin to be controlled by software directly. One has to use hardware sequencing and there it does not make much sense to separate the two (although we know the boundaries and could do so), or are there use cases for that in the wild? Like using the first chip for everything but the BIOS region and the second chip for the BIOS region only...? > What is the correct > method for only updating a single descriptor area? There is only one descriptor (area), but I presume you are meaning a region. Using a layout file allows to write only a part, but there are patches that extend the usage to other actions as well. The second (i.e. write) log is more or less useless due to: "Warning: Chip content is identical to the requested image." Although it would be somewhat interesting... because the descriptor tells us that the flash chip has 256 B erase blocks, which is very improbable. Do you know which flash chips are mounted there? (The first one could be determined by forcing software sequencing via the -p internal:ich_spi_mode=swseq). I'd also like to see a -VV log (you could also use the -o <logfile> parameter ;) because with the flashrom prints more detailed information about the descriptor... and I think either the descriptor is wrong or they have changed something about the erase block sizes too... I need to verify that before committing. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Stefan Tauner 14 Aug '14

14 Aug '14

On Thu, 14 Aug 2014 11:52:21 -0300 Ricardo Menzer <ricardomenzer(a)gmail.com> wrote: > (implicit question: is there a parameter to set SPI > frequency for the internal programmer?) Not for the Intel chipsets. But we use the lowest available frequency anyway (20 MHz), so it would probably not help you anyway. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Carl-Daniel Hailfinger 14 Aug '14

14 Aug '14

Hi Ricardo, your log is weird in a way I've never seen before. Details below. Am 13.08.2014 21:24 schrieb Ricardo Menzer: > I have also found that if I probe the chip three times, it will work > only once. I mean, if I probe for the chip and it is found, the next > two probes will fail. The third will work, and the next two will fail > again, and so on. > I'm attaching the logs for three consecutive probes and also the > output of lspci -vvxxxnn. > > > > Ricardo Menzer > ricardomenzer(a)gmail.com > (32)8865-8805 > > > 2014-08-13 12:15 GMT-03:00 Ricardo Menzer <ricardomenzer(a)gmail.com>: >> > Hi guys! >> > I'm working with this COM Express module from Adlink >> > (http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1001&seq=&id=&sid…) >> > and sometimes it doesn't recognize it's flash chip. >> > The following log happened after a failed probing. I then let the >> > board resting some time and tried to program again, with the results >> > bellow. >> > >> > This is a quite problematic module. Frequently it fails to probe the >> > flash chip. I have to reboot the system so it can see it again. It >> > also seems to corrupt the module flash even if I select to write to >> > the baseboard flash. I don't know if it's a flashrom issue or a >> > bios/hardware issue. >> > >> > I can safely reboot the system because we have a second flash on the baseboard. >> > >> > Right now I am using the module's flash to play with coreboot and i'm >> > maintaining a copy of the original BIOS on the baseboard. Changing the >> > role of both chips doesn't seem to change much, except for the >> > corruption issue (didn't made much tests yet, though). >> > >> > I have a Kontron module that I use in this same base board and it >> > works pretty well. >> > >> > >> > 14:55:12 root ~ # flashrom-0.9.7/flashrom -p internal -w >> > /media/sda1/coreboot.rom >> > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) >> > flashrom is free software, get the source code at http://www.flashrom.org >> > >> > Calibrating delay loop... OK. >> > sh: dmidecode: command not found >> > dmidecode execution unsuccessful - continuing without DMI info >> > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. >> > Please supply the board vendor and model name with the -p >> > internal:mainboard=<vendor>:<model> option. >> > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. >> > Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address >> > 0xffe00000. >> > Reading old flash chip contents... done. >> > Erasing and writing flash chip... timeout, ICH7_REG_SPIS=0x0001 >> > spi_block_erase_20 failed during command execution at address 0x0 >> > Reading current flash chip contents... Error: SCIP never cleared! >> > Can't read anymore! Aborting. >> > FAILED! >> > Uh oh. Erase/write failed. Checking if anything changed. >> > Error: SCIP never cleared! >> > Your flash chip is in an unknown state. >> > Get help on IRC at chat.freenode.net (channel #flashrom) or >> > mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! >> > ------------------------------------------------------------------------------- >> > DO NOT REBOOT OR POWEROFF! >> > 14:56:28 root ~ # flashrom-0.9.7/flashrom -p internal -w >> > /media/sda1/coreboot.rom >> > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) >> > flashrom is free software, get the source code at http://www.flashrom.org >> > >> > Calibrating delay loop... OK. >> > sh: dmidecode: command not found >> > dmidecode execution unsuccessful - continuing without DMI info >> > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. >> > Please supply the board vendor and model name with the -p >> > internal:mainboard=<vendor>:<model> option. >> > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. >> > Error: SCIP never cleared! >> > Error: SCIP never cleared! > > flash1.log > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > flashrom was built with libpci 3.2.0, GCC 4.8.2, little endian > Command line (3 args): /home/root/flashrom-0.9.7/flashrom -p internal -V > Calibrating delay loop... OS timer resolution is 4 usecs, 292M loops per second, 10 myus = 13 us, 100 myus = 101 us, 1000 myus = 1016 us, 10000 myus = 10057 us, 16 myus = 19 us, OK. > Initializing internal programmer > No coreboot table found. > Found Winbond Super I/O, id 0x52 > Please supply the board vendor and model name with the -p internal:mainboard=<vendor>:<model> option. > Found chipset "Intel Atom E6xx(T)/Tunnel Creek" with PCI ID 8086:8186. Enabling flash write... > BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled > BIOS Prefetch Enable: disabled, > Root Complex Register Block address = 0xfed1c000 > SPIBAR = 0xfed1c000 + 0x3020 > 0x00: 0x0004 (SPIS) > 0x02: 0x41c0 (SPIC) > 0x04: 0x00000000 (SPIA) > 0x08: 0x41414125 (SPID0) > 0x0c: 0x00000000 (SPID0+4) > 0x10: 0x00000000 (SPID1) > 0x14: 0x00000000 (SPID1+4) > 0x18: 0x00000000 (SPID2) > 0x1c: 0x00000000 (SPID2+4) > 0x20: 0x00000000 (SPID3) > 0x24: 0x00000000 (SPID3+4) > 0x28: 0x00000000 (SPID4) > 0x2c: 0x00000000 (SPID4+4) > 0x30: 0x00000000 (SPID5) > 0x34: 0x00000000 (SPID5+4) > 0x38: 0x00000000 (SPID6) > 0x3c: 0x00000000 (SPID6+4) > 0x40: 0x00000000 (SPID7) > 0x44: 0x00000000 (SPID7+4) > 0x50: 0x00000000 (BBAR) > 0x54: 0x5006 (PREOP) > 0x56: 0x063b (OPTYPE) > 0x58: 0x05200302 (OPMENU) > 0x5c: 0x0050019f (OPMENU+4) > 0x60: 0x00000000 (PBR0) > 0x64: 0x00000000 (PBR1) > 0x68: 0x00000000 (PBR2) > Programming OPCODES... done > SPI Read Configuration: prefetching disabled, caching enabled, OK. > The following protocols are supported: Parallel, LPC, FWH, SPI. > Probing for AMIC A25L05PT, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L10PU, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L40PT, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L16PT, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L020, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 As you can see, the chip continuously outputs 0xbf 0x25 0x41 in an endless loop. Normally, the SST SST25VF016B chip should always return the same ID response to probe_spi_rdid_generic: id1 0xbf, id2 0x2541. However, your chip seems to be cycling through shifted variants of that response. This indicates the chip never leaves ID (read JEDEC ID with command 0x9f) mode, probably because the CE# (chip enable) line is stuck on low. I've never seen that happen before, and it's certainly really weird. Do you have a multimeter to confirm that the CE# pin of the flash chip is indeed continuously at 0V? The Intel Tunnel Creek chipset may be at fault, or some other weird component is screwing things up. Two things I'd like you to try: - Compile latest flashrom from source, reboot and then write a log file with the new flashrom using -o logfile.txt . It needs to be the first run after the reboot or we'll get mostly random results. - Put an oscilloscope on the CE# line and check if it ever goes to high (3.3V) again after a flashrom run. Regards, Carl-Daniel

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Stefan Tauner 14 Aug '14

14 Aug '14

On Wed, 13 Aug 2014 16:24:43 -0300 Ricardo Menzer <ricardomenzer(a)gmail.com> wrote: > I have also found that if I probe the chip three times, it will work > only once. I mean, if I probe for the chip and it is found, the next > two probes will fail. The third will work, and the next two will fail > again, and so on. > I'm attaching the logs for three consecutive probes and also the > output of lspci -vvxxxnn. Hi, the logs look really weird. Is it possible that the boot* SPI bus is shared with something else? The block diagram in the datasheet does not look very detailed. *IIRC that SoC has more than one SPI master. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Chips requiring 12 volts on VPP for erase and write
by Daniele Forsi 14 Aug '14

14 Aug '14

Hello, I have an Intel P28F001 flash memory which flashrom knows as INTEL_28F001T and lists with .tested = TEST_OK_PR I can confirm that reading works with -p internal but erasing and writing don't work because according to its datasheet it needs 12 volts on VPP (min 11.4 max 12.6) should this fact about 12V VPP recorded somewhere? the same for the B variant (which I haven't got) -- Daniele Forsi

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Ricardo Menzer 13 Aug '14

13 Aug '14

I have also found that if I probe the chip three times, it will work only once. I mean, if I probe for the chip and it is found, the next two probes will fail. The third will work, and the next two will fail again, and so on. I'm attaching the logs for three consecutive probes and also the output of lspci -vvxxxnn. Ricardo Menzer ricardomenzer(a)gmail.com (32)8865-8805 2014-08-13 12:15 GMT-03:00 Ricardo Menzer <ricardomenzer(a)gmail.com>: > Hi guys! > I'm working with this COM Express module from Adlink > (http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1001&seq=&id=&sid…) > and sometimes it doesn't recognize it's flash chip. > The following log happened after a failed probing. I then let the > board resting some time and tried to program again, with the results > bellow. > > This is a quite problematic module. Frequently it fails to probe the > flash chip. I have to reboot the system so it can see it again. It > also seems to corrupt the module flash even if I select to write to > the baseboard flash. I don't know if it's a flashrom issue or a > bios/hardware issue. > > I can safely reboot the system because we have a second flash on the baseboard. > > Right now I am using the module's flash to play with coreboot and i'm > maintaining a copy of the original BIOS on the baseboard. Changing the > role of both chips doesn't seem to change much, except for the > corruption issue (didn't made much tests yet, though). > > I have a Kontron module that I use in this same base board and it > works pretty well. > > > 14:55:12 root ~ # flashrom-0.9.7/flashrom -p internal -w > /media/sda1/coreboot.rom > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > sh: dmidecode: command not found > dmidecode execution unsuccessful - continuing without DMI info > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. > Please supply the board vendor and model name with the -p > internal:mainboard=<vendor>:<model> option. > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. > Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address > 0xffe00000. > Reading old flash chip contents... done. > Erasing and writing flash chip... timeout, ICH7_REG_SPIS=0x0001 > spi_block_erase_20 failed during command execution at address 0x0 > Reading current flash chip contents... Error: SCIP never cleared! > Can't read anymore! Aborting. > FAILED! > Uh oh. Erase/write failed. Checking if anything changed. > Error: SCIP never cleared! > Your flash chip is in an unknown state. > Get help on IRC at chat.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! > ------------------------------------------------------------------------------- > DO NOT REBOOT OR POWEROFF! > 14:56:28 root ~ # flashrom-0.9.7/flashrom -p internal -w > /media/sda1/coreboot.rom > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > sh: dmidecode: command not found > dmidecode execution unsuccessful - continuing without DMI info > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. > Please supply the board vendor and model name with the -p > internal:mainboard=<vendor>:<model> option. > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > ^C > 14:58:09 root ~ # > > > Ricardo Menzer > ricardomenzer(a)gmail.com > (32)8865-8805

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FAILED: Adlink NanoX-TC
by Ricardo Menzer 13 Aug '14

13 Aug '14

Hi guys! I'm working with this COM Express module from Adlink (http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1001&seq=&id=&sid…) and sometimes it doesn't recognize it's flash chip. The following log happened after a failed probing. I then let the board resting some time and tried to program again, with the results bellow. This is a quite problematic module. Frequently it fails to probe the flash chip. I have to reboot the system so it can see it again. It also seems to corrupt the module flash even if I select to write to the baseboard flash. I don't know if it's a flashrom issue or a bios/hardware issue. I can safely reboot the system because we have a second flash on the baseboard. Right now I am using the module's flash to play with coreboot and i'm maintaining a copy of the original BIOS on the baseboard. Changing the role of both chips doesn't seem to change much, except for the corruption issue (didn't made much tests yet, though). I have a Kontron module that I use in this same base board and it works pretty well. 14:55:12 root ~ # flashrom-0.9.7/flashrom -p internal -w /media/sda1/coreboot.rom flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. sh: dmidecode: command not found dmidecode execution unsuccessful - continuing without DMI info Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. Please supply the board vendor and model name with the -p internal:mainboard=<vendor>:<model> option. Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address 0xffe00000. Reading old flash chip contents... done. Erasing and writing flash chip... timeout, ICH7_REG_SPIS=0x0001 spi_block_erase_20 failed during command execution at address 0x0 Reading current flash chip contents... Error: SCIP never cleared! Can't read anymore! Aborting. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Error: SCIP never cleared! Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! 14:56:28 root ~ # flashrom-0.9.7/flashrom -p internal -w /media/sda1/coreboot.rom flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. sh: dmidecode: command not found dmidecode execution unsuccessful - continuing without DMI info Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. Please supply the board vendor and model name with the -p internal:mainboard=<vendor>:<model> option. Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! ^C 14:58:09 root ~ # Ricardo Menzer ricardomenzer(a)gmail.com (32)8865-8805

1 0

Re: [flashrom] Avoton patches for flashrom
by TR Reardon 13 Aug '14

13 Aug '14

One other additional thought regarding partial read/write: the current logic all will fail to erase&write all-zero newcontent. Instead, if the reader bails (read_all_first == 0), the copy_old_content() logic should still read old included regions. In other words, it should do the opposite of what it currently does. +Reardon On Tue, Aug 12, 2014 at 8:53 PM, TR Reardon <thomas_reardon(a)hotmail.com> wrote: > Ok, sorry for my misunderstanding. But even with that change, > copy_old_content() still gets called to copy the old non-readable > regions. Shouldn't copy_old_content() just set oldcontent and > newcontent to all-ones for excluded regions? > > The unselected regions are not automatically skipped by the "do I need > to erase and then update this block?" comparison logic in > need_erase(), correct? At least, when I run it, the excluded regions > are erased (rather than skipped), but then not written. > > Anyway, I made one minor adjustment to your layout patches for partial > read, else segfault: > > --- > diff --git a/flashrom.c b/flashrom.c > index 27d1736..e3639ae 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1286,10 +1286,10 @@ int write_image_to_file(const unsigned char > *buf, unsigned long size, const char > l = get_next_included_romentry(0); > > while (l != NULL) { > - const char* name = (l->file[0] == '\0') ? l->name : l->file; > + const char* name = (l->file == NULL || l->file[0] == > '\0') ? l->name : l->file; > unsigned int len = l->end - l->start + 1; > msg_gdbg2("Writing \"%s\" to \"%s\" 0x%08x - 0x%08x (%uB)... ", > - l->name, l->file, l->start, l->end, len); > + l->name, name, l->start, l->end, len); > if (write_buf_to_file(buf + l->start, len, name) != 0) { > msg_gdbg2("failed.\n"); > return 1; > +Reardon > > > On Tue, Aug 12, 2014 at 4:33 PM, Stefan Tauner > <stefan.tauner(a)alumni.tuwien.ac.at> wrote: >> On Mon, 11 Aug 2014 19:14:53 -0400 >> TR Reardon <thomas_reardon(a)hotmail.com> wrote: >> >>> I'd like to start experimenting with partial-write support, now that >>> partial-read works well for me. But as of now doit() does a full read >>> before the write, which of course fails. Any updates that I could test? >>> Any useful log I can provide regarding successes? >>> >>> Note, I now have a buspirate so I can do full writes to recover, as needed >>> (this works successfully now, if slowly) >> >> As I wrote in my previous mail, (after applying the layout patches) you >> can disable the full read in doit() by setting read_all_first to 0. >> There are no further changes yet, because it does not make much sense >> until the proposed ones are merged... >> >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner >>

2 1

Re: [flashrom] flashrom Rangeley with WINDBOND25Q64
by Stefan Tauner 13 Aug '14

13 Aug '14

On Tue, 12 Aug 2014 15:54:20 -0600 Rich Futyma <rich.futyma(a)sanmina.com> wrote: > In addition to what Stefan described about ME descriptors, there is also > BIOS CNTL register, that if BIOS > enables it, you will not be able to write to flash using flashrom. Hello Rich, the above is true, but not relevant in this case, since the locking is disabled and writing enabled (according to the flashrom log). > CONFIDENTIALITY > This e-mail message and any attachments thereto, is intended only for use by the addressee(s) named herein and may contain legally privileged and/or confidential information. If you are not the intended recipient of this e-mail message, you are hereby notified that any dissemination, distribution or copying of this e-mail message, and any attachments thereto, is strictly prohibited. If you have received this e-mail message in error, please immediately notify the sender and permanently delete the original and any copies of this email and any prints thereof. > ABSENT AN EXPRESS STATEMENT TO THE CONTRARY HEREINABOVE, THIS E-MAIL IS NOT INTENDED AS A SUBSTITUTE FOR A WRITING. Notwithstanding the Uniform Electronic Transactions Act or the applicability of any other law of similar substance and effect, absent an express statement to the contrary hereinabove, this e-mail message its contents, and any attachments hereto are not intended to represent an offer or acceptance to enter into a contract and are not otherwise intended to bind the sender, Sanmina Corporation (or any of its subsidiaries), or any other person or entity. > You will be ridiculed sooner or later for using such a signature on public mailing lists ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Avoton patches for flashrom
by TR Reardon 13 Aug '14

13 Aug '14

Attempted write failed. Log attached. Haven't looked at further, but seems like partial reads work, but partial writes fail, due to early full-read before attempted partial-write. I use the term "partial" to mean a single region in the layout file. +Reardon

2 4

Re: [flashrom] [PATCH 1/3] Refine Flash Component descriptor handling.
by Marc Jones 13 Aug '14

13 Aug '14

On Fri, Aug 1, 2014 at 6:39 PM, Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Possible values as well as encodings have changed in newer chipsets as follows. > - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all > operations > - Since Cougar Point the chipsets support dual output fast reads (encoded > in bit 30). > - Flash component density encoding has changed from 3 to 4 bits with Lynx > Point, currently allowing for up to 64 MB chips. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > ich_descriptors.c | 182 +++++++++++++++++------ > ich_descriptors.h | 39 ++++- > ichspi.c | 24 ++- > util/ich_descriptors_tool/ich_descriptors_tool.c | 4 + > 4 files changed, 193 insertions(+), 56 deletions(-) > > diff --git a/ich_descriptors.c b/ich_descriptors.c > index 528717b..3977a4b 100644 > --- a/ich_descriptors.c > +++ b/ich_descriptors.c > @@ -64,7 +64,7 @@ void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) > void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) > { > prettyprint_ich_descriptor_content(&desc->content); > - prettyprint_ich_descriptor_component(desc); > + prettyprint_ich_descriptor_component(cs, desc); > prettyprint_ich_descriptor_region(desc); > prettyprint_ich_descriptor_master(&desc->master); > #ifdef ICH_DESCRIPTORS_FROM_DUMP > @@ -98,28 +98,97 @@ void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) > msg_pdbg2("\n"); > } > > -void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) > +static const char *pprint_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx) > +{ > + if (idx > 1) { > + msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); > + return NULL; > + } > + > + if (desc->content.NC == 0 && idx > 0) > + return "unused"; > + > + static const char * const size_str[] = { > + "512 kB", /* 0000 */ > + "1 MB", /* 0001 */ > + "2 MB", /* 0010 */ > + "4 MB", /* 0011 */ > + "8 MB", /* 0100 */ > + "16 MB", /* 0101 */ /* Maximum up to Lynx Point (excl.) */ > + "32 MB", /* 0110 */ > + "64 MB", /* 0111 */ > + }; > + > + switch (cs) { > + case CHIPSET_ICH8: > + case CHIPSET_ICH9: > + case CHIPSET_ICH10: > + case CHIPSET_5_SERIES_IBEX_PEAK: > + case CHIPSET_6_SERIES_COUGAR_POINT: > + case CHIPSET_7_SERIES_PANTHER_POINT: { > + uint8_t size_enc; > + if (idx == 0) { > + size_enc = desc->component.old.comp1_density; > + } else { > + size_enc = desc->component.old.comp2_density; > + } > + if (size_enc > 5) > + return "reserved"; > + return size_str[size_enc]; > + } > + case CHIPSET_8_SERIES_LYNX_POINT: > + case CHIPSET_8_SERIES_LYNX_POINT_LP: > + case CHIPSET_8_SERIES_WELLSBURG: { > + uint8_t size_enc; > + if (idx == 0) { > + size_enc = desc->component.new.comp1_density; > + } else { > + size_enc = desc->component.new.comp2_density; > + } > + if (size_enc > 7) > + return "reserved"; > + return size_str[size_enc]; > + } > + case CHIPSET_ICH_UNKNOWN: > + default: > + return "unknown"; > + } > +} > + > +static const char *pprint_freq(enum ich_chipset cs, uint8_t value) > { > static const char * const freq_str[8] = { > "20 MHz", /* 000 */ > "33 MHz", /* 001 */ > "reserved", /* 010 */ > "reserved", /* 011 */ > - "50 MHz", /* 100 */ > + "50 MHz", /* 100 */ /* New since Ibex Peak */ > "reserved", /* 101 */ > "reserved", /* 110 */ > "reserved" /* 111 */ > }; > - static const char * const size_str[8] = { > - "512 kB", /* 000 */ > - " 1 MB", /* 001 */ > - " 2 MB", /* 010 */ > - " 4 MB", /* 011 */ > - " 8 MB", /* 100 */ > - " 16 MB", /* 101 */ > - "reserved", /* 110 */ > - "reserved", /* 111 */ > - }; > + > + switch (cs) { > + case CHIPSET_ICH8: > + case CHIPSET_ICH9: > + case CHIPSET_ICH10: > + if (value > 1) > + return "reserved"; > + case CHIPSET_5_SERIES_IBEX_PEAK: > + case CHIPSET_6_SERIES_COUGAR_POINT: > + case CHIPSET_7_SERIES_PANTHER_POINT: > + case CHIPSET_8_SERIES_LYNX_POINT: > + case CHIPSET_8_SERIES_LYNX_POINT_LP: > + case CHIPSET_8_SERIES_WELLSBURG: > + return freq_str[value]; > + case CHIPSET_ICH_UNKNOWN: > + default: > + return "unknown"; > + } > +} > + > +void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc) > +{ > > msg_pdbg2("=== Component Section ===\n"); > msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); > @@ -127,24 +196,21 @@ void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) > msg_pdbg2("\n"); > > msg_pdbg2("--- Details ---\n"); > - msg_pdbg2("Component 1 density: %s\n", > - size_str[desc->component.comp1_density]); > + msg_pdbg2("Component 1 density: %s\n", pprint_density(cs, desc, 0)); > if (desc->content.NC) > - msg_pdbg2("Component 2 density: %s\n", > - size_str[desc->component.comp2_density]); > + msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1)); > else > msg_pdbg2("Component 2 is not used.\n"); > - msg_pdbg2("Read Clock Frequency: %s\n", > - freq_str[desc->component.freq_read]); > - msg_pdbg2("Read ID and Status Clock Freq.: %s\n", > - freq_str[desc->component.freq_read_id]); > - msg_pdbg2("Write and Erase Clock Freq.: %s\n", > - freq_str[desc->component.freq_write]); > - msg_pdbg2("Fast Read is %ssupported.\n", > - desc->component.fastread ? "" : "not "); > - if (desc->component.fastread) > + msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.common.freq_read)); > + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_read_id)); > + msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_write)); > + msg_pdbg2("Fast Read is %ssupported.\n", desc->component.common.fastread ? "" : "not "); > + if (desc->component.common.fastread) > msg_pdbg2("Fast Read Clock Frequency: %s\n", > - freq_str[desc->component.freq_fastread]); > + pprint_freq(cs, desc->component.common.freq_fastread)); > + if (cs > CHIPSET_6_SERIES_COUGAR_POINT) > + msg_pdbg2("Dual Output Fast Read Support: %sabled\n", > + desc->component.new.dual_output ? "dis" : "en"); > if (desc->component.FLILL == 0) > msg_pdbg2("No forbidden opcodes.\n"); > else { > @@ -273,7 +339,7 @@ static void prettyprint_ich_descriptor_straps_56_pciecs(uint8_t conf, uint8_t of > msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1); > > off *= 4; > - switch(conf){ > + switch (conf){ > case 0: > msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off); > break; > @@ -723,29 +789,57 @@ int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struc > #else /* ICH_DESCRIPTORS_FROM_DUMP */ > > /** Returns the integer representation of the component density with index > -idx in bytes or 0 if a correct size can not be determined. */ > -int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx) > +\em idx in bytes or -1 if the correct size can not be determined. */ > +int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx) > { > + if (idx > 1) { > + msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); > + return -1; > + } > + > + if (desc->content.NC == 0 && idx > 0) > + return 0; > + > uint8_t size_enc; > - > - switch(idx) { > - case 0: > - size_enc = desc->component.comp1_density; > + uint8_t size_max; > + > + switch (cs) { > + case CHIPSET_ICH8: > + case CHIPSET_ICH9: > + case CHIPSET_ICH10: > + case CHIPSET_5_SERIES_IBEX_PEAK: > + case CHIPSET_6_SERIES_COUGAR_POINT: > + case CHIPSET_7_SERIES_PANTHER_POINT: > + if (idx == 0) { > + size_enc = desc->component.old.comp1_density; > + } else { > + size_enc = desc->component.old.comp2_density; > + } > + size_max = 5; > break; > - case 1: > - if (desc->content.NC == 0) > - return 0; > - size_enc = desc->component.comp2_density; > + case CHIPSET_8_SERIES_LYNX_POINT: > + case CHIPSET_8_SERIES_LYNX_POINT_LP: > + case CHIPSET_8_SERIES_WELLSBURG: > + if (idx == 0) { > + size_enc = desc->component.new.comp1_density; > + } else { > + size_enc = desc->component.new.comp2_density; > + } > + size_max = 7; > break; > + case CHIPSET_ICH_UNKNOWN: > default: > - msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); > - return 0; > + msg_pwarn("Density encoding is unknown on this chipset.\n"); > + return -1; > } > - if (size_enc > 5) { > - msg_perr("Density of ICH SPI component with index %d is invalid. Encoded density is 0x%x.\n", > - idx, size_enc); > - return 0; > + > + if (size_enc > size_max) { > + msg_perr("Density of ICH SPI component with index %d is invalid." > + "Encoded density is 0x%x while maximum allowed is 0x%x.\n", > + idx, size_enc, size_max); > + return -1; > } > + > return (1 << (19 + size_enc)); > } > > diff --git a/ich_descriptors.h b/ich_descriptors.h > index 3a44740..b9213c8 100644 > --- a/ich_descriptors.h > +++ b/ich_descriptors.h > @@ -102,17 +102,44 @@ struct ich_desc_content { > struct ich_desc_component { > union { /* 0x00 */ > uint32_t FLCOMP; /* Flash Components Register */ > + /* FLCOMP encoding on various generations: > + * > + * Chipset/Generation max_speed dual_output density > + * [MHz] bits max. bits > + * ICH8: 33 N/A 5 0:2, 3:5 > + * ICH9: 33 N/A 5 0:2, 3:5 > + * ICH10: 33 N/A 5 0:2, 3:5 > + * Ibex Peak/5: 50 N/A 5 0:2, 3:5 > + * Cougar Point/6: 50 30 5 0:2, 3:5 > + * Patsburg: 50 30 5 0:2, 3:5 > + * Panther Point/7 50 30 5 0:2, 3:5 > + * Lynx Point/8: 50 30 7 0:3, 4:7 > + * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? > + */ > struct { > - uint32_t comp1_density :3, > - comp2_density :3, > - :11, > + uint32_t :17, > freq_read :3, > fastread :1, > freq_fastread :3, > freq_write :3, > freq_read_id :3, > :2; > - }; > + } common; > + struct { > + uint32_t comp1_density :3, > + comp2_density :3, > + :11, > + :13, > + :2; > + } old; > + struct { > + uint32_t comp1_density :4, /* new since Lynx Point/8 */ > + comp2_density :4, > + :9, > + :13, > + dual_output :1, /* new since Cougar Point/6 */ > + :1; > + } new; > }; > union { /* 0x04 */ > uint32_t FLILL; /* Flash Invalid Instructions Register */ > @@ -555,7 +582,7 @@ struct ich_descriptors { > void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc); > > void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); > -void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); > +void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc); > void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); > void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); > > @@ -568,7 +595,7 @@ int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struc > #else /* ICH_DESCRIPTORS_FROM_DUMP */ > > int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); > -int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx); > +int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx); > > #endif /* ICH_DESCRIPTORS_FROM_DUMP */ > #endif /* __ICH_DESCRIPTORS_H__ */ > diff --git a/ichspi.c b/ichspi.c > index 90bb0de..6744bef 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -1754,10 +1754,9 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) > > msg_pdbg("\n"); > if (desc_valid) { > - if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == > - ICH_RET_OK) > - prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, > - &desc); > + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) > + prettyprint_ich_descriptors(ich_gen, &desc); > + > /* If the descriptor is valid and indicates multiple > * flash devices we need to use hwseq to be able to > * access the second flash device. > @@ -1783,8 +1782,21 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) > "valid. Aborting.\n"); > return ERROR_FATAL; > } > - hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); > - hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); > + > + int tmpi = getFCBA_component_density(ich_generation, &desc, 0); > + if (tmpi < 0) { > + msg_perr("Could not determine density of flash component %d.\n", 0); > + return ERROR_FATAL; > + } > + hwseq_data.size_comp0 = tmpi; > + > + tmpi = getFCBA_component_density(ich_generation, &desc, 1); > + if (tmpi < 0) { > + msg_perr("Could not determine density of flash component %d.\n", 1); > + return ERROR_FATAL; > + } > + hwseq_data.size_comp1 = tmpi; > + > register_opaque_master(&opaque_master_ich_hwseq); > } else { > register_spi_master(&spi_master_ich9); > diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c > index 00ad1f3..4c1f05c 100644 > --- a/util/ich_descriptors_tool/ich_descriptors_tool.c > +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c > @@ -121,6 +121,7 @@ static void usage(char *argv[], char *error) > "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" > "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" > "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" > +"\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" > "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" > "the GbE blob that is required to initialize the GbE are also dumped to files.\n", > argv[0], argv[0]); > @@ -198,6 +199,9 @@ int main(int argc, char *argv[]) > else if ((strcmp(csn, "7") == 0) || > (strcmp(csn, "panther") == 0)) > cs = CHIPSET_7_SERIES_PANTHER_POINT; > + else if ((strcmp(csn, "8") == 0) || > + (strcmp(csn, "lynx") == 0)) > + cs = CHIPSET_8_SERIES_LYNX_POINT; > } > > ret = read_ich_descriptors_from_dump(buf, len, &desc); > -- > Kind regards, Stefan Tauner > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom I tested this branch on CC2: https://github.com/stefanct/flashrom/tree/intel See attached logs. Flashrom views both chips as a single flash space. What is the correct method for only updating a single descriptor area? Note that the descriptor allows r/w everything. I have not tried locking down regions. LGTM Acked-By:Tested-by: Marc Jones <marcj303(a)gmail.com> -- http://se-eng.com

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flashrom Rangeley with WINDBOND25Q64
by wenw＠adiengineering.com 12 Aug '14

12 Aug '14

Hello, I am testing flashrom on a Rangeley system using coreboot. The flash chip is W25Q64.V. I am using Stefan's refactored support for Baytrail/Rangeley: https://github.com/stefanct/flashrom/tree/intel. The read operation failed (log attached). Any suggestions to debug it would be appreciated! Thanks, Wen PS: Stefan - I finally got subscribed to the mailing list I think. My system was treating flashrom.org as spam initially. Thanks for responding my earlier email. -----Original Message----- From: "Stefan Tauner" <stefan.tauner(a)alumni.tuwien.ac.at> Sent: Monday, August 11, 2014 6:22pm To: "Wen Wang" <wen.wang(a)adiengineering.com> Subject: Re: flashrom Rangeley/Baytrail On Mon, 11 Aug 2014 12:20:15 -0400 "Wen Wang" <wen.wang(a)adiengineering.com> wrote: > Hello Stefan, > > I am trying to test the flashrom patch for Rangeley and Baytrail. I read in > your recent blog that you made some updates on top of Martin's patch. I am > very interested in trying your changes. Is it enough if I pull your branch > https://github.com/stefanct/flashrom/tree/intel? I have a Bayley Bay CRB and > a mohonpeak equivalent system to try. Hello, using that branch is fine, yes. Good luck, hopefully you won't need it :) > PS: I was trying to get onto the flashrom mailing list, but for some reason > I never got through. So I have to send an email to you directly. Maybe your server was not accepting mails from the flashrom host and you never got subscribed therefore (the flashrom.org domain had problems in the last weeks for some people which led to some servers not accepting mails from the list). Anyway, you can always send mails to the mailing list without being subscribed, we just have to moderate them manually. Please do so with any logs you create, and optionally you may wanna retry to subscribe... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

4 3

CHIPSET: PC Engines ALIX 2c3
by venture37 12 Aug '14

12 Aug '14

http://pcengines.ch/alix2c3.htm 00:01.0 Host bridge: Advanced Micro Devices, Inc. [AMD] CS5536 [Geode companion] Host Bridge (rev 31) Subsystem: Advanced Micro Devices, Inc. [AMD] CS5536 [Geode companion] Host Bridge Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Region 0: I/O ports at ac1c 00:01.2 Entertainment encryption device: Advanced Micro Devices, Inc. [AMD] Geode LX AES Security Block Subsystem: Advanced Micro Devices, Inc. [AMD] Geode LX AES Security Block Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 11 Region 0: Memory at fe010000 (32-bit, non-prefetchable) 00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) Subsystem: VIA Technologies, Inc. Device 0106 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (750ns min, 2000ns max), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at 1000 Region 1: Memory at fe019000 (32-bit, non-prefetchable) Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- 00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) Subsystem: VIA Technologies, Inc. Device 0106 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (750ns min, 2000ns max), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at 1400 Region 1: Memory at fe019100 (32-bit, non-prefetchable) Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- 00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) Subsystem: VIA Technologies, Inc. Device 0106 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (750ns min, 2000ns max), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 9 Region 0: I/O ports at 1800 Region 1: Memory at fe019200 (32-bit, non-prefetchable) Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- 00:0f.0 ISA bridge: Advanced Micro Devices, Inc. [AMD] CS5536 [Geode companion] ISA (rev 03) Subsystem: Advanced Micro Devices, Inc. [AMD] CS5536 [Geode companion] ISA Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Region 0: I/O ports at 24b0 Region 1: I/O ports at 1c00 Region 2: I/O ports at 2400 Region 3: I/O ports at 2480 Region 4: I/O ports at 2000 Region 5: I/O ports at 2440 00:0f.2 IDE interface: Advanced Micro Devices, Inc. [AMD] CS5536 [Geode companion] IDE (rev 01) (prog-if 80 [Master]) Subsystem: Advanced Micro Devices, Inc. [AMD] CS5536 [Geode companion] IDE Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 248 Region 4: I/O ports at 24a0 00:0f.4 USB controller: Advanced Micro Devices, Inc. [AMD] CS5536 [Geode companion] OHC (rev 02) (prog-if 10 [OHCI]) Subsystem: Advanced Micro Devices, Inc. [AMD] CS5536 [Geode companion] OHC Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin D routed to IRQ 9 Region 0: Memory at fe016000 (32-bit, non-prefetchable) Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 00:0f.5 USB controller: Advanced Micro Devices, Inc. [AMD] CS5536 [Geode companion] EHC (rev 02) (prog-if 20 [EHCI]) Subsystem: Advanced Micro Devices, Inc. [AMD] CS5536 [Geode companion] EHC Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin D routed to IRQ 9 Region 0: Memory at fe017000 (32-bit, non-prefetchable) Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-

1 0

Re: [flashrom] [PATCH] Fix probe_jedec() with continuation bytes, add EN29LV640T and get rid of probe_en29lv640b().
by Stefan Tauner 11 Aug '14

11 Aug '14

On Mon, 11 Aug 2014 00:12:56 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > We forgot to shift the addresses for continuation bytes in r1840. > Also, probe_en29lv640b() can easily be replaced with refined probe_jedec(). > Furthermore, add EN29LV640T which is the top boot sector-variant of > EN29LV640B. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > > Rudolf, if you still have access to the bifferboard, I'd very welcome > testing this patch on it. This would verify the change we did in r1840 > (+ its fix in this patch) + the refactoring as well. > > I might look into the write function later too, but currently probing > functions are my main focus. Actually I don't see anything unusual in the datasheet regarding writing either, where does it state that the chip has to be programmed in 16b words even if BYTE# is low?. I am not 100% if jedec_probe needs a refinement for shifted access too, but we should be able to get this to work in any case without an extra function, Carl-Daniel, please advice. :) PS: I have removed probe_en29lv640b() locally which I forgot on the posted patch. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[PATCH] Add en29lv640b
by Rudolf Marek 11 Aug '14

11 Aug '14

Hi Following patch adds the en29lv640b which needs special command sequences in 8 bit mode. Also, 8 bit programming needs actually 16bit double byte program. The chip is found on bifferboard. Please check the patch and let me know. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks Rudolf

4 6

Re: [flashrom] [PATCH 1/3] Refactor some CLI-relevant parts.
by Stefan Tauner 09 Aug '14

09 Aug '14

On Fri, 8 Aug 2014 16:25:07 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Begin to move functions that clearly belong to the (command line) > user interface out of flashrom's core files like flashrom.c. > > - Refine messages within check_chip_supported() and move it to newly > created cli_common.c. > - Move flashbuses_to_text() to cli_common.c as well. > - Move global verbosity variables to cli_output.c. > This was Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> after renaming check_chip_supported() to print_chip_support_status() and committed in r1841. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[commit] r1841 - trunk
by repository service 09 Aug '14

09 Aug '14

Author: stefanct Date: Sat Aug 9 01:52:33 2014 New Revision: 1841 URL: http://flashrom.org/trac/flashrom/changeset/1841 Log: Refactor some CLI-relevant parts. Begin to move functions that clearly belong to the (command line) user interface out of flashrom's core files like flashrom.c. - Refine messages within check_chip_supported(), rename it to print_chip_support_status() and move it to newly created cli_common.c. - Move flashbuses_to_text() to cli_common.c as well. - Move global verbosity variables to cli_output.c. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/cli_common.c (contents, props changed) Modified: trunk/Makefile trunk/cli_classic.c trunk/cli_output.c trunk/flash.h trunk/flashrom.c trunk/print.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Aug 8 10:33:01 2014 (r1840) +++ trunk/Makefile Sat Aug 9 01:52:33 2014 (r1841) @@ -363,7 +363,7 @@ ############################################################################### # Frontend related stuff. -CLI_OBJS = cli_classic.o cli_output.o print.o +CLI_OBJS = cli_classic.o cli_output.o cli_common.o print.o # Set the flashrom version string from the highest revision number of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Fri Aug 8 10:33:01 2014 (r1840) +++ trunk/cli_classic.c Sat Aug 9 01:52:33 2014 (r1841) @@ -499,7 +499,7 @@ fill_flash = &flashes[0]; - check_chip_supported(fill_flash->chip); + print_chip_support_status(fill_flash->chip); size = fill_flash->chip->total_size * 1024; if (check_max_decode(fill_flash->mst->buses_supported & fill_flash->chip->bustype, size) && (!force)) { Added: trunk/cli_common.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/cli_common.c Sat Aug 9 01:52:33 2014 (r1841) @@ -0,0 +1,117 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2011-2014 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include "flash.h" + +/* + * Return a string corresponding to the bustype parameter. + * Memory is obtained with malloc() and must be freed with free() by the caller. + */ +char *flashbuses_to_text(enum chipbustype bustype) +{ + char *ret = calloc(1, 1); + /* + * FIXME: Once all chipsets and flash chips have been updated, NONSPI + * will cease to exist and should be eliminated here as well. + */ + if (bustype == BUS_NONSPI) { + ret = strcat_realloc(ret, "Non-SPI, "); + } else { + if (bustype & BUS_PARALLEL) + ret = strcat_realloc(ret, "Parallel, "); + if (bustype & BUS_LPC) + ret = strcat_realloc(ret, "LPC, "); + if (bustype & BUS_FWH) + ret = strcat_realloc(ret, "FWH, "); + if (bustype & BUS_SPI) + ret = strcat_realloc(ret, "SPI, "); + if (bustype & BUS_PROG) + ret = strcat_realloc(ret, "Programmer-specific, "); + if (bustype == BUS_NONE) + ret = strcat_realloc(ret, "None, "); + } + /* Kill last comma. */ + ret[strlen(ret) - 2] = '\0'; + ret = realloc(ret, strlen(ret) + 1); + return ret; +} + + +void print_chip_support_status(const struct flashchip *chip) +{ + if (chip->feature_bits & FEATURE_OTP) { + msg_cdbg("This chip may contain one-time programmable memory. flashrom cannot read\n" + "and may never be able to write it, hence it may not be able to completely\n" + "clone the contents of this chip (see man page for details).\n"); + } + + if ((chip->tested.erase == NA) && (chip->tested.write == NA)) { + msg_cdbg("This chip's main memory can not be erased/written by design.\n"); + } + + if ((chip->tested.probe == BAD) || (chip->tested.probe == NT) || + (chip->tested.read == BAD) || (chip->tested.read == NT) || + (chip->tested.erase == BAD) || (chip->tested.erase == NT) || + (chip->tested.write == BAD) || (chip->tested.write == NT)){ + msg_cinfo("===\n"); + if ((chip->tested.probe == BAD) || + (chip->tested.read == BAD) || + (chip->tested.erase == BAD) || + (chip->tested.write == BAD)) { + msg_cinfo("This flash part has status NOT WORKING for operations:"); + if (chip->tested.probe == BAD) + msg_cinfo(" PROBE"); + if (chip->tested.read == BAD) + msg_cinfo(" READ"); + if (chip->tested.erase == BAD) + msg_cinfo(" ERASE"); + if (chip->tested.write == BAD) + msg_cinfo(" WRITE"); + msg_cinfo("\n"); + } + if ((chip->tested.probe == NT) || + (chip->tested.read == NT) || + (chip->tested.erase == NT) || + (chip->tested.write == NT)) { + msg_cinfo("This flash part has status UNTESTED for operations:"); + if (chip->tested.probe == NT) + msg_cinfo(" PROBE"); + if (chip->tested.read == NT) + msg_cinfo(" READ"); + if (chip->tested.erase == NT) + msg_cinfo(" ERASE"); + if (chip->tested.write == NT) + msg_cinfo(" WRITE"); + msg_cinfo("\n"); + } + msg_cinfo("The test status of this chip may have been updated in the latest development\n" + "version of flashrom. If you are running the latest development version,\n" + "please email a report to flashrom(a)flashrom.org if any of the above operations\n" + "work correctly for you with this flash chip. Please include the flashrom log\n" + "file for all operations you tested (see the man page for details), and mention\n" + "which mainboard or programmer you tested in the subject line.\n" + "Thanks for your help!\n"); + } +} + Modified: trunk/cli_output.c ============================================================================== --- trunk/cli_output.c Fri Aug 8 10:33:01 2014 (r1840) +++ trunk/cli_output.c Sat Aug 9 01:52:33 2014 (r1841) @@ -25,6 +25,9 @@ #include <errno.h> #include "flash.h" +int verbose_screen = MSG_INFO; +int verbose_logfile = MSG_DEBUG2; + #ifndef STANDALONE static FILE *logfile = NULL; Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Fri Aug 8 10:33:01 2014 (r1840) +++ trunk/flash.h Sat Aug 9 01:52:33 2014 (r1841) @@ -238,7 +238,6 @@ void chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); /* print.c */ -char *flashbuses_to_text(enum chipbustype bustype); int print_supported(void); void print_supported_wiki(void); @@ -251,8 +250,6 @@ void tolower_string(char *str); /* flashrom.c */ -extern int verbose_screen; -extern int verbose_logfile; extern const char flashrom_version[]; extern const char *chip_to_probe; void map_flash_registers(struct flashctx *flash); @@ -285,7 +282,13 @@ */ #define ERROR_FLASHROM_LIMIT -201 +/* cli_common.c */ +char *flashbuses_to_text(enum chipbustype bustype); +void print_chip_support_status(const struct flashchip *chip); + /* cli_output.c */ +extern int verbose_screen; +extern int verbose_logfile; #ifndef STANDALONE int open_logfile(const char * const filename); int close_logfile(void); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Fri Aug 8 10:33:01 2014 (r1840) +++ trunk/flashrom.c Sat Aug 9 01:52:33 2014 (r1841) @@ -42,11 +42,8 @@ const char flashrom_version[] = FLASHROM_VERSION; const char *chip_to_probe = NULL; -int verbose_screen = MSG_INFO; -int verbose_logfile = MSG_DEBUG2; static enum programmer programmer = PROGRAMMER_INVALID; - static const char *programmer_param = NULL; /* @@ -1783,73 +1780,6 @@ return ret; } -void check_chip_supported(const struct flashchip *chip) -{ - if (chip->feature_bits & FEATURE_OTP) { - msg_cdbg("This chip may contain one-time programmable memory. " - "flashrom cannot read\nand may never be able to write " - "it, hence it may not be able to completely\n" - "clone the contents of this chip (see man page for " - "details).\n"); - } - - if ((chip->tested.erase == NA) && (chip->tested.write == NA)) { - msg_cdbg("This chip's main memory can not be erased/written by design.\n"); - } - - if ((chip->tested.probe == BAD) || (chip->tested.probe == NT) || - (chip->tested.read == BAD) || (chip->tested.read == NT) || - (chip->tested.erase == BAD) || (chip->tested.erase == NT) || - (chip->tested.write == BAD) || (chip->tested.write == NT)){ - msg_cinfo("===\n"); - if ((chip->tested.probe == BAD) || - (chip->tested.read == BAD) || - (chip->tested.erase == BAD) || - (chip->tested.write == BAD)) { - msg_cinfo("This flash part has status NOT WORKING for operations:"); - if (chip->tested.probe == BAD) - msg_cinfo(" PROBE"); - if (chip->tested.read == BAD) - msg_cinfo(" READ"); - if (chip->tested.erase == BAD) - msg_cinfo(" ERASE"); - if (chip->tested.write == BAD) - msg_cinfo(" WRITE"); - msg_cinfo("\n"); - } - if ((chip->tested.probe == NT) || - (chip->tested.read == NT) || - (chip->tested.erase == NT) || - (chip->tested.write == NT)) { - msg_cinfo("This flash part has status UNTESTED for operations:"); - if (chip->tested.probe == NT) - msg_cinfo(" PROBE"); - if (chip->tested.read == NT) - msg_cinfo(" READ"); - if (chip->tested.erase == NT) - msg_cinfo(" ERASE"); - if (chip->tested.write == NT) - msg_cinfo(" WRITE"); - msg_cinfo("\n"); - } - /* FIXME: This message is designed towards CLI users. */ - msg_cinfo("The test status of this chip may have been updated " - "in the latest development\n" - "version of flashrom. If you are running the latest " - "development version,\n" - "please email a report to flashrom(a)flashrom.org if " - "any of the above operations\n" - "work correctly for you with this flash part. Please " - "include the flashrom\n" - "output with the additional -V option for all " - "operations you tested (-V, -Vr,\n" - "-VE, -Vw), and mention which mainboard or " - "programmer you tested.\n" - "Please mention your board in the subject line. " - "Thanks for your help!\n"); - } -} - /* FIXME: This function signature needs to be improved once doit() has a better * function signature. */ Modified: trunk/print.c ============================================================================== --- trunk/print.c Fri Aug 8 10:33:01 2014 (r1840) +++ trunk/print.c Sat Aug 9 01:52:33 2014 (r1841) @@ -59,39 +59,6 @@ } } -/* - * Return a string corresponding to the bustype parameter. - * Memory is obtained with malloc() and must be freed with free() by the caller. - */ -char *flashbuses_to_text(enum chipbustype bustype) -{ - char *ret = calloc(1, 1); - /* - * FIXME: Once all chipsets and flash chips have been updated, NONSPI - * will cease to exist and should be eliminated here as well. - */ - if (bustype == BUS_NONSPI) { - ret = strcat_realloc(ret, "Non-SPI, "); - } else { - if (bustype & BUS_PARALLEL) - ret = strcat_realloc(ret, "Parallel, "); - if (bustype & BUS_LPC) - ret = strcat_realloc(ret, "LPC, "); - if (bustype & BUS_FWH) - ret = strcat_realloc(ret, "FWH, "); - if (bustype & BUS_SPI) - ret = strcat_realloc(ret, "SPI, "); - if (bustype & BUS_PROG) - ret = strcat_realloc(ret, "Programmer-specific, "); - if (bustype == BUS_NONE) - ret = strcat_realloc(ret, "None, "); - } - /* Kill last comma. */ - ret[strlen(ret) - 2] = '\0'; - ret = realloc(ret, strlen(ret) + 1); - return ret; -} - static int print_supported_chips(void) { const char *delim = "/"; Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Fri Aug 8 10:33:01 2014 (r1840) +++ trunk/programmer.h Sat Aug 9 01:52:33 2014 (r1841) @@ -513,7 +513,6 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -void check_chip_supported(const struct flashchip *chip); int check_max_decode(enum chipbustype buses, uint32_t size); char *extract_programmer_param(const char *param_name);

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Efi password lost iMac27
by mustapha.rafik 09 Aug '14

09 Aug '14

Hello, I have lost the password of my imac27 looking a way to reset it. I found a link to a tutorial using a bus pirate and a flashrom. I am not sure I can do it by myself. I am far from being a specialist of computing and electronics. Do you have explanations on how to do it? Is it simple for a beginner? Thank you in advance, Regards Envoyé depuis un mobile Samsung

1 0

Re: [flashrom] [PATCH 2/3] Refine handling chips that exceed maximum programmer sizes.
by Stefan Tauner 08 Aug '14

08 Aug '14

On Fri, 8 Aug 2014 16:57:23 +0200 Daniele Forsi <dforsi(a)gmail.com> wrote: > 2014-08-08 16:25 GMT+02:00 Stefan Tauner: > > > --- a/cli_classic.c > > +++ b/cli_classic.c > > @@ -91,7 +91,6 @@ static int check_filename(char *filename, char *type) > > > > int main(int argc, char *argv[]) > > { > > - unsigned long size; > > /* Probe for up to three flash chips. */ > > const struct flashchip *chip = NULL; > > struct flashctx flashes[6] = {{0}}; > > unrelated to this changeset, but the comment above should read "six > flash chips" now > Yes, I am aware of that but thanks for reporting! Let's hope the whole array is gone soon ;) I have added the comment change to my tested_stuff branch #22 already just in case... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] [PATCH 2/3] Refine handling chips that exceed maximum programmer sizes.
by Daniele Forsi 08 Aug '14

08 Aug '14

2014-08-08 16:25 GMT+02:00 Stefan Tauner: > --- a/cli_classic.c > +++ b/cli_classic.c > @@ -91,7 +91,6 @@ static int check_filename(char *filename, char *type) > > int main(int argc, char *argv[]) > { > - unsigned long size; > /* Probe for up to three flash chips. */ > const struct flashchip *chip = NULL; > struct flashctx flashes[6] = {{0}}; unrelated to this changeset, but the comment above should read "six flash chips" now -- Daniele Forsi

1 0

[PATCH 3/3] Refine physical address mapping of flash chips.
by Stefan Tauner 08 Aug '14

08 Aug '14

Previously we did map the physical memory corresponding to all chips, even for SPI chips where it is completely unnecessary because we do not use it in any SPI-capable programmer. Also, the mapping was never undone before the program exited. Mapping of additional flash registers was done within probing methods instead of centrally. Besides all of that, this patch also adds proper error handling for mapping-related operations. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- 82802ab.c | 2 -- flash.h | 1 - flashrom.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++---------------- jedec.c | 6 ----- 4 files changed, 63 insertions(+), 30 deletions(-) diff --git a/82802ab.c b/82802ab.c index 70c6af0..5d015ba 100644 --- a/82802ab.c +++ b/82802ab.c @@ -83,8 +83,6 @@ int probe_82802ab(struct flashctx *flash) if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id) return 0; - if (flash->chip->feature_bits & FEATURE_REGISTERMAP) - map_flash_registers(flash); return 1; } diff --git a/flash.h b/flash.h index 82a8b74..998696c 100644 --- a/flash.h +++ b/flash.h @@ -252,7 +252,6 @@ void tolower_string(char *str); /* flashrom.c */ extern const char flashrom_version[]; extern const char *chip_to_probe; -void map_flash_registers(struct flashctx *flash); int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int erase_flash(struct flashctx *flash); int probe_flash(struct registered_master *mst, int startchip, struct flashctx *fill_flash, int force); diff --git a/flashrom.c b/flashrom.c index 0ff6b63..72bf157 100644 --- a/flashrom.c +++ b/flashrom.c @@ -528,12 +528,23 @@ void programmer_delay(unsigned int usecs) programmer_table[programmer].delay(usecs); } -void map_flash_registers(struct flashctx *flash) +static int map_flash_registers(struct flashctx *flash) { size_t size = flash->chip->total_size * 1024; /* Flash registers live 4 MByte below the flash. */ - /* FIXME: This is incorrect for nonstandard flashbase. */ - flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); + uintptr_t base = (flashbase != 0) ? flashbase : (0xffffffff - size + 1); + if (base < 0x400000) { + msg_perr("Base address is too low to map flash registers."); + return 1; + } + base -= 0x400000; + void *addr = programmer_map_flash_region("flash chip registers", base, size); + if (addr == ERROR_PTR) { + msg_perr("Could not map flash chip registers.\n"); + return 1; + } + flash->virtual_registers = (chipaddr)addr; + return 0; } int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, @@ -1052,12 +1063,49 @@ unsigned int count_max_decode_exceedings(struct flashctx *flash) return limitexceeded; } +void unmap_flash(struct flashctx *flash) +{ + if (flash->chip->bustype & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) { + if (flash->virtual_memory != 0) { + programmer_unmap_flash_region((void *)flash->virtual_memory, + flash->chip->total_size * 1024); + flash->virtual_memory = 0; + } + + if (flash->chip->feature_bits & FEATURE_REGISTERMAP && flash->virtual_registers != 0) { + programmer_unmap_flash_region((void *)flash->virtual_registers, + flash->chip->total_size * 1024); + flash->virtual_registers = 0; + } + } +} + +int map_flash(struct flashctx *flash) +{ + const unsigned long size = flash->chip->total_size; + if (flash->chip->bustype & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) { + uintptr_t base = flashbase ? flashbase : (0xffffffff - size + 1); + void *addr = programmer_map_flash_region("flash chip", base, size); + if (addr == ERROR_PTR) { + msg_perr("Could not map flash chip registers.\n"); + return 1; + } + flash->virtual_memory = (chipaddr)addr; + + if (flash->chip->feature_bits & FEATURE_REGISTERMAP) { + if (map_flash_registers(flash) != 0) { + unmap_flash(flash); + return 1; + } + } + } + + return 0; +} + int probe_flash(struct registered_master *mst, int startchip, struct flashctx *flash, int force) { const struct flashchip *chip; - unsigned long base = 0; - char location[64]; - uint32_t size; enum chipbustype buses_common; char *tmp; @@ -1082,9 +1130,8 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f memcpy(flash->chip, chip, sizeof(struct flashchip)); flash->mst = mst; - size = chip->total_size * 1024; - base = flashbase ? flashbase : (0xffffffff - size + 1); - flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); + if (map_flash(flash) != 0) + return -1; /* We handle a forced match like a real match, we just avoid probing. Note that probe_flash() * is only called with force=1 after normal probing failed. @@ -1133,8 +1180,7 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f break; /* Not the first flash chip detected on this bus, and it's just a generic match. Ignore it. */ notfound: - programmer_unmap_flash_region((void *)flash->virtual_memory, size); - flash->virtual_memory = (chipaddr)NULL; + unmap_flash(flash); free(flash->chip); flash->chip = NULL; } @@ -1142,16 +1188,9 @@ notfound: if (!flash->chip) return -1; -#if CONFIG_INTERNAL == 1 - if (programmer_table[programmer].map_flash_region == physmap) - snprintf(location, sizeof(location), "at physical address 0x%lx", base); - else -#endif - snprintf(location, sizeof(location), "on %s", programmer_table[programmer].name); - tmp = flashbuses_to_text(flash->chip->bustype); - msg_cinfo("%s %s flash chip \"%s\" (%d kB, %s) %s.\n", force ? "Assuming" : "Found", - flash->chip->vendor, flash->chip->name, flash->chip->total_size, tmp, location); + msg_cinfo("%s %s flash chip \"%s\" (%d kB, %s).\n", force ? "Assuming" : "Found", + flash->chip->vendor, flash->chip->name, flash->chip->total_size, tmp); free(tmp); /* Flash registers will not be mapped if the chip was forced. Lock info @@ -1872,7 +1911,8 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, flash->chip->unlock(flash); if (read_it) { - return read_flash_to_file(flash, filename); + ret = read_flash_to_file(flash, filename); + goto unmap; } oldcontents = malloc(size); @@ -1991,5 +2031,7 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, out: free(oldcontents); free(newcontents); +unmap: + unmap_flash(flash); return ret; } diff --git a/jedec.c b/jedec.c index 358b850..1345b89 100644 --- a/jedec.c +++ b/jedec.c @@ -166,9 +166,6 @@ int probe_jedec_29gl(struct flashctx *flash) if (man_id != chip->manufacture_id || dev_id != chip->model_id) return 0; - if (chip->feature_bits & FEATURE_REGISTERMAP) - map_flash_registers(flash); - return 1; } @@ -287,9 +284,6 @@ static int probe_jedec_common(struct flashctx *flash, unsigned int mask) if (largeid1 != chip->manufacture_id || largeid2 != chip->model_id) return 0; - if (chip->feature_bits & FEATURE_REGISTERMAP) - map_flash_registers(flash); - return 1; } -- Kind regards, Stefan Tauner

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[PATCH 2/3] Refine handling chips that exceed maximum programmer sizes.
by Stefan Tauner 08 Aug '14

08 Aug '14

- Change check_max_decode() to return the number of (common) busses where the flash chip exceeds the supported size of the programmer. - Refine its signature to use a flashctx pointer only. - Move CLI-related bits to cli_classic.c. - Rename check_max_decode() to count_max_decode_exceedings() to better reflect what it (now) really does. - Refine the messages printed by the caller to better integrate with the new setup, and simplify them. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- cli_classic.c | 16 ++++++++++++---- flashrom.c | 24 ++++++++---------------- programmer.h | 2 +- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/cli_classic.c b/cli_classic.c index 60b8b88..8034287 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -91,7 +91,6 @@ static int check_filename(char *filename, char *type) int main(int argc, char *argv[]) { - unsigned long size; /* Probe for up to three flash chips. */ const struct flashchip *chip = NULL; struct flashctx flashes[6] = {{0}}; @@ -501,9 +500,18 @@ int main(int argc, char *argv[]) check_chip_supported(fill_flash->chip); - size = fill_flash->chip->total_size * 1024; - if (check_max_decode(fill_flash->mst->buses_supported & fill_flash->chip->bustype, size) && (!force)) { - msg_cerr("Chip is too big for this programmer (-V gives details). Use --force to override.\n"); + unsigned int limitexceeded = count_max_decode_exceedings(fill_flash); + if (limitexceeded > 0 && !force) { + enum chipbustype commonbuses = fill_flash->mst->buses_supported & fill_flash->chip->bustype; + + /* Sometimes chip and programmer have more than one bus in common, + * and the limit is not exceeded on all buses. Tell the user. */ + if ((bitcount(commonbuses) > limitexceeded)) { + msg_pdbg("There is at least one interface available which could support the size of\n" + "the selected flash chip.\n"); + } + msg_cerr("This flash chip is too big for this programmer (--verbose/-V gives details).\n" + "Use --force/-f to override at your own risk.\n"); ret = 1; goto out_shutdown; } diff --git a/flashrom.c b/flashrom.c index eeed90b..0ff6b63 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1009,9 +1009,13 @@ int generate_testpattern(uint8_t *buf, uint32_t size, int variant) return 0; } -int check_max_decode(enum chipbustype buses, uint32_t size) +/* Returns the number of busses commonly supported by the current programmer and flash chip where the latter + * can not be completely accessed due to size/address limits of the programmer. */ +unsigned int count_max_decode_exceedings(struct flashctx *flash) { - int limitexceeded = 0; + unsigned int limitexceeded = 0; + uint32_t size = flash->chip->total_size * 1024; + enum chipbustype buses = flash->mst->buses_supported & flash->chip->bustype; if ((buses & BUS_PARALLEL) && (max_rom_decode.parallel < size)) { limitexceeded++; @@ -1045,17 +1049,7 @@ int check_max_decode(enum chipbustype buses, uint32_t size) "probe/read/erase/write may fail. ", size / 1024, max_rom_decode.spi / 1024, "SPI"); } - if (!limitexceeded) - return 0; - /* Sometimes chip and programmer have more than one bus in common, - * and the limit is not exceeded on all buses. Tell the user. - */ - if (bitcount(buses) > limitexceeded) - /* FIXME: This message is designed towards CLI users. */ - msg_pdbg("There is at least one common chip/programmer " - "interface which can support a chip of this size. " - "You can try --force at your own risk.\n"); - return 1; + return limitexceeded; } int probe_flash(struct registered_master *mst, int startchip, struct flashctx *flash, int force) @@ -1079,9 +1073,6 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f continue; } - size = chip->total_size * 1024; - check_max_decode(buses_common, size); - /* Start filling in the dynamic data. */ flash->chip = calloc(1, sizeof(struct flashchip)); if (!flash->chip) { @@ -1091,6 +1082,7 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f memcpy(flash->chip, chip, sizeof(struct flashchip)); flash->mst = mst; + size = chip->total_size * 1024; base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); diff --git a/programmer.h b/programmer.h index 62acfeb..7b0e77f 100644 --- a/programmer.h +++ b/programmer.h @@ -513,7 +513,7 @@ struct decode_sizes { extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -int check_max_decode(enum chipbustype buses, uint32_t size); +unsigned int count_max_decode_exceedings(struct flashctx *flash); char *extract_programmer_param(const char *param_name); /* spi.c */ -- Kind regards, Stefan Tauner

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[PATCH 1/3] Refactor some CLI-relevant parts.
by Stefan Tauner 08 Aug '14

08 Aug '14

Begin to move functions that clearly belong to the (command line) user interface out of flashrom's core files like flashrom.c. - Refine messages within check_chip_supported() and move it to newly created cli_common.c. - Move flashbuses_to_text() to cli_common.c as well. - Move global verbosity variables to cli_output.c. --- Other things that should be moved elsewhere because they do not embody core functionality but dictate command syntax and thereby become part of the UI: board_parse_parameter(), all code regarding extract_programmer_param (the parameters should be stored in a machine-readable form in struct flashctx instead), TBC Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Makefile | 2 +- cli_common.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ cli_output.c | 3 ++ flash.h | 9 +++-- flashrom.c | 70 ----------------------------------- print.c | 33 ----------------- programmer.h | 1 - 7 files changed, 127 insertions(+), 108 deletions(-) create mode 100644 cli_common.c diff --git a/Makefile b/Makefile index d0d6454..98230a5 100644 --- a/Makefile +++ b/Makefile @@ -363,7 +363,7 @@ LIB_OBJS = layout.o flashrom.o udelay.o programmer.o helpers.o ############################################################################### # Frontend related stuff. -CLI_OBJS = cli_classic.o cli_output.o print.o +CLI_OBJS = cli_classic.o cli_output.o cli_common.o print.o # Set the flashrom version string from the highest revision number of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" diff --git a/cli_common.c b/cli_common.c new file mode 100644 index 0000000..078c1f8 --- /dev/null +++ b/cli_common.c @@ -0,0 +1,117 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2011-2014 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include "flash.h" + +/* + * Return a string corresponding to the bustype parameter. + * Memory is obtained with malloc() and must be freed with free() by the caller. + */ +char *flashbuses_to_text(enum chipbustype bustype) +{ + char *ret = calloc(1, 1); + /* + * FIXME: Once all chipsets and flash chips have been updated, NONSPI + * will cease to exist and should be eliminated here as well. + */ + if (bustype == BUS_NONSPI) { + ret = strcat_realloc(ret, "Non-SPI, "); + } else { + if (bustype & BUS_PARALLEL) + ret = strcat_realloc(ret, "Parallel, "); + if (bustype & BUS_LPC) + ret = strcat_realloc(ret, "LPC, "); + if (bustype & BUS_FWH) + ret = strcat_realloc(ret, "FWH, "); + if (bustype & BUS_SPI) + ret = strcat_realloc(ret, "SPI, "); + if (bustype & BUS_PROG) + ret = strcat_realloc(ret, "Programmer-specific, "); + if (bustype == BUS_NONE) + ret = strcat_realloc(ret, "None, "); + } + /* Kill last comma. */ + ret[strlen(ret) - 2] = '\0'; + ret = realloc(ret, strlen(ret) + 1); + return ret; +} + + +void check_chip_supported(const struct flashchip *chip) +{ + if (chip->feature_bits & FEATURE_OTP) { + msg_cdbg("This chip may contain one-time programmable memory. flashrom cannot read\n" + "and may never be able to write it, hence it may not be able to completely\n" + "clone the contents of this chip (see man page for details).\n"); + } + + if ((chip->tested.erase == NA) && (chip->tested.write == NA)) { + msg_cdbg("This chip's main memory can not be erased/written by design.\n"); + } + + if ((chip->tested.probe == BAD) || (chip->tested.probe == NT) || + (chip->tested.read == BAD) || (chip->tested.read == NT) || + (chip->tested.erase == BAD) || (chip->tested.erase == NT) || + (chip->tested.write == BAD) || (chip->tested.write == NT)){ + msg_cinfo("===\n"); + if ((chip->tested.probe == BAD) || + (chip->tested.read == BAD) || + (chip->tested.erase == BAD) || + (chip->tested.write == BAD)) { + msg_cinfo("This flash part has status NOT WORKING for operations:"); + if (chip->tested.probe == BAD) + msg_cinfo(" PROBE"); + if (chip->tested.read == BAD) + msg_cinfo(" READ"); + if (chip->tested.erase == BAD) + msg_cinfo(" ERASE"); + if (chip->tested.write == BAD) + msg_cinfo(" WRITE"); + msg_cinfo("\n"); + } + if ((chip->tested.probe == NT) || + (chip->tested.read == NT) || + (chip->tested.erase == NT) || + (chip->tested.write == NT)) { + msg_cinfo("This flash part has status UNTESTED for operations:"); + if (chip->tested.probe == NT) + msg_cinfo(" PROBE"); + if (chip->tested.read == NT) + msg_cinfo(" READ"); + if (chip->tested.erase == NT) + msg_cinfo(" ERASE"); + if (chip->tested.write == NT) + msg_cinfo(" WRITE"); + msg_cinfo("\n"); + } + msg_cinfo("The test status of this chip may have been updated in the latest development\n" + "version of flashrom. If you are running the latest development version,\n" + "please email a report to flashrom(a)flashrom.org if any of the above operations\n" + "work correctly for you with this flash chip. Please include the flashrom log\n" + "file for all operations you tested (see the man page for details), and mention\n" + "which mainboard or programmer you tested in the subject line.\n" + "Thanks for your help!\n"); + } +} + diff --git a/cli_output.c b/cli_output.c index 5eff1c0..feafbd2 100644 --- a/cli_output.c +++ b/cli_output.c @@ -25,6 +25,9 @@ #include <errno.h> #include "flash.h" +int verbose_screen = MSG_INFO; +int verbose_logfile = MSG_DEBUG2; + #ifndef STANDALONE static FILE *logfile = NULL; diff --git a/flash.h b/flash.h index 8271da9..82a8b74 100644 --- a/flash.h +++ b/flash.h @@ -238,7 +238,6 @@ uint32_t chip_readl(const struct flashctx *flash, const chipaddr addr); void chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); /* print.c */ -char *flashbuses_to_text(enum chipbustype bustype); int print_supported(void); void print_supported_wiki(void); @@ -251,8 +250,6 @@ char *strcat_realloc(char *dest, const char *src); void tolower_string(char *str); /* flashrom.c */ -extern int verbose_screen; -extern int verbose_logfile; extern const char flashrom_version[]; extern const char *chip_to_probe; void map_flash_registers(struct flashctx *flash); @@ -285,7 +282,13 @@ int write_buf_to_file(const unsigned char *buf, unsigned long size, const char * */ #define ERROR_FLASHROM_LIMIT -201 +/* cli_common.c */ +char *flashbuses_to_text(enum chipbustype bustype); +void check_chip_supported(const struct flashchip *chip); + /* cli_output.c */ +extern int verbose_screen; +extern int verbose_logfile; #ifndef STANDALONE int open_logfile(const char * const filename); int close_logfile(void); diff --git a/flashrom.c b/flashrom.c index 3f29e6d..eeed90b 100644 --- a/flashrom.c +++ b/flashrom.c @@ -42,11 +42,8 @@ const char flashrom_version[] = FLASHROM_VERSION; const char *chip_to_probe = NULL; -int verbose_screen = MSG_INFO; -int verbose_logfile = MSG_DEBUG2; static enum programmer programmer = PROGRAMMER_INVALID; - static const char *programmer_param = NULL; /* @@ -1783,73 +1780,6 @@ int selfcheck(void) return ret; } -void check_chip_supported(const struct flashchip *chip) -{ - if (chip->feature_bits & FEATURE_OTP) { - msg_cdbg("This chip may contain one-time programmable memory. " - "flashrom cannot read\nand may never be able to write " - "it, hence it may not be able to completely\n" - "clone the contents of this chip (see man page for " - "details).\n"); - } - - if ((chip->tested.erase == NA) && (chip->tested.write == NA)) { - msg_cdbg("This chip's main memory can not be erased/written by design.\n"); - } - - if ((chip->tested.probe == BAD) || (chip->tested.probe == NT) || - (chip->tested.read == BAD) || (chip->tested.read == NT) || - (chip->tested.erase == BAD) || (chip->tested.erase == NT) || - (chip->tested.write == BAD) || (chip->tested.write == NT)){ - msg_cinfo("===\n"); - if ((chip->tested.probe == BAD) || - (chip->tested.read == BAD) || - (chip->tested.erase == BAD) || - (chip->tested.write == BAD)) { - msg_cinfo("This flash part has status NOT WORKING for operations:"); - if (chip->tested.probe == BAD) - msg_cinfo(" PROBE"); - if (chip->tested.read == BAD) - msg_cinfo(" READ"); - if (chip->tested.erase == BAD) - msg_cinfo(" ERASE"); - if (chip->tested.write == BAD) - msg_cinfo(" WRITE"); - msg_cinfo("\n"); - } - if ((chip->tested.probe == NT) || - (chip->tested.read == NT) || - (chip->tested.erase == NT) || - (chip->tested.write == NT)) { - msg_cinfo("This flash part has status UNTESTED for operations:"); - if (chip->tested.probe == NT) - msg_cinfo(" PROBE"); - if (chip->tested.read == NT) - msg_cinfo(" READ"); - if (chip->tested.erase == NT) - msg_cinfo(" ERASE"); - if (chip->tested.write == NT) - msg_cinfo(" WRITE"); - msg_cinfo("\n"); - } - /* FIXME: This message is designed towards CLI users. */ - msg_cinfo("The test status of this chip may have been updated " - "in the latest development\n" - "version of flashrom. If you are running the latest " - "development version,\n" - "please email a report to flashrom(a)flashrom.org if " - "any of the above operations\n" - "work correctly for you with this flash part. Please " - "include the flashrom\n" - "output with the additional -V option for all " - "operations you tested (-V, -Vr,\n" - "-VE, -Vw), and mention which mainboard or " - "programmer you tested.\n" - "Please mention your board in the subject line. " - "Thanks for your help!\n"); - } -} - /* FIXME: This function signature needs to be improved once doit() has a better * function signature. */ diff --git a/print.c b/print.c index b1faea7..243aa49 100644 --- a/print.c +++ b/print.c @@ -59,39 +59,6 @@ static const char *test_state_to_text(enum test_state test_state) } } -/* - * Return a string corresponding to the bustype parameter. - * Memory is obtained with malloc() and must be freed with free() by the caller. - */ -char *flashbuses_to_text(enum chipbustype bustype) -{ - char *ret = calloc(1, 1); - /* - * FIXME: Once all chipsets and flash chips have been updated, NONSPI - * will cease to exist and should be eliminated here as well. - */ - if (bustype == BUS_NONSPI) { - ret = strcat_realloc(ret, "Non-SPI, "); - } else { - if (bustype & BUS_PARALLEL) - ret = strcat_realloc(ret, "Parallel, "); - if (bustype & BUS_LPC) - ret = strcat_realloc(ret, "LPC, "); - if (bustype & BUS_FWH) - ret = strcat_realloc(ret, "FWH, "); - if (bustype & BUS_SPI) - ret = strcat_realloc(ret, "SPI, "); - if (bustype & BUS_PROG) - ret = strcat_realloc(ret, "Programmer-specific, "); - if (bustype == BUS_NONE) - ret = strcat_realloc(ret, "None, "); - } - /* Kill last comma. */ - ret[strlen(ret) - 2] = '\0'; - ret = realloc(ret, strlen(ret) + 1); - return ret; -} - static int print_supported_chips(void) { const char *delim = "/"; diff --git a/programmer.h b/programmer.h index 3ad553a..62acfeb 100644 --- a/programmer.h +++ b/programmer.h @@ -513,7 +513,6 @@ struct decode_sizes { extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -void check_chip_supported(const struct flashchip *chip); int check_max_decode(enum chipbustype buses, uint32_t size); char *extract_programmer_param(const char *param_name); -- Kind regards, Stefan Tauner

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[PATCH 0/3] Probing rewrite 2nd try - prefix
by Stefan Tauner 08 Aug '14

08 Aug '14

While creating a sane foundation to build the new probing upon the following patches were conceived. I'll rebase my probing patches on top of them hence they need to be reviewed before the refined probing patches to come. Especially the last one is rather important anyway because it fixes the problem of wrongly mapped flash memory ranges for SPI chips that provokes nasty warnings since a while ago. Stefan Tauner (3): Refactor some CLI-relevant parts. Refine handling chips that exceed maximum programmer sizes. Refine physical address mapping of flash chips. 82802ab.c | 2 - Makefile | 2 +- cli_classic.c | 16 ++++-- cli_common.c | 117 ++++++++++++++++++++++++++++++++++++++ cli_output.c | 3 + flash.h | 10 ++-- flashrom.c | 176 +++++++++++++++++++++++----------------------------------- jedec.c | 6 -- print.c | 33 ----------- programmer.h | 3 +- 10 files changed, 210 insertions(+), 158 deletions(-) create mode 100644 cli_common.c -- Kind regards, Stefan Tauner

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CHIPSET: ASRock N68-S
by tarqui＠aruba.it 08 Aug '14

08 Aug '14

# flashrom flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP61". Enabling flash write... This chipset is not really supported yet. Guesswork... Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. WARNING: unexpected second chipset match: "NVIDIA MCP61" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. # # # # lspci 00:00.0 RAM memory: NVIDIA Corporation MCP61 Host Bridge (rev a1) 00:01.0 ISA bridge: NVIDIA Corporation MCP61 LPC Bridge (rev a2) 00:01.1 SMBus: NVIDIA Corporation MCP61 SMBus (rev a2) 00:01.2 RAM memory: NVIDIA Corporation MCP61 Memory Controller (rev a2) 00:02.0 USB controller: NVIDIA Corporation MCP61 USB 1.1 Controller (rev a3) 00:02.1 USB controller: NVIDIA Corporation MCP61 USB 2.0 Controller (rev a3) 00:04.0 PCI bridge: NVIDIA Corporation MCP61 PCI bridge (rev a1) 00:05.0 Audio device: NVIDIA Corporation MCP61 High Definition Audio (rev a2) 00:06.0 IDE interface: NVIDIA Corporation MCP61 IDE (rev a2) 00:07.0 Bridge: NVIDIA Corporation MCP61 Ethernet (rev a2) 00:08.0 IDE interface: NVIDIA Corporation MCP61 SATA Controller (rev a2) 00:08.1 IDE interface: NVIDIA Corporation MCP61 SATA Controller (rev a2) 00:09.0 PCI bridge: NVIDIA Corporation MCP61 PCI Express bridge (rev a2) 00:0b.0 PCI bridge: NVIDIA Corporation MCP61 PCI Express bridge (rev a2) 00:0c.0 PCI bridge: NVIDIA Corporation MCP61 PCI Express bridge (rev a2) 00:0d.0 VGA compatible controller: NVIDIA Corporation C61 [GeForce 7025 / nForce 630a] (rev a2) 00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 01:0a.0 Ethernet controller: Qualcomm Atheros AR5212/AR5213 Wireless Network Adapter (rev 01) #

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ASRock N68-S: flashrom -V
by tarqui＠aruba.it 08 Aug '14

08 Aug '14

# flashrom flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP61". Enabling flash write... This chipset is not really supported yet. Guesswork... Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. WARNING: unexpected second chipset match: "NVIDIA MCP61" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. # # # # flashrom -V flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.2, little endian Command line (1 args): flashrom -V Calibrating delay loop... OS timer resolution is 1 usecs, 1392M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 995 us, 10000 myus = 10085 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "To Be Filled By O.E.M." DMI string system-product-name: "To Be Filled By O.E.M." DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: "ASRock" DMI string baseboard-product-name: "N68-S" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP61" with PCI ID 10de:03e1. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xfec80000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. WARNING: unexpected second chipset match: "NVIDIA MCP61" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. The following protocols are supported: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88 #

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Re: [flashrom] [PATCH] Unify non-shifted and shifted JEDEC access.
by Stefan Tauner 08 Aug '14

08 Aug '14

On Thu, 7 Aug 2014 23:49:57 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use > normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit) > for 8-bit mode. Some programmers can access them in 16-bit mode, but on > all flashrom-supported programmers so far, we access them in 8-bit mode. > This means we have to shift the addresses but apart from the addresses > we can share the code. > > This patch makes this possible by checking the chip's FEATURE_ADDR_SHIFTED > flag in common JEDEC functions and applying the right addresses respectively. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > > I have removed the obsolete code, changed the probe_timing field to 10 > plus a comment explaining it where relevant, applied the changes to a > few other chips that probably were not there before, and refined the > shift handling as discussed on IRC. Acked by Carl-Daniel and committed in r1840. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Flashed BIOS on M4N78 SE
by Dima Veselov 08 Aug '14

08 Aug '14

Hello! I have recently used flashrom on Asus M4N78SE motherboard. Flashrom advised me to send logs. Everything worked as expected. -- Sincerelly yours

2 3

[commit] r1840 - trunk
by repository service 08 Aug '14

08 Aug '14

Author: stefanct Date: Fri Aug 8 10:33:01 2014 New Revision: 1840 URL: http://flashrom.org/trac/flashrom/changeset/1840 Log: Unify non-shifted and shifted JEDEC access. Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit) for 8-bit mode. Some programmers can access them in 16-bit mode, but on all flashrom-supported programmers so far, we access them in 8-bit mode. This means we have to shift the addresses but apart from the addresses we can share the code. This patch makes this possible by checking the chip's FEATURE_ADDR_SHIFTED flag in common JEDEC functions and applying the right addresses respectively. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Deleted: trunk/m29f400bt.c Modified: trunk/82802ab.c trunk/Makefile trunk/chipdrivers.h trunk/en29lv640b.c trunk/flashchips.c trunk/jedec.c Modified: trunk/82802ab.c ============================================================================== --- trunk/82802ab.c Wed Aug 6 17:09:15 2014 (r1839) +++ trunk/82802ab.c Fri Aug 8 10:33:01 2014 (r1840) @@ -44,7 +44,7 @@ { chipaddr bios = flash->virtual_memory; uint8_t id1, id2, flashcontent1, flashcontent2; - int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) != 0; + int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0; /* Reset to get a clean state */ chip_writeb(flash, 0xFF, bios); Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed Aug 6 17:09:15 2014 (r1839) +++ trunk/Makefile Fri Aug 8 10:33:01 2014 (r1840) @@ -351,7 +351,7 @@ # Flash chip drivers and bus support infrastructure. CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ - sst28sf040.o m29f400bt.o 82802ab.o \ + sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o \ opaque.o sfdp.o en29lv640b.o at45db.o Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Wed Aug 6 17:09:15 2014 (r1839) +++ trunk/chipdrivers.h Fri Aug 8 10:33:01 2014 (r1840) @@ -155,10 +155,6 @@ int printlock_regspace2_block_eraser_0(struct flashctx *flash); int printlock_regspace2_block_eraser_1(struct flashctx *flash); -/* m29f400bt.c */ -int probe_m29f400bt(struct flashctx *flash); -int write_m29f400bt(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); - /* sst28sf040.c */ int erase_chip_28sf040(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int erase_sector_28sf040(struct flashctx *flash, unsigned int address, unsigned int sector_size); @@ -197,8 +193,6 @@ /* en29lv640b.c */ int probe_en29lv640b(struct flashctx *flash); -int erase_block_shifted_jedec(struct flashctx *flash, unsigned int start, unsigned int len); -int erase_chip_block_shifted_jedec(struct flashctx *flash, unsigned int start, unsigned int len); int write_en29lv640b(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); #endif /* !__CHIPDRIVERS_H__ */ Modified: trunk/en29lv640b.c ============================================================================== --- trunk/en29lv640b.c Wed Aug 6 17:09:15 2014 (r1839) +++ trunk/en29lv640b.c Fri Aug 8 10:33:01 2014 (r1840) @@ -85,51 +85,3 @@ return 0; } - -static int erase_chip_shifted_jedec(struct flashctx *flash) -{ - chipaddr bios = flash->virtual_memory; - - chip_writeb(flash, 0xAA, bios + 0xAAA); - chip_writeb(flash, 0x55, bios + 0x555); - chip_writeb(flash, 0x80, bios + 0xAAA); - - chip_writeb(flash, 0xAA, bios + 0xAAA); - chip_writeb(flash, 0x55, bios + 0x555); - chip_writeb(flash, 0x10, bios + 0xAAA); - - programmer_delay(10); - toggle_ready_jedec(flash, bios); - - /* FIXME: Check the status register for errors. */ - return 0; -} - -int erase_block_shifted_jedec(struct flashctx *flash, unsigned int start, unsigned int len) -{ - chipaddr bios = flash->virtual_memory; - chipaddr dst = bios + start; - - chip_writeb(flash, 0xAA, bios + 0xAAA); - chip_writeb(flash, 0x55, bios + 0x555); - chip_writeb(flash, 0x80, bios + 0xAAA); - - chip_writeb(flash, 0xAA, bios + 0xAAA); - chip_writeb(flash, 0x55, bios + 0x555); - chip_writeb(flash, 0x30, dst); - - programmer_delay(10); - toggle_ready_jedec(flash, bios); - - /* FIXME: Check the status register for errors. */ - return 0; -} - -int erase_chip_block_shifted_jedec(struct flashctx *flash, unsigned int address, unsigned int blocklen) -{ - if ((address != 0) || (blocklen != flash->chip->total_size * 1024)) { - msg_cerr("%s called with incorrect arguments\n", __func__); - return -1; - } - return erase_chip_shifted_jedec(flash); -} Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Aug 6 17:09:15 2014 (r1839) +++ trunk/flashchips.c Fri Aug 8 10:33:01 2014 (r1840) @@ -4869,7 +4869,7 @@ .model_id = EON_EN29LV640B, .total_size = 8192, .page_size = 8192, - .feature_bits = 0, + .feature_bits = FEATURE_ADDR_SHIFTED, .tested = TEST_OK_PREW, .probe = probe_en29lv640b, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ @@ -4880,10 +4880,10 @@ {8 * 1024, 8}, {64 * 1024, 127}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_block_jedec, }, { .eraseblocks = { {8 * 1024 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, }, }, .write = write_en29lv640b, @@ -5078,10 +5078,10 @@ .model_id = FUJITSU_MBM29F400BC, .total_size = 512, .page_size = 64 * 1024, - .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET, + .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, - .probe = probe_m29f400bt, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */ + .probe = probe_jedec, + .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt .block_erasers = { { @@ -5091,13 +5091,13 @@ {32 * 1024, 1}, {64 * 1024, 7}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, }, }, - .write = write_m29f400bt, + .write = write_jedec_1, .read = read_memmapped, .voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */ }, @@ -5110,10 +5110,10 @@ .model_id = FUJITSU_MBM29F400TC, .total_size = 512, .page_size = 64 * 1024, - .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET, + .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_AAA | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, - .probe = probe_m29f400bt, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */ + .probe = probe_jedec, + .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt .block_erasers = { { @@ -5123,13 +5123,13 @@ {8 * 1024, 2}, {16 * 1024, 1}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, }, }, - .write = write_m29f400bt, + .write = write_jedec_1, .read = read_memmapped, .voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */ }, @@ -5144,8 +5144,8 @@ .page_size = 0, .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_SHORT_RESET, .tested = TEST_UNTESTED, - .probe = probe_m29f400bt, - .probe_timing = TIMING_IGNORED, + .probe = probe_jedec, + .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt .block_erasers = { { @@ -5155,13 +5155,13 @@ {32 * 1024, 1}, {64 * 1024, 31}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_block_jedec, }, { .eraseblocks = { {2048 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, }, }, - .write = write_m29f400bt, /* Supports a fast mode too */ + .write = write_jedec_1, /* Supports a fast mode too */ .read = read_memmapped, .voltage = {3000, 3600}, /* 3.0-3.6V for type -70, others 2.7-3.6V */ }, @@ -5176,8 +5176,8 @@ .page_size = 0, .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_SHORT_RESET, .tested = TEST_UNTESTED, - .probe = probe_m29f400bt, - .probe_timing = TIMING_IGNORED, + .probe = probe_jedec, + .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt .block_erasers = { { @@ -5187,13 +5187,13 @@ {8 * 1024, 2}, {16 * 1024, 1}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_block_jedec, }, { .eraseblocks = { {2048 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, }, }, - .write = write_m29f400bt, /* Supports a fast mode too */ + .write = write_jedec_1, /* Supports a fast mode too */ .read = read_memmapped, .voltage = {3000, 3600}, /* 3.0-3.6V for type -70, others 2.7-3.6V */ }, @@ -12178,10 +12178,10 @@ .model_id = ST_M29F400BB, .total_size = 512, .page_size = 64 * 1024, - .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET, + .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, - .probe = probe_m29f400bt, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */ + .probe = probe_jedec, + .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt .block_erasers = { { @@ -12191,13 +12191,13 @@ {32 * 1024, 1}, {64 * 1024, 7}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, } }, - .write = write_m29f400bt, + .write = write_jedec_1, .read = read_memmapped, .voltage = {4500, 5500}, }, @@ -12210,10 +12210,10 @@ .model_id = ST_M29F400BT, .total_size = 512, .page_size = 64 * 1024, - .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET, + .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, - .probe = probe_m29f400bt, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */ + .probe = probe_jedec, + .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt .block_erasers = { { @@ -12223,13 +12223,13 @@ {8 * 1024, 2}, {16 * 1024, 1}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, } }, - .write = write_m29f400bt, + .write = write_jedec_1, .read = read_memmapped, .voltage = {4500, 5500}, }, Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Wed Aug 6 17:09:15 2014 (r1839) +++ trunk/jedec.c Fri Aug 8 10:33:01 2014 (r1840) @@ -4,7 +4,7 @@ * Copyright (C) 2000 Silicon Integrated System Corporation * Copyright (C) 2006 Giampiero Giancipoli <gianci(a)email.it> * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> - * Copyright (C) 2007, 2011 Carl-Daniel Hailfinger + * Copyright (C) 2007-2012 Carl-Daniel Hailfinger * Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com> * Copyright (C) 2014 Stefan Tauner * @@ -116,9 +116,11 @@ static void start_program_jedec_common(const struct flashctx *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); - chip_writeb(flash, 0xA0, bios + (0x5555 & mask)); + bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED); + + chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); + chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); + chip_writeb(flash, 0xA0, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); } int probe_jedec_29gl(struct flashctx *flash) @@ -174,6 +176,7 @@ { chipaddr bios = flash->virtual_memory; const struct flashchip *chip = flash->chip; + bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED); uint8_t id1, id2; uint32_t largeid1, largeid2; uint32_t flashcontent1, flashcontent2; @@ -203,31 +206,31 @@ /* Reset chip to a clean slate */ if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) { - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); if (probe_timing_exit) programmer_delay(10); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); if (probe_timing_exit) programmer_delay(10); } - chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); + chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); if (probe_timing_exit) programmer_delay(probe_timing_exit); /* Issue JEDEC Product ID Entry command */ - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); if (probe_timing_enter) programmer_delay(10); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); if (probe_timing_enter) programmer_delay(10); - chip_writeb(flash, 0x90, bios + (0x5555 & mask)); + chip_writeb(flash, 0x90, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); if (probe_timing_enter) programmer_delay(probe_timing_enter); /* Read product ID */ - id1 = chip_readb(flash, bios); - id2 = chip_readb(flash, bios + 0x01); + id1 = chip_readb(flash, bios + (0x00 << shifted)); + id2 = chip_readb(flash, bios + (0x01 << shifted)); largeid1 = id1; largeid2 = id2; @@ -246,14 +249,14 @@ /* Issue JEDEC Product ID Exit command */ if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) { - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); if (probe_timing_exit) programmer_delay(10); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); if (probe_timing_exit) programmer_delay(10); } - chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); + chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); if (probe_timing_exit) programmer_delay(probe_timing_exit); @@ -262,8 +265,8 @@ msg_cdbg(", id1 parity violation"); /* Read the product ID location again. We should now see normal flash contents. */ - flashcontent1 = chip_readb(flash, bios); - flashcontent2 = chip_readb(flash, bios + 0x01); + flashcontent1 = chip_readb(flash, bios + (0x00 << shifted)); + flashcontent2 = chip_readb(flash, bios + (0x01 << shifted)); /* Check if it is a continuation ID, this should be a while loop. */ if (flashcontent1 == 0x7F) { @@ -294,21 +297,23 @@ unsigned int pagesize, unsigned int mask) { chipaddr bios = flash->virtual_memory; + bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED); unsigned int delay_us = 0; + if(flash->chip->probe_timing != TIMING_ZERO) delay_us = 10; /* Issue the Sector Erase command */ - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); programmer_delay(delay_us); chip_writeb(flash, 0x30, bios + page); programmer_delay(delay_us); @@ -324,21 +329,23 @@ unsigned int blocksize, unsigned int mask) { chipaddr bios = flash->virtual_memory; + bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED); unsigned int delay_us = 0; + if(flash->chip->probe_timing != TIMING_ZERO) delay_us = 10; /* Issue the Sector Erase command */ - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); programmer_delay(delay_us); chip_writeb(flash, 0x50, bios + block); programmer_delay(delay_us); @@ -353,23 +360,25 @@ static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; + bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED); unsigned int delay_us = 0; + if(flash->chip->probe_timing != TIMING_ZERO) delay_us = 10; /* Issue the JEDEC Chip Erase command */ - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x10, bios + (0x5555 & mask)); + chip_writeb(flash, 0x10, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); programmer_delay(delay_us); toggle_ready_jedec_slow(flash, bios);

1 0

[PATCH] Allow shifted JEDEC access
by Carl-Daniel Hailfinger 07 Aug '14

07 Aug '14

Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit) for 8-bit mode. Some programmers can access them in 16-bit mode, but on all flashrom-supported programmers so far, we access them in 8-bit mode. This means we have to shift the addresses. Untested, should work. This is a patch written shortly after r886 was committed, and it has been forward-ported. Missing from this patch is the deletion of now-unused code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-jedec_shifted/jedec.c =================================================================== --- flashrom-jedec_shifted/jedec.c (Revision 1818) +++ flashrom-jedec_shifted/jedec.c (Arbeitskopie) @@ -4,7 +4,7 @@ * Copyright (C) 2000 Silicon Integrated System Corporation * Copyright (C) 2006 Giampiero Giancipoli <gianci(a)email.it> * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> - * Copyright (C) 2007 Carl-Daniel Hailfinger + * Copyright (C) 2007-2012 Carl-Daniel Hailfinger * Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com> * * This program is free software; you can redistribute it and/or modify @@ -115,15 +115,18 @@ static void start_program_jedec_common(const struct flashctx *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); - chip_writeb(flash, 0xA0, bios + (0x5555 & mask)); + int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0; + + chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask)); + chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask)); + chip_writeb(flash, 0xA0, bios + ((0x5555 << shifted) & mask)); } static int probe_jedec_common(struct flashctx *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; const struct flashchip *chip = flash->chip; + int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0; uint8_t id1, id2; uint32_t largeid1, largeid2; uint32_t flashcontent1, flashcontent2; @@ -153,31 +156,31 @@ /* Reset chip to a clean slate */ if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) { - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask)); if (probe_timing_exit) programmer_delay(10); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask)); if (probe_timing_exit) programmer_delay(10); } - chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); + chip_writeb(flash, 0xF0, bios + ((0x5555 << shifted) & mask)); if (probe_timing_exit) programmer_delay(probe_timing_exit); /* Issue JEDEC Product ID Entry command */ - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask)); if (probe_timing_enter) programmer_delay(10); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask)); if (probe_timing_enter) programmer_delay(10); - chip_writeb(flash, 0x90, bios + (0x5555 & mask)); + chip_writeb(flash, 0x90, bios + ((0x5555 << shifted) & mask)); if (probe_timing_enter) programmer_delay(probe_timing_enter); /* Read product ID */ - id1 = chip_readb(flash, bios); - id2 = chip_readb(flash, bios + 0x01); + id1 = chip_readb(flash, bios + (0x00 << shifted)); + id2 = chip_readb(flash, bios + (0x01 << shifted)); largeid1 = id1; largeid2 = id2; @@ -196,14 +199,14 @@ /* Issue JEDEC Product ID Exit command */ if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) { - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask)); if (probe_timing_exit) programmer_delay(10); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask)); if (probe_timing_exit) programmer_delay(10); } - chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); + chip_writeb(flash, 0xF0, bios + ((0x5555 << shifted) & mask)); if (probe_timing_exit) programmer_delay(probe_timing_exit); @@ -212,8 +215,8 @@ msg_cdbg(", id1 parity violation"); /* Read the product ID location again. We should now see normal flash contents. */ - flashcontent1 = chip_readb(flash, bios); - flashcontent2 = chip_readb(flash, bios + 0x01); + flashcontent1 = chip_readb(flash, bios + (0x00 << shifted)); + flashcontent2 = chip_readb(flash, bios + (0x01 << shifted)); /* Check if it is a continuation ID, this should be a while loop. */ if (flashcontent1 == 0x7F) { @@ -244,21 +247,23 @@ unsigned int pagesize, unsigned int mask) { chipaddr bios = flash->virtual_memory; + int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0; unsigned int delay_us = 0; + if(flash->chip->probe_timing != TIMING_ZERO) delay_us = 10; /* Issue the Sector Erase command */ - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + ((0x5555 << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask)); programmer_delay(delay_us); chip_writeb(flash, 0x30, bios + page); programmer_delay(delay_us); @@ -274,21 +279,23 @@ unsigned int blocksize, unsigned int mask) { chipaddr bios = flash->virtual_memory; + int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0; unsigned int delay_us = 0; + if(flash->chip->probe_timing != TIMING_ZERO) delay_us = 10; /* Issue the Sector Erase command */ - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + ((0x5555 << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask)); programmer_delay(delay_us); chip_writeb(flash, 0x50, bios + block); programmer_delay(delay_us); @@ -303,23 +310,25 @@ static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; + int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0; unsigned int delay_us = 0; + if(flash->chip->probe_timing != TIMING_ZERO) delay_us = 10; /* Issue the JEDEC Chip Erase command */ - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + ((0x5555 << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask)); programmer_delay(delay_us); - chip_writeb(flash, 0x10, bios + (0x5555 & mask)); + chip_writeb(flash, 0x10, bios + ((0x5555 << shifted) & mask)); programmer_delay(delay_us); toggle_ready_jedec_slow(flash, bios); Index: flashrom-jedec_shifted/82802ab.c =================================================================== --- flashrom-jedec_shifted/82802ab.c (Revision 1818) +++ flashrom-jedec_shifted/82802ab.c (Arbeitskopie) @@ -44,7 +44,7 @@ { chipaddr bios = flash->virtual_memory; uint8_t id1, id2, flashcontent1, flashcontent2; - int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) != 0; + int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0; /* Reset to get a clean state */ chip_writeb(flash, 0xFF, bios); Index: flashrom-jedec_shifted/flashchips.c =================================================================== --- flashrom-jedec_shifted/flashchips.c (Revision 1818) +++ flashrom-jedec_shifted/flashchips.c (Arbeitskopie) @@ -4892,10 +4892,10 @@ .model_id = FUJITSU_MBM29F400BC, .total_size = 512, .page_size = 64 * 1024, - .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET, + .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, - .probe = probe_m29f400bt, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */ + .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .block_erasers = { { @@ -4905,13 +4905,13 @@ {32 * 1024, 1}, {64 * 1024, 7}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, }, }, - .write = write_m29f400bt, + .write = write_jedec_1, .read = read_memmapped, .voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */ }, @@ -4924,10 +4924,10 @@ .model_id = FUJITSU_MBM29F400TC, .total_size = 512, .page_size = 64 * 1024, - .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET, + .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_AAA | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, - .probe = probe_m29f400bt, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */ + .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .block_erasers = { { @@ -4937,13 +4937,13 @@ {8 * 1024, 2}, {16 * 1024, 1}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, }, }, - .write = write_m29f400bt, + .write = write_jedec_1, .read = read_memmapped, .voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */ }, @@ -11388,10 +11388,10 @@ .model_id = ST_M29F400BB, .total_size = 512, .page_size = 64 * 1024, - .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET, + .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, - .probe = probe_m29f400bt, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */ + .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .block_erasers = { { @@ -11401,13 +11401,13 @@ {32 * 1024, 1}, {64 * 1024, 7}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, } }, - .write = write_m29f400bt, + .write = write_jedec_1, .read = read_memmapped, .voltage = {4500, 5500}, }, @@ -11420,10 +11420,10 @@ .model_id = ST_M29F400BT, .total_size = 512, .page_size = 64 * 1024, - .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET, + .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, - .probe = probe_m29f400bt, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */ + .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .block_erasers = { { @@ -11433,13 +11433,13 @@ {8 * 1024, 2}, {16 * 1024, 1}, }, - .block_erase = erase_block_shifted_jedec, + .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, - .block_erase = erase_chip_block_shifted_jedec, + .block_erase = erase_chip_block_jedec, } }, - .write = write_m29f400bt, + .write = write_jedec_1, .read = read_memmapped, .voltage = {4500, 5500}, }, -- http://www.hailfinger.org/

2 3

how does we design a flashrom
by phanquang thinh 07 Aug '14

07 Aug '14

Dear Sir/ Madam My name is Thinh, I am a student In Vietnam. I have a topic to reseach how does deaign flashrom so i searched on internet but i could not find any doument related that topic. can you help me some document or book on line so i can lear them my topic? Thank for your support Thinh

1 0

[commit] r1839 - in trunk: . Documentation
by repository service 06 Aug '14

06 Aug '14

Author: stefanct Date: Wed Aug 6 17:09:15 2014 New Revision: 1839 URL: http://flashrom.org/trac/flashrom/changeset/1839 Log: Add a bunch of new/tested stuff and various small changes 21. Tested mainboards: OK: - ASUS F2A85-M Reported by various corebooters - ASUS M2N-MX SE Plus Reported by Antonio - ASUS P5LD2 Reported by François Revol - Lenovo ThinkPad T530 Reported and partially authored by Edward O'Callaghan - MSI MS-7502 (Medion MD8833) Reported by naq on IRC - Shuttle AB61 Reported by olofolleola4 - ZOTAC IONITX-F-E Reported by Bernardo Kuri Flash chips: - Atmel AT45DB021D to PREW (+PREW) Reported by The Raven - Atmel AT25F4096 to PREW (+PREW) Reported by 공준혁 - GigaDevice GD25Q16(B) to PREW (+PREW) Reported by luxflow(a)live.com using a GD25Q16BSIG - Catalyst CAT28F512 Mark erase and write as known bad (not implemented) Miscellaneous: - Various spelling corrections by Daniele Forsi. - Added and refined a bunch of chips originally investigated by Carl-Daniel. - Marked the ARM-USB-OCD-H programmer as tested (reported by Ruud Schramp). - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/Documentation/serprog-protocol.txt trunk/atavia.c trunk/board_enable.c trunk/chipdrivers.h trunk/chipset_enable.c trunk/dmi.c trunk/flash.h trunk/flashchips.c trunk/flashchips.h trunk/flashrom.8.tmpl trunk/flashrom.c trunk/ft2232_spi.c trunk/it8212.c trunk/print.c trunk/sb600spi.c Modified: trunk/Documentation/serprog-protocol.txt ============================================================================== --- trunk/Documentation/serprog-protocol.txt Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/Documentation/serprog-protocol.txt Wed Aug 6 17:09:15 2014 (r1839) @@ -74,7 +74,7 @@ Send and receive bytes via SPI. Maximum slen is Q_WRNMAXLEN in case Q_BUSTYPE returns SPI only or S_BUSTYPE was used to set SPI exclusively before. Same for rlen and Q_RDNMAXLEN. - This operation is immediate, meaning it doesnt use the operation buffer. + This operation is immediate, meaning it doesn't use the operation buffer. 0x14 (S_SPI_FREQ): Set the SPI clock frequency. The 32-bit value indicates the requested frequency in Hertz. Value 0 is reserved and should Modified: trunk/atavia.c ============================================================================== --- trunk/atavia.c Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/atavia.c Wed Aug 6 17:09:15 2014 (r1839) @@ -113,7 +113,7 @@ } msg_pdbg2("\n%s: %s after %d tries (access=0x%02x, status=0x%02x)\n", - __func__, ready ? "suceeded" : "failed", try, access, status); + __func__, ready ? "succeeded" : "failed", try, access, status); atavia_prettyprint_access(access); return ready; } Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/board_enable.c Wed Aug 6 17:09:15 2014 (r1839) @@ -2374,7 +2374,7 @@ {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise}, - {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, + {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b0, 0x1043, 0x8179, "^P5LD2-MQ$", NULL, NULL, P3, "ASUS", "P5LD2-MQ", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, NT, intel_ich_gpio16_raise}, {0x8086, 0x27b0, 0x1043, 0x8179, 0x8086, 0x2770, 0x1043, 0x817a, "^P5LD2-VM DH$", NULL, NULL, P3, "ASUS", "P5LD2-VM DH", 0, OK, intel_ich_gpio16_raise}, @@ -2422,11 +2422,12 @@ {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, - {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60(s)", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "Lenovo", "X60(s)", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "Lenovo", "X201", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "Lenovo", "X230", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X201", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X230", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x27A0, 0x17AA, 0x2017, 0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X60(s)", 0, OK, p2_whitelist_laptop}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0, 0, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise}, Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/chipdrivers.h Wed Aug 6 17:09:15 2014 (r1839) @@ -158,7 +158,6 @@ /* m29f400bt.c */ int probe_m29f400bt(struct flashctx *flash); int write_m29f400bt(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); -void protect_m29f400bt(struct flashctx *flash, chipaddr bios); /* sst28sf040.c */ int erase_chip_28sf040(struct flashctx *flash, unsigned int addr, unsigned int blocklen); Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/chipset_enable.c Wed Aug 6 17:09:15 2014 (r1839) @@ -608,7 +608,7 @@ if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) { uint8_t buc = mmio_readb(rcrb + 0x3414); - msg_pdbg("Top Swap : %s\n", (buc & 1) ? "enabled (A16(+) inverted)" : "not enabled"); + msg_pdbg("Top Swap: %s\n", (buc & 1) ? "enabled (A16(+) inverted)" : "not enabled"); } /* Handle FWH-related parameters and initialization */ Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/dmi.c Wed Aug 6 17:09:15 2014 (r1839) @@ -188,7 +188,7 @@ /* - If a short entry is found (less than 4 bytes), not only it * is invalid, but we cannot reliably locate the next entry. * - If the length value indicates that this structure spreads - * accross the table border, something is fishy too. + * across the table border, something is fishy too. * Better stop at this point, and let the user know his/her * table is broken. */ Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/flash.h Wed Aug 6 17:09:15 2014 (r1839) @@ -187,7 +187,7 @@ * elements or set the function pointer to NULL. */ struct block_eraser { - struct eraseblock{ + struct eraseblock { unsigned int size; /* Eraseblock size in bytes */ unsigned int count; /* Number of contiguous blocks with that size */ } eraseblocks[NUM_ERASEREGIONS]; Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/flashchips.c Wed Aug 6 17:09:15 2014 (r1839) @@ -1994,7 +1994,7 @@ .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_at25f, .probe_timing = TIMING_ZERO, .block_erasers = @@ -2477,7 +2477,7 @@ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_at45db, .probe_timing = TIMING_ZERO, .block_erasers = @@ -3158,7 +3158,7 @@ .total_size = 64, .page_size = 0, /* unused */ .feature_bits = 0, - .tested = TEST_OK_PR, + .tested = {.probe = OK, .read = OK, .erase = BAD, .write = BAD }, .probe = probe_jedec, /* FIXME! */ .probe_timing = TIMING_ZERO, .block_erasers = @@ -5433,7 +5433,7 @@ .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 (B version only) */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -6627,7 +6627,7 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: Continously Program (CP) mode */ + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: Continuously Program (CP) mode */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ @@ -7641,7 +7641,7 @@ .block_erasers = { { - .eraseblocks = { {64 * 1024, 8}, }, + .eraseblocks = { {64 * 1024, 8} }, .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, @@ -10242,9 +10242,9 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, - .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */ + .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */ .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .read = spi_chip_read, /* Fast read (0x0B) and dual I/O (0x3B) supported */ .voltage = {2700, 3600}, }, @@ -10276,15 +10276,15 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, - .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */ + .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */ .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .read = spi_chip_read, /* Fast read (0x0B) and dual I/O (0x3B) supported */ .voltage = {2700, 3600}, }, { .vendor = "Spansion", - .name = "S25FL116K/S25FL216K", + .name = "S25FL116K/S25FL216K", /* FIXME: separate them */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, .model_id = SPANSION_S25FL216, @@ -10311,9 +10311,9 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, - .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */ + .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */ .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .read = spi_chip_read, /* Fast read (0x0B) and dual I/O (0x3B) supported */ .voltage = {2700, 3600}, }, @@ -10702,10 +10702,10 @@ { .vendor = "SST", - .name = "SST25VF512A", + .name = "SST25VF512(A)", .bustype = BUS_SPI, .manufacture_id = SST_ID, - .model_id = SST_SST25VF512A_REMS, + .model_id = SST_SST25VF512_REMS, .total_size = 64, .page_size = 256, .feature_bits = FEATURE_WRSR_EWSR, @@ -10722,25 +10722,25 @@ .block_erase = spi_block_erase_52, }, { .eraseblocks = { {32 * 1024, 2} }, - .block_erase = spi_block_erase_d8, + .block_erase = spi_block_erase_d8, /* Supported by SST25VF512A only */ }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { .eraseblocks = { {64 * 1024, 1} }, - .block_erase = spi_block_erase_c7, + .block_erase = spi_block_erase_c7, /* Supported by SST25VF512A only */ }, }, .printlock = spi_prettyprint_status_register_sst25, /* FIXME: No BP2 & 3 */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_1, /* AAI supported, but opcode is 0xAF */ - .read = spi_chip_read, /* Fast read (0x0B) supported */ + .read = spi_chip_read, /* Fast read (0x0B) supported by SST25VF512A only */ .voltage = {2700, 3600}, }, { .vendor = "SST", - .name = "SST25VF010", + .name = "SST25VF010(A)", .bustype = BUS_SPI, .manufacture_id = SST_ID, .model_id = SST_SST25VF010_REMS, @@ -10760,19 +10760,19 @@ .block_erase = spi_block_erase_52, }, { .eraseblocks = { {32 * 1024, 4} }, - .block_erase = spi_block_erase_d8, + .block_erase = spi_block_erase_d8, /* Supported by SST25VF010A only */ }, { .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { .eraseblocks = { {128 * 1024, 1} }, - .block_erase = spi_block_erase_c7, + .block_erase = spi_block_erase_c7, /* Supported by SST25VF010A only */ }, }, .printlock = spi_prettyprint_status_register_sst25, /* FIXME: No BP2 & 3 */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_1, /* AAI supported, but opcode is 0xAF */ - .read = spi_chip_read, /* Fast read (0x0B) supported */ + .read = spi_chip_read, /* Fast read (0x0B) supported by SST25VF010A only */ .voltage = {2700, 3600}, }, @@ -12157,7 +12157,7 @@ .block_erasers = { { - .eraseblocks = { {64 * 1024, 8}, }, + .eraseblocks = { {64 * 1024, 8} }, .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, @@ -12249,7 +12249,7 @@ .block_erasers = { { - .eraseblocks = { {16 * 1024, 8}, }, + .eraseblocks = { {16 * 1024, 8} }, .block_erase = erase_sector_jedec, }, { .eraseblocks = { {128 * 1024, 1} }, @@ -12276,7 +12276,7 @@ .block_erasers = { { - .eraseblocks = { {64 * 1024, 8}, }, + .eraseblocks = { {64 * 1024, 8} }, .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, @@ -12335,7 +12335,7 @@ }, .block_erase = erase_sector_stm50, }, { - .eraseblocks = { {64 * 1024, 8}, }, + .eraseblocks = { {64 * 1024, 8} }, .block_erase = erase_block_82802ab, } }, @@ -12368,7 +12368,7 @@ }, .block_erase = erase_sector_stm50, }, { - .eraseblocks = { {64 * 1024, 8}, }, + .eraseblocks = { {64 * 1024, 8} }, .block_erase = erase_block_82802ab, } }, @@ -12401,7 +12401,7 @@ }, .block_erase = erase_sector_stm50, }, { - .eraseblocks = { {64 * 1024, 16}, }, + .eraseblocks = { {64 * 1024, 16} }, .block_erase = erase_block_82802ab, } }, @@ -12435,7 +12435,7 @@ }, .block_erase = erase_sector_stm50, }, { - .eraseblocks = { {64 * 1024, 16}, }, + .eraseblocks = { {64 * 1024, 16} }, .block_erase = erase_block_82802ab, } }, @@ -12495,7 +12495,7 @@ .block_erasers = { { - .eraseblocks = { {64 * 1024, 32}, }, + .eraseblocks = { {64 * 1024, 32} }, .block_erase = erase_block_82802ab, } }, @@ -12520,7 +12520,7 @@ .block_erasers = { { - .eraseblocks = { {64 * 1024, 8}, }, + .eraseblocks = { {64 * 1024, 8} }, .block_erase = erase_block_82802ab, } }, @@ -12545,7 +12545,7 @@ .block_erasers = { { - .eraseblocks = { {64 * 1024, 16}, }, + .eraseblocks = { {64 * 1024, 16} }, .block_erase = erase_block_82802ab, } }, @@ -12570,7 +12570,7 @@ .block_erasers = { { - .eraseblocks = { {64 * 1024, 16}, }, + .eraseblocks = { {64 * 1024, 16} }, .block_erase = erase_block_82802ab, } }, @@ -14318,7 +14318,7 @@ .block_erasers = { { - .eraseblocks = { {64 * 1024, 16}, }, + .eraseblocks = { {64 * 1024, 16} }, .block_erase = erase_sector_jedec, }, { .eraseblocks = { {1024 * 1024, 1} }, @@ -14347,7 +14347,7 @@ .block_erasers = { { - .eraseblocks = { {64 * 1024, 8}, }, + .eraseblocks = { {64 * 1024, 8} }, .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/flashchips.h Wed Aug 6 17:09:15 2014 (r1839) @@ -75,6 +75,7 @@ #define AMD_AM29F800BT 0xD6 #define AMD_AM29LV001BB 0x6D #define AMD_AM29LV001BT 0xED +#define AMD_AM29LV010B 0x6E /* 1Mb, uniform */ #define AMD_AM29LV002BB 0xC2 #define AMD_AM29LV002BT 0x40 #define AMD_AM29LV004BB 0xB6 @@ -156,6 +157,10 @@ #define ATMEL_AT26DF161A 0x4601 #define ATMEL_AT26DF321 0x4700 /* Same as 25DF321 */ #define ATMEL_AT26F004 0x0400 +#define ATMEL_AT29LV512 0x3D +#define ATMEL_AT29LV010A 0x35 /* Same as AT29BV010A, the latter works down to 2.7V */ +#define ATMEL_AT29LV020 0xBA +#define ATMEL_AT29BV040A 0xC4 #define ATMEL_AT29C040A 0xA4 #define ATMEL_AT29C010A 0xD5 #define ATMEL_AT29C020 0xDA @@ -187,13 +192,15 @@ #define ATMEL_AT45DB321D 0x2701 /* Buggy data sheet */ #define ATMEL_AT45DB642 /* No ID (opcode) available for AT45DB642 */ #define ATMEL_AT45DB642D 0x2800 -#define ATMEL_AT49BV512 0x03 +#define ATMEL_AT49BV512 0x03 /* Same as AT49F512 */ +#define ATMEL_AT49F001N 0x05 /* Same as AT49F001 */ +#define ATMEL_AT49F001NT 0x04 /* Same as AT49F001T */ #define ATMEL_AT49F002N 0x07 /* for AT49F002(N) */ #define ATMEL_AT49LH002 0xE9 #define ATMEL_AT49LH00B4 0xED #define ATMEL_AT49LH004 0xEE #define ATMEL_AT49F002NT 0x08 /* for AT49F002(N)T */ -#define ATMEL_AT49F010 0x17 /* Same as AT49HF010 */ +#define ATMEL_AT49F010 0x17 /* Same as AT49HF010 (some erroneous datasheets say 0x87), AT49BV010, AT49HBV010, AT49HLV010 */ #define ATMEL_AT49F020 0x0B #define ATMEL_AT49F040 0x13 #define ATMEL_AT49F080 0x23 @@ -261,7 +268,7 @@ #define EON_EN25F80 0x3114 #define EON_EN25F16 0x3115 #define EON_EN25F32 0x3116 -#define EON_EN25F64 0x3117 /* guessed */ +#define EON_EN25F64 0x3117 #define EON_EN25Q40 0x3013 #define EON_EN25Q80 0x3014 #define EON_EN25Q16 0x3015 /* Same as EN25D16 */ @@ -561,7 +568,7 @@ * second byte is the device code, * third byte is a dummy byte. */ -#define SANYO_ID 0x62 /* Sanyo */ +#define SANYO_ID 0x62 /* Sanyo */ #define SANYO_LE25FW203A 0x1600 #define SANYO_LE25FW403A 0x1100 #define SANYO_LE25FW106 0x15 @@ -644,8 +651,13 @@ #define SST_SST25WF020 0x2503 #define SST_SST25WF040 0x2504 #define SST_SST25WF080 0x2505 -#define SST_SST25VF512A_REMS 0x48 /* REMS or RES opcode */ -#define SST_SST25VF010_REMS 0x49 /* REMS or RES opcode */ +/* There exist some successors to members of the SST25WF family with alphabetic suffixes. They have very weird + * IDs and were not spotted in the wild yet. Their datasheets show a 4 byte long response w/o a vendor ID. */ +#define SST_SST25WF020A /* 0x62 0x16 0x12 0x00 */ +#define SST_SST25WF040B /* 0x62 0x16 0x13 0x00 */ +#define SST_SST25WF080B /* 0x62 0x16 0x14 0x00 */ +#define SST_SST25VF512_REMS 0x48 /* REMS or RES opcode, same as SST25VF512A */ +#define SST_SST25VF010_REMS 0x49 /* REMS or RES opcode, same as SST25VF010A */ #define SST_SST25VF020_REMS 0x43 /* REMS or RES opcode, same as SST25LF020A */ #define SST_SST25VF020B 0x258C #define SST_SST25VF040_REMS 0x44 /* REMS or RES opcode, same as SST25LF040A */ @@ -667,6 +679,7 @@ #define SST_SST27VF010 0xA9 #define SST_SST27VF020 0xAA #define SST_SST28SF040 0x04 +#define SST_SST29LE512 0x3D /* Same as SST29VE512 */ #define SST_SST29EE512 0x5D #define SST_SST29EE010 0x07 #define SST_SST29LE010 0x08 /* Same as SST29VE010 */ @@ -685,6 +698,10 @@ #define SST_SST39VF020 0xD6 /* Same as 39LF020 */ #define SST_SST39VF040 0xD7 /* Same as 39LF040 */ #define SST_SST39VF080 0xD8 /* Same as 39LF080/39VF080/39VF088 */ +#define SST_SST45VF512 0x41 /* REMS, read opcode 0xFF */ +#define SST_SST45LF010 0x42 /* REMS, read opcode 0xFF, 'funny' other opcodes */ +#define SST_SST45VF010 0x45 /* REMS, read opcode 0xFF */ +#define SST_SST45VF020 0x43 /* REMS, read opcode 0xFF */ #define SST_SST49LF040B 0x50 #define SST_SST49LF040 0x51 #define SST_SST49LF020 0x61 @@ -785,6 +802,10 @@ #define SM_MVC_29C51002B 0xA2 /* Identical chips: {F,S,V}29C51002B */ #define SM_MVC_29C51004B 0xA3 /* Identical chips: {F,S,V}29C51004B */ +#define TENX_ID 0x7F7F5E /* Tenx Technologies */ +#define TENX_ID_NOPREFIX 0x5E +#define TENX_ICE25P05 0x01 /* Maybe? */ + #define TI_ID 0x97 /* Texas Instruments */ #define TI_OLD_ID 0x01 /* TI chips from last century */ #define TI_TMS29F002RT 0xB0 @@ -820,18 +841,18 @@ #define WINBOND_ID 0xDA /* Winbond */ #define WINBOND_W19B160BB 0x49 #define WINBOND_W19B160BT 0xC4 -#define WINBOND_W19B320SB 0x2A /* Same as W19L320SB */ -#define WINBOND_W19B320ST 0xBA /* Same as W19L320ST */ +#define WINBOND_W19B320SB 0x2A /* Same as W19L320SB */ +#define WINBOND_W19B320ST 0xBA /* Same as W19L320ST */ #define WINBOND_W19B322MB 0x92 #define WINBOND_W19B322MT 0x10 #define WINBOND_W19B323MB 0x94 #define WINBOND_W19B323MT 0x13 #define WINBOND_W19B324MB 0x97 #define WINBOND_W19B324MT 0x16 -#define WINBOND_W29C010 0xC1 /* Same as W29C010M, W29C011A, W29EE011, W29EE012, and ASD AE29F1008 */ -#define WINBOND_W29C020 0x45 /* Same as W29C020C, W29C022 and ASD AE29F2008 */ -#define WINBOND_W29C040 0x46 /* Same as W29C040P */ -#define WINBOND_W29C512A 0xC8 /* Same as W29EE512 */ +#define WINBOND_W29C010 0xC1 /* Same as W29C010M, W29C011A, W29EE011, W29EE012, and ASD AE29F1008 */ +#define WINBOND_W29C020 0x45 /* Same as W29C020C, W29C022 and ASD AE29F2008 */ +#define WINBOND_W29C040 0x46 /* Same as W29C040P */ +#define WINBOND_W29C512A 0xC8 /* Same as W29EE512 */ #define WINBOND_W29GL032CHL 0x7E1D01 /* Uniform Sectors, WP protects Top OR Bottom sector */ #define WINBOND_W29GL032CB 0x7E1A00 /* Top Boot Sector, WP protects Top 2 sectors */ #define WINBOND_W29GL032CT 0x7E1A01 /* Bottom Boot Sector, WP protects Bottom 2 sectors */ @@ -848,13 +869,13 @@ #define WINBOND_W39L512 0x38 #define WINBOND_W39V040A 0x3D #define WINBOND_W39V040FA 0x34 -#define WINBOND_W39V040B 0x54 /* Same as W39V040FB */ -#define WINBOND_W39V040C 0x50 /* Same as W39V040FC */ +#define WINBOND_W39V040B 0x54 /* Same as W39V040FB */ +#define WINBOND_W39V040C 0x50 /* Same as W39V040FC */ #define WINBOND_W39V080A 0xD0 #define WINBOND_W39V080FA 0xD3 -#define WINBOND_W39V080FA_DM 0x93 /* W39V080FA dual mode */ -#define WINBOND_W49F002 0x25 /* Same as W49F002B */ -#define WINBOND_W49F002U 0x0B /* Same as W49F002N and ASD AE49F2008 */ +#define WINBOND_W39V080FA_DM 0x93 /* W39V080FA dual mode */ +#define WINBOND_W49F002 0x25 /* Same as W49F002B */ +#define WINBOND_W49F002U 0x0B /* Same as W49F002N and ASD AE49F2008 */ #define WINBOND_W49F020 0x8C #define WINBOND_W49V002A 0xB0 #define WINBOND_W49V002FA 0x32 Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/flashrom.8.tmpl Wed Aug 6 17:09:15 2014 (r1839) @@ -229,7 +229,7 @@ .sp Some programmers have optional or mandatory parameters which are described in detail in the -.B PROGRAMMER SPECIFIC INFO +.B PROGRAMMER-SPECIFIC INFORMATION section. Support for some programmers can be disabled at compile time. .B "flashrom \-h" lists all supported programmers. @@ -242,11 +242,11 @@ .BR <logfile> . If the file already exists, it will be overwritten. This is the recommended way to gather logs from flashrom because they will be verbose even if the -on-screen messages are not verbose. +on-screen messages are not verbose and don't require output redirection. .TP .B "\-R, \-\-version" Show version information and exit. -.SH PROGRAMMER SPECIFIC INFO +.SH PROGRAMMER-SPECIFIC INFORMATION Some programmer drivers accept further parameters to set programmer-specific parameters. These parameters are separated from the programmer name by a colon. While some programmers take arguments at fixed positions, other @@ -474,7 +474,7 @@ .sp .B " flashrom \-p internal:laptop=this_is_not_a_laptop" .sp -to tell flashrom (at your own risk) that it does not running on a laptop. +to tell flashrom (at your own risk) that it is not running on a laptop. .SS .BR "dummy " programmer The dummy programmer operates on a buffer in memory only. It provides a safe @@ -595,7 +595,7 @@ .SS .BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ -, " satamv" , " atahpt" ", " atavia " and " it8212 " programmers +, " satamv" , " atahpt", " atavia " and " it8212 " programmers These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported by the selected programmer is installed in your system. The syntax is @@ -782,7 +782,7 @@ .B value can be .BR 1 " or " 2 -to select target chip 1 or 2 repectively. The default is target chip 1. +to select target chip 1 or 2 respectively. The default is target chip 1. .SS .BR "rayer_spi " programmer The default I/O base address used for the parallel port is 0x378 and you can use @@ -998,7 +998,7 @@ paragraph in the .B internal programmer subsection of the -.B PROGRAMMER SPECIFIC INFO +.B PROGRAMMER-SPECIFIC INFORMATION section and the information in our wiki at .BR "http://www.flashrom.org/Laptops " . .SS Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/flashrom.c Wed Aug 6 17:09:15 2014 (r1839) @@ -1757,7 +1757,7 @@ * depending on compiler flags, e.g. the target architecture, and can sometimes be 0. * For 'flashchips' we export the size explicitly to work around this and to be able to implement the * checks below. */ - if (flashchips_size <= 1 || flashchips[flashchips_size-1].name != NULL) { + if (flashchips_size <= 1 || flashchips[flashchips_size - 1].name != NULL) { msg_gerr("Flashchips table miscompilation!\n"); ret = 1; } else { Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/ft2232_spi.c Wed Aug 6 17:09:15 2014 (r1839) @@ -69,7 +69,7 @@ {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"}, {OLIMEX_VID, OLIMEX_ARM_OCD_PID, NT, "Olimex", "ARM-USB-OCD"}, {OLIMEX_VID, OLIMEX_ARM_TINY_PID, OK, "Olimex", "ARM-USB-TINY"}, - {OLIMEX_VID, OLIMEX_ARM_OCD_H_PID, NT, "Olimex", "ARM-USB-OCD-H"}, + {OLIMEX_VID, OLIMEX_ARM_OCD_H_PID, OK, "Olimex", "ARM-USB-OCD-H"}, {OLIMEX_VID, OLIMEX_ARM_TINY_H_PID, OK, "Olimex", "ARM-USB-TINY-H"}, {0}, Modified: trunk/it8212.c ============================================================================== --- trunk/it8212.c Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/it8212.c Wed Aug 6 17:09:15 2014 (r1839) @@ -28,7 +28,7 @@ #define PCI_VENDOR_ID_ITE 0x1283 const struct dev_entry devs_it8212[] = { - {PCI_VENDOR_ID_ITE, 0x8212, OK, "ITE", "8212F PATA RAID"}, + {PCI_VENDOR_ID_ITE, 0x8212, NT, "ITE", "8212F PATA RAID"}, {}, }; Modified: trunk/print.c ============================================================================== --- trunk/print.c Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/print.c Wed Aug 6 17:09:15 2014 (r1839) @@ -662,6 +662,7 @@ B("ASUS", "DSAN-DX", NT, "http://www.asus.com/Server_Workstation/Server_Motherboards/DSANDX/", NULL), B("ASUS", "E35M1-I DELUXE", OK, "http://www.asus.com/Motherboards/AMD_CPU_on_Board/E35M1I_DELUXE/", NULL), B("ASUS", "F1A75-V PRO", OK, "http://www.asus.com/Motherboard/F1A75V_PRO/", NULL), + B("ASUS", "F2A85-M", DEP, "https://www.asus.com/Motherboards/F2A85M/", "UEFI builds v6404 and above disable access to some parts of the flash, cf. http://www.coreboot.org/ASUS_F2A85-M#UEFI_builds_that_allow_flash_chip_acce…"), B("ASUS", "K8N", OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8N/", NULL), B("ASUS", "K8V", OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8V/", NULL), B("ASUS", "K8V SE Deluxe", OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8V_SE_Deluxe/", NULL), @@ -675,6 +676,7 @@ B("ASUS", "M2NBP-VM CSM", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2NBPVM_CSM/", NULL), B("ASUS", "M2N-E", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2NE/", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html"), B("ASUS", "M2N-E SLI", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2NE_SLI/", NULL), + B("ASUS", "M2N-MX SE Plus", OK, "http://www.asus.com/Motherboards/M2NMX_SE_Plus/", NULL), B("ASUS", "M2NPV-VM", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2NPVVM/", NULL), B("ASUS", "M2N-SLI Deluxe", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2NSLI_Deluxe/", NULL), B("ASUS", "M2V", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2V/", NULL), @@ -748,7 +750,7 @@ B("ASUS", "P5KPL-CM", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KPLCM/", NULL), B("ASUS", "P5L-MX", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LMX/", NULL), B("ASUS", "P5L-VM 1394", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LVM_1394/", NULL), - B("ASUS", "P5LD2", NT, NULL, "Untested board enable."), + B("ASUS", "P5LD2", OK, NULL, NULL), B("ASUS", "P5LD2-MQ", OK, "http://support.asus.com/download.aspx?SLanguage=en&p=8&s=12&m=Vintage-PH2&o…", "Found in ASUS Vintage-PH2 barebones."), B("ASUS", "P5LD2-VM", NT, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM/", "Untested board enable."), B("ASUS", "P5LD2-VM DH", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM_DH/", NULL), @@ -1005,6 +1007,7 @@ B("MSI", "MS-7376 (K9A2 Platinum V1)", OK, "http://www.msi.com/product/mb/K9A2-Platinum.html", NULL), B("MSI", "MS-7379 (G31M)", OK, "http://www.msi.com/product/mb/G31M.html", NULL), B("MSI", "MS-7399 1.1 (Persian)", OK, "http://acersupport.com/acerpanam/desktop/0000/Acer/AspireM5640/AspireM5640s…", "This is an OEM board used by Acer in e.g. Aspire M5640/M3640."), + B("MSI", "MS-7502", OK, NULL, "This is an OEM board used by Medion in e.g. Medion MD8833."), B("MSI", "MS-7522 (MSI X58 Pro-E)", OK, "http://www.msi.com/product/mb/X58_ProE.html", NULL), B("MSI", "MS-7529 (G31M3-L(S) V2)", OK, "http://www.msi.com/product/mb/G31M3-L-V2---G31M3-LS-V2.html", NULL), B("MSI", "MS-7529 (G31TM-P21)", OK, "http://www.msi.com/product/mb/G31TM-P21.html", NULL), @@ -1046,6 +1049,7 @@ B("RCA", "RM4100", OK, "http://www.settoplinux.org/index.php?title=RCA_RM4100", NULL), B("Samsung", "Polaris 32", OK, NULL, NULL), B("SAPPHIRE", "IPC-E350M1", OK, "http://www.sapphiretech.com/presentation/product/?pid=1034&lid=1", NULL), + B("Shuttle", "AB61", OK, "http://www.shuttle.eu/_archive/older/de/ab61.htm", NULL), B("Shuttle", "AK31", OK, "http://www.motherboard.cz/mb/shuttle/AK31.htm", NULL), B("Shuttle", "AK38N", OK, "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/", NULL), B("Shuttle", "AV11V30", OK, NULL, NULL), @@ -1149,7 +1153,8 @@ B("ZOTAC", "GeForce 8200", OK, NULL, NULL), B("ZOTAC", "H61-ITX WiFi (H61ITX-A-E)", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ZOTAC", "H67-ITX WiFi (H67ITX-C-E)", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), - B("ZOTAC", "IONITX-A", OK, NULL, NULL), + B("ZOTAC", "IONITX-A-E", OK, NULL, NULL), + B("ZOTAC", "IONITX-F-E", OK, NULL, NULL), B("ZOTAC", "nForce 630i Supreme (N73U-Supreme)", OK, NULL, NULL), B("ZOTAC", "ZBOX AD02 (PLUS)", OK, NULL, NULL), B("ZOTAC", "ZBOX HD-ID11", OK, NULL, NULL), @@ -1171,16 +1176,17 @@ B("Dell", "Latitude CPi A366XT", BAD, "http://www.coreboot.org/Dell_Latitude_CPi_A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop."), B("Dell", "Vostro 3700", BAD, NULL, "Locked ME, see http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html."), B("Dell", "Latitude E6520", BAD, NULL, "Locked ME, see http://www.flashrom.org/pipermail/flashrom/2012-June/009420.html."), - B("Elitegroup", "A928", OK, NULL, "Bootsector is locked and needs to be skipped with a layout file (writeable address range is 00000000:0003bfff"), + B("Elitegroup", "A928", OK, NULL, "Bootsector is locked and needs to be skipped with a layout file (writeable address range is 00000000:0003bfff)."), B("HP/Compaq", "EliteBook 8560p", BAD, NULL, "SPI lock down, SMM protection, PR in BIOS region, read-only descriptor, locked ME region."), B("HP/Compaq", "nx9005", BAD, "http://h18000.www1.hp.com/products/quickspecs/11602_na/11602_na.HTML", "Shuts down when probing for a chip. http://www.flashrom.org/pipermail/flashrom/2010-May/003321.html"), B("HP/Compaq", "nx9010", BAD, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)."), - B("IBM/Lenovo", "Thinkpad T40p", BAD, "http://www.thinkwiki.org/wiki/Category:T40p", NULL), - B("IBM/Lenovo", "Thinkpad T420", BAD, "http://www.thinkwiki.org/wiki/Category:T420", "Probing works (Macronix MX25L6405, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), - B("IBM/Lenovo", "Thinkpad T410s", BAD, "http://www.thinkwiki.org/wiki/Category:T410s", "Probing works (Winbond W25X64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), - B("IBM/Lenovo", "Thinkpad X1", BAD, "http://www.thinkwiki.org/wiki/Category:X1", "Probing works (ST M25PX64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), - B("IBM/Lenovo", "240", BAD, "http://www.stanford.edu/~bresnan//tp240.html", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later."), - B("Lenovo", "3000 V100 TF05Cxx", OK, "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…", NULL), + B("IBM/Lenovo", "ThinkPad T40p", BAD, "http://www.thinkwiki.org/wiki/Category:T40p", NULL), + B("IBM/Lenovo", "ThinkPad T420", BAD, "http://www.thinkwiki.org/wiki/Category:T420", "Probing works (Macronix MX25L6405, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), + B("IBM/Lenovo", "ThinkPad T410s", BAD, "http://www.thinkwiki.org/wiki/Category:T410s", "Probing works (Winbond W25X64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), + B("IBM/Lenovo", "ThinkPad X1", BAD, "http://www.thinkwiki.org/wiki/Category:X1", "Probing works (ST M25PX64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), + B("IBM/Lenovo", "ThinkPad T530", OK, "http://www.thinkwiki.org/wiki/Category:T530", "Works fine but only with coreboot (due to locked regions and additional PR restrictions)."), + B("IBM/Lenovo", "ThinkPad 240", BAD, "http://www.stanford.edu/~bresnan//tp240.html", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later."), + B("IBM/Lenovo", "3000 V100 TF05Cxx", OK, "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…", NULL), //B("MSI", "GT60-2OD", OK, "http://www.msi.com/product/nb/GT60_2OD.html", NULL), requires layout patches #endif Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Wed Aug 6 16:36:27 2014 (r1838) +++ trunk/sb600spi.c Wed Aug 6 17:09:15 2014 (r1839) @@ -191,7 +191,7 @@ return SPI_INVALID_LENGTH; } - unsigned int maxreadcnt = flash->mst->spi.max_data_read + 3; + unsigned int maxreadcnt = flash->mst->spi.max_data_read; if (readcnt > maxreadcnt) { msg_pinfo("%s: SPI controller can not receive %d bytes, it is limited to %d bytes\n", __func__, readcnt, maxreadcnt);

1 0

Re: [flashrom] [PATCH] Add support for S25FL128P, S25FL129P and refine it for S25FL128S chips.
by Antonio Ospite 06 Aug '14

06 Aug '14

On Mon, 4 Aug 2014 00:46:55 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Additionally to the existing S25FL128S......0 definition this patch > adds S25FL128P......0, S25FL128P......1 and S25FL128S......1, as well as > S25FL129P......0 and S25FL129P......1 definitions. > S25FL12xP seem to be the predecessor families of S25FL128S. All > associated chips can not be distinguished with RDID alone. > > Besides the new chips, this patch also fixes the name of the previously > supported S25FL128S model with uniform 256 kB sectors > (S25FL128P......1 not 0) and adds the hybrid sector version (0) as well. > > Due to the shared IDs the user has to select the right chip manually > with the -c parameter. To make this even possible, this patch enlarges > the respective array for results to 6. > Hi Stefan, the chip I've got is a S25FL129P......0, logs attached and some comments inlined below. Thanks. > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Tested-by: Antonio Ospite <ao2(a)ao2.it> > --- > cli_classic.c | 2 +- > flashchips.c | 182 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- > flashchips.h | 2 +- > 3 files changed, 181 insertions(+), 5 deletions(-) > > diff --git a/cli_classic.c b/cli_classic.c > index ee988a3..60b8b88 100644 > --- a/cli_classic.c > +++ b/cli_classic.c > @@ -94,7 +94,7 @@ int main(int argc, char *argv[]) > unsigned long size; > /* Probe for up to three flash chips. */ > const struct flashchip *chip = NULL; > - struct flashctx flashes[3] = {{0}}; > + struct flashctx flashes[6] = {{0}}; > struct flashctx *fill_flash; > const char *name; > int namelen, opt, i, j; > diff --git a/flashchips.c b/flashchips.c > index a1166e0..e587b28 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -10389,7 +10389,69 @@ const struct flashchip flashchips[] = { > > { > .vendor = "Spansion", > - .name = "S25FL128S......0", /* uniform 256kB sectors */ > + .name = "S25FL128P......0", /* uniform 64 kB sectors */ > + .bustype = BUS_SPI, > + .manufacture_id = SPANSION_ID, > + .model_id = SPANSION_S25FL128, > + .total_size = 16384, > + .page_size = 256, > + .feature_bits = FEATURE_WRSR_WREN, > + .tested = TEST_UNTESTED, > + .probe = probe_spi_rdid, > + .probe_timing = TIMING_ZERO, > + .block_erasers = { > + { > + .eraseblocks = { {64 * 1024, 256} }, > + .block_erase = spi_block_erase_20, > + }, { > + .eraseblocks = { {64 * 1024, 256} }, > + .block_erase = spi_block_erase_d8, > + }, { > + .eraseblocks = { { 16384 * 1024, 1} }, > + .block_erase = spi_block_erase_60, > + }, { > + .eraseblocks = { { 16384 * 1024, 1} }, > + .block_erase = spi_block_erase_c7, > + } > + }, > + .printlock = spi_prettyprint_status_register_bp3_srwd, > + .unlock = spi_disable_blockprotect_bp3_srwd, > + .write = spi_chip_write_256, > + .read = spi_chip_read, /* Fast read (0x0B) supported */ > + .voltage = {2700, 3600}, > + }, > + > + { > + .vendor = "Spansion", > + .name = "S25FL128P......1", /* uniform 256kB sectors */ > + .bustype = BUS_SPI, > + .manufacture_id = SPANSION_ID, > + .model_id = SPANSION_S25FL128, > + .total_size = 16384, > + .page_size = 256, > + .feature_bits = FEATURE_WRSR_WREN, > + .tested = TEST_UNTESTED, > + .probe = probe_spi_rdid, > + .probe_timing = TIMING_ZERO, > + .block_erasers = { > + { > + .eraseblocks = { {256 * 1024, 64} }, > + .block_erase = spi_block_erase_d8, > + }, { > + .eraseblocks = { { 16384 * 1024, 1} }, > + .block_erase = spi_block_erase_c7, > + } > + }, > + .printlock = spi_prettyprint_status_register_bp2_srwd, > + .unlock = spi_disable_blockprotect_bp2_srwd, > + .write = spi_chip_write_256, > + .read = spi_chip_read, /* Fast read (0x0B) supported */ > + .voltage = {2700, 3600}, > + }, > + > + { > + .vendor = "Spansion", > + .name = "S25FL128S......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ > .bustype = BUS_SPI, > .manufacture_id = SPANSION_ID, > .model_id = SPANSION_S25FL128, > @@ -10403,9 +10465,46 @@ const struct flashchip flashchips[] = { > .probe_timing = TIMING_ZERO, > .block_erasers = { > { > - .eraseblocks = { {4 * 1024, 4096} }, > - .block_erase = spi_block_erase_20, > + /* FIXME: erase opcodes 20h for (top or bottom) 4 kB parameter sectors only > + .eraseblocks = { > + {4 * 1024, 32}, > + {64 * 1024, 254}, // NOP > + }, > + .block_erase = NULL, > + }, { */ > + .eraseblocks = { { 64 * 1024, 256} }, > + .block_erase = spi_block_erase_d8, > + }, { > + .eraseblocks = { { 16384 * 1024, 1} }, > + .block_erase = spi_block_erase_60, > }, { > + .eraseblocks = { { 16384 * 1024, 1} }, > + .block_erase = spi_block_erase_c7, > + } > + }, > + .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: SR2 and many others */ > + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: various other locks */ > + .write = spi_chip_write_256, /* Multi I/O supported */ > + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ > + .voltage = {2700, 3600}, > + }, > + > + { > + .vendor = "Spansion", > + .name = "S25FL128S......1", /* uniform 256 kB sectors */ > + .bustype = BUS_SPI, > + .manufacture_id = SPANSION_ID, > + .model_id = SPANSION_S25FL128, > + .total_size = 16384, > + .page_size = 512, > + /* supports 4B addressing */ > + /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ > + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, > + .tested = TEST_UNTESTED, > + .probe = probe_spi_rdid, > + .probe_timing = TIMING_ZERO, > + .block_erasers = { > + { > .eraseblocks = { {256 * 1024, 64} }, > .block_erase = spi_block_erase_d8, > }, { > @@ -10422,6 +10521,83 @@ const struct flashchip flashchips[] = { > .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ > .voltage = {2700, 3600}, > }, > + { > + .vendor = "Spansion", > + .name = "S25FL129P......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ > + .bustype = BUS_SPI, > + .manufacture_id = SPANSION_ID, > + .model_id = SPANSION_S25FL128, > + .total_size = 16384, > + .page_size = 256, > + /* OTP: 506B total, 16B reserved; read 0x4B; write 0x42 */ > + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, > + .tested = TEST_UNTESTED, Probe and read work, and I tested write for all the supported block_erasers, each time with random data generated with: dd if=/dev/urandom count=$((16 * 1024 * 1024)) iflag=count_bytes of=random_data.bin > + .probe = probe_spi_rdid, > + .probe_timing = TIMING_ZERO, > + .block_erasers = { > + { > + /* FIXME: erase opcodes 20h for (top or bottom) 4 kB parameter sectors only > + .eraseblocks = { > + {4 * 1024, 32}, I also wanted to understand this "parameter sub-sector" thing a little better, it was not obvious to me what "(top or bottom)" meant in this context. Then I realized than sometimes these parameter sub-subsectors are at the start of the chip, sometimes they are at the end. Anyway, spi_block_erase_20 works with these 4KiB sub-sectors on the first two 64KiB sectors (i.e. up to 0x01f000-0x01ffff): ... 0x01f000-0x01ffff:EW, 0x020000-0x02ffff:EFAILED ... Just toe xperiment, I even tried to enable 4KiB sub-sectors for the whole flash but verification fails on the third 64KiB sector. ... 0x01f000-0x01ffff:EW, 0x020000-0x020fff:EFAILED ... > + {64 * 1024, 254}, // NOP as said verification fails here with spi_block_erase_20, is this because spi_block_erase_20 is a NOP from the third 64KiB sector on? If so, maybe the comment is a little too essential, it becomes clear only after you _know_ that it refers to opcode 20h. Maybe the comments can be modeled after the similar ones for some Intel chips (e.g. "25F160S33B8")? So if someone wanted to make this work should flashrom be changed so that it'd be possible to specify different eraser functions for different flash regions? Just curios. > + }, > + .block_erase = NULL, mention spi_block_erase_20 here and spi_block_erase_40 in the following item? > + }, { */ > + /* FIXME: erase opcodes 40h for (top or bottom) 2*4 kB parameter sectors only > + .eraseblocks = { > + {8 * 1024, 16}, > + {64 * 1024, 254}, // NOP > + }, > + .block_erase = NULL, I didn't play with this, because there's no spi_block_erase_40, but I guess the results would be consistent with the 4KiB blocks. > + }, { */ > + .eraseblocks = { { 64 * 1024, 256} }, > + .block_erase = spi_block_erase_d8, This one is OK. > + }, { > + .eraseblocks = { { 16384 * 1024, 1} }, > + .block_erase = spi_block_erase_60, This one is OK. > + }, { > + .eraseblocks = { { 16384 * 1024, 1} }, > + .block_erase = spi_block_erase_c7, This one is OK. > + } > + }, > + .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: Configuration register */ > + .unlock = spi_disable_blockprotect_bp2_srwd, > + .write = spi_chip_write_256, /* Multi I/O supported */ > + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ > + .voltage = {2700, 3600}, > + }, > + > + { > + .vendor = "Spansion", > + .name = "S25FL128P......1", /* uniform 256 kB sectors */ ^ This should be "S25FL129P......1". > + .bustype = BUS_SPI, > + .manufacture_id = SPANSION_ID, > + .model_id = SPANSION_S25FL128, > + .total_size = 16384, > + .page_size = 512, > + /* OTP: 506B total, 16B reserved; read 0x4B; write 0x42 */ > + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, > + .tested = TEST_UNTESTED, > + .probe = probe_spi_rdid, > + .probe_timing = TIMING_ZERO, > + .block_erasers = { > + { > + .eraseblocks = { {256 * 1024, 64} }, > + .block_erase = spi_block_erase_d8, > + }, { > + .eraseblocks = { { 16384 * 1024, 1} }, > + .block_erase = spi_block_erase_60, > + }, { > + .eraseblocks = { { 16384 * 1024, 1} }, > + .block_erase = spi_block_erase_c7, > + } > + }, > + .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: Configuration register */ > + .unlock = spi_disable_blockprotect_bp2_srwd, > + .write = spi_chip_write_256, /* Multi I/O supported */ > + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ > + .voltage = {2700, 3600}, > + }, > > { > .vendor = "SST", > diff --git a/flashchips.h b/flashchips.h > index 029bae8..b2c1d4d 100644 > --- a/flashchips.h > +++ b/flashchips.h > @@ -590,7 +590,7 @@ > #define SPANSION_S25FL016A 0x0214 > #define SPANSION_S25FL032A 0x0215 /* Same as S25FL032P, but the latter supports EDI and CFI */ > #define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */ > -#define SPANSION_S25FL128 0x2018 > +#define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */ > #define SPANSION_S25FL256 0x0219 > #define SPANSION_S25FL512 0x0220 > #define SPANSION_S25FL204 0x4013 > -- > Kind regards, Stefan Tauner > -- Antonio Ospite http://ao2.it A: Because it messes up the order in which people normally read text. See http://en.wikipedia.org/wiki/Posting_style Q: Why is top-posting such a bad thing?

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[commit] r1838 - trunk
by repository service 06 Aug '14

06 Aug '14

Author: stefanct Date: Wed Aug 6 16:36:27 2014 New Revision: 1838 URL: http://flashrom.org/trac/flashrom/changeset/1838 Log: Add support for S25FL128P, S25FL129P and refine it for S25FL128S chips. Additionally to the existing S25FL128S......0 definition this patch adds S25FL128P......0, S25FL128P......1 and S25FL128S......1, as well as S25FL129P......0 and S25FL129P......1 definitions. S25FL12xP seem to be the predecessor families of S25FL128S. All associated chips can not be distinguished with RDID alone. Besides the new chips, this patch also fixes the name of the previously supported S25FL128S model with uniform 256 kB sectors (S25FL128P......1 not 0) and adds the hybrid sector version (0) as well. Due to the shared IDs the user has to select the right chip manually with the -c parameter. To make this even possible, this patch enlarges the respective array for results to 6. Tested-by: Antonio Ospite <ao2(a)ao2.it> with a S25FL129P......0. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/cli_classic.c trunk/flashchips.c trunk/flashchips.h Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Wed Aug 6 01:28:47 2014 (r1837) +++ trunk/cli_classic.c Wed Aug 6 16:36:27 2014 (r1838) @@ -94,7 +94,7 @@ unsigned long size; /* Probe for up to three flash chips. */ const struct flashchip *chip = NULL; - struct flashctx flashes[3] = {{0}}; + struct flashctx flashes[6] = {{0}}; struct flashctx *fill_flash; const char *name; int namelen, opt, i, j; Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Aug 6 01:28:47 2014 (r1837) +++ trunk/flashchips.c Wed Aug 6 16:36:27 2014 (r1838) @@ -10389,7 +10389,69 @@ { .vendor = "Spansion", - .name = "S25FL128S......0", /* uniform 256kB sectors */ + .name = "S25FL128P......0", /* uniform 64 kB sectors */ + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp3_srwd, + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Spansion", + .name = "S25FL128P......1", /* uniform 256kB sectors */ + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_srwd, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Spansion", + .name = "S25FL128S......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, .model_id = SPANSION_S25FL128, @@ -10403,9 +10465,48 @@ .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 4096} }, + /* This chip supports erasing of the 32 so-called "parameter sectors" with + * opcode 0x20. Trying to access an address outside these 4kB blocks does + * have no effect on the memory contents, but sets a flag in the SR. + .eraseblocks = { + {4 * 1024, 32}, + {64 * 1024, 254} // inaccessible + }, .block_erase = spi_block_erase_20, + }, { */ + .eraseblocks = { { 64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: SR2 and many others */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: various other locks */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Spansion", + .name = "S25FL128S......1", /* uniform 256 kB sectors */ + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128, + .total_size = 16384, + .page_size = 512, + /* supports 4B addressing */ + /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { .eraseblocks = { {256 * 1024, 64} }, .block_erase = spi_block_erase_d8, }, { @@ -10421,6 +10522,86 @@ .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + }, + + { + .vendor = "Spansion", + .name = "S25FL129P......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128, + .total_size = 16384, + .page_size = 256, + /* OTP: 506B total, 16B reserved; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + /* FIXME: This chip supports erasing of the 32 so-called "parameter sectors" with + * opcode 0x20. Trying to access an address outside these 4kB blocks does have no + * effect on the memory contents, but sets a flag in the SR. + .eraseblocks = { + {4 * 1024, 32}, + {64 * 1024, 254} // inaccessible + }, + .block_erase = spi_block_erase_20, + }, { */ + /* FIXME: Additionally it also supports erase opcode 40h for the respective 2*4 kB pairs + .eraseblocks = { + {8 * 1024, 16}, + {64 * 1024, 254} // inaccessible + }, + .block_erase = spi_block_erase_40, + }, { */ + .eraseblocks = { { 64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: Configuration register */ + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Spansion", + .name = "S25FL129P......1", /* uniform 256 kB sectors */ + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128, + .total_size = 16384, + .page_size = 512, + /* OTP: 506B total, 16B reserved; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: Configuration register */ + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, }, { Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Wed Aug 6 01:28:47 2014 (r1837) +++ trunk/flashchips.h Wed Aug 6 16:36:27 2014 (r1838) @@ -590,7 +590,7 @@ #define SPANSION_S25FL016A 0x0214 #define SPANSION_S25FL032A 0x0215 /* Same as S25FL032P, but the latter supports EDI and CFI */ #define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */ -#define SPANSION_S25FL128 0x2018 +#define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */ #define SPANSION_S25FL256 0x0219 #define SPANSION_S25FL512 0x0220 #define SPANSION_S25FL204 0x4013

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Re: [flashrom] [PATCH] ichspi: fix missing set_addr on erases and possible crossings of 256 B boundaries.
by Stefan Tauner 06 Aug '14

06 Aug '14

On Sun, 3 Aug 2014 04:36:02 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Apparently the erase function did never set any address before issuing the > erase commands. How could this ever work? > Also, according to PCH documentation crossing 256 byte boundaries is invalid > and may cause wraparound due to the flash chip's pages. Check for this on > reads as well as writes. > > Thanks to Vladimir 'φ-coder/phcoder' Serbinenko for noticing these issues > and providing the initial patch. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Committed in r1837. Thanks again, phcoder! -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1837 - trunk
by repository service 06 Aug '14

06 Aug '14

Author: stefanct Date: Wed Aug 6 01:28:47 2014 New Revision: 1837 URL: http://flashrom.org/trac/flashrom/changeset/1837 Log: ichspi: fix missing set_addr on erases and possible crossings of 256 B boundaries. Apparently the erase function did never set any address before issuing the erase commands. How could this ever work? Also, according to PCH documentation crossing 256 byte boundaries is invalid and may cause wraparound due to the flash chip's pages. Check for this on reads as well as writes. Thanks to Vladimir 'φ-coder/phcoder' Serbinenko for noticing these issues and providing the initial patch. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed Aug 6 00:16:01 2014 (r1836) +++ trunk/ichspi.c Wed Aug 6 01:28:47 2014 (r1837) @@ -1272,6 +1272,7 @@ } msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + ich_hwseq_set_addr(addr); /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); @@ -1307,7 +1308,11 @@ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); while (len > 0) { + /* Obey programmer limit... */ block_len = min(len, flash->mst->opaque.max_data_read); + /* as well as flash chip page borders as demanded in the Intel datasheets. */ + block_len = min(block_len, 256 - (addr & 0xFF)); + ich_hwseq_set_addr(addr); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* set read operation */ @@ -1345,7 +1350,10 @@ while (len > 0) { ich_hwseq_set_addr(addr); + /* Obey programmer limit... */ block_len = min(len, flash->mst->opaque.max_data_write); + /* as well as flash chip page borders as demanded in the Intel datasheets. */ + block_len = min(block_len, 256 - (addr & 0xFF)); ich_fill_data(buf, block_len, ICH9_REG_FDATA0); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* clear operation */

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