- flashrom - mail.coreboot.org

W836xx: W840SU Series: flashrom -V
by Jörg Walter 31 Dec '14

31 Dec '14

flashrom v0.9.7-r1711 on Linux 3.17.7-gentoo (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.0, GCC 4.8.3, little endian Command line (3 args): flashrom --programmer internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 1594M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1001 us, 10000 myus = 10005 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Notebook " DMI string system-product-name: "W840SU Series " DMI string system-version: "Not Applicable " DMI string baseboard-manufacturer: "Notebook " DMI string baseboard-product-name: "W840SU Series " DMI string baseboard-version: "Not Applicable " DMI string chassis-type: "Laptop" Laptop detected via DMI. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found ITE EC, ID 0x8587, Rev 0x06 on port 0x2e. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. Error: Programmer initialization failed.

1 0

errent splash screen in front of bios boot screen.
by bob Rehcsif 31 Dec '14

31 Dec '14

1 0

Re: [flashrom] Intel 28F001BN/BX-T erase/write operation verified on 3C905B-TXNM
by Stefan Tauner 31 Dec '14

31 Dec '14

On Sat, 13 Dec 2014 05:42:33 +0800 Lu Xie <firexl(a)gmail.com> wrote: > Hi, > > I tried programming Intel 28F001BN/BX-T on 3C905B-TXNM but it failed at > erase/write. I checked that chip's datasheet and it says PIN 1 and 30 must > be pulled to 12V to accept erase/write operation, but the card can only > offer 5V at PIN 1 and NC at PIN 30. So I wired 12V to the two pins and then > flashrom erased/wrote the chip successfully. Please check the attached > output files for the two attempts. Hello Lu, Thanks for report! The successful log does not correspond 100% with the first one: the failure happens at the very beginning of the flash address space while the successful write does skip the first blocks and does only erase and write the last one. This can easily happen depending on the existing data and the image provided to flashrom. Just to make sure... can you please elaborate what happened between the two attempts that could explain what I wrote above? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

FAILED: wolf
by Nick Long 30 Dec '14

30 Dec '14

Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0 Verifiying flash... VERIFY FAILED at 0x00000062! Expected 0xff, Read=0x0b, failed byte count from 0x00000000-0x007fffff: 0x4 Your flash chip is in an unknown state.

1 0

Re: [flashrom] PCI BAR access thru sysfs
by Stefan Tauner 30 Dec '14

30 Dec '14

On Wed, 10 Dec 2014 15:03:39 -0800 Ed Swierk <eswierk(a)skyportsystems.com> wrote: > Various kernel options are known to interfere with flashrom's attempts to > access physical memory through /dev/mem. Some (like CONFIG_STRICT_DEVMEM) > are important security measures that cannot be disabled without recompiling > the kernel, and are likely to be used more widely over time. > > However, complete access to physical memory is unnecessary for some use > cases. For example, the SPI interface on an Intel NIC can be accessed by > mmapping a BAR resource file in the PCI device directory in sysfs. Has > anyone considered implementing such an alternative access method for PCI > devices in flashrom? Hello Ed, The issue is on our radar but we have not made any plans how to approach it. RFCs, PoCs and Patches very welcome ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Gigabyte GA-J1900N-D3V-1.x data
by Stefan Tauner 30 Dec '14

30 Dec '14

On Tue, 23 Dec 2014 00:55:47 -0800 Matt Taggart <matt(a)lackof.org> wrote: > Replying to just you to keep noise off the list. Please don't. The topic is quite generic and posting it on the list may save me some time in the future and discussing such stuff is exactly what the mailing list is for. > Stefan Tauner writes: > > > That's not unusual for various reasons (e.g. the firmware uses the > > flash as scratchpad). The rom.bin on your website looks sane to me and > > since I don't expect any problems regarding reading the chip with > > flashrom, I will mark probing and reading as tested, thanks. > > I would like to write test this board and I wanted to run my idea for a > testing procedure by you. > > I managed to find an older vendor BIOS version and can use the vendor DOS > flash tools to switch between them. I have used flashrom to read an image > of each. So how about trying this: > > 1) run 'flashrom -p internal -r rom1.bin' to get a dump of the current > vendor version > 2) run 'flashrom -p internal -w rom1.bin' to write the same version back, > and hopefully get back a report that they are identical > 3) run 'flashrom -p internal -w rom2.bin` to write the vendor's other > version, and hopefully the write succeeds > 4) reboot and confirm running the rom2.bin version > 5) run 'flashrom -p internal -w rom1.bin' to put the original back > 6) reboot and confirm running the rom1.bin version > 7) if anything went wrong, buy an external clip and use it to write one of > the images back. Since we think the reading is working, should the images I > have be the same as what I'd want to write with an external? (or would I > need an image originally read with the external?) Usually boards either allow to access the chip or they don't. So in theory one could simply do - flashrom -r backup - flashrom -E - flashrom -w backup Practically erase + write is slightly more risky than flashing another good image directly because flashrom writes in the smallest block size possible and that sometimes saves one from a brick. If you plan to hack on coreboot you should get a programmer anyway (I recommend a BBB because it is very versatile for coreboot development (SPI programmer (even easily convertible to 1.8V), USB debug). Images read with flashrom from a chip should always be identical no matter which programmer is used. The only reasons for differences are bugs and firmware that writes to the flash while booting (introducing discrepancies between the flash contents while powered on and off, which are usually benign... because the firmware must be prepared for crashing OSes ;) Hope that answers your questions. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

FAILED: HM77 (Macbook Pro retina)
by Trammell Hudson 29 Dec '14

29 Dec '14

No changes were written to the executable portions of the ROM. The data regions at 0x2000-0x2FFF, 0x6400-0x67FF, 0xC000-0x14FFF, 0x1C000, 0x3C000, 0x40000-0x4BFFF were overwritten correctly. My firmware image differed only in those regions below 0x190000, so it might have successfully written to the entire 0x0-0x4BFFF (or even higher) space. The ROM image that I was writing had changes in the executable firmware volume starting at 0x190000. These were not written to the ROM. I have successfully rebooted and can reflash via external SPI if necessary for further tests. Output log from flashrom -V during the write process: flashrom v0.9.6.1-r1564 on Darwin 12.0.0 (x86_64) flashrom was built with libpci 3.1.7, GCC 4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2336.1.00), little endian Command line (8 args): ./flashrom -p internal -V -f -o /Volumes/NO NAME/write.log -w /Volumes/NO NAME/mbp101.rom Calibrating delay loop... OS timer resolution is 1 usecs, 1597M loops per second, 10 myus = 9 us, 100 myus = 127 us, 1000 myus = 1003 us, 10000 myus = 9928 us, 4 myus = 4 us, OK. Initializing internal programmer Error accessing low megabyte, 0x100000 bytes at 0x00000000 Failed getting access to coreboot low tables. dmidecode execution unsuccessful - continuing without DMI info Found chipset "Intel HM77" with PCI ID 8086:1e57. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x9f, read w/o addr, none op[1]: 0x02, write w/ addr, none op[2]: 0x03, read w/ addr, none op[3]: 0x01, write w/o addr, none op[4]: 0x05, read w/o addr, none op[5]: 0x20, write w/ addr, none op[6]: 0xd8, write w/ addr, none op[7]: 0xff, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x06 0x06: 0x0004 (HSFC) HSFC: FGO=0, FCYCLE=2, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0190 FREG1: BIOS region (0x00190000-0x007fffff) is read-write. 0x5C: 0x018f0001 FREG2: Management Engine region (0x00001000-0x0018ffff) is read-write. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x866f0190 PR0: WARNING: 0x00190000-0x0066ffff is read-only. 0x78: 0x9fff0692 PR1: WARNING: 0x00692000-0x01ffffff is read-only. 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0xc4 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xfc4200 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=4 0x94: 0x0606 (PREOP) 0x96: 0x3c6c (OPTYPE) 0x98: 0x0103029f (OPMENU) 0x9C: 0xffd82005 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00800000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x64900024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 50 MHz Write and Erase Clock Freq.: 50 MHz Fast Read is supported. Fast Read Clock Frequency: 50 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x07ff0190 FLREG2 0x018f0001 FLREG3 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00190000 - 0x007fffff Region 2 (ME ) 0x00001000 - 0x0018ffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0xffff0000 FLMSTR2 0xffff0000 FLMSTR3 0xffff0118 --- Details --- Descr. BIOS ME GbE Platf. BIOS rw rw rw rw rw ME rw rw rw rw rw GbE rw rw rw rw rw SPI Read Configuration: prefetching disabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000. Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x70, id2 0x0e, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x70, id2 0x0e, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Found Macronix flash chip "MX25L6405" (8192 kB, SPI). Write/erase is not working yet on your programmer in its current configuration. Continuing anyway. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:EERASE FAILED at 0x00001000! Expected=0xff, Read=0x20, failed byte count from 0x00000000-0x0000ffff: 0xada4 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:EW, 0x010000-0x01ffff:EW, 0x020000-0x02ffff:S, 0x030000-0x03ffff:EW, 0x040000-0x04ffff:EW, 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:S, 0x080000-0x08ffff:S, 0x090000-0x09ffff:S, 0x0a0000-0x0affff:S, 0x0b0000-0x0bffff:S, 0x0c0000-0x0cffff:S, 0x0d0000-0x0dffff:S, 0x0e0000-0x0effff:S, 0x0f0000-0x0fffff:S, 0x100000-0x10ffff:S, 0x110000-0x11ffff:S, 0x120000-0x12ffff:S, 0x130000-0x13ffff:S, 0x140000-0x14ffff:S, 0x150000-0x15ffff:S, 0x160000-0x16ffff:S, 0x170000-0x17ffff:S, 0x180000-0x18ffff:S, 0x190000-0x19ffff:ETransaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=1, SPOP=0, COP=6, DBC=0, SME=0, SCF=4 Running OPCODE 0xd8 failed at address 0x190000 (payload length was 0). spi_block_erase_d8 failed during command execution at address 0x190000 Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x000000-0x7fffff:EInvalid OPCODE 0x06, will not execute. spi_chip_erase_60 failed during command execution Reading current flash chip contents... done. Looking for another erase function. Trying erase function 3... 0x000000-0x7fffff:EInvalid OPCODE 0x06, will not execute. spi_chip_erase_c7 failed during command execution Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Restoring MMIO space at 0x104cb28a0 Restoring PCI config space for 00:1f:0 reg 0xdc

3 3

Re: [flashrom] Add PICkit2 as an SPI programmer
by Stefan Tauner 27 Dec '14

27 Dec '14

Hello Justin, I was about to (eventually!) commit your patch when I discovered that you have never signed-off your patches. Please read http://flashrom.org/Development_Guidelines#Sign-off_Procedure for details, thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

updating BIOS for Shuttle SN21G5
by Eduardo de Juan 26 Dec '14

26 Dec '14

hi all I've tried to boot my linux Shuttle XPC from a USB stick but the option does not seem to be available so i guess it's time to update the BIOS. My box is a Shuttle XPC SN21G5. I've downloaded the flashrom program and I have a couple of doubts before I can start. 1.- do I need a .rom type file ? I've visited the Shuttle bios download page and everything there seems to be .bin files, for windows flash utilities. Do you know where I can find bios file that falshrom can use ? 2.- running flashrom in probe mode I get Found chip set "NVIDIA MCP51". This chip set is marked as untested. but I guess that means I just have to go ahead and try. BR, Eduardo

2 5

[PATCH] Fix wrong density encoding on Intel Silvermont.
by Stefan Tauner 26 Dec '14

26 Dec '14

Silvermont (Bay Trail, Rangeley, Avoton) seems to still use the old density encoding with 3 bits per chip. Documentation is unavailable (held concealed by Intel) but thanks to the efforts of Tai-Hong (Type) Wu the layout is clear now. This patch is based on his one but solves the issue differently reducing the code complexity. Signed-off-by: T.H.Wu Type <thwu(a)lunartoday.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Hello Tai-Hong, thanks a lot for your patch! And sorry for the late reply. Now that I got some time I have looked into your patch. Your solution seems to work fine but I decided that I'd rather move the dual output supported bit to the "common" bit field struct and rename all involved structs accordingly. This gets rid of the rather unreadable double ternary branch. I will probably commit this patch before you get a chance to test it again because I want to do the 0.9.8 release soonish, but I'd appreciate a later test very much too if you want to do that. ich_descriptors.c | 38 +++++++++++++++++++------------------- ich_descriptors.h | 18 +++++++----------- 2 files changed, 26 insertions(+), 30 deletions(-) diff --git a/ich_descriptors.c b/ich_descriptors.c index 1966f66..90f70ee 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -127,27 +127,27 @@ static const char *pprint_density(enum ich_chipset cs, const struct ich_descript case CHIPSET_ICH10: case CHIPSET_5_SERIES_IBEX_PEAK: case CHIPSET_6_SERIES_COUGAR_POINT: - case CHIPSET_7_SERIES_PANTHER_POINT: { + case CHIPSET_7_SERIES_PANTHER_POINT: + case CHIPSET_BAYTRAIL: { uint8_t size_enc; if (idx == 0) { - size_enc = desc->component.old.comp1_density; + size_enc = desc->component.dens_old.comp1_density; } else { - size_enc = desc->component.old.comp2_density; + size_enc = desc->component.dens_old.comp2_density; } if (size_enc > 5) return "reserved"; return size_str[size_enc]; } case CHIPSET_8_SERIES_LYNX_POINT: - case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: case CHIPSET_9_SERIES_WILDCAT_POINT: { uint8_t size_enc; if (idx == 0) { - size_enc = desc->component.new.comp1_density; + size_enc = desc->component.dens_new.comp1_density; } else { - size_enc = desc->component.new.comp2_density; + size_enc = desc->component.dens_new.comp2_density; } if (size_enc > 7) return "reserved"; @@ -207,16 +207,16 @@ void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_ msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1)); else msg_pdbg2("Component 2 is not used.\n"); - msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.common.freq_read)); - msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_read_id)); - msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_write)); - msg_pdbg2("Fast Read is %ssupported.\n", desc->component.common.fastread ? "" : "not "); - if (desc->component.common.fastread) + msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.modes.freq_read)); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_read_id)); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_write)); + msg_pdbg2("Fast Read is %ssupported.\n", desc->component.modes.fastread ? "" : "not "); + if (desc->component.modes.fastread) msg_pdbg2("Fast Read Clock Frequency: %s\n", - pprint_freq(cs, desc->component.common.freq_fastread)); + pprint_freq(cs, desc->component.modes.freq_fastread)); if (cs > CHIPSET_6_SERIES_COUGAR_POINT) msg_pdbg2("Dual Output Fast Read Support: %sabled\n", - desc->component.new.dual_output ? "dis" : "en"); + desc->component.modes.dual_output ? "dis" : "en"); if (desc->component.FLILL == 0) msg_pdbg2("No forbidden opcodes.\n"); else { @@ -816,22 +816,22 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors case CHIPSET_5_SERIES_IBEX_PEAK: case CHIPSET_6_SERIES_COUGAR_POINT: case CHIPSET_7_SERIES_PANTHER_POINT: + case CHIPSET_BAYTRAIL: if (idx == 0) { - size_enc = desc->component.old.comp1_density; + size_enc = desc->component.dens_old.comp1_density; } else { - size_enc = desc->component.old.comp2_density; + size_enc = desc->component.dens_old.comp2_density; } size_max = 5; break; case CHIPSET_8_SERIES_LYNX_POINT: - case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: case CHIPSET_9_SERIES_WILDCAT_POINT: if (idx == 0) { - size_enc = desc->component.new.comp1_density; + size_enc = desc->component.dens_new.comp1_density; } else { - size_enc = desc->component.new.comp2_density; + size_enc = desc->component.dens_new.comp2_density; } size_max = 7; break; @@ -842,7 +842,7 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors } if (size_enc > size_max) { - msg_perr("Density of ICH SPI component with index %d is invalid." + msg_perr("Density of ICH SPI component with index %d is invalid.\n" "Encoded density is 0x%x while maximum allowed is 0x%x.\n", idx, size_enc, size_max); return -1; diff --git a/ich_descriptors.h b/ich_descriptors.h index c41f9d9..2c21598 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -123,23 +123,19 @@ struct ich_desc_component { freq_fastread :3, freq_write :3, freq_read_id :3, - :2; - } common; + dual_output :1, /* new since Cougar Point/6 */ + :1; + } modes; struct { uint32_t comp1_density :3, comp2_density :3, - :11, - :13, - :2; - } old; + :26; + } dens_old; struct { uint32_t comp1_density :4, /* new since Lynx Point/8 */ comp2_density :4, - :9, - :13, - dual_output :1, /* new since Cougar Point/6 */ - :1; - } new; + :24; + } dens_new; }; union { /* 0x04 */ uint32_t FLILL; /* Flash Invalid Instructions Register */ -- Kind regards, Stefan Tauner

1 0

Fwd: Intel 28F001BN/BX-T erase/write operation verified on 3C905B-TXNM
by Lu Xie 25 Dec '14

25 Dec '14

I am forwarding this email since I haven't heard any confirmation after weeks. Happy holidays! Lu ---------- Forwarded message ---------- From: Lu Xie <firexl(a)gmail.com> Date: Fri, Dec 12, 2014 at 4:42 PM Subject: Intel 28F001BN/BX-T erase/write operation verified on 3C905B-TXNM To: flashrom(a)flashrom.org Hi, I tried programming Intel 28F001BN/BX-T on 3C905B-TXNM but it failed at erase/write. I checked that chip's datasheet and it says PIN 1 and 30 must be pulled to 12V to accept erase/write operation, but the card can only offer 5V at PIN 1 and NC at PIN 30. So I wired 12V to the two pins and then flashrom erased/wrote the chip successfully. Please check the attached output files for the two attempts. Lu

1 0

Unable to access a supported mobo: P5GC-MX/1333
by belg4mit＠pthbb.org 24 Dec '14

24 Dec '14

Hello, I have a P5GC-MX/133 (Rev 305g). This model is listed as supported on the website*, After building trunk from source, I invoked flashrom as shown, but the tool indicates the board is not supported. Am I missing something? # flashrom --programmer internal:mainboard=ASUS:P5GC-MX/1333 flashrom v0.9.7-r1850 on Linux 2.6.32-65-generic (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel ICH7/ICH7R". Enabling flash write... OK. No suitable board enable found for vendor="ASUS", model="P5GC-MX/1333". Aborting to be safe. Error: Programmer initialization failed. Thanks! -Jerrad * Apparently per http://flashrom.org/pipermail/flashrom/2010-June/003501.html

3 7

Re: [flashrom] Flashrom with FTDI support
by Stefan Tauner 24 Dec '14

24 Dec '14

On Mon, 22 Dec 2014 08:08:40 +0000 Ohad Benjamin <ohad(a)panpwr.com> wrote: > This is the output I get after compiling and trying to run flashrom.exe with the programmer connected: > > flashrom v0.9.7-r1711 on Windows 6.1 (x86) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Unable to open FTDI device: -6 (ftdi_usb_reset failed). > Error: Programmer initialization failed. > > This is what I get when the programmer is disconnected: > > $ flashrom.exe -p ft2232_spi:type=232H > flashrom v0.9.7-r1711 on Windows 6.1 (x86) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Unable to open FTDI device: -3 (device not found). > Error: Programmer initialization failed. > That might be some incompatibility between the ftdi and usb drivers and/or Windows. I can't really help with that. I recommend testing the same hardware setup with Linux or another Unix. Another approach would be to try to use libftdi-1.0... there is a number of bit-rotting patches dealing with this, see http://patchwork.coreboot.org/patch/3904/ etc. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Flashrom with FTDI support
by Stefan Tauner 22 Dec '14

22 Dec '14

On Thu, 18 Dec 2014 15:10:13 +0000 Ohad Benjamin <ohad(a)panpwr.com> wrote: > I tried compiling my own version from source, but the output could not communicate with the FTDI port. Hello Ohad, I'd focus on that part because from that description alone I suppose another binary would have the same problems. Please describe your symptoms and post a verbose flashrom log. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Gigabyte GA-J1900N-D3V-1.x data
by Matt Taggart 20 Dec '14

20 Dec '14

Hi coreboot and flashrom, I recently got a Gigabyte GA-J1900N-D3V-1.x board. This board is interesting to me because A) it's Bay Trail, B) it's got dual NICs and real serial ports, and C) it's inexpensive. I followed the guide at http://www.coreboot.org/Motherboard_Porting_Guide I put the logs and a README with more info at http://lackof.org/taggart/hacking/coreboot/GA-J1900N-D3V-1.x/ (and a tarball of that dir in the parent dir) The flashrom output is from SVN trunk as of today to ensure latest chip support. In particular flashrom reports untested: Found chipset "Intel Bay Trail" with PCI ID 8086:0f1c. Found Macronix flash chip "MX25U6435E/F" (8192 kB, SPI). I haven't yet attempted anything beyond that. I don't yet have an off-board way to flash the chips, I'm hoping to order something soon. If you have ideas of other things to try please let me know. Thanks, -- Matt Taggart matt(a)lackof.org

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Re: [flashrom] Unable to update BIOS for my MainBoard MS7816 =Z87-G43
by Stefan Tauner 20 Dec '14

20 Dec '14

On Mon, 17 Nov 2014 09:33:17 +0100 (CET) nabil.massaoudi(a)free.fr wrote: > another point : in Flashrom web; page Supported Hardware, noted MS7816(H87-G43), MS7816 is ref for Z87-G43. The MSI reference number is not unique but refer to a family of boards (presumably sharing the same firmware). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Success report
by Måns Thörnqvist 20 Dec '14

20 Dec '14

Hi! Ive successfully read and written my Gigabyte GA-P55-USB3 motherboard bios (update från F8 to F10g). This should probably be added to the list of supported hardware. Thanks for a great app! /Måns

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Failed BIOS dump report
by Peter Eckersley 20 Dec '14

20 Dec '14

This is what I get with the latest flashrom from svn, running on a Thinkpad X1 Carbon (2014/Haswell edition): pde@host:~/src/flashrom$ sudo flashrom -p internal -r /tmp/blah -V flashrom v0.9.7-r1852 on Linux 3.17-1-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.9.1, little endian Command line (5 args): flashrom -p internal -r /tmp/blah -V Calibrating delay loop... OS timer resolution is 1 usecs, 2578M loops per second, 10 myus = 10 us, 100 myus = 127 us, 1000 myus = 1020 us, 10000 myus = 10004 us, 4 myus = 15 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. No DMI table found. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Please send the output of "flashrom -V -p internal" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel Lynx Point LP Premium" with PCI ID 8086:9c43. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0x21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007f3972d92000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x0300 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=3, SME=0 0x50: 0x00004a4b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x4a, BRRA 0x4b 0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x07ff0180 FREG1: BIOS region (0x00180000-0x007fffff) is read-write. 0x5C: 0x017f0003 FREG2: Warning: Management Engine region (0x00003000-0x0017ffff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see http://flashrom.org/ME for details. 0x78: 0x87ff0740 PR1: Warning: 0x00740000-0x007fffff is read-only. 0x7C: 0x86df06b1 PR2: Warning: 0x006b1000-0x006dffff is read-only. 0x80: 0x86b006b0 PR3: Warning: 0x006b0000-0x006b0fff is read-only. 0x84: 0x86af0400 PR4: Warning: 0x00400000-0x006affff is read-only. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0xc4 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf90000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=1 0x94: 0x0606 (PREOP) 0x96: 0xfe40 (OPTYPE) 0x98: 0x0135059f (OPMENU) 0x9C: 0x20d80203 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x80802025 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002025 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xD0: 0x50444653 (FPB) OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ032/A25LQ32A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DL081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DL161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F512, 64 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F512A, 64 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F1024(A), 128 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F2048, 256 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F4096, 512 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ESMT F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ESMT F25L32PA, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q20(B), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q80(B), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q16(B), 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q32(B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q64(B), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q128B, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25T80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L1654, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L3254, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L6454, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L12854, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L512(E)/MX25V512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1005(C)/MX25L1006E, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L2005(C), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L4005(A/C), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L8005/MX25V8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605A/MX25L1606E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605D/MX25L1608D/MX25L1673E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3206E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3273E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6405(D), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6406E/MX25L6436E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6445E/MX25L6473E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L12805(D), 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U3235E/F, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U6435E/F, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U12835F, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P20-old, 256 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q128..1E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q128..3E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD256C, 32 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD010(C), 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD020(C), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD040(C), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV512(A), 64 kB: Invalid OPCODE 0xab, will not execute. Probing for PMC Pm25LV010, 128 kB: Invalid OPCODE 0xab, will not execute. Probing for PMC Pm25LV010A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW106, 128 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW406A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FU406B, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW203A, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW403A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW418A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW806, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW808, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL204K, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL208K, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL116K/S25FL216K, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL132K, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL164K, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128P......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128P......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128S......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128S......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL129P......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL129P......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25LF020A, 256 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080(A), 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF512(A), 64 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF010(A), 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF020, 256 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF020B, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q40.V, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q80.V, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q16.V, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q32.V, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q64.V, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Found Winbond flash chip "W25Q64.V" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Chip status register is 0x00. Probing for Winbond W25Q128.V, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q20.W, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q40.W, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q80.W, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x4d, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x4d, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x4d, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x44, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x4d, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x4d, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Winbond flash chip "W25Q64.V" (8192 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading flash... Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=63, SME=0, SCF=1 Running OPCODE 0x03 failed at address 0x003000 (payload length was 64). Read operation failed! FAILED. Restoring MMIO space at 0x7f3972d958a0 Restoring PCI config space for 00:1f:0 reg 0xdc -- Peter Eckersley pde(a)eff.org Technology Projects Director Tel +1 415 436 9333 x131 Electronic Frontier Foundation Fax +1 415 436 9993

2 1

[commit] r1860 - trunk
by repository service 20 Dec '14

20 Dec '14

Author: stefanct Date: Sat Dec 20 21:25:19 2014 New Revision: 1860 URL: http://flashrom.org/trac/flashrom/changeset/1860 Log: Add support for the MSTAR I2C ISP protocol. Basically, among other chips, MSTAR manufactures SoCs that equip TV sets and computer screens, and it seems that all of their products use the same in-system programming protocol. Basically, they use the DDC channel of VGA or DVI connectors, which is actually an I2C bus, to encapsulate SPI frames (the flash chip is connected to the SoC through an SPI bus). I wrote this patch since the screen I bought had a software bug, and the manufacturer only released a new firmware binary, but no tool or instructions on flashing it. More details can be found here: http://boeglin.org/blog/index.php?entry=Flashing-a-BenQ-Z-series-for-free(d… I only read code from Linux kernel archives published by Acer to figure out the protocol (for a touchscreen controller and an NFC chip, both by MSTAR, that share the same ISP protocol), so I don't think there are any legal problems with it. Compilation is currently disabled by default in the Makefile. If in doubt, additional Makefile bugs were added by Stefan. Signed-off-by: Alexandre Boeglin <alex(a)boeglin.org> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Added: trunk/mstarddc_spi.c (contents, props changed) Modified: trunk/Makefile trunk/flashrom.8.tmpl trunk/flashrom.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat Dec 20 17:45:31 2014 (r1859) +++ trunk/Makefile Sat Dec 20 21:25:19 2014 (r1860) @@ -300,6 +300,11 @@ else override CONFIG_LINUX_SPI = no endif +ifeq ($(CONFIG_MSTARDDC_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_MSTARDDC_SPI=yes +else +override CONFIG_MSTARDDC_SPI = no +endif endif ############################################################################### @@ -413,6 +418,9 @@ # Always enable Altera USB-Blaster dongles for now. CONFIG_USBBLASTER_SPI ?= yes +# MSTAR DDC support needs more tests/reviews/cleanups. +CONFIG_MSTARDDC_SPI ?= no + # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes @@ -670,6 +678,13 @@ PROGRAMMER_OBJS += linux_spi.o endif +ifeq ($(CONFIG_MSTARDDC_SPI), yes) +# This is a totally ugly hack. +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "LINUX_I2C_SUPPORT := yes" .features && printf "%s" "-D'CONFIG_MSTARDDC_SPI=1'") +NEED_LINUX_I2C := yes +PROGRAMMER_OBJS += mstarddc_spi.o +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif @@ -927,6 +942,19 @@ endef export LINUX_SPI_TEST +define LINUX_I2C_TEST +#include <linux/i2c-dev.h> +#include <linux/i2c.h> + +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + return 0; +} +endef +export LINUX_I2C_TEST + features: compiler @echo "FEATURES := yes" > .features.tmp ifeq ($(NEED_FTDI), yes) @@ -948,6 +976,13 @@ ( echo "yes."; echo "LINUX_SPI_SUPPORT := yes" >> .features.tmp ) || \ ( echo "no."; echo "LINUX_SPI_SUPPORT := no" >> .features.tmp ) endif +ifeq ($(NEED_LINUX_I2C), yes) + @printf "Checking if Linux I2C headers are present... " + @echo "$$LINUX_I2C_TEST" > .featuretest.c + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ + ( echo "yes."; echo "LINUX_I2C_SUPPORT := yes" >> .features.tmp ) || \ + ( echo "no."; echo "LINUX_I2C_SUPPORT := no" >> .features.tmp ) +endif @printf "Checking for utsname support... " @echo "$$UTSNAME_TEST" > .featuretest.c @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sat Dec 20 17:45:31 2014 (r1859) +++ trunk/flashrom.8.tmpl Sat Dec 20 21:25:19 2014 (r1860) @@ -227,6 +227,8 @@ .sp .BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" .sp +.BR "* mstarddc_spi" " (for SPI flash ROMs accessible through DDC in MSTAR-equipped displays)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER-SPECIFIC INFORMATION @@ -889,6 +891,51 @@ .B " flashrom \-p linux_spi:dev=/dev/spidevX.Y,spispeed=8000" .sp Please note that the linux_spi driver only works on Linux. +.SS +.BR "mstarddc_spi " programmer +The Display Data Channel (DDC) is an I2C bus present on VGA and DVI connectors, that allows exchanging +informations between a computer and attached displays. Its most common uses are getting display capabilities +through EDID (at I2C address 0x50) and sending commands to the display using the DDC/CI protocol (at address +0x37). On displays driven by MSTAR SoCs, it is also possible to access the SoC firmware flash (connected to +the Soc through another SPI bus) using an In-System Programming (ISP) port, usually at address 0x49. +This flashrom module allows the latter via Linux's I2C driver. +.sp +.B IMPORTANT: +Before using this programmer, the display +.B MUST +be in standby mode, and only connected to the computer that will run flashrom using a VGA cable, to an +inactive VGA output. It absolutely +.B MUST NOT +be used as a display during the procedure! +.sp +You have to specify the DDC/I2C controller and I2C address to use with the +.sp +.B " flashrom \-p mstarddc_spi:dev=/dev/i2c-X:YY" +.sp +syntax where +.B /dev/i2c-X +is the Linux device node for your I2C controller connected to the display's DDC channel, and +.B YY +is the (hexadecimal) address of the MSTAR ISP port (address 0x49 is usually used). +Example that uses I2C controller /dev/i2c-1 and address 0x49: +.sp +.B " flashrom \-p mstarddc_spi:dev=/dev/i2c-1:49 +.sp +It is also possible to inhibit the reset command that is normally sent to the display once the flashrom +operation is completed using the optional +.B noreset +parameter. A value of 1 prevents flashrom from sending the reset command. +Example that does not reset the display at the end of the operation: +.sp +.B " flashrom \-p mstarddc_spi:dev=/dev/i2c-1:49,noreset=1 +.sp +Please note that sending the reset command is also inhibited in the event an error occured during the operation. +To send the reset command afterwards, you can simply run flashrom once more, in chip probe mode (not specifying +an operation), without the +.B noreset +parameter, once the flash read/write operation you intended to perform has completed successfully. +.sp +Please also note that the mstarddc_spi driver only works on Linux. .SH EXAMPLES To back up and update your BIOS, run .sp Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Dec 20 17:45:31 2014 (r1859) +++ trunk/flashrom.c Sat Dec 20 21:25:19 2014 (r1860) @@ -354,6 +354,18 @@ }, #endif +#if CONFIG_MSTARDDC_SPI == 1 + { + .name = "mstarddc_spi", + .type = OTHER, + .devs.note = "MSTAR DDC devices addressable via /dev/i2c-* on Linux.\n", + .init = mstarddc_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Added: trunk/mstarddc_spi.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/mstarddc_spi.c Sat Dec 20 21:25:19 2014 (r1860) @@ -0,0 +1,234 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Alexandre Boeglin <alex(a)boeglin.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if CONFIG_MSTARDDC_SPI == 1 + +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <ctype.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <errno.h> +#include <sys/ioctl.h> +#include <linux/i2c-dev.h> +#include <linux/i2c.h> +#include "flash.h" +#include "programmer.h" +#include "spi.h" + +static const struct spi_master spi_master_mstarddc; + +static int mstarddc_fd; +static int mstarddc_addr; +static int mstarddc_doreset = 1; + +// MSTAR DDC Commands +#define MSTARDDC_SPI_WRITE 0x10 +#define MSTARDDC_SPI_READ 0x11 +#define MSTARDDC_SPI_END 0x12 +#define MSTARDDC_SPI_RESET 0x24 + +/* Returns 0 upon success, a negative number upon errors. */ +static int mstarddc_spi_shutdown(void *data) +{ + // Reset, disables ISP mode + if (mstarddc_doreset == 1) { + uint8_t cmd = MSTARDDC_SPI_RESET; + if (write(mstarddc_fd, &cmd, 1) < 0) { + msg_perr("Error sending reset command: errno %d.\n", + errno); + return -1; + } + } else { + msg_pinfo("Info: Reset command was not sent. " + "Either the noreset=1 option was used, " + "or an error occured.\n"); + } + + if (close(mstarddc_fd) < 0) { + msg_perr("Error closing device: errno %d.\n", errno); + return -1; + } + return 0; +} + +/* Returns 0 upon success, a negative number upon errors. */ +int mstarddc_spi_init(void) +{ + char *i2c_device; + char *i2c_address; + char *noreset; + + // Get device, address from command-line + i2c_device = extract_programmer_param("dev"); + if (i2c_device && strlen(i2c_device)) { + if ((i2c_address = strchr(i2c_device, ':'))) { + *i2c_address = '\0'; + i2c_address++; + } + if (!i2c_address || !strlen(i2c_address)) { + msg_perr("Error: no address specified.\n" + "Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n"); + return -1; + } + mstarddc_addr = strtol(i2c_address, NULL, 16); + } else { + msg_perr("Error: no device specified.\n" + "Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n"); + return -1; + } + msg_pinfo("Info: Will try to use device %s and address 0x%02x.\n", + i2c_device, mstarddc_addr); + + // Get noreset=1 option from command-line + if ((noreset = extract_programmer_param("noreset")) + && noreset[0] == '1') + mstarddc_doreset = 0; + msg_pinfo("Info: WILL %sreset the device at the end.\n", + mstarddc_doreset ? "" : "NOT "); + // Open device + if ((mstarddc_fd = open(i2c_device, O_RDWR)) < 0) { + switch (errno) { + case EACCES: + msg_perr("Error opening %s: Permission denied.\n" + "Please use sudo or run as root.\n", + i2c_device); + break; + case ENOENT: + msg_perr("Error opening %s: No such file.\n" + "Please check you specified the correct device.\n", + i2c_device); + break; + default: + msg_perr("Error opening %s: errno %d.\n", + i2c_device, errno); + } + return -1; + } + // Set slave address + if (ioctl(mstarddc_fd, I2C_SLAVE, mstarddc_addr) < 0) { + msg_perr("Error setting slave address 0x%02x: errno %d.\n", + mstarddc_addr, errno); + return -1; + } + // Enable ISP mode + uint8_t cmd[5] = { 'M', 'S', 'T', 'A', 'R' }; + if (write(mstarddc_fd, cmd, 5) < 0) { + int enable_err = errno; + uint8_t end_cmd = MSTARDDC_SPI_END; + + // Assume device is already in ISP mode, try to send END command + if (write(mstarddc_fd, &end_cmd, 1) < 0) { + msg_perr("Error enabling ISP mode: errno %d & %d.\n" + "Please check that device (%s) and address (0x%02x) are correct.\n", + enable_err, errno, i2c_device, mstarddc_addr); + return -1; + } + } + // Register shutdown function + register_shutdown(mstarddc_spi_shutdown, NULL); + + // Register programmer + register_spi_master(&spi_master_mstarddc); + return 0; +} + +/* Returns 0 upon success, a negative number upon errors. */ +static int mstarddc_spi_send_command(struct flashctx *flash, + unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + int ret = 0; + uint8_t *cmd; + + if ((cmd = malloc((writecnt + 1) * sizeof(uint8_t))) < 0) { + msg_perr("Error allocating memory: errno %d.\n", errno); + ret = -1; + } + + if (!ret && writecnt) { + cmd[0] = MSTARDDC_SPI_WRITE; + memcpy(cmd + 1, writearr, writecnt); + if (write(mstarddc_fd, cmd, writecnt + 1) < 0) { + msg_perr("Error sending write command: errno %d.\n", + errno); + ret = -1; + } + } + + if (!ret && readcnt) { + struct i2c_rdwr_ioctl_data i2c_data; + struct i2c_msg msg[2]; + + cmd[0] = MSTARDDC_SPI_READ; + i2c_data.nmsgs = 2; + i2c_data.msgs = msg; + i2c_data.msgs[0].addr = mstarddc_addr; + i2c_data.msgs[0].len = 1; + i2c_data.msgs[0].flags = 0; + i2c_data.msgs[0].buf = cmd; + i2c_data.msgs[1].addr = mstarddc_addr; + i2c_data.msgs[1].len = readcnt; + i2c_data.msgs[1].flags = I2C_M_RD; + i2c_data.msgs[1].buf = readarr; + + if (ioctl(mstarddc_fd, I2C_RDWR, &i2c_data) < 0) { + msg_perr("Error sending read command: errno %d.\n", + errno); + ret = -1; + } + } + + if (!ret && (writecnt || readcnt)) { + cmd[0] = MSTARDDC_SPI_END; + if (write(mstarddc_fd, cmd, 1) < 0) { + msg_perr("Error sending end command: errno %d.\n", + errno); + ret = -1; + } + } + + /* Do not reset if something went wrong, as it might prevent from + * retrying flashing. */ + if (ret != 0) + mstarddc_doreset = 0; + + if (cmd) + free(cmd); + + return ret; +} + +static const struct spi_master spi_master_mstarddc = { + .type = SPI_CONTROLLER_MSTARDDC, + .max_data_read = 256, + .max_data_write = 256, + .command = mstarddc_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +#endif Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Dec 20 17:45:31 2014 (r1859) +++ trunk/programmer.h Sat Dec 20 21:25:19 2014 (r1860) @@ -99,6 +99,9 @@ #if CONFIG_USBBLASTER_SPI == 1 PROGRAMMER_USBBLASTER_SPI, #endif +#if CONFIG_MSTARDDC_SPI == 1 + PROGRAMMER_MSTARDDC_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -474,6 +477,11 @@ extern const struct dev_entry devs_usbblasterspi[]; #endif +/* mstarddc_spi.c */ +#if CONFIG_MSTARDDC_SPI == 1 +int mstarddc_spi_init(void); +#endif + /* rayer_spi.c */ #if CONFIG_RAYER_SPI == 1 int rayer_spi_init(void); @@ -555,6 +563,9 @@ #if CONFIG_USBBLASTER_SPI == 1 SPI_CONTROLLER_USBBLASTER, #endif +#if CONFIG_MSTARDDC_SPI == 1 + SPI_CONTROLLER_MSTARDDC, +#endif }; #define MAX_DATA_UNSPECIFIED 0

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Re: [flashrom] [PATCH] Fix handling of write protection at register space address +2.
by Stefan Tauner 20 Dec '14

20 Dec '14

On Sat, 20 Dec 2014 20:30:09 +0400 Roman Lebedev <lebedev.ri(a)gmail.com> wrote: Thanks for all the tests. I have committed the last version in r1859. > The only two lines that look suspicious are: > W836xx enter config mode worked or we were already in config mode. > W836xx leave config mode had no effect. > Active config mode, unknown reg 0x20 ID: 00. > Is that normal? That's because flashrom lacks support for the superio/EC on the board and that's the cryptic message it spits out to tell us that. It is of no concern in most cases (i.e. when we can access the flash chip without help from the EC). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1859 - trunk
by repository service 20 Dec '14

20 Dec '14

Author: stefanct Date: Sat Dec 20 17:45:31 2014 New Revision: 1859 URL: http://flashrom.org/trac/flashrom/changeset/1859 Log: Fix handling of write protection at register space address +2. Since r1833 we added the offset of the virtual register in several functions, which produced segfaults. This patch renames a few parameters and reorganizes/fixes various parts of the changelock_regspace2_block() function - hence the rather big diff. Thanks to Roman Lebedev for reporting this issue and testing numerous revisions of this patch. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipdrivers.h trunk/jedec.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Fri Dec 12 01:32:03 2014 (r1858) +++ trunk/chipdrivers.h Sat Dec 20 17:45:31 2014 (r1859) @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_64k(struct flashctx *flash); int unlock_regspace2_block_eraser_0(struct flashctx *flash); int unlock_regspace2_block_eraser_1(struct flashctx *flash); -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); int printlock_regspace2_uniform_64k(struct flashctx *flash); int printlock_regspace2_block_eraser_0(struct flashctx *flash); int printlock_regspace2_block_eraser_1(struct flashctx *flash); Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Fri Dec 12 01:32:03 2014 (r1858) +++ trunk/jedec.c Sat Dec 20 17:45:31 2014 (r1859) @@ -589,11 +589,10 @@ #define REG2_LOCKDOWN (1 << 1) #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) -static int printlock_regspace2_block(const struct flashctx *flash, chipaddr offset) +static int printlock_regspace2_block(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t state = chip_readb(flash, wrprotect); - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, offset); + uint8_t state = chip_readb(flash, lockreg); + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, lockreg); switch (state & REG2_MASK) { case 0: msg_cdbg("Full Access.\n"); @@ -656,67 +655,81 @@ return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); } -static int changelock_regspace2_block(const struct flashctx *flash, chipaddr offset, uint8_t new_bits) -{ - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t old; - - if (new_bits & ~REG2_MASK) { - msg_cerr("Invalid locking change 0x%02x requested at 0x%0*" PRIxPTR "! " +/* Try to change the lock register at address lockreg from cur to new. + * + * - Try to unlock the lock bit if requested and it is currently set (although this is probably futile). + * - Try to change the read/write bits if requested. + * - Try to set the lockdown bit if requested. + * Return an error immediately if any of this fails. */ +static int changelock_regspace2_block(const struct flashctx *flash, chipaddr lockreg, uint8_t cur, uint8_t new) +{ + /* Only allow changes to known read/write/lockdown bits */ + if (((cur ^ new) & ~REG2_MASK) != 0) { + msg_cerr("Invalid lock change from 0x%02x to 0x%02x requested at 0x%0*" PRIxPTR "!\n" "Please report a bug at flashrom(a)flashrom.org\n", - new_bits, PRIxPTR_WIDTH, offset); + cur, new, PRIxPTR_WIDTH, lockreg); return -1; } - old = chip_readb(flash, wrprotect); - /* Early exist if no change (of read/write/lockdown) was requested. */ - if (((old ^ new_bits) & REG2_MASK) == 0) { - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not changed\n", PRIxPTR_WIDTH, offset); + + /* Exit early if no change (of read/write/lockdown bits) was requested. */ + if (((cur ^ new) & REG2_MASK) == 0) { + msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", PRIxPTR_WIDTH, lockreg); return 0; } - /* Normally lockdowns can not be cleared. Try nevertheless if requested. */ - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); - if (chip_readb(flash, wrprotect) != (old & ~REG2_LOCKDOWN)) { - msg_cerr("Lockdown can't be removed at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Normally the lockdown bit can not be cleared. Try nevertheless if requested. */ + if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { + chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg); + cur = chip_readb(flash, lockreg); + if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) { + msg_cwarn("Lockdown can't be removed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } } - /* Change read or write lock? */ - if ((old ^ new_bits) & REG2_RWLOCK) { + + /* Change read and/or write bit */ + if ((cur ^ new) & REG2_RWLOCK) { /* Do not lockdown yet. */ - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); - if (chip_readb(flash, wrprotect) != (new_bits & REG2_RWLOCK)) { - msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & REG2_RWLOCK); + chip_writeb(flash, wanted, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != wanted) { + msg_cerr("Changing lock bits failed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } + msg_cdbg("Changed lock bits at 0x%0*" PRIxPTR " to 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); } - /* Enable lockdown if requested. */ - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", PRIxPTR_WIDTH, offset); - chip_writeb(flash, new_bits, wrprotect); - if (chip_readb(flash, wrprotect) != new_bits) { - msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Eventually, enable lockdown if requested. */ + if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { + chip_writeb(flash, new, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != new) { + msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } + msg_cdbg("Enabled lockdown at 0x%0*" PRIxPTR ".\n", PRIxPTR_WIDTH, lockreg); } return 0; } -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) +static int unlock_regspace2_block_generic(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + off + 2; - uint8_t old = chip_readb(flash, wrprotect); + uint8_t old = chip_readb(flash, lockreg); /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); + return changelock_regspace2_block(flash, lockreg, old, old & ~REG2_RWLOCK); } static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) { const unsigned int elems = flash->chip->total_size * 1024 / block_size; struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; - return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic); } int unlock_regspace2_uniform_64k(struct flashctx *flash) @@ -734,7 +747,7 @@ // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } int unlock_regspace2_block_eraser_1(struct flashctx *flash) @@ -742,6 +755,6 @@ // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); }

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Re: [flashrom] [PATCH] Fix handling of write protection at register space address +2.
by Roman Lebedev 20 Dec '14

20 Dec '14

Hi. > Third time lucky. It indeed looks like to be a case here :) # flashrom --programmer internal -r 1002.bin.patch4 -V flashrom v0.9.7-r1858 on Linux 3.16.0-4-686-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.9.2, little endian Command line (5 args): flashrom --programmer internal -r 1002.bin.patch4 -V Calibrating delay loop... OS timer resolution is 1 usecs, 534M loops per second, 10 myus = 11 us, 100 myus = 107 us, 1000 myus = 1024 us, 10000 myus = 10026 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "ASUSTeK COMPUTER INC." DMI string system-product-name: "PCH-DR" DMI string system-version: "1.XX " DMI string baseboard-manufacturer: "ASUSTek Computer INC." DMI string baseboard-product-name: "PCH-DR" DMI string baseboard-version: "1.XX " Found Winbond Super I/O, id 0x82 W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Please send the output of "flashrom -V -p internal" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel 6300ESB" with PCI ID 8086:25a1. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled OK. The following protocols are supported: FWH. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x08, id2 0x14, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) mapped at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x08, id2 0x14, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Changed lock bits at 0xb733a002 to 0xf8. Changed lock bits at 0xb734a002 to 0xf8. Changed lock bits at 0xb735a002 to 0xf8. Changed lock bits at 0xb736a002 to 0xf8. Changed lock bits at 0xb737a002 to 0xf8. Changed lock bits at 0xb738a002 to 0xf8. Changed lock bits at 0xb739a002 to 0xf8. Changed lock bits at 0xb73aa002 to 0xf8. Reading flash... done. Restoring PCI config space for 00:1f:0 reg 0x4e The only two lines that look suspicious are: W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Is that normal? Thanks for this patches! Roman. On Sat, Dec 20, 2014 at 7:07 PM, Stefan Tauner < stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Previously we added the offset of the virtual register in several > functions, > which produced segfaults. This patch renames a few parameters and > reorganizes/fixes various parts of the changelock_regspace2_block() > function - hence the rather big diff. > > Thanks to Roman Lebedev for reporting this issue and testing numerous > revisions of this patch. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > > $"!%§$&%%$"Q! > Third time lucky. > Sorry everybody for the spam. > > chipdrivers.h | 1 - > jedec.c | 93 > ++++++++++++++++++++++++++++++++++------------------------- > 2 files changed, 53 insertions(+), 41 deletions(-) > > diff --git a/chipdrivers.h b/chipdrivers.h > index 8529c74..cac94f3 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_32k(struct flashctx > *flash); > int unlock_regspace2_uniform_64k(struct flashctx *flash); > int unlock_regspace2_block_eraser_0(struct flashctx *flash); > int unlock_regspace2_block_eraser_1(struct flashctx *flash); > -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); > int printlock_regspace2_uniform_64k(struct flashctx *flash); > int printlock_regspace2_block_eraser_0(struct flashctx *flash); > int printlock_regspace2_block_eraser_1(struct flashctx *flash); > diff --git a/jedec.c b/jedec.c > index 1345b89..19babf9 100644 > --- a/jedec.c > +++ b/jedec.c > @@ -589,11 +589,10 @@ static int regspace2_walk_unlockblocks(const struct > flashctx *flash, const struc > #define REG2_LOCKDOWN (1 << 1) > #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) > > -static int printlock_regspace2_block(const struct flashctx *flash, > chipaddr offset) > +static int printlock_regspace2_block(const struct flashctx *flash, > chipaddr lockreg) > { > - chipaddr wrprotect = flash->virtual_registers + offset + 2; > - uint8_t state = chip_readb(flash, wrprotect); > - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", > PRIxPTR_WIDTH, offset); > + uint8_t state = chip_readb(flash, lockreg); > + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", > PRIxPTR_WIDTH, lockreg); > switch (state & REG2_MASK) { > case 0: > msg_cdbg("Full Access.\n"); > @@ -656,67 +655,81 @@ int printlock_regspace2_block_eraser_1(struct > flashctx *flash) > return regspace2_walk_unlockblocks(flash, unlockblocks, > &printlock_regspace2_block); > } > > -static int changelock_regspace2_block(const struct flashctx *flash, > chipaddr offset, uint8_t new_bits) > -{ > - chipaddr wrprotect = flash->virtual_registers + offset + 2; > - uint8_t old; > - > - if (new_bits & ~REG2_MASK) { > - msg_cerr("Invalid locking change 0x%02x requested at > 0x%0*" PRIxPTR "! " > +/* Try to change the lock register at address lockreg from cur to new. > + * > + * - Try to unlock the lock bit if requested and it is currently set > (although this is probably futile). > + * - Try to change the read/write bits if requested. > + * - Try to set the lockdown bit if requested. > + * Return an error immediately if any of this fails. */ > +static int changelock_regspace2_block(const struct flashctx *flash, > chipaddr lockreg, uint8_t cur, uint8_t new) > +{ > + /* Only allow changes to known read/write/lockdown bits */ > + if (((cur ^ new) & ~REG2_MASK) != 0) { > + msg_cerr("Invalid lock change from 0x%02x to 0x%02x > requested at 0x%0*" PRIxPTR "!\n" > "Please report a bug at flashrom(a)flashrom.org\n", > - new_bits, PRIxPTR_WIDTH, offset); > + cur, new, PRIxPTR_WIDTH, lockreg); > return -1; > } > - old = chip_readb(flash, wrprotect); > - /* Early exist if no change (of read/write/lockdown) was > requested. */ > - if (((old ^ new_bits) & REG2_MASK) == 0) { > - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not > changed\n", PRIxPTR_WIDTH, offset); > + > + /* Exit early if no change (of read/write/lockdown bits) was > requested. */ > + if (((cur ^ new) & REG2_MASK) == 0) { > + msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", > PRIxPTR_WIDTH, lockreg); > return 0; > } > - /* Normally lockdowns can not be cleared. Try nevertheless if > requested. */ > - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { > - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); > - if (chip_readb(flash, wrprotect) != (old & > ~REG2_LOCKDOWN)) { > - msg_cerr("Lockdown can't be removed at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + > + /* Normally the lockdown bit can not be cleared. Try nevertheless > if requested. */ > + if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { > + chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg); > + cur = chip_readb(flash, lockreg); > + if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) { > + msg_cwarn("Lockdown can't be removed at 0x%0*" > PRIxPTR "! New value: 0x%02x.\n", > + PRIxPTR_WIDTH, lockreg, cur); > return -1; > } > } > - /* Change read or write lock? */ > - if ((old ^ new_bits) & REG2_RWLOCK) { > + > + /* Change read and/or write bit */ > + if ((cur ^ new) & REG2_RWLOCK) { > /* Do not lockdown yet. */ > - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to > 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); > - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); > - if (chip_readb(flash, wrprotect) != (new_bits & > REG2_RWLOCK)) { > - msg_cerr("Locking status change FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & > REG2_RWLOCK); > + chip_writeb(flash, wanted, lockreg); > + cur = chip_readb(flash, lockreg); > + if (cur != wanted) { > + msg_cerr("Changing lock bits failed at 0x%0*" > PRIxPTR "! New value: 0x%02x.\n", > + PRIxPTR_WIDTH, lockreg, cur); > return -1; > } > + msg_cdbg("Changed lock bits at 0x%0*" PRIxPTR " to > 0x%02x.\n", > + PRIxPTR_WIDTH, lockreg, cur); > } > - /* Enable lockdown if requested. */ > - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { > - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", > PRIxPTR_WIDTH, offset); > - chip_writeb(flash, new_bits, wrprotect); > - if (chip_readb(flash, wrprotect) != new_bits) { > - msg_cerr("Enabling lockdown FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + > + /* Eventually, enable lockdown if requested. */ > + if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { > + chip_writeb(flash, new, lockreg); > + cur = chip_readb(flash, lockreg); > + if (cur != new) { > + msg_cerr("Enabling lockdown FAILED at 0x%0*" > PRIxPTR "! New value: 0x%02x.\n", > + PRIxPTR_WIDTH, lockreg, cur); > return -1; > } > + msg_cdbg("Enabled lockdown at 0x%0*" PRIxPTR ".\n", > PRIxPTR_WIDTH, lockreg); > } > > return 0; > } > > -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) > +static int unlock_regspace2_block_generic(const struct flashctx *flash, > chipaddr lockreg) > { > - chipaddr wrprotect = flash->virtual_registers + off + 2; > - uint8_t old = chip_readb(flash, wrprotect); > + uint8_t old = chip_readb(flash, lockreg); > /* We don't care for the lockdown bit as long as the RW locks are > 0 after we're done */ > - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); > + return changelock_regspace2_block(flash, lockreg, old, old & > ~REG2_RWLOCK); > } > > static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long > block_size) > { > const unsigned int elems = flash->chip->total_size * 1024 / > block_size; > struct unlockblock blocks[2] = {{.size = block_size, .count = > elems}}; > - return regspace2_walk_unlockblocks(flash, blocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, blocks, > &unlock_regspace2_block_generic); > } > > int unlock_regspace2_uniform_64k(struct flashctx *flash) > @@ -734,7 +747,7 @@ int unlock_regspace2_block_eraser_0(struct flashctx > *flash) > // FIXME: this depends on the eraseblocks not to be filled up > completely (i.e. to be null-terminated). > const struct unlockblock *unlockblocks = > (const struct unlockblock > *)flash->chip->block_erasers[0].eraseblocks; > - return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block_generic); > } > > int unlock_regspace2_block_eraser_1(struct flashctx *flash) > @@ -742,6 +755,6 @@ int unlock_regspace2_block_eraser_1(struct flashctx > *flash) > // FIXME: this depends on the eraseblocks not to be filled up > completely (i.e. to be null-terminated). > const struct unlockblock *unlockblocks = > (const struct unlockblock > *)flash->chip->block_erasers[1].eraseblocks; > - return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block_generic); > } > > -- > Kind regards, Stefan Tauner > >

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[PATCH] Fix handling of write protection at register space address +2.
by Stefan Tauner 20 Dec '14

20 Dec '14

Previously we added the offset of the virtual register in several functions, which produced segfaults. This patch renames a few parameters and reorganizes/fixes various parts of the changelock_regspace2_block() function - hence the rather big diff. Thanks to Roman Lebedev for reporting this issue and testing numerous revisions of this patch. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- $"!%§$&%%$"Q! Third time lucky. Sorry everybody for the spam. chipdrivers.h | 1 - jedec.c | 93 ++++++++++++++++++++++++++++++++++------------------------- 2 files changed, 53 insertions(+), 41 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 8529c74..cac94f3 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_32k(struct flashctx *flash); int unlock_regspace2_uniform_64k(struct flashctx *flash); int unlock_regspace2_block_eraser_0(struct flashctx *flash); int unlock_regspace2_block_eraser_1(struct flashctx *flash); -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); int printlock_regspace2_uniform_64k(struct flashctx *flash); int printlock_regspace2_block_eraser_0(struct flashctx *flash); int printlock_regspace2_block_eraser_1(struct flashctx *flash); diff --git a/jedec.c b/jedec.c index 1345b89..19babf9 100644 --- a/jedec.c +++ b/jedec.c @@ -589,11 +589,10 @@ static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struc #define REG2_LOCKDOWN (1 << 1) #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) -static int printlock_regspace2_block(const struct flashctx *flash, chipaddr offset) +static int printlock_regspace2_block(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t state = chip_readb(flash, wrprotect); - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, offset); + uint8_t state = chip_readb(flash, lockreg); + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, lockreg); switch (state & REG2_MASK) { case 0: msg_cdbg("Full Access.\n"); @@ -656,67 +655,81 @@ int printlock_regspace2_block_eraser_1(struct flashctx *flash) return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); } -static int changelock_regspace2_block(const struct flashctx *flash, chipaddr offset, uint8_t new_bits) -{ - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t old; - - if (new_bits & ~REG2_MASK) { - msg_cerr("Invalid locking change 0x%02x requested at 0x%0*" PRIxPTR "! " +/* Try to change the lock register at address lockreg from cur to new. + * + * - Try to unlock the lock bit if requested and it is currently set (although this is probably futile). + * - Try to change the read/write bits if requested. + * - Try to set the lockdown bit if requested. + * Return an error immediately if any of this fails. */ +static int changelock_regspace2_block(const struct flashctx *flash, chipaddr lockreg, uint8_t cur, uint8_t new) +{ + /* Only allow changes to known read/write/lockdown bits */ + if (((cur ^ new) & ~REG2_MASK) != 0) { + msg_cerr("Invalid lock change from 0x%02x to 0x%02x requested at 0x%0*" PRIxPTR "!\n" "Please report a bug at flashrom(a)flashrom.org\n", - new_bits, PRIxPTR_WIDTH, offset); + cur, new, PRIxPTR_WIDTH, lockreg); return -1; } - old = chip_readb(flash, wrprotect); - /* Early exist if no change (of read/write/lockdown) was requested. */ - if (((old ^ new_bits) & REG2_MASK) == 0) { - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not changed\n", PRIxPTR_WIDTH, offset); + + /* Exit early if no change (of read/write/lockdown bits) was requested. */ + if (((cur ^ new) & REG2_MASK) == 0) { + msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", PRIxPTR_WIDTH, lockreg); return 0; } - /* Normally lockdowns can not be cleared. Try nevertheless if requested. */ - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); - if (chip_readb(flash, wrprotect) != (old & ~REG2_LOCKDOWN)) { - msg_cerr("Lockdown can't be removed at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Normally the lockdown bit can not be cleared. Try nevertheless if requested. */ + if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { + chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg); + cur = chip_readb(flash, lockreg); + if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) { + msg_cwarn("Lockdown can't be removed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } } - /* Change read or write lock? */ - if ((old ^ new_bits) & REG2_RWLOCK) { + + /* Change read and/or write bit */ + if ((cur ^ new) & REG2_RWLOCK) { /* Do not lockdown yet. */ - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); - if (chip_readb(flash, wrprotect) != (new_bits & REG2_RWLOCK)) { - msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & REG2_RWLOCK); + chip_writeb(flash, wanted, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != wanted) { + msg_cerr("Changing lock bits failed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } + msg_cdbg("Changed lock bits at 0x%0*" PRIxPTR " to 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); } - /* Enable lockdown if requested. */ - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", PRIxPTR_WIDTH, offset); - chip_writeb(flash, new_bits, wrprotect); - if (chip_readb(flash, wrprotect) != new_bits) { - msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Eventually, enable lockdown if requested. */ + if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { + chip_writeb(flash, new, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != new) { + msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } + msg_cdbg("Enabled lockdown at 0x%0*" PRIxPTR ".\n", PRIxPTR_WIDTH, lockreg); } return 0; } -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) +static int unlock_regspace2_block_generic(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + off + 2; - uint8_t old = chip_readb(flash, wrprotect); + uint8_t old = chip_readb(flash, lockreg); /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); + return changelock_regspace2_block(flash, lockreg, old, old & ~REG2_RWLOCK); } static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) { const unsigned int elems = flash->chip->total_size * 1024 / block_size; struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; - return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic); } int unlock_regspace2_uniform_64k(struct flashctx *flash) @@ -734,7 +747,7 @@ int unlock_regspace2_block_eraser_0(struct flashctx *flash) // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } int unlock_regspace2_block_eraser_1(struct flashctx *flash) @@ -742,6 +755,6 @@ int unlock_regspace2_block_eraser_1(struct flashctx *flash) // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } -- Kind regards, Stefan Tauner

1 0

[PATCH] Fix handling of write protection at register space address +2.
by Stefan Tauner 20 Dec '14

20 Dec '14

Previously we added the offset of the virtual register in several functions, which produced segfaults. This patch renames a few parameters and reorganizes/fixes various parts of the changelock_regspace2_block() function - hence the rather big diff. Thanks to Roman Lebedev for reporting this issue and testing numerous revisions of this patch. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- The last mail was a bit too quick... this one rearranges the print outs a bit and is hopefully the revision to be committed. I have reworked that stupid function completely. Normally we are not embedding that many mistakes in such a short routine hence the unexpectedly high number of patch iterations... sorry! I was just not reviewing everything before because i only anticipated tiny mistakes :) chipdrivers.h | 1 - jedec.c | 91 +++++++++++++++++++++++++++++++++-------------------------- 2 files changed, 51 insertions(+), 41 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 8529c74..cac94f3 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_32k(struct flashctx *flash); int unlock_regspace2_uniform_64k(struct flashctx *flash); int unlock_regspace2_block_eraser_0(struct flashctx *flash); int unlock_regspace2_block_eraser_1(struct flashctx *flash); -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); int printlock_regspace2_uniform_64k(struct flashctx *flash); int printlock_regspace2_block_eraser_0(struct flashctx *flash); int printlock_regspace2_block_eraser_1(struct flashctx *flash); diff --git a/jedec.c b/jedec.c index 1345b89..4e2b24d 100644 --- a/jedec.c +++ b/jedec.c @@ -589,11 +589,10 @@ static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struc #define REG2_LOCKDOWN (1 << 1) #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) -static int printlock_regspace2_block(const struct flashctx *flash, chipaddr offset) +static int printlock_regspace2_block(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t state = chip_readb(flash, wrprotect); - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, offset); + uint8_t state = chip_readb(flash, lockreg); + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, lockreg); switch (state & REG2_MASK) { case 0: msg_cdbg("Full Access.\n"); @@ -656,47 +655,60 @@ int printlock_regspace2_block_eraser_1(struct flashctx *flash) return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); } -static int changelock_regspace2_block(const struct flashctx *flash, chipaddr offset, uint8_t new_bits) -{ - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t old; - - if (new_bits & ~REG2_MASK) { - msg_cerr("Invalid locking change 0x%02x requested at 0x%0*" PRIxPTR "! " +/* Try to change the lock register at address lockreg from cur to new. + * + * - Try to unlock the lock bit if requested and it is currently set (although this is probably futile). + * - Try to change the read/write bits if requested. + * - Try to set the lockdown bit if requested. + * Return an error immediately if any of this fails. */ +static int changelock_regspace2_block(const struct flashctx *flash, chipaddr lockreg, uint8_t cur, uint8_t new) +{ + /* Only allow changes to known read/write/lockdown bits */ + if (((cur ^ new) & ~REG2_MASK) != 0) { + msg_cerr("Invalid lock change from 0x%02x to 0x%02x requested at 0x%0*" PRIxPTR "!\n" "Please report a bug at flashrom(a)flashrom.org\n", - new_bits, PRIxPTR_WIDTH, offset); + cur, new, PRIxPTR_WIDTH, lockreg); return -1; } - old = chip_readb(flash, wrprotect); - /* Early exist if no change (of read/write/lockdown) was requested. */ - if (((old ^ new_bits) & REG2_MASK) == 0) { - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not changed\n", PRIxPTR_WIDTH, offset); + + /* Exit early if no change (of read/write/lockdown bits) was requested. */ + if (((cur ^ new) & REG2_MASK) == 0) { + msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", PRIxPTR_WIDTH, lockreg); return 0; } - /* Normally lockdowns can not be cleared. Try nevertheless if requested. */ - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); - if (chip_readb(flash, wrprotect) != (old & ~REG2_LOCKDOWN)) { - msg_cerr("Lockdown can't be removed at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Normally the lockdown bit can not be cleared. Try nevertheless if requested. */ + if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { + chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg); + cur = chip_readb(flash, lockreg); + if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) { + msg_cwarn("Lockdown can't be removed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } } - /* Change read or write lock? */ - if ((old ^ new_bits) & REG2_RWLOCK) { + + /* Change read and/or write bit */ + if ((cur ^ new) & REG2_RWLOCK) { /* Do not lockdown yet. */ - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); - if (chip_readb(flash, wrprotect) != (new_bits & REG2_RWLOCK)) { - msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & REG2_RWLOCK); + msg_cdbg("Changing lock bits at 0x%0*" PRIxPTR " to 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, wanted); + chip_writeb(flash, wanted, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != wanted) { + msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } } - /* Enable lockdown if requested. */ - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", PRIxPTR_WIDTH, offset); - chip_writeb(flash, new_bits, wrprotect); - if (chip_readb(flash, wrprotect) != new_bits) { - msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Eventually, enable lockdown if requested. */ + if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { + msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR ".\n", PRIxPTR_WIDTH, lockreg); + chip_writeb(flash, new, lockreg); + if (chip_readb(flash, lockreg) != new) { + msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); return -1; } } @@ -704,19 +716,18 @@ static int changelock_regspace2_block(const struct flashctx *flash, chipaddr off return 0; } -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) +static int unlock_regspace2_block_generic(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + off + 2; - uint8_t old = chip_readb(flash, wrprotect); + uint8_t old = chip_readb(flash, lockreg); /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); + return changelock_regspace2_block(flash, lockreg, old, old & ~REG2_RWLOCK); } static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) { const unsigned int elems = flash->chip->total_size * 1024 / block_size; struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; - return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic); } int unlock_regspace2_uniform_64k(struct flashctx *flash) @@ -734,7 +745,7 @@ int unlock_regspace2_block_eraser_0(struct flashctx *flash) // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } int unlock_regspace2_block_eraser_1(struct flashctx *flash) @@ -742,6 +753,6 @@ int unlock_regspace2_block_eraser_1(struct flashctx *flash) // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } -- Kind regards, Stefan Tauner

1 0

[PATCH] Fix handling of write protection at register space address +2.
by Stefan Tauner 20 Dec '14

20 Dec '14

Previously we added the offset of the virtual register in several functions, which produced segfaults. This patch renames a few parameters and reorganizes/fixes various parts of the changelock_regspace2_block() function - hence the rather big diff. Thanks to Roman Lebedev for reporting this issue and testing numerous revisions of this patch. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- I have reworked that stupid function completely. Normally we are not embedding that many mistakes in such a short routine hence the unexpectedly high number of patch iterations... sorry! I was just not reviewing everything before because i only anticipated tiny mistakes :) chipdrivers.h | 1 - jedec.c | 91 +++++++++++++++++++++++++++++++++-------------------------- 2 files changed, 51 insertions(+), 41 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 8529c74..cac94f3 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_32k(struct flashctx *flash); int unlock_regspace2_uniform_64k(struct flashctx *flash); int unlock_regspace2_block_eraser_0(struct flashctx *flash); int unlock_regspace2_block_eraser_1(struct flashctx *flash); -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); int printlock_regspace2_uniform_64k(struct flashctx *flash); int printlock_regspace2_block_eraser_0(struct flashctx *flash); int printlock_regspace2_block_eraser_1(struct flashctx *flash); diff --git a/jedec.c b/jedec.c index 1345b89..4e2b24d 100644 --- a/jedec.c +++ b/jedec.c @@ -589,11 +589,10 @@ static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struc #define REG2_LOCKDOWN (1 << 1) #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) -static int printlock_regspace2_block(const struct flashctx *flash, chipaddr offset) +static int printlock_regspace2_block(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t state = chip_readb(flash, wrprotect); - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, offset); + uint8_t state = chip_readb(flash, lockreg); + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, lockreg); switch (state & REG2_MASK) { case 0: msg_cdbg("Full Access.\n"); @@ -656,47 +655,60 @@ int printlock_regspace2_block_eraser_1(struct flashctx *flash) return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); } -static int changelock_regspace2_block(const struct flashctx *flash, chipaddr offset, uint8_t new_bits) -{ - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t old; - - if (new_bits & ~REG2_MASK) { - msg_cerr("Invalid locking change 0x%02x requested at 0x%0*" PRIxPTR "! " +/* Try to change the lock register at address lockreg from cur to new. + * + * - Try to unlock the lock bit if requested and it is currently set (although this is probably futile). + * - Try to change the read/write bits if requested. + * - Try to set the lockdown bit if requested. + * Return an error immediately if any of this fails. */ +static int changelock_regspace2_block(const struct flashctx *flash, chipaddr lockreg, uint8_t cur, uint8_t new) +{ + /* Only allow changes to known read/write/lockdown bits */ + if (((cur ^ new) & ~REG2_MASK) != 0) { + msg_cerr("Invalid lock change from 0x%02x to 0x%02x requested at 0x%0*" PRIxPTR "!\n" "Please report a bug at flashrom(a)flashrom.org\n", - new_bits, PRIxPTR_WIDTH, offset); + cur, new, PRIxPTR_WIDTH, lockreg); return -1; } - old = chip_readb(flash, wrprotect); - /* Early exist if no change (of read/write/lockdown) was requested. */ - if (((old ^ new_bits) & REG2_MASK) == 0) { - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not changed\n", PRIxPTR_WIDTH, offset); + + /* Exit early if no change (of read/write/lockdown bits) was requested. */ + if (((cur ^ new) & REG2_MASK) == 0) { + msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", PRIxPTR_WIDTH, lockreg); return 0; } - /* Normally lockdowns can not be cleared. Try nevertheless if requested. */ - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); - if (chip_readb(flash, wrprotect) != (old & ~REG2_LOCKDOWN)) { - msg_cerr("Lockdown can't be removed at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Normally the lockdown bit can not be cleared. Try nevertheless if requested. */ + if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { + chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg); + cur = chip_readb(flash, lockreg); + if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) { + msg_cwarn("Lockdown can't be removed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } } - /* Change read or write lock? */ - if ((old ^ new_bits) & REG2_RWLOCK) { + + /* Change read and/or write bit */ + if ((cur ^ new) & REG2_RWLOCK) { /* Do not lockdown yet. */ - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); - if (chip_readb(flash, wrprotect) != (new_bits & REG2_RWLOCK)) { - msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & REG2_RWLOCK); + msg_cdbg("Changing lock bits at 0x%0*" PRIxPTR " to 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, wanted); + chip_writeb(flash, wanted, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != wanted) { + msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } } - /* Enable lockdown if requested. */ - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", PRIxPTR_WIDTH, offset); - chip_writeb(flash, new_bits, wrprotect); - if (chip_readb(flash, wrprotect) != new_bits) { - msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Eventually, enable lockdown if requested. */ + if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { + msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR ".\n", PRIxPTR_WIDTH, lockreg); + chip_writeb(flash, new, lockreg); + if (chip_readb(flash, lockreg) != new) { + msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); return -1; } } @@ -704,19 +716,18 @@ static int changelock_regspace2_block(const struct flashctx *flash, chipaddr off return 0; } -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) +static int unlock_regspace2_block_generic(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + off + 2; - uint8_t old = chip_readb(flash, wrprotect); + uint8_t old = chip_readb(flash, lockreg); /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); + return changelock_regspace2_block(flash, lockreg, old, old & ~REG2_RWLOCK); } static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) { const unsigned int elems = flash->chip->total_size * 1024 / block_size; struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; - return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic); } int unlock_regspace2_uniform_64k(struct flashctx *flash) @@ -734,7 +745,7 @@ int unlock_regspace2_block_eraser_0(struct flashctx *flash) // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } int unlock_regspace2_block_eraser_1(struct flashctx *flash) @@ -742,6 +753,6 @@ int unlock_regspace2_block_eraser_1(struct flashctx *flash) // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } -- Kind regards, Stefan Tauner

1 0

Motherboard Asus M3N-H/HDMI
by Sofia SERRES 20 Dec '14

20 Dec '14

flashrom v0.9.7-r1782 on Linux 3.16.0-29-lowlatency (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian Command line (3 args): flashrom --programmer internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 1092M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 1004 us, 10000 myus = 9996 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M3N-H/HDMI" DMI string baseboard-version: "1.XX" Found ITE Super I/O, ID 0x8716 on port 0x2e Found chipset "NVIDIA MCP78S" with PCI ID 10de:075c. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Found SMBus device 10de:0752 at 00:01:1 MCP SPI BAR is at 0xfdf80000 SPI control is 0xc012, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. No IT87* serial flash segment enabled. The following protocols are supported: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032/A25LQ32A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512A, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F1024(A), 128 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F2048, 256 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F4096, 512 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ESMT F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25S10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25S20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25S40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25S80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25S16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25S32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25S64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q20(B), 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q80(B), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q16(B), 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q32(B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q64(B), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q128B, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25T80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L512(E)/MX25V512(C), 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005(C)/MX25L1006E, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005(C), 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005(A/C), 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005/MX25V8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Found Macronix flash chip "MX25L8005/MX25V8005" (1024 kB, SPI) at physical address 0xfff00000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1605A/MX25L1606E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1605D/MX25L1608D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3206E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405(D), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6406E/MX25L6436E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6445E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805(D), 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25U1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25U3235E/F, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25U6435E/F, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25P20-old, 256 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25PX80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M45PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M45PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M45PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M45PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST M45PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST N25Q128..1E, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Micron/Numonyx/ST N25Q128..3E, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Nantronics N25S10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Nantronics N25S20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Nantronics N25S40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Nantronics N25S80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Nantronics N25S16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LD256C, 32 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LD512(C), 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LD010(C), 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LD020(C), 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LD040(C), 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512(A), 64 kB: probe_spi_res3: id1 0x1313, id2 0x13 Probing for PMC Pm25LV010, 128 kB: probe_spi_res3: id1 0x1313, id2 0x13 Probing for PMC Pm25LV010A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo LE25FW203A, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo LE25FW403A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo LE25FW418A, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for Sanyo LE25FW806, 1024 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for Sanyo LE25FW808, 1024 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL204K, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL208K, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL116K/S25FL216K, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL128S......0, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25LF080(A), 1024 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF512A, 64 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF020, 256 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF020B, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q80.V, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16.V, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32.V, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64.V, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128.V, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q20.W, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q40.W, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q80.W, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16.W, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32.W, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64.W, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Unknown SFDP-capable chip, 0 kB: No SFDP signature found. Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Found Macronix flash chip "MX25L8005/MX25V8005" (1024 kB, SPI). No operations were specified.

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Flashrom with FTDI support
by Ohad Benjamin 18 Dec '14

18 Dec '14

Hi, I tried using the precompiled 0.9.7 version mingw32-w64-flashrom-r1781.exe This precompiled version has no FTDI support but should support my EEPROM Micron's N25Q. I tried compiling my own version from source, but the output could not communicate with the FTDI port. Could you please upload a version that supports FTDI and my EEPROM. Thank you, Ohad Benjamin, Sr. Embedded SW Engineer Office: +972-9-7667600 ext 122 | Fax: +972-9-7667610 ohad(a)panpwr.com<mailto:ohad@panpwr.com> | www.panpwr.com<http://www.panpwr.com/> [Panoramic_logo_new]

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Re: [flashrom] [PATCH] Fix handling of write protection at register space address +2.
by Roman Lebedev 17 Dec '14

17 Dec '14

Hi. So i have tested this third patch version, and i must say that it certainly a progress :) it still produces same correct fw image (same md5), but i this time, the message is different. # flashrom --programmer internal -r 1002.bin.patch3 -V flashrom v0.9.7-r1858 on Linux 3.16.0-4-686-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.9.2, little endian Command line (5 args): flashrom --programmer internal -r 1002.bin.patch3 -V Calibrating delay loop... OS timer resolution is 1 usecs, 534M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 9999 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "ASUSTeK COMPUTER INC." DMI string system-product-name: "PCH-DR" DMI string system-version: "1.XX " DMI string baseboard-manufacturer: "ASUSTek Computer INC." DMI string baseboard-product-name: "PCH-DR" DMI string baseboard-version: "1.XX " Found Winbond Super I/O, id 0x82 W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Please send the output of "flashrom -V -p internal" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel 6300ESB" with PCI ID 8086:25a1. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled OK. The following protocols are supported: FWH. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x08, id2 0x14, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) mapped at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x08, id2 0x14, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Changing locking status at 0xb73df002 to 0x00 Locking status change FAILED at 0xb73df002! Reading flash... done. Restoring PCI config space for 00:1f:0 reg 0x4e Roman. On Mon, Dec 15, 2014 at 1:32 AM, Stefan Tauner < stefan.tauner(a)alumni.tuwien.ac.at> wrote: > > Previously we added the offset of the virtual register in several > functions, > which produced segfaults. This patch renames a few parameters hence the > rather big diff. > > Thanks to Roman Lebedev for reporting this issue and testing the patch. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > > Yes, you are right Roman, stupid error on my side. I forgot to add > the negation I announced in my previous email: line 660 should > contain ~REG2_MASK instead of just REG2_MASK. > > chipdrivers.h | 1 - > jedec.c | 65 > +++++++++++++++++++++++++++-------------------------------- > 2 files changed, 30 insertions(+), 36 deletions(-) > > diff --git a/chipdrivers.h b/chipdrivers.h > index 8529c74..cac94f3 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_32k(struct flashctx > *flash); > int unlock_regspace2_uniform_64k(struct flashctx *flash); > int unlock_regspace2_block_eraser_0(struct flashctx *flash); > int unlock_regspace2_block_eraser_1(struct flashctx *flash); > -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); > int printlock_regspace2_uniform_64k(struct flashctx *flash); > int printlock_regspace2_block_eraser_0(struct flashctx *flash); > int printlock_regspace2_block_eraser_1(struct flashctx *flash); > diff --git a/jedec.c b/jedec.c > index 1345b89..f92b354 100644 > --- a/jedec.c > +++ b/jedec.c > @@ -589,11 +589,10 @@ static int regspace2_walk_unlockblocks(const struct > flashctx *flash, const struc > #define REG2_LOCKDOWN (1 << 1) > #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) > > -static int printlock_regspace2_block(const struct flashctx *flash, > chipaddr offset) > +static int printlock_regspace2_block(const struct flashctx *flash, > chipaddr lockreg) > { > - chipaddr wrprotect = flash->virtual_registers + offset + 2; > - uint8_t state = chip_readb(flash, wrprotect); > - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", > PRIxPTR_WIDTH, offset); > + uint8_t state = chip_readb(flash, lockreg); > + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", > PRIxPTR_WIDTH, lockreg); > switch (state & REG2_MASK) { > case 0: > msg_cdbg("Full Access.\n"); > @@ -656,47 +655,44 @@ int printlock_regspace2_block_eraser_1(struct > flashctx *flash) > return regspace2_walk_unlockblocks(flash, unlockblocks, > &printlock_regspace2_block); > } > > -static int changelock_regspace2_block(const struct flashctx *flash, > chipaddr offset, uint8_t new_bits) > +static int changelock_regspace2_block(const struct flashctx *flash, > chipaddr lockreg, uint8_t old, uint8_t new) > { > - chipaddr wrprotect = flash->virtual_registers + offset + 2; > - uint8_t old; > - > - if (new_bits & ~REG2_MASK) { > - msg_cerr("Invalid locking change 0x%02x requested at > 0x%0*" PRIxPTR "! " > + if (((old ^ new) & ~REG2_MASK) != 0) { > + msg_cerr("Invalid locking change from 0x%02x to 0x%02x > requested at 0x%0*" PRIxPTR "!\n" > "Please report a bug at flashrom(a)flashrom.org\n", > - new_bits, PRIxPTR_WIDTH, offset); > + old, new, PRIxPTR_WIDTH, lockreg); > return -1; > } > - old = chip_readb(flash, wrprotect); > /* Early exist if no change (of read/write/lockdown) was > requested. */ > - if (((old ^ new_bits) & REG2_MASK) == 0) { > - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not > changed\n", PRIxPTR_WIDTH, offset); > + if (((old ^ new) & REG2_MASK) == 0) { > + msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not > changed\n", PRIxPTR_WIDTH, lockreg); > return 0; > } > /* Normally lockdowns can not be cleared. Try nevertheless if > requested. */ > - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { > - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); > - if (chip_readb(flash, wrprotect) != (old & > ~REG2_LOCKDOWN)) { > - msg_cerr("Lockdown can't be removed at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + if ((old & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { > + chip_writeb(flash, old & ~REG2_LOCKDOWN, lockreg); > + if (chip_readb(flash, lockreg) != (old & ~REG2_LOCKDOWN)) { > + msg_cerr("Lockdown can't be removed at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); > return -1; > } > } > /* Change read or write lock? */ > - if ((old ^ new_bits) & REG2_RWLOCK) { > + if ((old ^ new) & REG2_RWLOCK) { > /* Do not lockdown yet. */ > - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to > 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); > - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); > - if (chip_readb(flash, wrprotect) != (new_bits & > REG2_RWLOCK)) { > - msg_cerr("Locking status change FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to > 0x%02x\n", > + PRIxPTR_WIDTH, lockreg, new & REG2_RWLOCK); > + chip_writeb(flash, new & REG2_RWLOCK, lockreg); > + if (chip_readb(flash, lockreg) != (new & REG2_RWLOCK)) { > + msg_cerr("Locking status change FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); > return -1; > } > } > /* Enable lockdown if requested. */ > - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { > - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", > PRIxPTR_WIDTH, offset); > - chip_writeb(flash, new_bits, wrprotect); > - if (chip_readb(flash, wrprotect) != new_bits) { > - msg_cerr("Enabling lockdown FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + if (!(old & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { > + msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", > PRIxPTR_WIDTH, lockreg); > + chip_writeb(flash, new, lockreg); > + if (chip_readb(flash, lockreg) != new) { > + msg_cerr("Enabling lockdown FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); > return -1; > } > } > @@ -704,19 +700,18 @@ static int changelock_regspace2_block(const struct > flashctx *flash, chipaddr off > return 0; > } > > -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) > +static int unlock_regspace2_block_generic(const struct flashctx *flash, > chipaddr lockreg) > { > - chipaddr wrprotect = flash->virtual_registers + off + 2; > - uint8_t old = chip_readb(flash, wrprotect); > + uint8_t old = chip_readb(flash, lockreg); > /* We don't care for the lockdown bit as long as the RW locks are > 0 after we're done */ > - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); > + return changelock_regspace2_block(flash, lockreg, old, old & > ~REG2_RWLOCK); > } > > static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long > block_size) > { > const unsigned int elems = flash->chip->total_size * 1024 / > block_size; > struct unlockblock blocks[2] = {{.size = block_size, .count = > elems}}; > - return regspace2_walk_unlockblocks(flash, blocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, blocks, > &unlock_regspace2_block_generic); > } > > int unlock_regspace2_uniform_64k(struct flashctx *flash) > @@ -734,7 +729,7 @@ int unlock_regspace2_block_eraser_0(struct flashctx > *flash) > // FIXME: this depends on the eraseblocks not to be filled up > completely (i.e. to be null-terminated). > const struct unlockblock *unlockblocks = > (const struct unlockblock > *)flash->chip->block_erasers[0].eraseblocks; > - return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block_generic); > } > > int unlock_regspace2_block_eraser_1(struct flashctx *flash) > @@ -742,6 +737,6 @@ int unlock_regspace2_block_eraser_1(struct flashctx > *flash) > // FIXME: this depends on the eraseblocks not to be filled up > completely (i.e. to be null-terminated). > const struct unlockblock *unlockblocks = > (const struct unlockblock > *)flash->chip->block_erasers[1].eraseblocks; > - return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block_generic); > } > > -- > Kind regards, Stefan Tauner > >

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Re: [flashrom] Testing of EN25QH16
by Stefan Tauner 15 Dec '14

15 Dec '14

On Sun, 14 Dec 2014 15:30:22 -0800 Ben Johnson <circuitben(a)gmail.com> wrote: > I have tested read, erase, and write on an Eon EN25QH16. > The program asked me to send a report, so here it is. > […] Hello Ben, thanks for your report! I have marked the flash chip as fully tested and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Verified Asus P5LD2-VM
by Dima Veselov 15 Dec '14

15 Dec '14

Hello, I confirm flashing Asus P5LD2-VM motherboard. flashrom -p internal:laptop=this_is_not_a_laptop,boardenable=force -w P5LD2-VM-1401.ROM I didn't saved logfile of flashing, but rerun command to get some technical data attached. Flash succeeded, motherboard is alive. -- Sincerelly yours

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Testing of EN25QH16
by Ben Johnson 15 Dec '14

15 Dec '14

I have tested read, erase, and write on an Eon EN25QH16. The program asked me to send a report, so here it is. I was using the most recent git version, commit 4524e5f73eff4f3244fc94ce87039af5480a16bc. I modified the makefile slightly to work with the current libftdi (v1.2), but these changes were only for the pkg-config name and fixing some include problems. I used an FTDI FT2232H mini-module, configured to be self-powered. The target was mounted on a small breakout board with a 47nF bypass capacitor and connected to the mini-module with individual jumper wires about six inches long. The HOLD# pin was tied high at the device. The WP# was tied low/high at the device as described below. The logs are (in order of operations): log_read: Reading before any erase or write operations were attempted. log_erase_wp: Erasing with WP# tied low (failed, and the chip contents were retained). At this point, I tied WP# high. log_erase: Erasing (succeeded). log_read_after_erase: Reading after erasing but before writing. The data was verified to be all FF's. log_write: Writing (succeeded with verification). log_read_after_write: Reading after the erase and write operations. The data read here was verified to be correct.

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[PATCH] Fix handling of write protection at register space address +2.
by Stefan Tauner 14 Dec '14

14 Dec '14

Previously we added the offset of the virtual register in several functions, which produced segfaults. This patch renames a few parameters hence the rather big diff. Thanks to Roman Lebedev for reporting this issue and testing the patch. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Yes, you are right Roman, stupid error on my side. I forgot to add the negation I announced in my previous email: line 660 should contain ~REG2_MASK instead of just REG2_MASK. chipdrivers.h | 1 - jedec.c | 65 +++++++++++++++++++++++++++-------------------------------- 2 files changed, 30 insertions(+), 36 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 8529c74..cac94f3 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_32k(struct flashctx *flash); int unlock_regspace2_uniform_64k(struct flashctx *flash); int unlock_regspace2_block_eraser_0(struct flashctx *flash); int unlock_regspace2_block_eraser_1(struct flashctx *flash); -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); int printlock_regspace2_uniform_64k(struct flashctx *flash); int printlock_regspace2_block_eraser_0(struct flashctx *flash); int printlock_regspace2_block_eraser_1(struct flashctx *flash); diff --git a/jedec.c b/jedec.c index 1345b89..f92b354 100644 --- a/jedec.c +++ b/jedec.c @@ -589,11 +589,10 @@ static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struc #define REG2_LOCKDOWN (1 << 1) #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) -static int printlock_regspace2_block(const struct flashctx *flash, chipaddr offset) +static int printlock_regspace2_block(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t state = chip_readb(flash, wrprotect); - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, offset); + uint8_t state = chip_readb(flash, lockreg); + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, lockreg); switch (state & REG2_MASK) { case 0: msg_cdbg("Full Access.\n"); @@ -656,47 +655,44 @@ int printlock_regspace2_block_eraser_1(struct flashctx *flash) return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); } -static int changelock_regspace2_block(const struct flashctx *flash, chipaddr offset, uint8_t new_bits) +static int changelock_regspace2_block(const struct flashctx *flash, chipaddr lockreg, uint8_t old, uint8_t new) { - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t old; - - if (new_bits & ~REG2_MASK) { - msg_cerr("Invalid locking change 0x%02x requested at 0x%0*" PRIxPTR "! " + if (((old ^ new) & ~REG2_MASK) != 0) { + msg_cerr("Invalid locking change from 0x%02x to 0x%02x requested at 0x%0*" PRIxPTR "!\n" "Please report a bug at flashrom(a)flashrom.org\n", - new_bits, PRIxPTR_WIDTH, offset); + old, new, PRIxPTR_WIDTH, lockreg); return -1; } - old = chip_readb(flash, wrprotect); /* Early exist if no change (of read/write/lockdown) was requested. */ - if (((old ^ new_bits) & REG2_MASK) == 0) { - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not changed\n", PRIxPTR_WIDTH, offset); + if (((old ^ new) & REG2_MASK) == 0) { + msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not changed\n", PRIxPTR_WIDTH, lockreg); return 0; } /* Normally lockdowns can not be cleared. Try nevertheless if requested. */ - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); - if (chip_readb(flash, wrprotect) != (old & ~REG2_LOCKDOWN)) { - msg_cerr("Lockdown can't be removed at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + if ((old & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { + chip_writeb(flash, old & ~REG2_LOCKDOWN, lockreg); + if (chip_readb(flash, lockreg) != (old & ~REG2_LOCKDOWN)) { + msg_cerr("Lockdown can't be removed at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); return -1; } } /* Change read or write lock? */ - if ((old ^ new_bits) & REG2_RWLOCK) { + if ((old ^ new) & REG2_RWLOCK) { /* Do not lockdown yet. */ - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); - if (chip_readb(flash, wrprotect) != (new_bits & REG2_RWLOCK)) { - msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to 0x%02x\n", + PRIxPTR_WIDTH, lockreg, new & REG2_RWLOCK); + chip_writeb(flash, new & REG2_RWLOCK, lockreg); + if (chip_readb(flash, lockreg) != (new & REG2_RWLOCK)) { + msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); return -1; } } /* Enable lockdown if requested. */ - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", PRIxPTR_WIDTH, offset); - chip_writeb(flash, new_bits, wrprotect); - if (chip_readb(flash, wrprotect) != new_bits) { - msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + if (!(old & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { + msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", PRIxPTR_WIDTH, lockreg); + chip_writeb(flash, new, lockreg); + if (chip_readb(flash, lockreg) != new) { + msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); return -1; } } @@ -704,19 +700,18 @@ static int changelock_regspace2_block(const struct flashctx *flash, chipaddr off return 0; } -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) +static int unlock_regspace2_block_generic(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + off + 2; - uint8_t old = chip_readb(flash, wrprotect); + uint8_t old = chip_readb(flash, lockreg); /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); + return changelock_regspace2_block(flash, lockreg, old, old & ~REG2_RWLOCK); } static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) { const unsigned int elems = flash->chip->total_size * 1024 / block_size; struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; - return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic); } int unlock_regspace2_uniform_64k(struct flashctx *flash) @@ -734,7 +729,7 @@ int unlock_regspace2_block_eraser_0(struct flashctx *flash) // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } int unlock_regspace2_block_eraser_1(struct flashctx *flash) @@ -742,6 +737,6 @@ int unlock_regspace2_block_eraser_1(struct flashctx *flash) // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } -- Kind regards, Stefan Tauner

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[PATCH] Fix the --mainboard parameter that controls board enables.
by Stefan Tauner 14 Dec '14

14 Dec '14

We refactored board_match_name()/--mainboard handling in r1577 and apparently broke it because since then we were always comparing to the respective coreboot values of board and vendor names instead of the user-supplied strings. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- board_enable.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/board_enable.c b/board_enable.c index 966c490..456e206 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2524,20 +2524,24 @@ int board_parse_parameter(const char *boardstring, const char **vendor, const ch /* * Match boards on vendor and model name. - * Hint: the parameters can come either from the coreboot table or the command line (i.e. the user). + * The string parameters can come either from the coreboot table or the command line (i.e. the user). + * The boolean needs to be set accordingly to compare them to the right entries of the board enables table. * Require main PCI IDs to match too as extra safety. - * vendor and model must be non-NULL! + * Parameters vendor and model must be non-NULL! */ -static const struct board_match *board_match_name(const char *vendor, const char *model) +static const struct board_match *board_match_name(const char *vendor, const char *model, bool cb) { const struct board_match *board = board_matches; const struct board_match *partmatch = NULL; for (; board->vendor_name; board++) { - if (!board->lb_vendor || strcasecmp(board->lb_vendor, vendor)) + const char *cur_vendor = cb ? board->lb_vendor : board->vendor_name; + const char *cur_model = cb ? board->lb_part : board->board_name; + + if (!cur_vendor || strcasecmp(cur_vendor, vendor)) continue; - if (!board->lb_part || strcasecmp(board->lb_part, model)) + if (!cur_model || strcasecmp(cur_model, model)) continue; if (!pci_dev_find(board->first_vendor, board->first_device)) { @@ -2680,7 +2684,7 @@ int board_flash_enable(const char *vendor, const char *model, const char *cb_ven int ret = 0; if (vendor != NULL && model != NULL) { - board = board_match_name(vendor, model); + board = board_match_name(vendor, model, false); if (!board) { /* If a board was given by the user it has to match, else we abort here. */ msg_perr("No suitable board enable found for vendor=\"%s\", model=\"%s\".\n", vendor, model); @@ -2688,7 +2692,7 @@ int board_flash_enable(const char *vendor, const char *model, const char *cb_ven } } if (board == NULL && cb_vendor != NULL && cb_model != NULL) { - board = board_match_name(cb_vendor, cb_model); + board = board_match_name(cb_vendor, cb_model, true); if (!board) { /* Failure is an option here, because many cb boards don't require an enable. */ msg_pdbg2("No board enable found matching coreboot IDs vendor=\"%s\", model=\"%s\".\n", cb_vendor, cb_model); -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH] Fix handling of write protection at register space address +2.
by Roman Lebedev 14 Dec '14

14 Dec '14

Hi. I have tested it, it still produces same correct fw image (same md5), but i think that the message is still there (unless i horribly miss-apply patch, which is unlikely) # flashrom --programmer internal -r 1002.bin.patch2 -V flashrom v0.9.7-r1857 on Linux 3.16.0-4-686-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.9.2, little endian Command line (5 args): flashrom --programmer internal -r 1002.bin.patch2 -V Calibrating delay loop... OS timer resolution is 1 usecs, 572M loops per second, 10 myus = 11 us, 100 myus = 147 us, 1000 myus = 1094 us, 10000 myus = 10740 us, 4 myus = 7 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "ASUSTeK COMPUTER INC." DMI string system-product-name: "PCH-DR" DMI string system-version: "1.XX " DMI string baseboard-manufacturer: "ASUSTek Computer INC." DMI string baseboard-product-name: "PCH-DR" DMI string baseboard-version: "1.XX " Found Winbond Super I/O, id 0x82 W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Please send the output of "flashrom -V -p internal" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel 6300ESB" with PCI ID 8086:25a1. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled OK. The following protocols are supported: FWH. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x08, id2 0x14, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) mapped at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x08, id2 0x14, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Invalid locking change from 0xf9 to 0xf8 requested at 0xb73cf002! Please report a bug at flashrom(a)flashrom.org Reading flash... done. Restoring PCI config space for 00:1f:0 reg 0x4e Roman. On Fri, Dec 12, 2014 at 3:25 AM, Stefan Tauner < stefan.tauner(a)alumni.tuwien.ac.at> wrote: > > Previously we added the offset of the virtual register in several > functions cumulatively, which produced segfaults. This patch renames > a few parameters hence the rather big diff. > > Thanks to Roman Lebedev for reporting this issue and testing the patch. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > > Roman, if you got some time could you please retest this refined version > of the patch (it is against r1857)? It should behave pretty much the same > on your setup apart from not showing the message you saw with the last > version. > > chipdrivers.h | 1 - > jedec.c | 65 > +++++++++++++++++++++++++++-------------------------------- > 2 files changed, 30 insertions(+), 36 deletions(-) > > diff --git a/chipdrivers.h b/chipdrivers.h > index 8529c74..cac94f3 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_32k(struct flashctx > *flash); > int unlock_regspace2_uniform_64k(struct flashctx *flash); > int unlock_regspace2_block_eraser_0(struct flashctx *flash); > int unlock_regspace2_block_eraser_1(struct flashctx *flash); > -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); > int printlock_regspace2_uniform_64k(struct flashctx *flash); > int printlock_regspace2_block_eraser_0(struct flashctx *flash); > int printlock_regspace2_block_eraser_1(struct flashctx *flash); > diff --git a/jedec.c b/jedec.c > index 1345b89..6de6745 100644 > --- a/jedec.c > +++ b/jedec.c > @@ -589,11 +589,10 @@ static int regspace2_walk_unlockblocks(const struct > flashctx *flash, const struc > #define REG2_LOCKDOWN (1 << 1) > #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) > > -static int printlock_regspace2_block(const struct flashctx *flash, > chipaddr offset) > +static int printlock_regspace2_block(const struct flashctx *flash, > chipaddr lockreg) > { > - chipaddr wrprotect = flash->virtual_registers + offset + 2; > - uint8_t state = chip_readb(flash, wrprotect); > - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", > PRIxPTR_WIDTH, offset); > + uint8_t state = chip_readb(flash, lockreg); > + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", > PRIxPTR_WIDTH, lockreg); > switch (state & REG2_MASK) { > case 0: > msg_cdbg("Full Access.\n"); > @@ -656,47 +655,44 @@ int printlock_regspace2_block_eraser_1(struct > flashctx *flash) > return regspace2_walk_unlockblocks(flash, unlockblocks, > &printlock_regspace2_block); > } > > -static int changelock_regspace2_block(const struct flashctx *flash, > chipaddr offset, uint8_t new_bits) > +static int changelock_regspace2_block(const struct flashctx *flash, > chipaddr lockreg, uint8_t old, uint8_t new) > { > - chipaddr wrprotect = flash->virtual_registers + offset + 2; > - uint8_t old; > - > - if (new_bits & ~REG2_MASK) { > - msg_cerr("Invalid locking change 0x%02x requested at > 0x%0*" PRIxPTR "! " > + if (((old ^ new) & REG2_MASK) != 0) { > + msg_cerr("Invalid locking change from 0x%02x to 0x%02x > requested at 0x%0*" PRIxPTR "!\n" > "Please report a bug at flashrom(a)flashrom.org\n", > - new_bits, PRIxPTR_WIDTH, offset); > + old, new, PRIxPTR_WIDTH, lockreg); > return -1; > } > - old = chip_readb(flash, wrprotect); > /* Early exist if no change (of read/write/lockdown) was > requested. */ > - if (((old ^ new_bits) & REG2_MASK) == 0) { > - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not > changed\n", PRIxPTR_WIDTH, offset); > + if (((old ^ new) & REG2_MASK) == 0) { > + msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not > changed\n", PRIxPTR_WIDTH, lockreg); > return 0; > } > /* Normally lockdowns can not be cleared. Try nevertheless if > requested. */ > - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { > - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); > - if (chip_readb(flash, wrprotect) != (old & > ~REG2_LOCKDOWN)) { > - msg_cerr("Lockdown can't be removed at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + if ((old & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { > + chip_writeb(flash, old & ~REG2_LOCKDOWN, lockreg); > + if (chip_readb(flash, lockreg) != (old & ~REG2_LOCKDOWN)) { > + msg_cerr("Lockdown can't be removed at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); > return -1; > } > } > /* Change read or write lock? */ > - if ((old ^ new_bits) & REG2_RWLOCK) { > + if ((old ^ new) & REG2_RWLOCK) { > /* Do not lockdown yet. */ > - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to > 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); > - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); > - if (chip_readb(flash, wrprotect) != (new_bits & > REG2_RWLOCK)) { > - msg_cerr("Locking status change FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to > 0x%02x\n", > + PRIxPTR_WIDTH, lockreg, new & REG2_RWLOCK); > + chip_writeb(flash, new & REG2_RWLOCK, lockreg); > + if (chip_readb(flash, lockreg) != (new & REG2_RWLOCK)) { > + msg_cerr("Locking status change FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); > return -1; > } > } > /* Enable lockdown if requested. */ > - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { > - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", > PRIxPTR_WIDTH, offset); > - chip_writeb(flash, new_bits, wrprotect); > - if (chip_readb(flash, wrprotect) != new_bits) { > - msg_cerr("Enabling lockdown FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + if (!(old & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { > + msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", > PRIxPTR_WIDTH, lockreg); > + chip_writeb(flash, new, lockreg); > + if (chip_readb(flash, lockreg) != new) { > + msg_cerr("Enabling lockdown FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, lockreg); > return -1; > } > } > @@ -704,19 +700,18 @@ static int changelock_regspace2_block(const struct > flashctx *flash, chipaddr off > return 0; > } > > -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) > +static int unlock_regspace2_block_generic(const struct flashctx *flash, > chipaddr lockreg) > { > - chipaddr wrprotect = flash->virtual_registers + off + 2; > - uint8_t old = chip_readb(flash, wrprotect); > + uint8_t old = chip_readb(flash, lockreg); > /* We don't care for the lockdown bit as long as the RW locks are > 0 after we're done */ > - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); > + return changelock_regspace2_block(flash, lockreg, old, old & > ~REG2_RWLOCK); > } > > static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long > block_size) > { > const unsigned int elems = flash->chip->total_size * 1024 / > block_size; > struct unlockblock blocks[2] = {{.size = block_size, .count = > elems}}; > - return regspace2_walk_unlockblocks(flash, blocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, blocks, > &unlock_regspace2_block_generic); > } > > int unlock_regspace2_uniform_64k(struct flashctx *flash) > @@ -734,7 +729,7 @@ int unlock_regspace2_block_eraser_0(struct flashctx > *flash) > // FIXME: this depends on the eraseblocks not to be filled up > completely (i.e. to be null-terminated). > const struct unlockblock *unlockblocks = > (const struct unlockblock > *)flash->chip->block_erasers[0].eraseblocks; > - return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block_generic); > } > > int unlock_regspace2_block_eraser_1(struct flashctx *flash) > @@ -742,6 +737,6 @@ int unlock_regspace2_block_eraser_1(struct flashctx > *flash) > // FIXME: this depends on the eraseblocks not to be filled up > completely (i.e. to be null-terminated). > const struct unlockblock *unlockblocks = > (const struct unlockblock > *)flash->chip->block_erasers[1].eraseblocks; > - return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block_generic); > } > > -- > Kind regards, Stefan Tauner > >

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Intel 28F001BN/BX-T erase/write operation verified on 3C905B-TXNM
by Lu Xie 12 Dec '14

12 Dec '14

Hi, I tried programming Intel 28F001BN/BX-T on 3C905B-TXNM but it failed at erase/write. I checked that chip's datasheet and it says PIN 1 and 30 must be pulled to 12V to accept erase/write operation, but the card can only offer 5V at PIN 1 and NC at PIN 30. So I wired 12V to the two pins and then flashrom erased/wrote the chip successfully. Please check the attached output files for the two attempts. Lu

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[commit] r1858 - trunk
by repository service 12 Dec '14

12 Dec '14

Author: stefanct Date: Fri Dec 12 01:32:03 2014 New Revision: 1858 URL: http://flashrom.org/trac/flashrom/changeset/1858 Log: Add support for Spansion S25FL127S. This flash chip can be configured (one time) to use 64 KiB or 256 KiB sectors. Additionally, in the 64 KiB mode it supports 16 4 KiB sub-sectors that can be (one time) programmed to be on the top or bottom of the device. The sub-sectors can be erased with the 0x20 opcode but because this opcode does not work with the remaining sectors and flashrom can not cope with that the 0x20 opcode is not supported yet. This patch adds two definitions, one for the 64 KiB and 256 KiB configuration respectively. The device also shares the RDID with the various S25FL128 devices so we have to increase the maximum number of successfully probed chips to 8. The 64 KiB mode was tested on real hardware. Signed-off-by: Jernej Škrabec <jernej.skrabec(a)planet.si> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/cli_classic.c trunk/flashchips.c trunk/flashchips.h Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Sun Dec 7 22:57:53 2014 (r1857) +++ trunk/cli_classic.c Fri Dec 12 01:32:03 2014 (r1858) @@ -91,9 +91,9 @@ int main(int argc, char *argv[]) { - /* Probe for up to three flash chips. */ const struct flashchip *chip = NULL; - struct flashctx flashes[6] = {{0}}; + /* Probe for up to eight flash chips. */ + struct flashctx flashes[8] = {{0}}; struct flashctx *fill_flash; const char *name; int namelen, opt, i, j; Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Dec 7 22:57:53 2014 (r1857) +++ trunk/flashchips.c Fri Dec 12 01:32:03 2014 (r1858) @@ -10464,6 +10464,83 @@ { .vendor = "Spansion", + .name = "S25FL127S-64kB", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128, + .total_size = 16384, + .page_size = 256, + /* supports 4B addressing */ + /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + /* FIXME: we should distinguish the configuration on probing time like we do for AT45DB chips */ + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + /* This chip supports erasing of 32 so-called "parameter sectors" with + * opcode 0x20 which may be configured to be on top or bottom of the address + * space. Trying to access an address outside these 4kB blocks does have no + * effect on the memory contents, e.g. + .eraseblocks = { + {4 * 1024, 32}, + {64 * 1024, 254} // inaccessible + }, + .block_erase = spi_block_erase_20, + }, { */ + .eraseblocks = { { 64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_srwd, + .unlock = spi_disable_blockprotect_bp2_srwd, /* #WP pin write-protects SRWP bit. */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Spansion", + .name = "S25FL127S-256kB", /* uniform 256kB sectors */ + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128, + .total_size = 16384, + .page_size = 512, + /* supports 4B addressing */ + /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_srwd, + .unlock = spi_disable_blockprotect_bp2_srwd, /* #WP pin write-protects SRWP bit. */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Spansion", .name = "S25FL128P......0", /* uniform 64 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Dec 7 22:57:53 2014 (r1857) +++ trunk/flashchips.h Fri Dec 12 01:32:03 2014 (r1858) @@ -600,7 +600,7 @@ #define SPANSION_S25FL016A 0x0214 #define SPANSION_S25FL032A 0x0215 /* Same as S25FL032P, but the latter supports EDI and CFI */ #define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */ -#define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */ +#define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL127S, S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */ #define SPANSION_S25FL256 0x0219 #define SPANSION_S25FL512 0x0220 #define SPANSION_S25FL204 0x4013

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Re: [flashrom] [PATCH] Fix handling of write protection at register space address +2.
by Stefan Tauner 12 Dec '14

12 Dec '14

On Wed, 10 Dec 2014 21:24:27 +0400 Roman Lebedev <lebedev.ri(a)gmail.com> wrote: > Invalid locking change 0xf8 requested at 0xb7323002! Please report a bug at > flashrom(a)flashrom.org Thanks for testing Roman! Carl-Daniel, do you have any idea why we do the "new_bits & ~REG2_MASK" in changelock_regspace2_block() in jedec.c at all? It is essentially your code, c.f. http://patchwork.coreboot.org/patch/3412/ I propose to use "(old ^ new) & ~REG2_MASK" instead, i.e. check if the caller requests a change of bits not related to the write protection. I guess that was your original intention anyway, is that correct? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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PCI BAR access thru sysfs
by Ed Swierk 11 Dec '14

11 Dec '14

Various kernel options are known to interfere with flashrom's attempts to access physical memory through /dev/mem. Some (like CONFIG_STRICT_DEVMEM) are important security measures that cannot be disabled without recompiling the kernel, and are likely to be used more widely over time. However, complete access to physical memory is unnecessary for some use cases. For example, the SPI interface on an Intel NIC can be accessed by mmapping a BAR resource file in the PCI device directory in sysfs. Has anyone considered implementing such an alternative access method for PCI devices in flashrom? --Ed

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Re: [flashrom] [PATCH] Fix handling of write protection at register space address +2.
by Roman Lebedev 10 Dec '14

10 Dec '14

Hi. Sorry for not replying, i got buried with other stuff. So, after some hassle with svn, i managed to apply that patch (patch -l -m -i ../flashrom.patch) ontop of current svn tip (r1857) That indeed fixed flash reading (-r), md5 of files generated with this patch, and with r1832 match. Here is the output, also do note "Invalid locking change 0xf8 requested" at the end!!! # flashrom --programmer internal -r 1002.bin.patch -V flashrom v0.9.7-r1857 on Linux 3.16.0-4-686-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.9.2, little endian Command line (5 args): flashrom --programmer internal -r 1002.bin.patch -V Calibrating delay loop... OS timer resolution is 1 usecs, 534M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10002 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "ASUSTeK COMPUTER INC." DMI string system-product-name: "PCH-DR" DMI string system-version: "1.XX " DMI string baseboard-manufacturer: "ASUSTek Computer INC." DMI string baseboard-product-name: "PCH-DR" DMI string baseboard-version: "1.XX " Found Winbond Super I/O, id 0x82 W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Please send the output of "flashrom -V -p internal" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel 6300ESB" with PCI ID 8086:25a1. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled OK. The following protocols are supported: FWH. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x08, id2 0x14, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) mapped at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x08, id2 0x14, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Invalid locking change 0xf8 requested at 0xb7323002! Please report a bug at flashrom(a)flashrom.org Reading flash... done. # Roman. On Sun, Dec 7, 2014 at 2:06 AM, Stefan Tauner < stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Previously we added the offset of the virtual register in several > functions, which produced segfaults. This patch renames a few > parameters hence the rather big diff. > > Thanks to Roman Lebedev for reporting this issue. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > chipdrivers.h | 1 - > jedec.c | 54 ++++++++++++++++++++++++------------------------------ > 2 files changed, 24 insertions(+), 31 deletions(-) > > diff --git a/chipdrivers.h b/chipdrivers.h > index 8529c74..cac94f3 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_32k(struct flashctx > *flash); > int unlock_regspace2_uniform_64k(struct flashctx *flash); > int unlock_regspace2_block_eraser_0(struct flashctx *flash); > int unlock_regspace2_block_eraser_1(struct flashctx *flash); > -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); > int printlock_regspace2_uniform_64k(struct flashctx *flash); > int printlock_regspace2_block_eraser_0(struct flashctx *flash); > int printlock_regspace2_block_eraser_1(struct flashctx *flash); > diff --git a/jedec.c b/jedec.c > index 1345b89..944f9d0 100644 > --- a/jedec.c > +++ b/jedec.c > @@ -589,11 +589,10 @@ static int regspace2_walk_unlockblocks(const struct > flashctx *flash, const struc > #define REG2_LOCKDOWN (1 << 1) > #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) > > -static int printlock_regspace2_block(const struct flashctx *flash, > chipaddr offset) > +static int printlock_regspace2_block(const struct flashctx *flash, > chipaddr wrprotect) > { > - chipaddr wrprotect = flash->virtual_registers + offset + 2; > uint8_t state = chip_readb(flash, wrprotect); > - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", > PRIxPTR_WIDTH, offset); > + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", > PRIxPTR_WIDTH, wrprotect); > switch (state & REG2_MASK) { > case 0: > msg_cdbg("Full Access.\n"); > @@ -656,47 +655,43 @@ int printlock_regspace2_block_eraser_1(struct > flashctx *flash) > return regspace2_walk_unlockblocks(flash, unlockblocks, > &printlock_regspace2_block); > } > > -static int changelock_regspace2_block(const struct flashctx *flash, > chipaddr offset, uint8_t new_bits) > +static int changelock_regspace2_block(const struct flashctx *flash, > chipaddr wrprotect, uint8_t old, uint8_t new) > { > - chipaddr wrprotect = flash->virtual_registers + offset + 2; > - uint8_t old; > - > - if (new_bits & ~REG2_MASK) { > + if (new & ~REG2_MASK) { > msg_cerr("Invalid locking change 0x%02x requested at > 0x%0*" PRIxPTR "! " > "Please report a bug at flashrom(a)flashrom.org\n", > - new_bits, PRIxPTR_WIDTH, offset); > + new, PRIxPTR_WIDTH, wrprotect); > return -1; > } > - old = chip_readb(flash, wrprotect); > /* Early exist if no change (of read/write/lockdown) was > requested. */ > - if (((old ^ new_bits) & REG2_MASK) == 0) { > - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not > changed\n", PRIxPTR_WIDTH, offset); > + if (((old ^ new) & REG2_MASK) == 0) { > + msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not > changed\n", PRIxPTR_WIDTH, wrprotect); > return 0; > } > /* Normally lockdowns can not be cleared. Try nevertheless if > requested. */ > - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { > + if ((old & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { > chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); > if (chip_readb(flash, wrprotect) != (old & > ~REG2_LOCKDOWN)) { > - msg_cerr("Lockdown can't be removed at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + msg_cerr("Lockdown can't be removed at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, wrprotect); > return -1; > } > } > /* Change read or write lock? */ > - if ((old ^ new_bits) & REG2_RWLOCK) { > + if ((old ^ new) & REG2_RWLOCK) { > /* Do not lockdown yet. */ > - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to > 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); > - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); > - if (chip_readb(flash, wrprotect) != (new_bits & > REG2_RWLOCK)) { > - msg_cerr("Locking status change FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to > 0x%02x\n", PRIxPTR_WIDTH, wrprotect, new & REG2_RWLOCK); > + chip_writeb(flash, new & REG2_RWLOCK, wrprotect); > + if (chip_readb(flash, wrprotect) != (new & REG2_RWLOCK)) { > + msg_cerr("Locking status change FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, wrprotect); > return -1; > } > } > /* Enable lockdown if requested. */ > - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { > - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", > PRIxPTR_WIDTH, offset); > - chip_writeb(flash, new_bits, wrprotect); > - if (chip_readb(flash, wrprotect) != new_bits) { > - msg_cerr("Enabling lockdown FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + if (!(old & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { > + msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", > PRIxPTR_WIDTH, wrprotect); > + chip_writeb(flash, new, wrprotect); > + if (chip_readb(flash, wrprotect) != new) { > + msg_cerr("Enabling lockdown FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, wrprotect); > return -1; > } > } > @@ -704,19 +699,18 @@ static int changelock_regspace2_block(const struct > flashctx *flash, chipaddr off > return 0; > } > > -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) > +static int unlock_regspace2_block_generic(const struct flashctx *flash, > chipaddr wrprotect) > { > - chipaddr wrprotect = flash->virtual_registers + off + 2; > uint8_t old = chip_readb(flash, wrprotect); > /* We don't care for the lockdown bit as long as the RW locks are > 0 after we're done */ > - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); > + return changelock_regspace2_block(flash, wrprotect, old, old & > ~REG2_RWLOCK); > } > > static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long > block_size) > { > const unsigned int elems = flash->chip->total_size * 1024 / > block_size; > struct unlockblock blocks[2] = {{.size = block_size, .count = > elems}}; > - return regspace2_walk_unlockblocks(flash, blocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, blocks, > &unlock_regspace2_block_generic); > } > > int unlock_regspace2_uniform_64k(struct flashctx *flash) > @@ -734,7 +728,7 @@ int unlock_regspace2_block_eraser_0(struct flashctx > *flash) > // FIXME: this depends on the eraseblocks not to be filled up > completely (i.e. to be null-terminated). > const struct unlockblock *unlockblocks = > (const struct unlockblock > *)flash->chip->block_erasers[0].eraseblocks; > - return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block_generic); > } > > int unlock_regspace2_block_eraser_1(struct flashctx *flash) > @@ -742,6 +736,6 @@ int unlock_regspace2_block_eraser_1(struct flashctx > *flash) > // FIXME: this depends on the eraseblocks not to be filled up > completely (i.e. to be null-terminated). > const struct unlockblock *unlockblocks = > (const struct unlockblock > *)flash->chip->block_erasers[1].eraseblocks; > - return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block_generic); > } > > -- > Kind regards, Stefan Tauner > >

1 0

Re: [flashrom] updating Coreboot
by Stefan Tauner 08 Dec '14

08 Dec '14

On Fri, 5 Dec 2014 18:26:46 +0100 Mathilde <allatoja(a)gmail.com> wrote: > Hello, > > Being not an informatician, I need help for updating my BIOS Coreboot (on a > Thinkpad X60), because of heat issues. > > I dowloaded the last release here http://libreboot.org/docs/release.html, > and installed the build dependencies. Could you explain me step by step > what to do now? > > I did'nt understand whether I am to compile flashrom or not. In advance > thank you very much! Hi, you probably want to ask the libreboot guys not us ;) Please see the contact information on http://libreboot.org at the bottom. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Flashrom Serprog Arduino Uno Winbond 25Q32BVSIG
by Paulo Ribeiro 08 Dec '14

08 Dec '14

I finally managed to get the chip recognised by flashrom using the following circuit: Chip --- Arduino 1 10 2 12 3 3.3V 4 GND 5 11 6 13 7 3.3V 8 3.3V The problem now is with the reading. With the flag -VVVr I get the following: Reading flash... serprog_spi_send_command, writecnt=4, readcnt=65536 serprog_spi_send_command, writecnt=4, readcnt=65536 serprog_spi_send_command, writecnt=4, readcnt=65536 serprog_spi_send_command, writecnt=4, readcnt=65536 serprog_spi_send_command, writecnt=4, readcnt=65536 serprog_spi_send_command, writecnt=4, readcnt=65536 It outputs a different number of lines each time but always stops. Any idea what the problem may be? Any help will be greatly appreciated. Best regards, Paulo Ribeiro

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Chip working
by Markus Hirsch 08 Dec '14

08 Dec '14

Hi, I have successfully flashed a EN25Q64 that was rated untested. It was for an 8MB version of openWRT. My setup was a Raspberry Pi with flashrom 0.9.5.2-r1546 and Linux 3.12.22+. I made a little SMD adapter like shown in the picture that plugs directly in the Pi header. Regards Markus

2 1

Re: [flashrom] rayer_spi
by Stefan Tauner 08 Dec '14

08 Dec '14

On Tue, 23 Sep 2014 20:29:55 +0330 Arman Khodabande <amal555(a)gmail.com> wrote: > Hello > As I checked Supported hardware on the Flashrom website the chip > EN25F32 has unknown status. I wanted to inform you that successfully > tested the Read and Write operations of this chip on a Rayer_spi > programmer. The EN25F32 chip acts as the Bios in the Dell XPS L502 > Laptops. Here's the log with (-V): > > […] > > Perhaps the verification process failed which maybe because of > programmer disconnection or fault. It may have been succeeded. So I'm > unsure. > > Verifying flash... VERIFY FAILED at 0x00008134! Expected=0xed, > Read=0xef, failed byte count from 0x00000000-0x003fffff: 0xbe54 > Your flash chip is in an unknown state. > Get help on IRC at chat.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org with the subject "FAILED: "! > > I verified the chip with another program called SPIPGM and it showed > no errors. so the READ and WRITE process was fine by flashrom. Hello Arman, thanks for your report! I'll pretend the verification errors never happened, because the LPT-based programmers are usually to blame and not flashrom itself. Thus I have marked the flash chip as fully tested and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] AT25DF041A PREW tested(with r1850)
by Stefan Tauner 08 Dec '14

08 Dec '14

On Fri, 3 Oct 2014 16:01:16 +0800 Tai-hwa Liang <atliang(a)gmail.com> wrote: > Hi, > > Just want to report successful programming to AT25DF041A with > Flyswatter board(http://www.tincantools.com/JTAG/Flyswatter.html). > > The flash itself is wired to A_TCLK(24)/A_TDI(23)/A_TDO(22)/A_TMS(21) > directly rather than connecting to the JTAG socket(J2) on Flyswatter as > the on board SN74AVC4T245 will require extra output enable signal to > activate, which needs extra flashrom mods. Hello, thanks for your report! I have marked the flash chip as fully tested and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Add Eon EN29LV040A
by Denis 'GNUtoo' Carikli 07 Dec '14

07 Dec '14

Hi, This serie is adding the Eon EN29LV040A. It was tested with the following programmer(satasii): 04:06.0 RAID bus controller [0104]: Silicon Image, Inc. PCI0680 Ultra ATA-133 Host Controller [1095:0680] (rev 02) Do I need to send flashrom -VV logs too? Denis.

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[commit] r1857 - trunk
by repository service 07 Dec '14

07 Dec '14

Author: stefanct Date: Sun Dec 7 22:57:53 2014 New Revision: 1857 URL: http://flashrom.org/trac/flashrom/changeset/1857 Log: Add support for Eon EN29LV040 and EN29LV040A. Both use the same ID and are mostly identical. Tested-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Fri Dec 5 23:56:13 2014 (r1856) +++ trunk/flashchips.c Sun Dec 7 22:57:53 2014 (r1857) @@ -4863,6 +4863,33 @@ { .vendor = "Eon", + .name = "EN29LV040(A)", + .bustype = BUS_PARALLEL, + .manufacture_id = EON_ID, + .model_id = EON_EN29LV040, + .total_size = 512, + .page_size = 4 * 1024, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sector_jedec, + }, + { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {3000, 3600}, /* 3.0-3.6V for type -45R and 55R, others 2.7-3.6V */ + }, + + { + .vendor = "Eon", .name = "EN29LV640B", .bustype = BUS_PARALLEL, .manufacture_id = EON_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Fri Dec 5 23:56:13 2014 (r1856) +++ trunk/flashchips.h Sun Dec 7 22:57:53 2014 (r1857) @@ -293,7 +293,7 @@ #define EON_EN29F010 0x20 #define EON_EN29F040A 0x7F04 #define EON_EN29LV010 0x7F6E -#define EON_EN29LV040A 0x7F4F /* EN29LV040(A) */ +#define EON_EN29LV040 0x4F /* Same as EN29LV040A */ #define EON_EN29LV640B 0xCB #define EON_EN29F002T 0x7F92 /* Same as EN29F002A */ #define EON_EN29F002B 0x7F97 /* Same as EN29F002AN */

1 0

Re: [flashrom] Success with flashing AOPEN UK79G-1394 (EZ18) -Vw
by Stefan Tauner 07 Dec '14

07 Dec '14

Hello Lawrence, thanks for your report! I have added your board to our list of supported hardware and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[PATCH] Support for S25FL127S
by Jernej Škrabec 07 Dec '14

07 Dec '14

Hi! I'm attaching a patch which adds support for Spansion S25FL127S flash chip in 64KiB and 256KiB mode. I also tested 64KiB mode with FT4232H Mini Module which works fine (please see attached logs). Best regards, Jernej Skrabec

2 6

Re: [flashrom] Regression in r1833
by Carl-Daniel Hailfinger 07 Dec '14

07 Dec '14

Hi Roman, thanks for your bug report. On 01.12.2014 21:55, Roman Lebedev wrote: > Hello. > > I had a segfault with current version of flashrom, and with some help > from stefanct at IRC i was able to bisect it down to r1833. > > I attach backtraces. The backtraces were very helpful in determining the bug. Can you please edit jedec.c function static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struct unlockblock *block, unlockblock_func func) The line chipaddr off = flash->virtual_registers + 2; should be replaced with chipaddr off = 0; This is expected to fix the bug. I haven't checked if other places have the same bug, but right now a test of the potential fix would be appreciated. Regards, Carl-Daniel

2 1

[PATCH] Add support for Intel 82599 10G NICs
by Ed Swierk 05 Dec '14

05 Dec '14

The Intel 82599 series of 10G Ethernet controllers has a bit-banged SPI interface that's register-compatible with the one in the 1G controllers, except the register addresses are shifted up by 0x10000. See http://www.intel.com/content/www/us/en/ethernet-controllers/82599-10-gbe-co…. I tested this with a board that has the 0x10fc device and a Micron M25P40 SPI flash chip. I filled in device IDs for other 82599 devices per https://www-ssl.intel.com/content/www/us/en/ethernet-controllers/82599-10-g… and lifted the name strings from the PCI SIG device ID registry. Signed-off-by: Ed Swierk <eswierk(a)skyportsystems.com> =================================================================== diff --git a/trunk/nicintel_spi.c b/trunk/nicintel_spi.c --- a/trunk/nicintel_spi.c (revision 1855) +++ b/trunk/nicintel_spi.c (working copy) @@ -80,6 +80,13 @@ {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10f7, NT, "Intel", "10 Gigabit BR KX4 Dual Port Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x10f8, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Connection"}, + {PCI_VENDOR_ID_INTEL, 0x10f9, NT, "Intel", "82599 10 Gigabit Dual Port Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x10fb, NT, "Intel", "82599ES 10-Gigabit SFI/SFP+ Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x10fc, OK, "Intel", "82599 10 Gigabit Dual Port Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit Network Connection"}, + {0}, }; @@ -183,7 +190,13 @@ if (!io_base_addr) return 1; - nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); + if (dev->device_id < 0x10f0) { + nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, + MEMMAP_SIZE); + } else { + nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, + MEMMAP_SIZE); + } if (nicintel_spibar == ERROR_PTR) return 1;

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