- flashrom - mail.coreboot.org

flashrom Windows port
by Carl-Daniel Hailfinger 19 Nov '09

19 Nov '09

Hi, what's the current state of the Windows port of flashrom (and DirectIO, for that matter)? I'm willing to review/merge/update anything which brings us closer, as long as functionality on supported platforms is not affected. Patches I'm talking about are: http://patchwork.coreboot.org/patch/97/ (but one of the patches in that mail is missing) http://patchwork.coreboot.org/patch/98/ Subject was: [flashrom] [PATCH] new windows port Regards, Carl-Daniel -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

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FAIL: AsRock K8Upgrade, weird write behavior, board still intact
by Adrian Glaubitz 18 Nov '09

18 Nov '09

Hi, I tried flashing an AsRock K8Upgrade board (yes, the model name is really "K8Upgrade"). flashrom didn't detect the chipset but it detected the flash chip. I attempted to write the flash which initially seemed to work: flashrom indicated that it was writing some pages however progress was *very* slow (as opposed to the Elitegroup K7S5A which I successfully flashed for example). Thus while the flash was written I already suspected something going wrong. Eventually flashrom gave up. However, when I reread the flash and compared it with the flash before write the images matched. So I suspect the bios is still intact. Please see the attached logs of lspci -nnvvvxxx, superiotool -dV and flashrom -V plus the output for the failed flash attempt. Adrian

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FAIL: Asus P4PE-X, board still intact, couldn't erase
by Adrian Glaubitz 18 Nov '09

18 Nov '09

Hi, I tried flashing an P4PE-X. Erasing the flash failed, however, the flash is still intact. Please see the attached logs of lspci -nnvvvxxx, superiotool -dV and flashrom -V plus the output for the failed flash attempt. Adrian

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FAIL: Asus P5B, board still intact, couldn't erase
by Adrian Glaubitz 18 Nov '09

18 Nov '09

Hi, I tried flashing an P5B today. However, opposed to the previously reported working "Asus P5B Deluxe" in the Wiki, the P5B doesn't seem to be supported. Please see the attached logs of lspci -nnvvvxxx, superiotool -dV and flashrom -V plus the output for the failed flash attempt. Adrian

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Verbose output of lspci, superiotool and flashrom - AsRock K7S8X (unsupported)
by Adrian Glaubitz 18 Nov '09

18 Nov '09

Hi, tested an AsRock K7S8X, however no Super I/O chip was detected and therefore flashing was not possible. Please see the attached logs of lspci -nnvvvxxx, superiotool -dV and flashrom -V. Adrian

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Issues with ASUS P4T
by Adrian Glaubitz 18 Nov '09

18 Nov '09

Hi, I tried flashing an ASUS P4T today. However, there were several problems which probably arise due a misdetected flash chip: - first the chip and the original BIOS image from ASUS mismatch in size, the image is 256kb large, flashrom detects the chip to be 512kb - second, the erasing of the flash fails; the BIOS is still intact though, see logs attached So my wild guess is that the flash chip is not properly detected. Please see the attached logs of lspci -nnvvvxxx, superiotool -dV and flashrom -V plus the output for the failed flash attempt. Adrian

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[PATCH] Clean up main loop
by Carl-Daniel Hailfinger 17 Nov '09

17 Nov '09

To prepare for libflashrom I wanted to make the main loop more readable and more correct and factor out stuff which can be useful in libflashrom. - Factor out printing of supported devices to print.c. - Adjust name of wiki printing function to fit the pattern. - Abort if the user specified --verify and --noverify at the same time. - Check for extra parameters which don't fit commandline syntax. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-mainloop_cleanup/flash.h =================================================================== --- flashrom-mainloop_cleanup/flash.h (Revision 755) +++ flashrom-mainloop_cleanup/flash.h (Arbeitskopie) @@ -338,11 +338,9 @@ /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); -void print_supported_chips(void); -void print_supported_chipsets(void); -void print_supported_boards(void); +void print_supported(void); void print_supported_pcidevs(struct pcidev_status *devs); -void print_wiki_tables(void); +void print_supported_wiki(void); /* board_enable.c */ void w836xx_ext_enter(uint16_t port); Index: flashrom-mainloop_cleanup/flashrom.c =================================================================== --- flashrom-mainloop_cleanup/flashrom.c (Revision 755) +++ flashrom-mainloop_cleanup/flashrom.c (Arbeitskopie) @@ -801,14 +801,25 @@ write_it = 1; break; case 'v': + //FIXME: gracefully handle superfluous -v if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); exit(1); } + if (dont_verify_it) { + fprintf(stderr, "--verify and --noverify are" + "mutually exclusive. Aborting.\n"); + exit(1); + } verify_it = 1; break; case 'n': + if (verify_it) { + fprintf(stderr, "--verify and --noverify are" + "mutually exclusive. Aborting.\n"); + exit(1); + } dont_verify_it = 1; break; case 'c': @@ -896,29 +907,13 @@ } if (list_supported) { - print_supported_chips(); - print_supported_chipsets(); - print_supported_boards(); - printf("\nSupported PCI devices flashrom can use " - "as programmer:\n\n"); -#if NIC3COM_SUPPORT == 1 - print_supported_pcidevs(nics_3com); -#endif -#if GFXNVIDIA_SUPPORT == 1 - print_supported_pcidevs(gfx_nvidia); -#endif -#if DRKAISER_SUPPORT == 1 - print_supported_pcidevs(drkaiser_pcidev); -#endif -#if SATASII_SUPPORT == 1 - print_supported_pcidevs(satas_sii); -#endif + print_supported(); exit(0); } #if PRINT_WIKI_SUPPORT == 1 if (list_supported_wiki) { - print_wiki_tables(); + print_supported_wiki(); exit(0); } #endif @@ -930,6 +925,11 @@ if (optind < argc) filename = argv[optind++]; + + if (optind < argc) { + printf("Error: Extra parameter found.\n"); + usage(argv[0]); + } if (programmer_init()) { fprintf(stderr, "Error: Programmer initialization failed.\n"); @@ -1146,7 +1146,7 @@ if (write_it) programmer_delay(1000*1000); ret = verify_flash(flash, buf); - /* If we tried to write, and now we don't properly verify, we + /* If we tried to write, and verification now fails, we * might have an emergency situation. */ if (ret && write_it) Index: flashrom-mainloop_cleanup/print_wiki.c =================================================================== --- flashrom-mainloop_cleanup/print_wiki.c (Revision 755) +++ flashrom-mainloop_cleanup/print_wiki.c (Arbeitskopie) @@ -535,7 +535,7 @@ } } -void print_wiki_tables(void) +void print_supported_wiki(void) { time_t t = time(NULL); Index: flashrom-mainloop_cleanup/print.c =================================================================== --- flashrom-mainloop_cleanup/print.c (Revision 755) +++ flashrom-mainloop_cleanup/print.c (Arbeitskopie) @@ -222,7 +222,28 @@ "Laptops which have been verified to NOT work yet"); } +void print_supported(void) +{ + print_supported_chips(); + print_supported_chipsets(); + print_supported_boards(); + printf("\nSupported PCI devices flashrom can use " + "as programmer:\n\n"); +#if NIC3COM_SUPPORT == 1 + print_supported_pcidevs(nics_3com); +#endif +#if GFXNVIDIA_SUPPORT == 1 + print_supported_pcidevs(gfx_nvidia); +#endif +#if DRKAISER_SUPPORT == 1 + print_supported_pcidevs(drkaiser_pcidev); +#endif +#if SATASII_SUPPORT == 1 + print_supported_pcidevs(satas_sii); +#endif +} + /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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[commit] r766 - trunk
by svn＠flashrom.org 17 Nov '09

17 Nov '09

Author: hailfinger Date: 2009-11-17 10:57:34 +0100 (Tue, 17 Nov 2009) New Revision: 766 Modified: trunk/flash.h trunk/flashrom.c trunk/print.c trunk/print_wiki.c Log: To prepare for libflashrom I wanted to make the main loop more readable and more correct and factor out stuff which can be useful in libflashrom. - Factor out printing of supported devices to print.c. - Adjust name of wiki printing function to fit the pattern. - Abort if the user specified --verify and --noverify at the same time. - Check for extra parameters which don't fit commandline syntax. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-11-16 21:22:24 UTC (rev 765) +++ trunk/flash.h 2009-11-17 09:57:34 UTC (rev 766) @@ -338,11 +338,9 @@ /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); -void print_supported_chips(void); -void print_supported_chipsets(void); -void print_supported_boards(void); +void print_supported(void); void print_supported_pcidevs(struct pcidev_status *devs); -void print_wiki_tables(void); +void print_supported_wiki(void); /* board_enable.c */ void w836xx_ext_enter(uint16_t port); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-11-16 21:22:24 UTC (rev 765) +++ trunk/flashrom.c 2009-11-17 09:57:34 UTC (rev 766) @@ -801,14 +801,25 @@ write_it = 1; break; case 'v': + //FIXME: gracefully handle superfluous -v if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); exit(1); } + if (dont_verify_it) { + fprintf(stderr, "--verify and --noverify are" + "mutually exclusive. Aborting.\n"); + exit(1); + } verify_it = 1; break; case 'n': + if (verify_it) { + fprintf(stderr, "--verify and --noverify are" + "mutually exclusive. Aborting.\n"); + exit(1); + } dont_verify_it = 1; break; case 'c': @@ -896,29 +907,13 @@ } if (list_supported) { - print_supported_chips(); - print_supported_chipsets(); - print_supported_boards(); - printf("\nSupported PCI devices flashrom can use " - "as programmer:\n\n"); -#if NIC3COM_SUPPORT == 1 - print_supported_pcidevs(nics_3com); -#endif -#if GFXNVIDIA_SUPPORT == 1 - print_supported_pcidevs(gfx_nvidia); -#endif -#if DRKAISER_SUPPORT == 1 - print_supported_pcidevs(drkaiser_pcidev); -#endif -#if SATASII_SUPPORT == 1 - print_supported_pcidevs(satas_sii); -#endif + print_supported(); exit(0); } #if PRINT_WIKI_SUPPORT == 1 if (list_supported_wiki) { - print_wiki_tables(); + print_supported_wiki(); exit(0); } #endif @@ -930,6 +925,11 @@ if (optind < argc) filename = argv[optind++]; + + if (optind < argc) { + printf("Error: Extra parameter found.\n"); + usage(argv[0]); + } if (programmer_init()) { fprintf(stderr, "Error: Programmer initialization failed.\n"); @@ -1146,7 +1146,7 @@ if (write_it) programmer_delay(1000*1000); ret = verify_flash(flash, buf); - /* If we tried to write, and now we don't properly verify, we + /* If we tried to write, and verification now fails, we * might have an emergency situation. */ if (ret && write_it) Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-11-16 21:22:24 UTC (rev 765) +++ trunk/print.c 2009-11-17 09:57:34 UTC (rev 766) @@ -222,7 +222,28 @@ "Laptops which have been verified to NOT work yet"); } +void print_supported(void) +{ + print_supported_chips(); + print_supported_chipsets(); + print_supported_boards(); + printf("\nSupported PCI devices flashrom can use " + "as programmer:\n\n"); +#if NIC3COM_SUPPORT == 1 + print_supported_pcidevs(nics_3com); +#endif +#if GFXNVIDIA_SUPPORT == 1 + print_supported_pcidevs(gfx_nvidia); +#endif +#if DRKAISER_SUPPORT == 1 + print_supported_pcidevs(drkaiser_pcidev); +#endif +#if SATASII_SUPPORT == 1 + print_supported_pcidevs(satas_sii); +#endif +} + /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-11-16 21:22:24 UTC (rev 765) +++ trunk/print_wiki.c 2009-11-17 09:57:34 UTC (rev 766) @@ -539,7 +539,7 @@ } } -void print_wiki_tables(void) +void print_supported_wiki(void) { time_t t = time(NULL);

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info about Asus P4P800 SE
by Dev 17 Nov '09

17 Nov '09

MotherBoard: Asus P4P800 SE additional info attached. thanks for your support. Regards, Evgeny

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Success: Gigabyte GA-EP45-DS3 (rev. 1.0), MX25L8005
by alsterwassermann＠gmx.de 17 Nov '09

17 Nov '09

Hi, I'd like to provide an update to http://www.flashrom.org/Flashrom#Supported_chips I just flashed a MX25L8005 successfully - that's on a Gigabyte GA-EP45-DS3 (rev. 1.0). Need anything else? Just ping me... # uname -a Linux mybox 2.6.26-2-xen-amd64 #1 SMP Mon Oct 26 12:43:40 UTC 2009 x86_64 GNU/Linux # # flashrom flashrom v0.9.1-r736 No coreboot table found. Found chipset "Intel ICH10", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. No operations were specified. # # lspci -nn 00:00.0 Host bridge [0600]: Intel Corporation 4 Series Chipset DRAM Controller [8086:2e20] (rev 03) 00:01.0 PCI bridge [0604]: Intel Corporation 4 Series Chipset PCI Express Root Port [8086:2e21] (rev 03) 00:1a.0 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #4 [8086:3a37] 00:1a.1 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #5 [8086:3a38] 00:1a.2 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #6 [8086:3a39] 00:1a.7 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #2 [8086:3a3c] 00:1b.0 Audio device [0403]: Intel Corporation 82801JI (ICH10 Family) HD Audio Controller [8086:3a3e] 00:1c.0 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 1 [8086:3a40] 00:1c.1 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 2 [8086:3a42] 00:1c.3 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 4 [8086:3a46] 00:1c.4 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 5 [8086:3a48] 00:1c.5 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 6 [8086:3a4a] 00:1d.0 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #1 [8086:3a34] 00:1d.1 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #2 [8086:3a35] 00:1d.2 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #3 [8086:3a36] 00:1d.7 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #1 [8086:3a3a] 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev 90) 00:1f.0 ISA bridge [0601]: Intel Corporation 82801JIB (ICH10) LPC Interface Controller [8086:3a18] 00:1f.2 SATA controller [0106]: Intel Corporation 82801JI (ICH10 Family) SATA AHCI Controller [8086:3a22] 00:1f.3 SMBus [0c05]: Intel Corporation 82801JI (ICH10 Family) SMBus Controller [8086:3a30] 01:00.0 VGA compatible controller [0300]: ATI Technologies Inc Radeon X1650 XT (Primary) (PCIE) [1002:7291] 01:00.1 Display controller [0380]: ATI Technologies Inc Radeon X1650 XT (Secondary) (PCIE) [1002:72b1] 03:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 01) 04:00.0 IDE interface [0101]: JMicron Technologies, Inc. JMB368 IDE controller [197b:2368] 05:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 02) 06:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 02) 07:00.0 Network controller [0280]: Atheros Communications Inc. AR5416 802.11abgn Wireless PCI Adapter [168c:0023] (rev 01) 07:01.0 Multimedia video controller [0400]: Conexant CX23880/1/2/3 PCI Video and Audio Decoder [14f1:8800] (rev 05) 07:01.2 Multimedia controller [0480]: Conexant CX23880/1/2/3 PCI Video and Audio Decoder [MPEG Port] [14f1:8802] (rev 05) # # flashrom flashrom v0.9.1-r736 No coreboot table found. Found chipset "Intel ICH10", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. No operations were specified. debbyhost:~/flashrom# flashrom -V flashrom v0.9.1-r736 No coreboot table found. Found chipset "Intel ICH10", enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 Root Complex Register Block address = 0xfed1c000 GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x2008 (HSFS) FLOCKDN 0, FDV 0, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 0x50: 0x00000202 (FRAP) BMWAG 0, BMRAG 0, BRWA 2, BRRA 2 0x54: 0x00001fff (FREG0) 0x58: 0x00001fff (FREG1) 0x5C: 0x00001fff (FREG2) 0x60: 0x00001fff (FREG3) 0x64: 0x00001fff (FREG4) 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x00426004 (SSFS, SSFC) 0x94: 0x0006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00000000 (FDOC) Programming OPCODES... program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190 done SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... 760M loops per second, 100 myus = 200 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A25L40P, 512 KB: RDID returned 0xc2 0x20 0x14 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25D16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x24, id2 0xc8 Probing for Macronix MX25L512, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm29F0002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm29F0002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0x24, id2 0xc8 Probing for Spansion S25FL016A, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF016B, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040B, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 KB: REMS returned c2 13. probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: REMS returned c2 13. probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0x24, id2 0xc8, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0x24, id2 0xc8 Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x24, id2 0xc8, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 KB: RDID returned 0xc2 0x20 0x14. Probing for ST M25P10-A, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 KB: RDID returned 0xc2 0x20 0x14. Probing for ST M25P20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 KB: RDID returned 0xc2 0x20 0x14. Probing for ST M25P80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x24, id2 0xc8, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x24, id2 0xc8, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x24, id2 0xc8 Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0x24, id2 0xc8, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x24, id2 0xc8, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x100000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x100000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x100000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x100000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x100000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x100000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) No operations were specified. #

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[commit] r765 - trunk
by svn＠flashrom.org 16 Nov '09

16 Nov '09

Author: hailfinger Date: 2009-11-16 22:22:24 +0100 (Mon, 16 Nov 2009) New Revision: 765 Modified: trunk/Makefile Log: Fix incorrect comment about wiki printing in Makefile. Spotted by Benjamin BELLEC <b.bellec(a)gmail.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-11-16 15:03:35 UTC (rev 764) +++ trunk/Makefile 2009-11-16 21:22:24 UTC (rev 765) @@ -89,7 +89,7 @@ # Always enable Dr. Kaiser for now. CONFIG_DRKAISER ?= yes -# Always enable wiki printing for now. +# Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no ifeq ($(CONFIG_SERPROG), yes)

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Tiny mistake in the Makefile (I think)
by Benjamin BELLEC 16 Nov '09

16 Nov '09

Hello, I was reading the Makefile (r764) and I saw at line 92-92 : 92 - # Always enable wiki printing for now. 93 - CONFIG_PRINT_WIKI ?= no Given the precedent lines I think this is not coherent, right ? Benjamin

2 1

SUCCESS: AsRock K8S8X, SuperI/O not detected however
by Adrian Glaubitz 16 Nov '09

16 Nov '09

Hello, I successfully flashed a new BIOS version onto an AsRock K8S8X. Used flashrom r764. flashrom did not detect the SuperI/O though. Chipset is SiS 755. The board works absolutely fine and there were NO issues during flash, worked like a charm :). Please see the attached logs and mark the board as *supported*. Thanks, Adrian

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[PATCH] Show ICH flash descriptor info only if valid
by Carl-Daniel Hailfinger 16 Nov '09

16 Nov '09

Show ICH flash descriptor info only if valid. Otherwise it is just confusing the developers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich_spi_descriptor/chipset_enable.c =================================================================== --- flashrom-ich_spi_descriptor/chipset_enable.c (Revision 764) +++ flashrom-ich_spi_descriptor/chipset_enable.c (Arbeitskopie) @@ -426,7 +426,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { - int ret, i; + int ret, i, hwseq = 0; uint8_t old, new, bbs, buc; uint16_t spibar_offset, tmp2; uint32_t tmp, gcs; @@ -540,30 +540,50 @@ printf_debug("0x04: 0x%04x (HSFS)\n", tmp2); printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1)); printf_debug("FDV %i, ", (tmp2 >> 14) & 1); + /* Flash Descriptor Override Pin-Strap Status, but unfortunately + * there is no info on how it affects hardware sequencing if + * FDV=1, nor do we know whether FDOPSS needs to be ORed or + * XORed with FDV. + */ printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1); printf_debug("SCIP %i, ", (tmp2 >> 5) & 1); printf_debug("BERASE %i, ", (tmp2 >> 3) & 3); printf_debug("AEL %i, ", (tmp2 >> 2) & 1); printf_debug("FCERR %i, ", (tmp2 >> 1) & 1); printf_debug("FDONE %i\n", (tmp2 >> 0) & 1); + /* If the flash descriptor is valid, hardware sequencing is + * supported and software sequencing may encounter transaction + * errors if it tries to access regions outside the BIOS area. + * See the FDOPSS note above for potential pitfalls. + */ + hwseq = (tmp2 >> 14) & 1; + if (hwseq) { + tmp = mmio_readl(spibar + 0x0); + printf("WARNING: SPI descriptor mode is active, " + "flashing may fail in some regions.\n"); + printf_debug("0x00: 0x%08x (BPFR)\n", tmp); + printf_debug("PRB 0x%x, ", (tmp & 0x1FFF) << 12); + tmp >>= 16; + printf_debug("PRL 0x%x, ", (tmp & 0x1FFF) << 12); - tmp = mmio_readl(spibar + 0x50); - printf_debug("0x50: 0x%08x (FRAP)\n", tmp); - printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); - printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); - printf_debug("BRWA %i, ", (tmp >> 8) & 0xff); - printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); + tmp = mmio_readl(spibar + 0x50); + printf_debug("0x50: 0x%08x (FRAP)\n", tmp); + printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); + printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); + printf_debug("BRWA %i, ", (tmp >> 8) & 0xff); + printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); - printf_debug("0x54: 0x%08x (FREG0)\n", - mmio_readl(spibar + 0x54)); - printf_debug("0x58: 0x%08x (FREG1)\n", - mmio_readl(spibar + 0x58)); - printf_debug("0x5C: 0x%08x (FREG2)\n", - mmio_readl(spibar + 0x5C)); - printf_debug("0x60: 0x%08x (FREG3)\n", - mmio_readl(spibar + 0x60)); - printf_debug("0x64: 0x%08x (FREG4)\n", - mmio_readl(spibar + 0x64)); + printf_debug("0x54: 0x%08x (FREG0)\n", + mmio_readl(spibar + 0x54)); + printf_debug("0x58: 0x%08x (FREG1)\n", + mmio_readl(spibar + 0x58)); + printf_debug("0x5C: 0x%08x (FREG2)\n", + mmio_readl(spibar + 0x5C)); + printf_debug("0x60: 0x%08x (FREG3)\n", + mmio_readl(spibar + 0x60)); + printf_debug("0x64: 0x%08x (FREG4)\n", + mmio_readl(spibar + 0x64)); + } printf_debug("0x74: 0x%08x (PR0)\n", mmio_readl(spibar + 0x74)); printf_debug("0x78: 0x%08x (PR1)\n", @@ -586,8 +606,10 @@ mmio_readl(spibar + 0x9C)); printf_debug("0xA0: 0x%08x (BBAR)\n", mmio_readl(spibar + 0xA0)); - printf_debug("0xB0: 0x%08x (FDOC)\n", - mmio_readl(spibar + 0xB0)); + if (hwseq) { + printf_debug("0xB0: 0x%08x (FDOC)\n", + mmio_readl(spibar + 0xB0)); + } if (tmp2 & (1 << 15)) { printf("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

1 1

[commit] r764 - trunk
by svn＠flashrom.org 16 Nov '09

16 Nov '09

Author: hailfinger Date: 2009-11-16 16:03:35 +0100 (Mon, 16 Nov 2009) New Revision: 764 Modified: trunk/spi.c Log: If a SPI command taking an address does fail, we want to know the address for easier debugging. Vincent wrote: This patch provided help to debug the partial write on ICH in descriptor mode. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Vincent S. Cojot <openlook(a)cojot.name> Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-11-16 14:13:09 UTC (rev 763) +++ trunk/spi.c 2009-11-16 15:03:35 UTC (rev 764) @@ -615,8 +615,8 @@ result = spi_send_multicommand(cmds); if (result) { - fprintf(stderr, "%s failed during command execution\n", - __func__); + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -659,7 +659,8 @@ result = spi_send_multicommand(cmds); if (result) { - fprintf(stderr, "%s failed during command execution\n", __func__); + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -721,8 +722,8 @@ result = spi_send_multicommand(cmds); if (result) { - fprintf(stderr, "%s failed during command execution\n", - __func__); + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -827,21 +828,21 @@ result = spi_send_multicommand(cmds); if (result) { - fprintf(stderr, "%s failed during command execution\n", - __func__); + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); } return result; } -int spi_nbyte_program(int address, uint8_t *bytes, int len) +int spi_nbyte_program(int addr, uint8_t *bytes, int len) { int result; /* FIXME: Switch to malloc based on len unless that kills speed. */ unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { JEDEC_BYTE_PROGRAM, - (address >> 16) & 0xff, - (address >> 8) & 0xff, - (address >> 0) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff, }; struct spi_command cmds[] = { { @@ -874,8 +875,8 @@ result = spi_send_multicommand(cmds); if (result) { - fprintf(stderr, "%s failed during command execution\n", - __func__); + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); } return result; }

1 0

Re: [flashrom] [PATCH] More verbose failures for SPI commands
by Carl-Daniel Hailfinger 16 Nov '09

16 Nov '09

Hi Vincent, On 16.11.2009 16:00, vincent(a)cojot.name wrote: > This patch provided help to debug the issue.. > Acked-by: Vincent S. Cojot <openlook(a)cojot.name> thanks for testing. Committed in r764. Regards, Carl-Daniel -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

1 0

[PATCH] More verbose failures for SPI commands
by Carl-Daniel Hailfinger 16 Nov '09

16 Nov '09

If a SPI command taking an address does fail, we want to know the address for easier debugging. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_command_failure_verbose/spi.c =================================================================== --- flashrom-spi_command_failure_verbose/spi.c (Revision 763) +++ flashrom-spi_command_failure_verbose/spi.c (Arbeitskopie) @@ -615,8 +615,8 @@ result = spi_send_multicommand(cmds); if (result) { - fprintf(stderr, "%s failed during command execution\n", - __func__); + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -659,7 +659,8 @@ result = spi_send_multicommand(cmds); if (result) { - fprintf(stderr, "%s failed during command execution\n", __func__); + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -721,8 +722,8 @@ result = spi_send_multicommand(cmds); if (result) { - fprintf(stderr, "%s failed during command execution\n", - __func__); + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -827,21 +828,21 @@ result = spi_send_multicommand(cmds); if (result) { - fprintf(stderr, "%s failed during command execution\n", - __func__); + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); } return result; } -int spi_nbyte_program(int address, uint8_t *bytes, int len) +int spi_nbyte_program(int addr, uint8_t *bytes, int len) { int result; /* FIXME: Switch to malloc based on len unless that kills speed. */ unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { JEDEC_BYTE_PROGRAM, - (address >> 16) & 0xff, - (address >> 8) & 0xff, - (address >> 0) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff, }; struct spi_command cmds[] = { { @@ -874,8 +875,8 @@ result = spi_send_multicommand(cmds); if (result) { - fprintf(stderr, "%s failed during command execution\n", - __func__); + fprintf(stderr, "%s failed during command execution at address 0x%x\n", + __func__, addr); } return result; } -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

2 1

[commit] r763 - trunk
by svn＠flashrom.org 16 Nov '09

16 Nov '09

Author: hailfinger Date: 2009-11-16 15:13:09 +0100 (Mon, 16 Nov 2009) New Revision: 763 Modified: trunk/print_wiki.c Log: Add URLs for boards ASUS K8V, ASUS K8V SE Deluxe, Elitegroup K7S5A. Add a note for ASUS M2N-E. Change "iff" to "if". Most people don't understand what "iff" means and the meaning of both words is close enough to hopefully give users the right idea. Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-11-16 14:05:13 UTC (rev 762) +++ trunk/print_wiki.c 2009-11-16 14:13:09 UTC (rev 763) @@ -115,6 +115,8 @@ { "ASUS", "A8V Deluxe", "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU" }, { "ASUS", "A8V-E Deluxe", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=376&model…" }, { "ASUS", "A8V-E SE", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=576&model…" }, + { "ASUS", "K8V", "http://www.asus.com/product.aspx?P_ID=fG2KZOWF7v6MRFRm" }, + { "ASUS", "K8V SE Deluxe", "http://www.asus.com/product.aspx?P_ID=65HeDI8XM1u6Uy6o" }, { "ASUS", "M2A-MX", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=583&l4=0&model=1909&modelm…" }, { "ASUS", "M2A-VM", "http://www.asus.com.tw/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&mod…" }, { "ASUS", "M2N-E", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=308&l4=0&model=1181&modelm…" }, @@ -131,6 +133,7 @@ { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100" }, + { "Elitegroup", "K7S5A", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=279&…" }, { "Elitegroup", "P6VAP-A+", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…" }, { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, @@ -282,7 +285,8 @@ { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, { "ASUS", "M2A-VM", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html." }, { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, - { "GIGABYTE", "GA-7ZM", "Works fine iff you remove jumper JP9 on the board and disable the flash protection BIOS option." }, + { "GIGABYTE", "GA-7ZM", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." }, + { "ASUS", "M2N-E", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" }, /* Verified working boards that DO need write-enables. */ { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." },

1 0

[commit] r762 - trunk
by svn＠flashrom.org 16 Nov '09

16 Nov '09

Author: hailfinger Date: 2009-11-16 15:05:13 +0100 (Mon, 16 Nov 2009) New Revision: 762 Modified: trunk/Makefile Log: Retrieve the proper linker flags for libftdi via pkg-config and fall back if pkg-config isn't available or if it doesn't know libftdi. Fix $LIBS and $FEATURE_LIBS to honor dependency order. The original patch is from J?\195?\182rg, it has been updated by Carl-Daniel to work on the current tree and to have a fallback in case pkg-config is not available or not working. Signed-off-by: J?\195?\182rg Mayer <jmayer(a)loplof.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: J?\195?\182rg Mayer <jmayer(a)loplof.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-11-15 17:23:59 UTC (rev 761) +++ trunk/Makefile 2009-11-16 14:05:13 UTC (rev 762) @@ -120,10 +120,11 @@ OBJS += satasii.o endif +FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") ifeq ($(CONFIG_FT2232SPI), yes) # This is a totally ugly hack. FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") -FEATURE_LIBS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") +FEATURE_LIBS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "$(FTDILIBS)") OBJS += ft2232_spi.o endif @@ -146,7 +147,7 @@ FEATURE_LIBS += $(shell LC_ALL=C grep -q "NEEDLIBZ := yes" .libdeps && printf "%s" "-lz") $(PROGRAM): $(OBJS) - $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) + $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(FEATURE_LIBS) $(LIBS) # TAROPTIONS reduces information leakage from the packager's system. # If other tar programs support command line arguments for setting uid/gid of @@ -218,7 +219,7 @@ echo "struct ftdi_context *ftdic = NULL;"; \ echo "int main(int argc, char **argv)"; \ echo "{ return ftdi_init(ftdic); }"; ) > .featuretest.c ) - @$(CC) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest $(LIBS) -lftdi >/dev/null 2>&1 && \ + @$(CC) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest $(FTDILIBS) $(LIBS) >/dev/null 2>&1 && \ ( echo "found."; echo "FTDISUPPORT := yes" >> .features.tmp ) || \ ( echo "not found."; echo "FTDISUPPORT := no" >> .features.tmp ) @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features

1 0

Fix feature detection when fdti requires libusb for linking
by Joerg Mayer 16 Nov '09

16 Nov '09

see attached patch. patch is too small to be copyrightable... ciao Joerg -- Joerg Mayer <jmayer(a)loplof.de> We are stuck with technology when what we really want is just stuff that works. Some say that should read Microsoft instead of technology.

3 5

[commit] r761 - trunk
by svn＠flashrom.org 15 Nov '09

15 Nov '09

Author: hailfinger Date: 2009-11-15 18:23:59 +0100 (Sun, 15 Nov 2009) New Revision: 761 Modified: trunk/ Log: svn:ignore .libdeps Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Property changes on: trunk ___________________________________________________________________ Modified: svn:ignore - flashrom .features .dependencies + flashrom .features .dependencies .libdeps

1 0

[commit] r760 - trunk
by svn＠flashrom.org 15 Nov '09

15 Nov '09

Author: hailfinger Date: 2009-11-15 18:20:21 +0100 (Sun, 15 Nov 2009) New Revision: 760 Modified: trunk/chipset_enable.c trunk/print.c Log: Mark Elitegroup K7S5A as supported. Mark SiS 735 as supported. Remove "SiS" from the model number to avoid printing it twice. Reported by Adrian Glaubitz. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-11-15 17:13:29 UTC (rev 759) +++ trunk/chipset_enable.c 2009-11-15 17:20:21 UTC (rev 760) @@ -1155,34 +1155,34 @@ {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp55}, - {0x1039, 0x0496, NT, "SiS", "SiS 85C496+497", enable_flash_sis85c496}, - {0x1039, 0x0406, NT, "SiS", "SiS 501/5101/5501", enable_flash_sis501}, - {0x1039, 0x5511, NT, "SiS", "SiS 5511", enable_flash_sis5511}, - {0x1039, 0x5596, NT, "SiS", "SiS 5596", enable_flash_sis5596}, - {0x1039, 0x5571, NT, "SiS", "SiS 5571", enable_flash_sis530}, - {0x1039, 0x5591, NT, "SiS", "SiS 5591/5592", enable_flash_sis530}, - {0x1039, 0x5597, NT, "SiS", "SiS 5597/5598/5581/5120", enable_flash_sis530}, - {0x1039, 0x0530, NT, "SiS", "SiS 530", enable_flash_sis530}, - {0x1039, 0x5600, NT, "SiS", "SiS 600", enable_flash_sis530}, - {0x1039, 0x0620, NT, "SiS", "SiS 620", enable_flash_sis530}, - {0x1039, 0x0540, NT, "SiS", "SiS 540", enable_flash_sis540}, - {0x1039, 0x0630, NT, "SiS", "SiS 630", enable_flash_sis630}, - {0x1039, 0x0635, NT, "SiS", "SiS 635", enable_flash_sis630}, - {0x1039, 0x0640, NT, "SiS", "SiS 640", enable_flash_sis630}, - {0x1039, 0x0645, NT, "SiS", "SiS 645", enable_flash_sis630}, - {0x1039, 0x0646, NT, "SiS", "SiS 645DX", enable_flash_sis630}, - {0x1039, 0x0648, NT, "SiS", "SiS 648", enable_flash_sis630}, - {0x1039, 0x0650, NT, "SiS", "SiS 650", enable_flash_sis630}, - {0x1039, 0x0651, NT, "SiS", "SiS 651", enable_flash_sis630}, - {0x1039, 0x0655, NT, "SiS", "SiS 655", enable_flash_sis630}, - {0x1039, 0x0730, NT, "SiS", "SiS 730", enable_flash_sis630}, - {0x1039, 0x0733, NT, "SiS", "SiS 733", enable_flash_sis630}, - {0x1039, 0x0735, NT, "SiS", "SiS 735", enable_flash_sis630}, - {0x1039, 0x0740, NT, "SiS", "SiS 740", enable_flash_sis630}, - {0x1039, 0x0745, NT, "SiS", "SiS 745", enable_flash_sis630}, - {0x1039, 0x0746, NT, "SiS", "SiS 746", enable_flash_sis630}, - {0x1039, 0x0748, NT, "SiS", "SiS 748", enable_flash_sis630}, - {0x1039, 0x0755, NT, "SiS", "SiS 755", enable_flash_sis630}, + {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, + {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, + {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511}, + {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5596}, + {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530}, + {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530}, + {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, + {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530}, + {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, + {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, + {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, + {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis630}, + {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis630}, + {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis630}, + {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis630}, + {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis630}, + {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis630}, + {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis630}, + {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis630}, + {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis630}, + {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis630}, + {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis630}, + {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis630}, + {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis630}, + {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis630}, + {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis630}, + {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis630}, + {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis630}, {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x}, Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-11-15 17:13:29 UTC (rev 759) +++ trunk/print.c 2009-11-15 17:20:21 UTC (rev 760) @@ -260,6 +260,7 @@ { "ASUS", "P6T Deluxe V2", }, { "A-Trend", "ATC-6220", }, { "BCOM", "WinNET100", }, + { "Elitegroup", "K7S5A", }, { "Elitegroup", "P6VAP-A+", }, { "GIGABYTE", "GA-6BXC", }, { "GIGABYTE", "GA-6BXDU", },

1 0

[commit] r759 - trunk
by svn＠flashrom.org 15 Nov '09

15 Nov '09

Author: hailfinger Date: 2009-11-15 18:13:29 +0100 (Sun, 15 Nov 2009) New Revision: 759 Modified: trunk/chipset_enable.c trunk/flash.h trunk/internal.c Log: Add support for every single SiS chipset out there. The two existing SiS chipset enables (compared to the 28 in this patch) were refactored, and one of them was fixed. A function to match PCI vendor/class combinations was added to generic code. Tested on the "Elitegroup K7S5A". Results are somewhat unexpected (some PCI settings seem to be inaccessible, but it still works). This is not based on any docs, but rather on detailed analysis of existing opensource code for some of the chipsets. Thanks to for Adrian Glaubitz testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Adrian Glaubitz <glaubitz(a)physik.fu-berlin.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-11-14 03:58:58 UTC (rev 758) +++ trunk/chipset_enable.c 2009-11-15 17:13:29 UTC (rev 759) @@ -70,54 +70,193 @@ return 0; } +static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) +{ + uint8_t tmp; + + tmp = pci_read_byte(dev, 0xd0); + tmp |= 0xf8; + pci_write_byte(dev, 0xd0, tmp); + + return 0; +} + +static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name) +{ + uint8_t new, newer; + + /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ + /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ + new = pci_read_byte(dev, 0x40); + new &= (~0x04); /* No idea why we clear bit 2. */ + new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */ + pci_write_byte(dev, 0x40, new); + newer = pci_read_byte(dev, 0x40); + if (newer != new) { + printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + printf_debug("Stuck at 0x%x\n", newer); + return -1; + } + return 0; +} + +static struct pci_dev *find_southbridge(uint16_t vendor, const char *name) +{ + struct pci_dev *sbdev; + + sbdev = pci_dev_find_vendorclass(vendor, 0x0601); + if (!sbdev) + sbdev = pci_dev_find_vendorclass(vendor, 0x0680); + if (!sbdev) + sbdev = pci_dev_find_vendorclass(vendor, 0x0000); + if (!sbdev) + fprintf(stderr, "No southbridge found for %s!\n", name); + if (sbdev) + printf_debug("Found southbridge %04x:%04x at %02x:%02x:%01x\n", + sbdev->vendor_id, sbdev->device_id, + sbdev->bus, sbdev->dev, sbdev->func); + return sbdev; +} + +static int enable_flash_sis501(struct pci_dev *dev, const char *name) +{ + uint8_t tmp; + int ret = 0; + struct pci_dev *sbdev; + + sbdev = find_southbridge(dev->vendor_id, name); + if (!sbdev) + return -1; + + ret = enable_flash_sis_mapping(sbdev, name); + + tmp = sio_read(0x22, 0x80); + tmp &= (~0x20); + tmp |= 0x4; + sio_write(0x22, 0x80, tmp); + + tmp = sio_read(0x22, 0x70); + tmp &= (~0x20); + tmp |= 0x4; + sio_write(0x22, 0x70, tmp); + + return ret; +} + +static int enable_flash_sis5511(struct pci_dev *dev, const char *name) +{ + uint8_t tmp; + int ret = 0; + struct pci_dev *sbdev; + + sbdev = find_southbridge(dev->vendor_id, name); + if (!sbdev) + return -1; + + ret = enable_flash_sis_mapping(sbdev, name); + + tmp = sio_read(0x22, 0x50); + tmp &= (~0x20); + tmp |= 0x4; + sio_write(0x22, 0x50, tmp); + + return ret; +} + +static int enable_flash_sis5596(struct pci_dev *dev, const char *name) +{ + int ret; + + ret = enable_flash_sis5511(dev, name); + + /* FIXME: Needs same superio handling as enable_flash_sis630 */ + return ret; +} + +static int enable_flash_sis530(struct pci_dev *dev, const char *name) +{ + uint8_t new, newer; + int ret = 0; + struct pci_dev *sbdev; + + sbdev = find_southbridge(dev->vendor_id, name); + if (!sbdev) + return -1; + + ret = enable_flash_sis_mapping(sbdev, name); + + new = pci_read_byte(sbdev, 0x45); + new &= (~0x20); + new |= 0x4; + pci_write_byte(sbdev, 0x45, new); + newer = pci_read_byte(dev, 0x45); + if (newer != new) { + printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + printf_debug("Stuck at 0x%x\n", newer); + ret = -1; + } + + return ret; +} + +static int enable_flash_sis540(struct pci_dev *dev, const char *name) +{ + uint8_t new, newer; + int ret = 0; + struct pci_dev *sbdev; + + sbdev = find_southbridge(dev->vendor_id, name); + if (!sbdev) + return -1; + + ret = enable_flash_sis_mapping(sbdev, name); + + new = pci_read_byte(sbdev, 0x45); + new &= (~0x80); + new |= 0x40; + pci_write_byte(sbdev, 0x45, new); + newer = pci_read_byte(dev, 0x45); + if (newer != new) { + printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + printf_debug("Stuck at 0x%x\n", newer); + ret = -1; + } + + return ret; +} + static int enable_flash_sis630(struct pci_dev *dev, const char *name) { - uint8_t b; + uint8_t tmp; + uint16_t siobase; + int ret; - /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ - b = pci_read_byte(dev, 0x40); - pci_write_byte(dev, 0x40, b | 0xb); + ret = enable_flash_sis540(dev, name); - /* Flash write enable on SiS 540/630. */ - b = pci_read_byte(dev, 0x45); - pci_write_byte(dev, 0x45, b | 0x40); - /* The same thing on SiS 950 Super I/O side... */ /* First probe for Super I/O on config port 0x2e. */ - OUTB(0x87, 0x2e); - OUTB(0x01, 0x2e); - OUTB(0x55, 0x2e); - OUTB(0x55, 0x2e); + siobase = 0x2e; + enter_conf_mode_ite(siobase); - if (INB(0x2f) != 0x87) { + if (INB(siobase + 1) != 0x87) { /* If that failed, try config port 0x4e. */ - OUTB(0x87, 0x4e); - OUTB(0x01, 0x4e); - OUTB(0x55, 0x4e); - OUTB(0xaa, 0x4e); - if (INB(0x4f) != 0x87) { - printf("Can not access SiS 950\n"); + siobase = 0x4e; + enter_conf_mode_ite(siobase); + if (INB(siobase + 1) != 0x87) { + printf("Can not find SuperI/O.\n"); return -1; } - OUTB(0x24, 0x4e); - b = INB(0x4f) | 0xfc; - OUTB(0x24, 0x4e); - OUTB(b, 0x4f); - OUTB(0x02, 0x4e); - OUTB(0x02, 0x4f); } - OUTB(0x24, 0x2e); - printf_debug("2f is %#x\n", INB(0x2f)); - b = INB(0x2f) | 0xfc; - OUTB(0x24, 0x2e); - OUTB(b, 0x2f); + /* Enable flash mapping. Works for most old ITE style SuperI/O. */ + tmp = sio_read(siobase, 0x24); + tmp |= 0xfc; + sio_write(siobase, 0x24, tmp); - OUTB(0x02, 0x2e); - OUTB(0x02, 0x2f); + exit_conf_mode_ite(siobase); - return 0; + return ret; } /* Datasheet: @@ -603,38 +742,6 @@ return 0; } -static int enable_flash_sis5595(struct pci_dev *dev, const char *name) -{ - uint8_t new, newer; - - new = pci_read_byte(dev, 0x45); - - new &= (~0x20); /* Clear bit 5. */ - new |= 0x4; /* Set bit 2. */ - - pci_write_byte(dev, 0x45, new); - - newer = pci_read_byte(dev, 0x45); - if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf_debug("Stuck at 0x%x\n", newer); - return -1; - } - - /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ - new = pci_read_byte(dev, 0x40); - new &= 0xFB; - new |= 0x3; - pci_write_byte(dev, 0x40, new); - newer = pci_read_byte(dev, 0x40); - if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); - printf_debug("Stuck at 0x%x\n", newer); - return -1; - } - return 0; -} - /* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) { @@ -1048,8 +1155,34 @@ {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp55}, - {0x1039, 0x0008, OK, "SiS", "SiS5595", enable_flash_sis5595}, - {0x1039, 0x0630, NT, "SiS", "SiS630", enable_flash_sis630}, + {0x1039, 0x0496, NT, "SiS", "SiS 85C496+497", enable_flash_sis85c496}, + {0x1039, 0x0406, NT, "SiS", "SiS 501/5101/5501", enable_flash_sis501}, + {0x1039, 0x5511, NT, "SiS", "SiS 5511", enable_flash_sis5511}, + {0x1039, 0x5596, NT, "SiS", "SiS 5596", enable_flash_sis5596}, + {0x1039, 0x5571, NT, "SiS", "SiS 5571", enable_flash_sis530}, + {0x1039, 0x5591, NT, "SiS", "SiS 5591/5592", enable_flash_sis530}, + {0x1039, 0x5597, NT, "SiS", "SiS 5597/5598/5581/5120", enable_flash_sis530}, + {0x1039, 0x0530, NT, "SiS", "SiS 530", enable_flash_sis530}, + {0x1039, 0x5600, NT, "SiS", "SiS 600", enable_flash_sis530}, + {0x1039, 0x0620, NT, "SiS", "SiS 620", enable_flash_sis530}, + {0x1039, 0x0540, NT, "SiS", "SiS 540", enable_flash_sis540}, + {0x1039, 0x0630, NT, "SiS", "SiS 630", enable_flash_sis630}, + {0x1039, 0x0635, NT, "SiS", "SiS 635", enable_flash_sis630}, + {0x1039, 0x0640, NT, "SiS", "SiS 640", enable_flash_sis630}, + {0x1039, 0x0645, NT, "SiS", "SiS 645", enable_flash_sis630}, + {0x1039, 0x0646, NT, "SiS", "SiS 645DX", enable_flash_sis630}, + {0x1039, 0x0648, NT, "SiS", "SiS 648", enable_flash_sis630}, + {0x1039, 0x0650, NT, "SiS", "SiS 650", enable_flash_sis630}, + {0x1039, 0x0651, NT, "SiS", "SiS 651", enable_flash_sis630}, + {0x1039, 0x0655, NT, "SiS", "SiS 655", enable_flash_sis630}, + {0x1039, 0x0730, NT, "SiS", "SiS 730", enable_flash_sis630}, + {0x1039, 0x0733, NT, "SiS", "SiS 733", enable_flash_sis630}, + {0x1039, 0x0735, NT, "SiS", "SiS 735", enable_flash_sis630}, + {0x1039, 0x0740, NT, "SiS", "SiS 740", enable_flash_sis630}, + {0x1039, 0x0745, NT, "SiS", "SiS 745", enable_flash_sis630}, + {0x1039, 0x0746, NT, "SiS", "SiS 746", enable_flash_sis630}, + {0x1039, 0x0748, NT, "SiS", "SiS 748", enable_flash_sis630}, + {0x1039, 0x0755, NT, "SiS", "SiS 755", enable_flash_sis630}, {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x}, Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-11-14 03:58:58 UTC (rev 758) +++ trunk/flash.h 2009-11-15 17:13:29 UTC (rev 759) @@ -389,6 +389,7 @@ /* internal.c */ struct pci_dev *pci_dev_find_filter(struct pci_filter filter); +struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-11-14 03:58:58 UTC (rev 758) +++ trunk/internal.c 2009-11-15 17:13:29 UTC (rev 759) @@ -42,6 +42,26 @@ return NULL; } +struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class) +{ + struct pci_dev *temp; + struct pci_filter filter; + uint16_t tmp2; + + pci_filter_init(NULL, &filter); + filter.vendor = vendor; + + for (temp = pacc->devices; temp; temp = temp->next) + if (pci_filter_match(&filter, temp)) { + /* Read PCI class */ + tmp2 = pci_read_word(temp, 0x0a); + if (tmp2 == class) + return temp; + } + + return NULL; +} + struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device) { struct pci_dev *temp;

1 0

[PATCH] Add support for every single SiS chipset out there
by Carl-Daniel Hailfinger 15 Nov '09

15 Nov '09

Add support for every single SiS chipset out there. The two existing SiS chipset enables (compared to the 28 in this patch) were refactored, and one of them was fixed. A function to match PCI vendor/class combinations was added to generic code. Untested. This is not based on any docs, but rather on detailed analysis of existing opensource code for some of the chipsets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-sis_all/flash.h =================================================================== --- flashrom-sis_all/flash.h (Revision 758) +++ flashrom-sis_all/flash.h (Arbeitskopie) @@ -389,6 +389,7 @@ /* internal.c */ struct pci_dev *pci_dev_find_filter(struct pci_filter filter); +struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); Index: flashrom-sis_all/chipset_enable.c =================================================================== --- flashrom-sis_all/chipset_enable.c (Revision 758) +++ flashrom-sis_all/chipset_enable.c (Arbeitskopie) @@ -70,54 +70,190 @@ return 0; } +static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) +{ + uint8_t tmp; + + tmp = pci_read_byte(dev, 0xd0); + tmp |= 0xf8; + pci_write_byte(dev, 0xd0, tmp); + + return 0; +} + +static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name) +{ + uint8_t new, newer; + + /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ + /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ + new = pci_read_byte(dev, 0x40); + new &= (~0x04); /* No idea why we clear bit 2. */ + new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */ + pci_write_byte(dev, 0x40, new); + newer = pci_read_byte(dev, 0x40); + if (newer != new) { + printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + printf_debug("Stuck at 0x%x\n", newer); + return -1; + } + return 0; +} + +static struct pci_dev *find_southbridge(uint16_t vendor, const char *name) +{ + struct pci_dev *sbdev; + + sbdev = pci_dev_find_vendorclass(vendor, 0x0601); + if (!sbdev) + sbdev = pci_dev_find_vendorclass(vendor, 0x0680); + if (!sbdev) + sbdev = pci_dev_find_vendorclass(vendor, 0x0000); + if (!sbdev) + fprintf(stderr, "No southbridge found for %s!\n", name); + + return sbdev; +} + +static int enable_flash_sis501(struct pci_dev *dev, const char *name) +{ + uint8_t tmp; + int ret = 0; + struct pci_dev *sbdev; + + sbdev = find_southbridge(dev->vendor_id, name); + if (!sbdev) + return -1; + + ret = enable_flash_sis_mapping(sbdev, name); + + tmp = sio_read(0x22, 0x80); + tmp &= (~0x20); + tmp |= 0x4; + sio_write(0x22, 0x80, tmp); + + tmp = sio_read(0x22, 0x70); + tmp &= (~0x20); + tmp |= 0x4; + sio_write(0x22, 0x70, tmp); + + return ret; +} + +static int enable_flash_sis5511(struct pci_dev *dev, const char *name) +{ + uint8_t tmp; + int ret = 0; + struct pci_dev *sbdev; + + sbdev = find_southbridge(dev->vendor_id, name); + if (!sbdev) + return -1; + + ret = enable_flash_sis_mapping(sbdev, name); + + tmp = sio_read(0x22, 0x50); + tmp &= (~0x20); + tmp |= 0x4; + sio_write(0x22, 0x50, tmp); + + return ret; +} + +static int enable_flash_sis5596(struct pci_dev *dev, const char *name) +{ + int ret; + + ret = enable_flash_sis5511(dev, name); + + /* FIXME: Needs same superio handling as enable_flash_sis630 */ + return ret; +} + +static int enable_flash_sis530(struct pci_dev *dev, const char *name) +{ + uint8_t new, newer; + int ret = 0; + struct pci_dev *sbdev; + + sbdev = find_southbridge(dev->vendor_id, name); + if (!sbdev) + return -1; + + ret = enable_flash_sis_mapping(sbdev, name); + + new = pci_read_byte(sbdev, 0x45); + new &= (~0x20); + new |= 0x4; + pci_write_byte(sbdev, 0x45, new); + newer = pci_read_byte(dev, 0x45); + if (newer != new) { + printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + printf_debug("Stuck at 0x%x\n", newer); + ret = -1; + } + + return ret; +} + +static int enable_flash_sis540(struct pci_dev *dev, const char *name) +{ + uint8_t new, newer; + int ret = 0; + struct pci_dev *sbdev; + + sbdev = find_southbridge(dev->vendor_id, name); + if (!sbdev) + return -1; + + ret = enable_flash_sis_mapping(sbdev, name); + + new = pci_read_byte(sbdev, 0x45); + new &= (~0x80); + new |= 0x40; + pci_write_byte(sbdev, 0x45, new); + newer = pci_read_byte(dev, 0x45); + if (newer != new) { + printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + printf_debug("Stuck at 0x%x\n", newer); + ret = -1; + } + + return ret; +} + static int enable_flash_sis630(struct pci_dev *dev, const char *name) { - uint8_t b; + uint8_t tmp; + uint16_t siobase; + int ret; - /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ - b = pci_read_byte(dev, 0x40); - pci_write_byte(dev, 0x40, b | 0xb); + ret = enable_flash_sis540(dev, name); - /* Flash write enable on SiS 540/630. */ - b = pci_read_byte(dev, 0x45); - pci_write_byte(dev, 0x45, b | 0x40); - /* The same thing on SiS 950 Super I/O side... */ /* First probe for Super I/O on config port 0x2e. */ - OUTB(0x87, 0x2e); - OUTB(0x01, 0x2e); - OUTB(0x55, 0x2e); - OUTB(0x55, 0x2e); + siobase = 0x2e; + enter_conf_mode_ite(siobase); - if (INB(0x2f) != 0x87) { + if (INB(siobase + 1) != 0x87) { /* If that failed, try config port 0x4e. */ - OUTB(0x87, 0x4e); - OUTB(0x01, 0x4e); - OUTB(0x55, 0x4e); - OUTB(0xaa, 0x4e); - if (INB(0x4f) != 0x87) { - printf("Can not access SiS 950\n"); + siobase = 0x4e; + enter_conf_mode_ite(siobase); + if (INB(siobase + 1) != 0x87) { + printf("Can not find SuperI/O.\n"); return -1; } - OUTB(0x24, 0x4e); - b = INB(0x4f) | 0xfc; - OUTB(0x24, 0x4e); - OUTB(b, 0x4f); - OUTB(0x02, 0x4e); - OUTB(0x02, 0x4f); } - OUTB(0x24, 0x2e); - printf_debug("2f is %#x\n", INB(0x2f)); - b = INB(0x2f) | 0xfc; - OUTB(0x24, 0x2e); - OUTB(b, 0x2f); + /* Enable flash mapping. Works for most old ITE style SuperI/O. */ + tmp = sio_read(siobase, 0x24); + tmp |= 0xfc; + sio_write(siobase, 0x24, tmp); - OUTB(0x02, 0x2e); - OUTB(0x02, 0x2f); + exit_conf_mode_ite(siobase); - return 0; + return ret; } /* Datasheet: @@ -603,38 +739,6 @@ return 0; } -static int enable_flash_sis5595(struct pci_dev *dev, const char *name) -{ - uint8_t new, newer; - - new = pci_read_byte(dev, 0x45); - - new &= (~0x20); /* Clear bit 5. */ - new |= 0x4; /* Set bit 2. */ - - pci_write_byte(dev, 0x45, new); - - newer = pci_read_byte(dev, 0x45); - if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf_debug("Stuck at 0x%x\n", newer); - return -1; - } - - /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ - new = pci_read_byte(dev, 0x40); - new &= 0xFB; - new |= 0x3; - pci_write_byte(dev, 0x40, new); - newer = pci_read_byte(dev, 0x40); - if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); - printf_debug("Stuck at 0x%x\n", newer); - return -1; - } - return 0; -} - /* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) { @@ -1048,8 +1152,34 @@ {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp55}, - {0x1039, 0x0008, OK, "SiS", "SiS5595", enable_flash_sis5595}, - {0x1039, 0x0630, NT, "SiS", "SiS630", enable_flash_sis630}, + {0x1039, 0x0496, NT, "SiS", "SiS 85C496+497", enable_flash_sis85c496}, + {0x1039, 0x0406, NT, "SiS", "SiS 501/5101/5501", enable_flash_sis501}, + {0x1039, 0x5511, NT, "SiS", "SiS 5511", enable_flash_sis5511}, + {0x1039, 0x5596, NT, "SiS", "SiS 5596", enable_flash_sis5596}, + {0x1039, 0x5571, NT, "SiS", "SiS 5571", enable_flash_sis530}, + {0x1039, 0x5591, NT, "SiS", "SiS 5591/5592", enable_flash_sis530}, + {0x1039, 0x5597, NT, "SiS", "SiS 5597/5598/5581/5120", enable_flash_sis530}, + {0x1039, 0x0530, NT, "SiS", "SiS 530", enable_flash_sis530}, + {0x1039, 0x5600, NT, "SiS", "SiS 600", enable_flash_sis530}, + {0x1039, 0x0620, NT, "SiS", "SiS 620", enable_flash_sis530}, + {0x1039, 0x0540, NT, "SiS", "SiS 540", enable_flash_sis540}, + {0x1039, 0x0630, NT, "SiS", "SiS 630", enable_flash_sis630}, + {0x1039, 0x0635, NT, "SiS", "SiS 635", enable_flash_sis630}, + {0x1039, 0x0640, NT, "SiS", "SiS 640", enable_flash_sis630}, + {0x1039, 0x0645, NT, "SiS", "SiS 645", enable_flash_sis630}, + {0x1039, 0x0646, NT, "SiS", "SiS 645DX", enable_flash_sis630}, + {0x1039, 0x0648, NT, "SiS", "SiS 648", enable_flash_sis630}, + {0x1039, 0x0650, NT, "SiS", "SiS 650", enable_flash_sis630}, + {0x1039, 0x0651, NT, "SiS", "SiS 651", enable_flash_sis630}, + {0x1039, 0x0655, NT, "SiS", "SiS 655", enable_flash_sis630}, + {0x1039, 0x0730, NT, "SiS", "SiS 730", enable_flash_sis630}, + {0x1039, 0x0733, NT, "SiS", "SiS 733", enable_flash_sis630}, + {0x1039, 0x0735, NT, "SiS", "SiS 735", enable_flash_sis630}, + {0x1039, 0x0740, NT, "SiS", "SiS 740", enable_flash_sis630}, + {0x1039, 0x0745, NT, "SiS", "SiS 745", enable_flash_sis630}, + {0x1039, 0x0746, NT, "SiS", "SiS 746", enable_flash_sis630}, + {0x1039, 0x0748, NT, "SiS", "SiS 748", enable_flash_sis630}, + {0x1039, 0x0755, NT, "SiS", "SiS 755", enable_flash_sis630}, {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x}, Index: flashrom-sis_all/internal.c =================================================================== --- flashrom-sis_all/internal.c (Revision 758) +++ flashrom-sis_all/internal.c (Arbeitskopie) @@ -42,6 +42,26 @@ return NULL; } +struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class) +{ + struct pci_dev *temp; + struct pci_filter filter; + uint16_t tmp2; + + pci_filter_init(NULL, &filter); + filter.vendor = vendor; + + for (temp = pacc->devices; temp; temp = temp->next) + if (pci_filter_match(&filter, temp)) { + /* Read PCI class */ + tmp2 = pci_read_word(temp, 0x0a); + if (tmp2 == class) + return temp; + } + + return NULL; +} + struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device) { struct pci_dev *temp; -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

2 6

Output of flashrom -V on several boards
by Adrian Glaubitz 15 Nov '09

15 Nov '09

Hello, I've played around with flashrom on several different machines in my university. I haven't flashed yet any of the boards. However, there are alot of boards where flashrom detects the chip but it's not listed on the webpage. I will try flashing these boards within the next weeks once I have more time (it's not the flashing that takes so much time but the recovery of the machine in case the flash failed :)). AsRock Conroe945G: http://pastebin.org/53578 - Chip detected: "Winbond W39V040B" (512 KB, LPC) AsRock K7S8X: http://pastebin.org/53576 - NO Chip detected AsRock K8Upgrade: http://pastebin.org/53574 - Chip detected: "PMC Pm49FL002" (256 KB, LPC,FWH) ASUS K8V-XSE: http://pastebin.org/53579 - Chip detected: "PMC Pm49FL004" (512 KB, LPC,FWH) ASUS P4P-X: http://pastebin.org/53573 - Chip detected: "PMC Pm49FL002" (256 KB, LPC,FWH) ASUS P4T-E: http://pastebin.org/53572 - Chip detected: "SST SST49LF002A/B" (256 KB, FWH) ASUS P5B: http://pastebin.org/53580 - Chip detected: "SST SST25VF080B" (1024 KB, SPI) Elitegroup K7S5A: http://pastebin.org/53571 - NO Chip detected Supermicro H8DAR-T: http://pastebin.org/53583 - Chip detected: "SST SST49LF004A/B" (512 KB, FWH) Supermicro H8DA8: http://pastebin.org/53585 - Chip detected: "SST SST49LF004A/B" (512 KB, FWH) Looking forward to provide more reports, then *with* actual flashing of the boards. Adrian

2 2

Sucessfully used Flashrom with Asus M2V mainboard.
by Johannes Sjölund 14 Nov '09

14 Nov '09

Hi, I wanted to update the proprietary firmware on an Asus M2V mainboard from version 1603 to 2101. Having no floppy drive or Windows OS I browsed for the easiest way to do it on Linux and found Flashrom. I read the wiki page and found out the mainboard was supported. After downloading a package from the Asus website containing the firmware I checked with people on the IRC channel to get confirmation the filesize was correct. It was, so I charged ahead and wrote the new firmware to the chip, verified it against the file and rebooted. It worked prefectly! After that I was told that I should have read out what I had written on the chip and compared the md5sum with the downloaded firmware file. It seems I was a little reckless, but it ended well. Thank you for your good work on Flashrom!

2 1

[commit] r758 - trunk
by svn＠flashrom.org 14 Nov '09

14 Nov '09

Author: hailfinger Date: 2009-11-14 04:58:58 +0100 (Sat, 14 Nov 2009) New Revision: 758 Modified: trunk/print.c Log: Mark "Asus K8V" as supported. Reported by martin f krafft <madduck(a)madduck.net> Mark "Asus K8V SE Deluxe" as supported. Reported by Luke Dashjr <luke_coreboot(a)dashjr.org> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-11-14 03:48:33 UTC (rev 757) +++ trunk/print.c 2009-11-14 03:58:58 UTC (rev 758) @@ -242,6 +242,8 @@ { "ASUS", "A8V Deluxe", }, { "ASUS", "A8V-E Deluxe", }, { "ASUS", "A8V-E SE", }, + { "ASUS", "K8V", }, + { "ASUS", "K8V SE Deluxe", }, { "ASUS", "M2A-MX", }, { "ASUS", "M2A-VM", }, { "ASUS", "M2N-E", },

1 0

Success: Asus K8V (plain) motherboard (VIA VT8237)
by martin f krafft 14 Nov '09

14 Nov '09

Hey folks, Just wanted to report success in flashrom'ing a plain Asus K8V (no -X, -SE, Deluxe, whatever) using the ROM obtained from here: http://support.asus.com/download/download_item.aspx?product=1&model=K8V # flashrom -w K8VB1007.AMI Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found chip "Winbond W29C040P" (512 KB) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 2047 at address: 0x0007ff00 Reading and verifying similarly worked. I used flashrom from Debian lenny, version 0.0+r3397-1. Thanks a lot. flashrom made my life a lot easier today! -- martin | http://madduck.net/ | http://two.sentenc.es/ "they that can give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -- benjamin franklin spamtraps: madduck.bogus(a)madduck.net

2 1

[commit] r757 - trunk
by svn＠flashrom.org 14 Nov '09

14 Nov '09

Author: hailfinger Date: 2009-11-14 04:48:33 +0100 (Sat, 14 Nov 2009) New Revision: 757 Modified: trunk/flashchips.c trunk/jedec.c Log: The automatic retry in write_page_write_jedec didn't retry flashing the correct range, essentially rendering the functionality useless. This patch simplifies the code and fixes the bug. Thanks to Luke Dashjr for testing. Mark Winbond W29C040P as supported. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luke Dashjr <luke_coreboot(a)dashjr.org> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-11-06 18:09:42 UTC (rev 756) +++ trunk/flashchips.c 2009-11-14 03:48:33 UTC (rev 757) @@ -3060,7 +3060,7 @@ .model_id = W_29C040P, .total_size = 512, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .erase = erase_chip_jedec, Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-11-06 18:09:42 UTC (rev 756) +++ trunk/jedec.c 2009-11-14 03:48:33 UTC (rev 757) @@ -262,7 +262,7 @@ int write_page_write_jedec(struct flashchip *flash, uint8_t *src, int start, int page_size) { - int i, tried = 0, start_index = 0, ok; + int i, tried = 0, ok; uint8_t *s = src; chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; @@ -275,7 +275,7 @@ chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - for (i = start_index; i < page_size; i++) { + for (i = 0; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) chip_writeb(*src, dst); @@ -290,7 +290,7 @@ ok = !verify_range(flash, src, start, page_size, NULL); if (!ok && tried++ < MAX_REFLASH_TRIES) { - start_index = i; + fprintf(stderr, "retrying.\n"); goto retry; } if (!ok) {

1 0

Fix write_page_write_jedec retry, mark W29C040P as OK
by Carl-Daniel Hailfinger 14 Nov '09

14 Nov '09

The automatic retry in write_page_write_jedec didn't retry flashing the correct range, essentially rendering the functionality useless. This patch simplifies the code and fixes the bug. Mark Winbond W29C040P as supported. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-write_page_write_jedec_retry/jedec.c =================================================================== --- flashrom-write_page_write_jedec_retry/jedec.c (Revision 756) +++ flashrom-write_page_write_jedec_retry/jedec.c (Arbeitskopie) @@ -262,7 +262,7 @@ int write_page_write_jedec(struct flashchip *flash, uint8_t *src, int start, int page_size) { - int i, tried = 0, start_index = 0, ok; + int i, tried = 0, ok; uint8_t *s = src; chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; @@ -275,7 +275,7 @@ chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - for (i = start_index; i < page_size; i++) { + for (i = 0; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) chip_writeb(*src, dst); @@ -290,7 +290,7 @@ ok = !verify_range(flash, src, start, page_size, NULL); if (!ok && tried++ < MAX_REFLASH_TRIES) { - start_index = i; + fprintf(stderr, "retrying.\n"); goto retry; } if (!ok) { Index: flashrom-write_page_write_jedec_retry/flashchips.c =================================================================== --- flashrom-write_page_write_jedec_retry/flashchips.c (Revision 756) +++ flashrom-write_page_write_jedec_retry/flashchips.c (Arbeitskopie) @@ -3060,7 +3060,7 @@ .model_id = W_29C040P, .total_size = 512, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .erase = erase_chip_jedec, -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

2 2

Help: DO NOT REBOOT OR POWEROFF!
by NotLim 10 Nov '09

10 Nov '09

Hi there. I'm at #flashrom at freenode, but no one responds... so... can you give me a hand? Here's the problem: http://pastebin.com/m11614dbc Thanks!

4 3

[commit] r756 - trunk
by svn＠flashrom.org 06 Nov '09

06 Nov '09

Author: hailfinger Date: 2009-11-06 18:09:42 +0000 (Fri, 06 Nov 2009) New Revision: 756 Modified: trunk/flashchips.c Log: Fix incorrect comment in SST49LF004A/B description. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-10-31 01:53:09 UTC (rev 755) +++ trunk/flashchips.c 2009-11-06 18:09:42 UTC (rev 756) @@ -2236,7 +2236,7 @@ .block_erase = erase_sector_jedec, /* missing unlock */ }, { .eraseblocks = { {64 * 1024, 8} }, - .block_erase = erase_sst_fwhub_block, /* same as erase_sector_block, but with unlock */ + .block_erase = erase_sst_fwhub_block, /* same as erase_block_jedec, but with unlock */ }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = NULL, /* AA 55 80 AA 55 10, only in PP mode */

1 0

Remarks on flashing ASUS M2N-E
by Adrian Glaubitz 06 Nov '09

06 Nov '09

Hi guys, I have used flashrom (version 0.9.1+r736-1 from Debian testing) to program the latest BIOS into my ASUS M2N-E mainboard. According to flashrom, erasing and programming the BIOS chip was successful. However, after rebooting the machine wouldn't fire up again. It powered up but there was no sync signal on the VGA/DVI connector, also no reaction to keyboard input. Fortunately, I could restore normal operation by resetting the CMOS settings. The computer worked fine again except that the hardware network address had changed to an arbitrary value so that I couldn't connect to my local network at first anymore. I think, however, that the MAC can be restored with the AWDFLASH.EXE flash utility which has an option called "/MAC:" (haven't tried yet, network works fine after matching the MAC on our local DHCP servers). Thus, it would be nice if you could update the entry in the flashrom wiki with two footnotes on the ASUS M2N-E: [1] If the machine doesn't come up again after flashing, try resetting the CMOS. [2] Hardware address of the onboard network card might change to an arbitrary value. Especially [1] should be put as a footnote because despite the fact that it is *always* recommended to reset your CMOS settings after flashing a new BIOS version, the machine usually still comes up again after flashing, prompting with something like "CMOS checksum error or invalid settings". I just want to provide flashrom users with as much information on possible caveats as possible. Regards, Adrian

1 0

ECS P4VXASD2+
by Kyle Kienapfel 03 Nov '09

03 Nov '09

I've got a supported chipset and according to flashrom -L, a supported flash chip, but flashrom isn't detecting the flash chip. I verified that the read is accurate when I force it. Exact part number on the flash is W49F002U-12B I'd like to get this to work as the amiflash tool rebooted without warning making it scary to use. root@Console:~# /root/flashrom -r /tmp/fij2 flashrom v0.9.1-r710 No coreboot table found. Found chipset "VIA VT8235", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. root@Console:~# root@Console:~# /root/flashrom -c W49F002U -r /tmp/fij2 -f flashrom v0.9.1-r710 No coreboot table found. Found chipset "VIA VT8235", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Found chip "Winbond W49F002U" (256 KB, Parallel) at physical address 0xfffc0000 Please note that forced reads most likely contain garbage. Reading flash... done. root@Console:~# root@Console:~# /root/flashrom -V |grep W49F002U Probing for Winbond W49F002U, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content root@Console:~# root@Console:~# lspci -vvnnxxx 00:00.0 Host bridge [0600]: VIA Technologies, Inc. VT8753 [P4X266 AGP] [1106:3128] (rev 01) Subsystem: VIA Technologies, Inc. Device [1106:0000] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ INTx- Latency: 8 Region 0: Memory at e0000000 (32-bit, prefetchable) [size=64M] Capabilities: [a0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: via-agp, ipmi_si 00: 06 11 28 31 06 00 30 a2 01 00 00 06 00 08 00 00 10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 18 88 80 82 44 00 00 99 99 88 80 82 44 00 00 50: e8 be e7 88 6e 85 20 20 0e 00 00 00 10 20 20 20 60: 08 aa 00 20 20 d9 00 20 f9 29 32 50 40 04 00 00 70: 02 c8 00 01 31 01 10 00 01 00 00 00 00 00 00 00 80: 0f 61 00 00 c0 b0 88 00 02 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 c0 20 00 07 02 00 1f 00 00 00 00 2d 92 04 00 b0: 78 9b 10 9b 40 00 00 00 a8 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 71 38 74 00 e0: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 11 00 00 00 00 00 00 00 00 00 00:01.0 PCI bridge [0604]: VIA Technologies, Inc. VT8633 [Apollo Pro266 AGP] [1106:b091] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 Memory behind bridge: dde00000-dfefffff Prefetchable memory behind bridge: cdc00000-ddcfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: ipmi_si, shpchp 00: 06 11 91 b0 07 01 30 22 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 00 00 20: e0 dd e0 df c0 cd c0 dd 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00 40: 83 c7 00 44 24 72 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 02 02 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10) !!! Invalid class 0200 for header type 02 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR+ INTx- Latency: 32 Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at ec00 [size=256] Bus: primary=00, secondary=00, subordinate=02, sec-latency=0 Secondary status: SERR BridgeCtl: Parity- SERR+ ISA- VGA- MAbort+ >Reset- 16bInt- PostWrite- Kernel driver in use: 8139too Kernel modules: ipmi_si, 8139cp, 8139too 00: ec 10 3b 81 07 01 92 82 10 00 02 02 00 20 02 00 10: 01 ec 02 00 00 ff ff df 00 00 02 00 00 00 02 00 20: 00 00 02 00 00 00 02 00 00 00 02 00 ec 10 3b 81 30: 00 00 02 00 50 00 02 00 00 00 02 00 0b 01 22 40 40: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 50: 01 00 c2 f7 00 00 02 00 00 00 02 00 00 00 02 00 60: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 70: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 80: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 90: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 a0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 b0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 c0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 d0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 e0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 f0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 00:10.0 USB Controller [0c03]: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] (rev 80) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 5 Region 4: I/O ports at e000 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: ipmi_si, uhci-hcd 00: 06 11 38 30 17 00 10 02 80 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e0 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 05 01 00 00 40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.1 USB Controller [0c03]: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] (rev 80) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin B routed to IRQ 5 Region 4: I/O ports at e400 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: ipmi_si, uhci-hcd 00: 06 11 38 30 17 00 10 02 80 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e4 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 05 02 00 00 40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.2 USB Controller [0c03]: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] (rev 80) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin C routed to IRQ 5 Region 4: I/O ports at e800 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: ipmi_si, uhci-hcd 00: 06 11 38 30 17 00 10 02 80 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e8 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 05 03 00 00 40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.3 USB Controller [0c03]: VIA Technologies, Inc. USB 2.0 [1106:3104] (rev 82) (prog-if 20 [EHCI]) Subsystem: VIA Technologies, Inc. USB 2.0 [1106:3104] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 128 bytes Interrupt: pin D routed to IRQ 11 Region 0: Memory at dffffe00 (32-bit, non-prefetchable) [size=256] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd Kernel modules: ipmi_si, ehci-hcd 00: 06 11 04 31 17 00 10 02 82 20 03 0c 20 20 00 00 10: 00 fe ff df 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 04 31 30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 04 00 00 40: 00 00 03 00 00 00 00 00 a0 20 00 09 00 00 00 00 50: 00 5a 00 80 00 00 00 00 04 0b 88 88 53 88 00 00 60: 20 20 01 00 00 00 00 00 01 00 00 00 00 00 08 c0 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:11.0 ISA bridge [0601]: VIA Technologies, Inc. VT8235 ISA Bridge [1106:3177] Subsystem: VIA Technologies, Inc. KT4AV motherboard [1106:0000] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: ipmi_si, i2c-viapro, via-ircc 00: 06 11 77 31 87 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 44 00 f8 00 00 00 00 00 0c 20 00 00 44 00 08 08 50: 81 1d 09 00 00 50 55 b0 23 80 ff 00 00 00 04 08 60: 00 00 00 00 10 00 02 04 00 00 00 00 00 00 00 00 70: 06 11 00 00 00 00 00 00 00 00 00 00 20 00 00 00 80: 20 84 59 00 9a 10 00 00 01 08 00 00 00 18 00 00 90: 00 02 f3 00 b0 c4 00 00 10 a9 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 04 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00:11.1 IDE interface [0101]: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571] (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE [1106:0571] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Interrupt: pin A routed to IRQ 255 Region 4: I/O ports at fc00 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: VIA_IDE Kernel modules: via82cxxx 00: 06 11 71 05 07 00 90 02 06 8a 01 01 00 20 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fc 00 00 00 00 00 00 00 00 00 00 06 11 71 05 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 01 00 00 40: 0b f2 09 35 18 1c c0 00 a8 a8 a8 20 ff 00 b6 20 50: 07 07 07 07 0c 00 00 00 a8 a8 a8 a8 00 00 00 00 60: 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 70: 42 01 00 00 00 00 00 00 82 01 00 00 00 00 00 00 80: 00 70 15 1f 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 06 00 71 05 06 11 71 05 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 07 00 00 00 00 00 00 00 00 00 00:11.5 Multimedia audio controller [0401]: VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller [1106:3059] (rev 50) Subsystem: Elitegroup Computer Systems Device [1019:0a83] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin C routed to IRQ 5 Region 0: I/O ports at dc00 [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: ipmi_si, via82cxxx_audio, snd-via82xx 00: 06 11 59 30 01 00 10 02 50 00 01 04 00 00 00 00 10: 01 dc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 83 0a 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 03 00 00 40: 01 c8 00 00 00 00 00 00 00 00 00 00 3f 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 06 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 02 06 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:12.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6102 [Rhine-II] [1106:3065] (rev 74) Subsystem: VIA Technologies, Inc. VT6102 [Rhine II] Embeded Ethernet Controller on VT8235 [1106:0102] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (750ns min, 2000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 5 Region 0: I/O ports at d800 [size=256] Region 1: Memory at dffffd00 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: via-rhine Kernel modules: ipmi_si, via-rhine 00: 06 11 65 30 17 01 10 02 74 00 00 02 08 20 00 00 10: 01 d8 00 00 00 fd ff df 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 02 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 05 01 03 08 40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 VGA compatible controller [0300]: nVidia Corporation NV34 [GeForce FX 5500] [10de:0326] (rev a1) (prog-if 00 [VGA controller]) Subsystem: Chaintech Computer Co. Ltd Device [270f:1954] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (1250ns min, 250ns max) Interrupt: pin A routed to IRQ 5 Region 0: Memory at de000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at d0000000 (32-bit, prefetchable) [size=128M] Expansion ROM at dfee0000 [disabled] [size=128K] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [44] AGP version 3.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Kernel modules: ipmi_si, nvidiafb 00: de 10 26 03 07 00 b0 02 a1 00 00 03 00 20 00 00 10: 00 00 00 de 08 00 00 d0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 0f 27 54 19 30: 00 00 ee df 60 00 00 00 00 00 00 00 05 01 05 01 40: 0f 27 54 19 02 00 30 00 17 02 00 1f 00 00 00 00 50: 01 00 00 00 01 00 00 00 ce d6 23 00 0f 00 00 00 60: 01 44 02 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

1 0

Try on Lenovo TP T400s
by Ariel Garcia 01 Nov '09

01 Nov '09

Hello, i've tried flashrom on a Lenovo ThinkPad T400s laptop running kernel 2.6.31 (package version 2.6.31-trunk-amd64, Debian testing). See attached file pci.txt for the output of lspci Reading the ROM *seems* to work when run with -r, but complains Transaction error! run OPCODE 0x03 failed when run with -rV (see attached file flash.txt) The flash output file is also attached, although of a big size it seems to be empty because it compresses to 200 bytes :-( Let me know if i can test further. Best regards, Ariel

1 0

Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Spangler, Mike T 31 Oct '09

31 Oct '09

Carl-Daniel - I can tell everyone's very busy. Just wanted to make sure that I haven't been forgotten. The system is still up and ready for testing. Mike -----Original Message----- From: Spangler, Mike T Sent: Friday, September 18, 2009 4:48 PM To: 'Carl-Daniel Hailfinger' Cc: flashrom(a)flashrom.org Subject: RE: [flashrom] Trial of ARIMA:HDAMA Motherboard Carl-Daniel - Yes, we are stuck with factory bios for now and a lot of it's due to our reliance on HP hardware and their maintenance requirements. We do have legacy Linux Networx gear that I could run coreboot on with gPXE. I'll have to investigate that solution at a later date. Also, the good thing about my method of reading the bios and flashing what I read is that it moves my bios settings with the flash. If you pull the flash off of the factory distribution, you have to redo the bios settings for every node one at a time. Below is the lspci output per your request: 0000:00:18.0 Class 0600: 1022:1100 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] #08 [2101] Capabilities: [a0] #08 [2101] Capabilities: [c0] #08 [2101] 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 05 00 04 04 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 10 00 01 00 e4 00 00 00 00 c8 00 0f 74 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 20 00 11 11 22 04 75 80 02 00 00 00 90: 56 04 51 02 00 01 04 00 07 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:18.1 Class 0600: 1022:1101 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 ff 00 03 00 00 01 01 00 ff 01 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 03 00 f8 00 00 1f fb 00 c0: 03 10 00 00 00 20 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:18.2 Class 0600: 1022:1102 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 10 00 00 01 20 00 00 01 30 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 44 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 8c 33 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: fd 2f 13 bf d0 00 00 00 d7 ff 5e 81 d0 87 9f 90 c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 05 12 57 44 8d 44 e0 76 fe 8e 08 60 6d c8 54 69 e0: 14 44 63 6b e5 42 f3 db 33 8e 62 1c f4 4c b9 3a f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:18.3 Class 0600: 1022:1103 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 c0 02 00 00 00 00 00 00 00 00 50: 08 86 bb c0 60 00 00 00 16 16 16 00 40 d7 be 22 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 03 00 00 00 7a 00 00 00 00 dd ef 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 3c 00 00 80 db e5 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 07 e2 04 00 00 00 00 00 25 00 00 e0: 00 00 00 00 20 0c 57 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.0 Class 0600: 1022:1100 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] #08 [2101] Capabilities: [a0] #08 [2101] Capabilities: [c0] #08 [2101] 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 04 04 01 00 01 01 05 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 11 00 01 00 e4 00 00 00 00 c8 00 0f 7c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 90: 56 04 51 02 00 00 00 00 00 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 0c 34 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.1 Class 0600: 1022:1101 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 ff 00 03 00 00 01 01 00 ff 01 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 03 00 f8 00 00 1f fb 00 c0: 03 10 00 00 00 20 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.2 Class 0600: 1022:1102 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 10 00 00 01 20 00 00 01 30 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 44 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 8c 33 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 6f 68 15 bf d0 00 00 00 50 3e 50 02 c0 a1 42 d4 c0: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 58 6f ff 13 b4 43 27 ba b5 7f 19 9f 74 7f eb bb e0: f9 f6 cf bb 95 cd f3 bc 7d dc 8d af fd 99 ce a3 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.3 Class 0600: 1022:1103 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 c0 02 00 00 00 00 00 00 00 00 50: 88 71 e6 db 21 00 00 00 16 16 16 00 c0 d3 be 22 60: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 03 00 00 00 7a 00 00 00 00 dd ef 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 36 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 07 e2 04 00 00 00 00 00 25 00 00 e0: 00 00 00 00 20 10 55 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:01.0 Class 0604: 1022:7450 (rev 12) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=02, subordinate=02, sec-latency=64 I/O behind bridge: 00002000-00001fff Memory behind bridge: fb000000-fb0fffff Prefetchable memory behind bridge: 00000000fb100000-00000000fb000000 BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [a0] Capabilities: [b8] #08 [8000] Capabilities: [c0] #08 [0041] 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 01 02 02 40 21 11 20 22 20: 00 fb 00 fb 11 fb 01 fb 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 03 00 40: 07 00 1f 00 00 00 00 00 02 0c 00 00 01 2c 00 00 50: 00 00 03 00 00 00 05 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 03 00 08 01 03 00 0e 00 0e 00 02 00 02 00 b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 03 c0: 08 00 41 00 22 00 11 11 22 00 00 00 22 04 35 00 d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 04 04 10 00 04 04 0d 00 04 04 16 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:01.1 Class 0800: 1022:7451 (rev 01) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at fb100000 (64-bit, non-prefetchable) 00: 22 10 51 74 02 00 00 02 01 10 00 08 00 00 00 00 10: 04 00 10 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 03 00 00 00 04 00 10 fb 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:02.0 Class 0604: 1022:7450 (rev 12) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=03, subordinate=03, sec-latency=64 I/O behind bridge: 00002000-00001fff Memory behind bridge: fb100000-fb0fffff Prefetchable memory behind bridge: 00000000fa000000-00000000faf00000 BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [a0] Capabilities: [b8] #08 [8000] 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 01 03 03 40 21 11 20 a3 20: 10 fb 00 fb 01 fa f1 fa 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 03 00 40: 05 00 1f 00 00 00 00 00 00 00 00 00 01 2c 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 c3 00 10 01 03 00 0e 00 0e 00 02 00 02 00 b0: 00 00 00 00 00 00 00 00 08 00 00 80 00 00 00 04 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:02.1 Class 0800: 1022:7451 (rev 01) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at fb101000 (64-bit, non-prefetchable) 00: 22 10 51 74 02 00 00 02 01 10 00 08 00 00 00 00 10: 04 10 10 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 03 00 00 00 04 10 10 fb 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:03.0 Class 0604: 1022:7460 (rev 07) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=04, subordinate=04, sec-latency=64 I/O behind bridge: 00001000-00001fff Memory behind bridge: f8000000-f90fffff Prefetchable memory behind bridge: fb100000-fb0fffff Expansion ROM at 00001000 [disabled] [size=4K] BridgeCtl: Parity+ SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [c0] #08 [0083] Capabilities: [f0] #08 [8000] 00: 22 10 60 74 47 01 30 02 07 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 01 04 04 40 10 10 00 22 20: 00 f8 00 f9 10 fb 00 fb 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0f 08 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 08 f0 83 00 22 00 00 00 d0 00 00 00 22 00 01 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 0f 00 08 00 11 00 0f 00 17 00 00 00 00 00 f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.0 Class 0601: 1022:7468 (rev 05) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: 22 10 68 74 0f 00 20 02 05 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 30 07 c0 01 00 00 02 9f fd 00 01 00 00 00 c0 50: 00 00 00 00 85 01 00 00 44 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 de 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.1 Class 0101: 1022:7469 (rev 03) (prog-if 8a [Master SecP PriP]) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Region 4: I/O ports at 0f00 [size=16] 00: 22 10 69 74 05 00 00 02 03 8a 01 01 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: 43 f0 0f 00 00 00 00 00 5e 5e 5e 20 2a 00 ff 20 50: 03 03 03 c6 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.2 Class 0c05: 1022:746a (rev 02) Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: I/O ports at 2400 00: 22 10 6a 74 01 00 00 02 02 00 05 0c 00 40 00 00 10: 01 24 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 40: 02 00 05 0c 00 00 00 00 06 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.3 Class 0000: 1022:746b (rev 05) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 6b 74 00 00 80 02 05 00 00 00 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 d1 00 04 00 00 00 00 20 14 10 00 00 00 00 00 50: 00 80 00 00 0f 00 00 00 01 20 00 00 00 00 00 00 60: 00 00 00 00 13 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 54 ac 76 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:02:03.0 Class 0200: 14e4:16a6 (rev 02) Subsystem: 14e4:000c Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (16000ns min), cache line size 10 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fb000000 (64-bit, non-prefetchable) [size=1026M] Expansion ROM at 00010000 [disabled] Capabilities: [40] PCI-X non-bridge device. Command: DPERE- ERO- RBC=0 OST=0 Status: Bus=255 Dev=31 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=1, RSCEM- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Address: fcfb626b00cc0528 Data: 0109 00: e4 14 a6 16 46 01 b0 02 02 00 00 02 10 40 00 00 10: 04 00 00 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 30: 00 00 20 40 40 00 00 00 00 00 00 00 00 01 40 00 40: 07 48 00 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 50: 03 58 00 00 0a 80 a0 22 05 00 86 00 28 05 cc 00 60: 6b 62 fb fc 09 01 00 00 98 02 02 10 00 00 3f 76 70: fe 10 00 00 df 00 00 80 4c 5b 03 00 00 00 00 00 80: 00 00 00 00 9f 13 88 f6 34 00 13 04 82 10 08 00 90: 09 92 00 01 83 01 00 00 00 00 00 00 83 01 00 00 a0: 00 00 00 00 bb 00 00 00 00 00 00 00 cd 01 00 00 b0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 c0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 d0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 e0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 f0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 0000:02:04.0 Class 0200: 14e4:16a6 (rev 02) Subsystem: 14e4:000c Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (16000ns min), cache line size 10 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fb010000 (64-bit, non-prefetchable) [size=106M] Expansion ROM at 00010000 [disabled] Capabilities: [40] PCI-X non-bridge device. Command: DPERE- ERO+ RBC=0 OST=0 Status: Bus=255 Dev=31 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=1, RSCEM- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Address: fcfd56ebfbf37f4c Data: eff5 00: e4 14 a6 16 46 01 b0 02 02 00 00 02 10 40 00 00 10: 04 00 01 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 30: 00 00 ad 06 40 00 00 00 00 00 00 00 00 01 40 00 40: 07 48 02 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 50: 03 58 b8 00 f7 e5 fe 79 05 00 86 00 4c 7f f3 fb 60: eb 56 fd fc f5 ef 00 00 9a 02 02 10 00 00 3f 76 70: be 12 00 00 df 00 00 00 50 00 00 00 00 00 00 00 80: 03 58 b8 00 5f bf f5 eb 34 00 00 00 fe 10 08 00 90: 01 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:03:01.0 Class 0280: 14c1:8043 (rev 04) Subsystem: 14c1:8043 Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR+ Interrupt: pin A routed to IRQ 17 Region 0: Memory at fa000000 (64-bit, prefetchable) Capabilities: [44] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [54] PCI-X non-bridge device. Command: DPERE- ERO- RBC=0 OST=0 Status: Bus=3 Dev=1 Func=0 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=3, DMOST=0, DMCRS=2, RSCEM-00: c1 14 43 80 42 00 30 80 04 00 80 02 10 40 00 00 10: 0c 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 c1 14 43 80 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 00 00 40: 00 00 00 55 05 54 80 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 07 00 00 00 08 03 63 08 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 ac 00 60 dd 48 b1 80 0000:04:00.0 Class 0c03: 1022:7464 (rev 0b) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9000000 (32-bit, non-prefetchable) 00: 22 10 64 74 02 01 80 02 0b 10 03 0c 00 40 80 00 10: 00 00 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 50 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:04:00.1 Class 0c03: 1022:7464 (rev 0b) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9001000 (32-bit, non-prefetchable) 00: 22 10 64 74 02 01 80 02 0b 10 03 0c 00 40 00 00 10: 00 10 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 50 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:04:00.2 Class 0c03: 1022:7463 (rev 02) (prog-if 20) Subsystem: 1022:7463 Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9003000 (32-bit, non-prefetchable) Region 1: Memory at f9004000 (32-bit, non-prefetchable) [size=32] Capabilities: [80] #0a [4000] Capabilities: [88] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=100mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 22 10 63 74 02 00 10 02 02 20 03 0c 00 40 00 00 10: 00 30 00 f9 00 40 00 f9 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 63 74 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 04 00 00 40: 01 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 22 10 63 74 01 00 00 00 40 30 00 01 00 00 00 00 80: 0a 88 00 40 00 00 00 00 01 00 82 fe 00 00 00 00 90: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:04:06.0 Class 0300: 1002:4752 (rev 27) Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 0 Region 0: Memory at f8000000 (32-bit, non-prefetchable) Region 1: I/O ports at 1000 [size=256] Region 2: Memory at f9002000 (32-bit, non-prefetchable) [size=4K] Capabilities: [5c] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 02 10 52 47 83 00 90 02 27 00 00 03 10 40 00 00 10: 00 00 00 f8 01 10 00 00 00 20 00 f9 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 5c 00 00 00 00 00 00 00 00 01 08 00 40: 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 5c 10 00 01 00 00 ff 00 00 00 00 01 00 02 06 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Friday, September 18, 2009 3:18 PM To: Spangler, Mike T Cc: flashrom(a)flashrom.org Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard Hi Mike, On 18.09.2009 18:55, Spangler, Mike T wrote: > I've corrected my email and am now sending to the group. > Thanks. >> Of course I'd prefer it if you tried to flash coreboot (new name of >> LinuxBIOS) to these boards, but that's your choice. Anyway, you said you >> have the factory BIOS around somewhere. Is it the one at >> http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? >> > > I can't use flash coreboot (LinuxBIOS) because our cluster management tools require pxeboot. We've transitioned away from it. > That's unfortunate. Did you know that coreboot+SeaBIOS works fine with gPXE? We coreboot/flashrom developers are always interested in helping people update coreboot to the latest and greatest. So if you need PXE booting, there's no need to move back to the factory BIOS, a simple coreboot update should suffice. > So, the bios zip file above is correct, but I'm not using it. It will not work for flashing a chip with LinuxBios. The way I do this is to do a "flashrom -r" on a system with factory bios and then take that newly created flashrom file and do a "flashrom -w" with it on a board with LinuxBios. That's one option. The other option would be to extract the BIOS from the .ROM file. That looks reasonably easy. No guarantees, though. dd if=something.ROM of=bios.bin bs=1k count=512 > This is the method we used with the old bios_copy software from Linux Networx, but that was extremely unreliable. > flashrom strives to be the most reliable flashing tool out there. The current version has builtin verification for every step it does. >> Hmm ok. I think we have enough docs to iterate through all possible >> board enables. How many of these boards do you have (in case we trash >> the ROM of one of them)? >> > > The ROM is removeable, so we only potentially trash a PLCC chip. I have a half dozen or so spares. > Great. And with hotplugging/hotflashing it should be possible to reflash a trashed chip in another board. Can you supply the output of "lspci -nnvvvxxx" as root? That will allow me to dig further. I'd like to limit the search to a reasonable subset of options. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[commit] r755 - trunk
by svn＠flashrom.org 30 Oct '09

30 Oct '09

Author: hailfinger Date: 2009-10-31 02:53:09 +0100 (Sat, 31 Oct 2009) New Revision: 755 Modified: trunk/chipset_enable.c trunk/flash.h trunk/flashrom.c Log: Add infrastructure to check and report to the user the maximum supported decode size for chipsets and tested mainboards. The rationale is to warn users when they, for example, try to flash a 512KB parallel flash chip but their chipset only supports 256KB, or they try to flash 512KB and the chipset _does_ theoretically support 512KB but their special board doesn't wire all address lines and thus supports only 256 KB ROM chips at maximum. This has cost Uwe hours of debugging on some board already, until he figured out what was going on. We should try warn our users where possible about this. The chipset and the chip may have more than one bus in common (e.g. SB600 and Pm49* can both speak LPC+FWH) and on SB600/SB7x0/SB8x0 there are different limits for LPC and FWH. The only way to tell the user about the exact circumstances is to spew error messages per bus. The code will issue a warning during probe (which does fail for some chips if the size is too big) and abort before the first real read/write/erase action. If no action is specified, the warning is printed anyway. That way, a user can find out why probe might not have worked, and will be stopped before he/she gets incorrect results. Add a bitcount function to the infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/chipset_enable.c 2009-10-31 01:53:09 UTC (rev 755) @@ -42,6 +42,17 @@ enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; +/** + * Programmers supporting multiple buses can have differing size limits on + * each bus. Store the limits for each bus in a common struct. + */ +struct decode_sizes max_rom_decode = { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff +}; + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/flash.h 2009-10-31 01:53:09 UTC (rev 755) @@ -352,9 +352,17 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); int board_flash_enable(const char *vendor, const char *part); +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; + /* chipset_enable.c */ extern enum chipbustype buses_supported; int chipset_flash_enable(void); +extern struct decode_sizes max_rom_decode; extern unsigned long flashbase; Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/flashrom.c 2009-10-31 01:53:09 UTC (rev 755) @@ -299,6 +299,15 @@ return (a > b) ? a : b; } +int bitcount(unsigned long a) +{ + int i = 0; + for (; a != 0; a >>= 1) + if (a & 1) + i++; + return i; +} + char *strcat_realloc(char *dest, const char *src) { dest = realloc(dest, strlen(dest) + strlen(src) + 1); @@ -398,10 +407,60 @@ return ret; } +int check_max_decode(enum chipbustype buses, uint32_t size) +{ + int limitexceeded = 0; + if ((buses & CHIP_BUSTYPE_PARALLEL) && + (max_rom_decode.parallel < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.parallel / 1024, "Parallel"); + } + if ((buses & CHIP_BUSTYPE_LPC) && (max_rom_decode.lpc < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.lpc / 1024, "LPC"); + } + if ((buses & CHIP_BUSTYPE_FWH) && (max_rom_decode.fwh < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.fwh / 1024, "FWH"); + } + if ((buses & CHIP_BUSTYPE_SPI) && (max_rom_decode.spi < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.spi / 1024, "SPI"); + } + if (!limitexceeded) + return 0; + /* Sometimes chip and programmer have more than one bus in common, + * and the limit is not exceeded on all buses. Tell the user. + */ + if (bitcount(buses) > limitexceeded) + printf_debug("There is at least one common chip/programmer " + "interface which can support a chip of this size. " + "You can try --force at your own risk.\n"); + return 1; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; - unsigned long base = 0, size; + unsigned long base = 0; + uint32_t size; + enum chipbustype buses_common; char *tmp; for (flash = first_flash; flash && flash->name; flash++) { @@ -413,7 +472,8 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } - if (!(buses_supported & flash->bustype)) { + buses_common = buses_supported & flash->bustype; + if (!buses_common) { tmp = flashbuses_to_text(buses_supported); printf_debug("skipped. Host bus type %s ", tmp); free(tmp); @@ -424,6 +484,7 @@ } size = flash->total_size * 1024; + check_max_decode(buses_common, size); base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); @@ -956,6 +1017,15 @@ "mainboard you tested. Thanks for your help!\n===\n"); } + size = flash->total_size * 1024; + if (check_max_decode((buses_supported & flash->bustype), size) && + (!force)) { + fprintf(stderr, "Chip is too big for this programmer " + "(-V gives details). Use --force to override.\n"); + programmer_shutdown(); + return 1; + } + if (!(read_it | write_it | verify_it | erase_it)) { printf("No operations were specified.\n"); // FIXME: flash writes stay enabled! @@ -974,7 +1044,6 @@ if (write_it && !dont_verify_it) verify_it = 1; - size = flash->total_size * 1024; buf = (uint8_t *) calloc(size, sizeof(char)); if (erase_it) {

1 0

[commit] r754 - trunk
by svn＠flashrom.org 30 Oct '09

30 Oct '09

Author: hailfinger Date: 2009-10-30 22:12:39 +0100 (Fri, 30 Oct 2009) New Revision: 754 Modified: trunk/pcidev.c Log: Adjust a help text for external PCI programmers to the new parameter scheme. Pointed out by Maciej Pijanka. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/pcidev.c =================================================================== --- trunk/pcidev.c 2009-10-22 15:07:30 UTC (rev 753) +++ trunk/pcidev.c 2009-10-30 21:12:39 UTC (rev 754) @@ -100,7 +100,7 @@ exit(1); } else if (found > 1) { fprintf(stderr, "Error: Multiple supported PCI devices found. " - "Use 'flashrom -p xxxx=bb:dd.f' \n" + "Use 'flashrom -p xxxx:bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); exit(1);

1 0

Need help to flash bios HP Omnibook 4150B
by guillaumeg 29 Oct '09

29 Oct '09

Good evening i installed fedora 11 in my laptop Intel pentium III coppermine i'd like to flash the bios using flashrom the objectif is ( i hope) to fix a display problem - stripes on the screen, especially when i move the mouse. i tried to fix the problem with Xorg.conf and system-config-display withoot any success. Some people drived me in the french fedora forum. They invite my to join the flashrom IRC chat. for your information here a report when i launch flashrom with a terminal. flashrom v0.9.1-r710 No coreboot table found. Found chipset "Intel PIIX4/4E/4M", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. i will stay connect on #flashrom as much as I can. Thank you for your help hope to hear from you soon regards guillaume de bamako

2 1

[PATCH] Error out when chipset/board doesn't decode full ROM
by Uwe Hermann 29 Oct '09

29 Oct '09

See patch. I'm thankful for better suggestions to track which chipsets and especially boards can decode how much. For boards we need to autodetect them (not possible for all boards unfortunately). For those with board-enables we could reuse that table and enhance/add board-enables, whether that's a good idea is another issue. For boards that cannot be autodetected we should at least have a table of the max. supported ROM chip size, which can be printed in "flashrom -L" and in the wiki. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 5

Board: Acorp 6A815EPD autodetectable.
by Luc Verhaegen 28 Oct '09

28 Oct '09

3 4

new board enable type: attacking intel bios
by ron minnich 26 Oct '09

26 Oct '09

http://www.blackhat.com/presentations/bh-usa-09/WOJTCZUK/BHUSA09-Wojtczuk-A… interesting. Install a shell by changing the OEM logo. Would this be an "external flasher" in flashrom :-) it seems that more than ever the rule in the closed bios world is security through obscurity. we know how well that one works. ron

2 1

[PATCH] Boards: Yet another way to set an intel ICH GPIO line.
by Luc Verhaegen 25 Oct '09

25 Oct '09

Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 371 ++++++++++++++++++++++++++++++++++---------------------- 1 files changed, 225 insertions(+), 146 deletions(-) diff --git a/board_enable.c b/board_enable.c index 21b91f1..35f43ba 100644 --- a/board_enable.c +++ b/board_enable.c @@ -523,32 +523,6 @@ static int board_epox_ep_bx3(const char *name) } /** - * Suited for Acorp 6A815EPD. - */ -static int board_acorp_6a815epd(const char *name) -{ - struct pci_dev *dev; - uint16_t port; - uint8_t val; - - dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */ - if (!dev) { - fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n"); - return -1; - } - - /* Use GPIOBASE register to find where the GPIO is mapped. */ - port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE; - - val = INB(port); - val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ - val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ - OUTB(val, port); - - return 0; -} - -/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -590,105 +564,262 @@ static int board_artecgroup_dbe6x(const char *name) } /** - * Set the specified GPIO on the specified ICHx southbridge to high. - * - * @param name The name of this board. - * @param ich_vendor PCI vendor ID of the specified ICHx southbridge. - * @param ich_device PCI device ID of the specified ICHx southbridge. - * @param gpiobase_reg GPIOBASE register offset in the LPC bridge. - * @param gp_lvl Offset of GP_LVL register in I/O space, relative to GPIOBASE. - * @param gp_lvl_bitmask GP_LVL bitmask (set GPIO bits to 1, all others to 0). - * @param gpio_bit The bit (GPIO) which shall be set to high. - * @return If the write-enable was successful return 0, otherwise return -1. + * Set a GPIO line on a given intel ICH LPC controller. */ -static int ich_gpio_raise(const char *name, uint16_t ich_vendor, - uint16_t ich_device, uint8_t gpiobase_reg, - uint8_t gp_lvl, uint32_t gp_lvl_bitmask, - unsigned int gpio_bit) +static int intel_ich_gpio_set(int gpio, int raise) { + /* table mapping the different intel ICH LPC chipsets. */ + static struct { + uint16_t id; + uint8_t base_reg; + uint32_t bank0; + uint32_t bank1; + uint32_t bank2; + } intel_ich_gpio_table[] = { + {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */ + {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */ + {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */ + {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */ + {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */ + {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */ + {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */ + {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */ + {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */ + {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */ + {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */ + {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */ + {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */ + {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */ + {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */ + {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */ + {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */ + {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */ + {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */ + {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */ + {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */ + {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */ + {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */ + {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */ + {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */ + {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */ + {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */ + {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */ + {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */ + {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */ + {0, 0, 0, 0, 0} /* end marker */ + }; + struct pci_dev *dev; - uint16_t gpiobar; - uint32_t reg32; + uint16_t base; + uint32_t tmp; + int i, allowed; + + /* First, look for a known LPC bridge */ + for (dev = pacc->devices; dev; dev = dev->next) + if ((dev->vendor_id == 0x8086) && + (dev->device_class == 0x0601)) { /* ISA Bridge */ + /* Is this device in our list? */ + for (i = 0; intel_ich_gpio_table[i].id; i++) + if (dev->device_id == intel_ich_gpio_table[i].id) + break; + + if (intel_ich_gpio_table[i].id) + break; + } - dev = pci_dev_find(ich_vendor, ich_device); /* Intel ICHx LPC */ if (!dev) { - fprintf(stderr, "\nERROR: ICHx LPC dev %4x:%4x not found.\n", - ich_vendor, ich_device); + fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n"); return -1; } - /* Use GPIOBASE register to find the I/O space for GPIO. */ - gpiobar = pci_read_word(dev, gpiobase_reg) & gp_lvl_bitmask; + /* According to the datasheets, all intel ICHs have the gpio bar 5:1 + strapped to zero. From some mobile ich9 version on, this becomes + 6:1. The mask below catches all. */ + base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; - /* Set specified GPIO to high. */ - reg32 = INL(gpiobar + gp_lvl); - reg32 |= (1 << gpio_bit); - OUTL(reg32, gpiobar + gp_lvl); + /* check whether the line is allowed */ + if (gpio < 32) + allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01; + else if (gpio < 64) + allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01; + else + allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; + + if (!allowed) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow" + " setting GPIO%02d\n", gpio); + return -1; + } + + printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", + raise ? "Rais" : "Dropp", gpio); + + if (gpio < 32) { + /* Set line to GPIO */ + tmp = INL(base); + /* ICH/ICH0 multiplexes 27/28 on the line set. */ + if ((gpio == 28) && + ((dev->device_id == 0x2410) || (dev->device_id == 0x2420))) + tmp |= 1 << 27; + else + tmp |= 1 << gpio; + OUTL(tmp, base); + + /* As soon as we are talking to ICH8 and above, this register + decides whether we can set the gpio or not. */ + if (dev->device_id > 0x2800) { + tmp = INL(base); + if (!(tmp & (1 << gpio))) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge" + " does not allow setting GPIO%02d\n", + gpio); + return -1; + } + } + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x04); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x04); + + /* Raise GPIO line */ + tmp = INL(base + 0x0C); + if (raise) + tmp |= 1 << gpio; + else + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x0C); + } else if (gpio < 64) { + gpio -= 32; + + /* Set line to GPIO */ + tmp = INL(base + 0x30); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x30); + + /* As soon as we are talking to ICH8 and above, this register + decides whether we can set the gpio or not. */ + if (dev->device_id > 0x2800) { + tmp = INL(base + 30); + if (!(tmp & (1 << gpio))) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge" + " does not allow setting GPIO%02d\n", + gpio + 32); + return -1; + } + } + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x34); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x34); + + /* Raise GPIO line */ + tmp = INL(base + 0x38); + if (raise) + tmp |= 1 << gpio; + else + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x38); + } else { + gpio -= 64; + + /* Set line to GPIO */ + tmp = INL(base + 0x40); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x40); + + tmp = INL(base + 40); + if (!(tmp & (1 << gpio))) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge does " + "not allow setting GPIO%02d\n", gpio + 64); + return -1; + } + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x44); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x44); + + /* Raise GPIO line */ + tmp = INL(base + 0x48); + if (raise) + tmp |= 1 << gpio; + else + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x48); + } return 0; } /** - * Suited for ASUS P4B266. + * Suited for Abit IP35: Intel P35 + ICH9R. */ -static int ich2_gpio22_raise(const char *name) +static int intel_ich_gpio16_raise(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x2440, 0x58, 0x0c, 0xffc0, 22); + return intel_ich_gpio_set(16, 1); } /** - * Suited for the Dell PowerEdge 1850. All parameters except the last one are - * documented in the public Intel 82801EB ICH5 / 82801ER ICH5R datasheet. The - * last parameter (GPIO number) has to be in the range [16,31] according to - * said Intel datasheet and was found by exhaustive search. + * Suited for MSI MS-7046: LGA775 + 915P + ICH6. */ -static int ich5_gpio23_raise(const char *name) +static int intel_ich_gpio19_raise(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, 23); + return intel_ich_gpio_set(19, 1); } /** - * Suited for MSI MS-7046. + * Suited for Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ -static int ich6_gpio19_raise(const char *name) +static int intel_ich_gpio21_raise(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x2640, 0x48, 0x0c, 0xffc0, 19); + return intel_ich_gpio_set(21, 1); } -static int board_kontron_986lcd_m(const char *name) +/** + * Suited for ASUS P4B266: socket478 + intel 845D + ICH2. + */ +static int intel_ich_gpio22_raise(const char *name) { - struct pci_dev *dev; - uint16_t gpiobar; - uint32_t val; + return intel_ich_gpio_set(22, 1); +} -#define ICH7_GPIO_LVL2 0x38 +/** + * Suited for Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + */ +static int intel_ich_gpio23_raise(const char *name) +{ + return intel_ich_gpio_set(23, 1); +} - dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC */ - if (!dev) { - // This will never happen on this board - fprintf(stderr, "\nERROR: ICH7 LPC bridge not found.\n"); - return -1; - } +/** + * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. + */ +static int board_acorp_6a815epd(const char *name) +{ + int ret; - /* Use GPIOBASE register to find where the GPIO is mapped. */ - gpiobar = pci_read_word(dev, 0x48) & 0xfffc; + /* Lower Blocks Lock -- pin 7 of PLCC32 */ + ret = intel_ich_gpio_set(22, 1); + if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */ + ret = intel_ich_gpio_set(23, 1); - val = INL(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ - printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val); + return ret; +} - /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1 - * bit 2 (0x04) = 1 #TBL --> bootblock locking = 0 - * bit 3 (0x08) = 0 #WP --> block locking = 1 - * bit 3 (0x08) = 1 #WP --> block locking = 0 - * - * To enable full block locking, you would do: - * val &= ~ ((1 << 2) | (1 << 3)); - */ - val |= (1 << 2) | (1 << 3); +/** + * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R. + */ +static int board_kontron_986lcd_m(const char *name) +{ + int ret; - OUTL(val, gpiobar + ICH7_GPIO_LVL2); + ret = intel_ich_gpio_set(34, 1); /* #TBL */ + if (!ret) + ret = intel_ich_gpio_set(35, 1); /* #WP */ - return 0; + return ret; } /** @@ -881,32 +1012,6 @@ static int board_mitac_6513wu(const char *name) } /** - * Suited for Abit IP35: Intel P35 + ICH9R. - */ -static int board_abit_ip35(const char *name) -{ - struct pci_dev *dev; - uint16_t base; - uint8_t tmp; - - dev = pci_dev_find(0x8086, 0x2916); /* Intel ICH9R LPC Interface */ - if (!dev) { - fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); - return -1; - } - - /* get LPC GPIO base */ - base = pci_read_long(dev, 0x48) & 0x0000FFC0; - - /* Raise GPIO 16 */ - tmp = INB(base + 0x0E); - tmp |= 0x01; - OUTB(tmp, base + 0x0E); - - return 0; -} - -/** * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A */ static int board_asus_a7v8x(const char *name) @@ -1009,32 +1114,6 @@ static int board_asus_a7v600x(const char *name) } /** - * Suited for Asus P4P800-E Deluxe: Intel Intel 865PE + ICH5R. - */ -static int board_asus_p4p800(const char *name) -{ - struct pci_dev *dev; - uint16_t base; - uint8_t tmp; - - dev = pci_dev_find(0x8086, 0x24D0); /* Intel ICH5R ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: Intel ICH5R ISA Bridge not found.\n"); - return -1; - } - - /* get PM IO base */ - base = pci_read_long(dev, 0x58) & 0x0000FFC0; - - /* Raise GPIO 21 */ - tmp = INB(base + 0x0E); - tmp |= 0x20; - OUTB(tmp, base + 0x0E); - - return 0; -} - -/** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. * @@ -1063,7 +1142,7 @@ static int board_asus_p4p800(const char *name) /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ - {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", board_abit_ip35}, + {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise}, {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, @@ -1073,12 +1152,12 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, - {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, - {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, + {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise}, + {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, - {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", ich5_gpio23_raise}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, @@ -1103,7 +1182,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, - {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, + {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, -- 1.6.0.2 --cNdxnHkX5QqsyA0e--

1 0

Flashing of ASUS M2N4-SLI BIOS
by Michael Stephenson 25 Oct '09

25 Oct '09

Hi, My motherboard is an ASUS M2N4-SLI, and I attempted to flash it with the 1205 BIOS available from the ASUS website, the flash went without incident as can be seen here http://www.pastebin.ca/1642685 When I rebooted everything seemed to work fine until I reached GDM where I found my usb mouse no longer worked, so I dropped to console (fortunately am using a PS/2 keyboard) where I discovered my ethernet card had not been discovered, after rebooting a few times and tinkering with the BIOS to no effect I decided to restore my backup. Where everything worked fine again. Speaking to Carldani in irc he made the comments: > carldani: they store the ethernet address in the bios image, so if you reflash, you lose the ethernet address... > carldani: if you have a hex editor, you could try to locate your mac address in the backup file > carldani: the mac address may be stored in reverse... > carldani: maybe someone on the mailing list knows the mac extraction procedure better than I do I have attached the output of lspci -nnvvvxxx and flashrom -V Thanks Michael

1 0

motherboard report - TYAN S2885, PMC 4Mbit
by Mick Reed 25 Oct '09

25 Oct '09

I can confirm that flashrom works on TYAN S2885, for at least read and write. The S2885 has a socketed 32-PLCC, the same as the S2881. I have glued over the part numbers?? but I know it comes with a PMC 4Mbit, the exact same chip as the S2881 (I have an old broken one of those). I was able to read out the old 2.05 bios and write the latest 2.08 into the chip. I can't remember whether it was automatically "verified" or whether I did it manually, but I know it worked (it's my main machine, which I am using now). FYI I am going to use an SST49LF016C-33-4C-NHE (8Mbit) for a fun coreboot project. It's been a while, I haven't touched that one yet, I'll report on that if it works. Anything else, let me know. Thanks. Mick Reed # flashrom -V flashrom v0.9.1-r753 No coreboot table found. Found chipset "AMD AMD8111", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 536M loops per second, 100 myus = 216 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F080B, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Intel 28F001BX-B, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Intel 28F001BX-T, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29F001T, 128 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29LV040, 512 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F0002T, 256 KB: probe_29f040b: id1 0x04, id2 0x36 Probing for PMC Pm29F0002B, 256 KB: probe_29f040b: id1 0x04, id2 0x36 Probing for PMC Pm39LV010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x9d, id2 0x6e (here it is!!) Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0xff, id2 0xff Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M50FLW040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M50FLW040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M50FLW080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x04, id2 0x36 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for TI TMS29F002RT, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No operations were specified.

1 1

[PATCH] Boards: Unify all intel ICH GPIO raising.
by Luc Verhaegen 25 Oct '09

25 Oct '09

Ok, big change here which will require several of the people on the list below to test and Ack this patch. But one has to admit; the result is worth it. Jonathan, can you verify this patch on your acorp 6A815EPD (preferably also with the previous patch)? Thanks for having replied that swiftly last time :) Uwe, it seems that the Asus P4B266 is yours, the code was committed as r247. Can you send in an lspci -vvnnxxx to the list as well? Carl-Daniel, the Dell is from your commit, r728. Any lspci on that? David, i would guess that the MSI MS-7046 is your board (original commit r414), can you go and verify this code on this hardware? We would like to have an lspci -vvnnxxx for this board too. Stepan, it seems that you committed the kontron 986LCD-M board enable. Can you check whether this code still works with your board, and can you also provide an lspci -vvnnxxx? I would also like to get rid of the entry which just matches one pci devices, and the coreboot ids in the table. Richie, can you give this code a spin on your Abit IP35? (original commit r642) Bojan? Asus P4P800-E seems to be yours and it was added just under two months ago in r682. Can you give this code a run too? I would like to see at least 4 of these boards get an Ack before this can be committed. Thanks all, now i can send in at least two more board enables which go on top of this stuff. Luc Verhaegen.

4 18

[PATCH] Board match for ASRock P4i65GV.
by Luc Verhaegen 23 Oct '09

23 Oct '09

Same board enable as the Dell PowerEdge 1850: raise gpio23 on ich5r. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 03930f4..19825eb 100644 --- a/board_enable.c +++ b/board_enable.c @@ -739,7 +739,9 @@ static int board_asus_p4p800(const char *name) } /** - * Suited for Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + * Suited for: + * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R. * * The GPIO number has to be in the range [16,31] according to the public Intel * 82801EB ICH5 / 82801ER ICH5R datasheet and was found by exhaustive search. @@ -1136,6 +1138,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", board_abit_ip35}, {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, + {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", board_dell_pe_1850}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400}, -- 1.6.0.2 --Qxx1br4bt0+wmkIi--

1 0

[PATCH] Board enable for Asus P4B266-LM.
by Luc Verhaegen 23 Oct '09

23 Oct '09

Board shipped in the Sony Vaio PCV-RX650. Raises GPIO21 on intel ICH2. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 2332209..03930f4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -665,6 +665,25 @@ static void intel_ich_gpio_raise(struct pci_dev *dev, unsigned int gpio) } /** + * Suited for Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. + */ +static int board_asus_p4b266_lm(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 ISA Bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH2 ISA Bridge not found.\n"); + return -1; + } + + intel_ich_gpio_raise(dev, 21); + + return 0; +} + + +/** * Suited for ASUS P4B266: socket478 + intel 845D + ICH2. */ static int board_asus_p4b266(const char *name) @@ -1126,6 +1145,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", board_asus_p4b266}, + {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", board_asus_p4b266_lm}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, -- 1.6.0.2 --ftEhullJWpWg/VHq--

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[PATCH] Boards: Unify all intel ICH GPIO setting in one function.
by Luc Verhaegen 23 Oct '09

23 Oct '09

The new intel_ich_gpio_raise function should be general for all intel ich southbridges. There are a few comments to this function, which should be considered before using this function. Plus, this function does not only raise the gpio line, it switches the signal to gpio and sets it to output as well. A few boards have been moved around to sit below the intel_ich_gpio_raise function which makes this patch more unsightly than it could be. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 326 ++++++++++++++++++++++++++++++++------------------------ 1 files changed, 189 insertions(+), 137 deletions(-) diff --git a/board_enable.c b/board_enable.c index 21b91f1..2332209 100644 --- a/board_enable.c +++ b/board_enable.c @@ -523,32 +523,6 @@ static int board_epox_ep_bx3(const char *name) } /** - * Suited for Acorp 6A815EPD. - */ -static int board_acorp_6a815epd(const char *name) -{ - struct pci_dev *dev; - uint16_t port; - uint8_t val; - - dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */ - if (!dev) { - fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n"); - return -1; - } - - /* Use GPIOBASE register to find where the GPIO is mapped. */ - port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE; - - val = INB(port); - val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ - val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ - OUTB(val, port); - - return 0; -} - -/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -590,103 +564,233 @@ static int board_artecgroup_dbe6x(const char *name) } /** - * Set the specified GPIO on the specified ICHx southbridge to high. + * Raises a GPIO line on intel ICH, ICH0 and ICH2 through ICH10 southbridges. * - * @param name The name of this board. - * @param ich_vendor PCI vendor ID of the specified ICHx southbridge. - * @param ich_device PCI device ID of the specified ICHx southbridge. - * @param gpiobase_reg GPIOBASE register offset in the LPC bridge. - * @param gp_lvl Offset of GP_LVL register in I/O space, relative to GPIOBASE. - * @param gp_lvl_bitmask GP_LVL bitmask (set GPIO bits to 1, all others to 0). - * @param gpio_bit The bit (GPIO) which shall be set to high. - * @return If the write-enable was successful return 0, otherwise return -1. + * GPIO lines are not actually checked. + * More than 32 GPIO pins only become available with the ICH3. + * From ICH10, a third bank appears, but ICH10 only implements GPIO72. + * + * In hardware, the GPIO BARs have the lower bits (5:1) zeroed, starting + * with a mobile ich9 version bits 6:1 are zeroed. The 0xFFC0 mask should + * catch all just fine. + */ +static void intel_ich_gpio_raise(struct pci_dev *dev, unsigned int gpio) +{ + uint16_t base; + uint32_t tmp; + + /* get PM IO base */ + switch (dev->device_id) { + case 0x2410: /* 82801AA (ICH) */ + case 0x2420: /* 82801AB (ICH0) */ + case 0x2440: /* 82801BA (ICH2) */ + case 0x244C: /* 82801BAM (ICH2M) */ + case 0x2450: /* 82801E (C-ICH) */ + case 0x2480: /* 82801CA (ICH3-S) */ + case 0x248C: /* 82801CAM (ICH3-M) */ + case 0x24C0: /* 82801DB/DBL (ICH4/ICH4-L) */ + case 0x24CC: /* 82801DBM (ICH4-M) */ + case 0x24D0: /* 82801EB/ER (ICH5/ICH5R) */ + case 0x24DC: /* 82801EB (ICH5) */ + base = pci_read_long(dev, 0x58) & 0x0000FFC0; + break; + case 0x2640: /* 82801FB/FR (ICH6/ICH6R) */ + case 0x2641: /* 82801FBM (ICH6M) */ + case 0x2642: /* 82801FW/FRW (ICH6W/ICH6RW) */ + case 0x27B0: /* 82801GH (ICH7DH) */ + case 0x27B8: /* 82801GB/GR (ICH7 Family) */ + case 0x27B9: /* 82801GBM (ICH7-M) */ + case 0x27BD: /* 82801GHM (ICH7-M DH) */ + case 0x2810: /* 82801HB/HR (ICH8/R) */ + case 0x2811: /* 82801HBM (ICH8M-E) */ + case 0x2812: /* 82801HH (ICH8DH) */ + case 0x2814: /* 82801HO (ICH8DO) */ + case 0x2815: /* 82801HEM (ICH8M) */ + case 0x2912: /* 82801IH (ICH9DH) */ + case 0x2914: /* 82801IO (ICH9DO) */ + case 0x2916: /* 82801IR (ICH9R) */ + case 0x2917: /* 82801IEM (ICH9M-E) */ + case 0x2918: /* 82801IB (ICH9) */ + case 0x2919: /* 82801IBM (ICH9M) */ + case 0x3A14: /* 82801JDO (ICH10DO) */ + case 0x3A16: /* 82801JIR (ICH10R) */ + case 0x3A18: /* 82801JIB (ICH10) */ + case 0x3A1A: /* 82801JD (ICH10D) */ + base = pci_read_long(dev, 0x48) & 0x0000FFC0; + break; + default: + fprintf(stderr, "\nERROR: Unknown Intel ICH: 0x%04X.\n", + dev->device_id); + return; + } + + if (gpio < 32) { + /* Set line to GPIO */ + tmp = INL(base); + /* ICH/ICH0 multiplexes 27/28 on the line set. */ + if ((gpio == 28) && + ((dev->device_id == 0x2410) || (dev->device_id == 0x2420))) + tmp |= 1 << 27; + else + tmp |= 1 << gpio; + OUTL(tmp, base); + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x04); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x04); + + /* Raise GPIO line */ + tmp = INL(base + 0x0C); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x0C); + } else { + gpio -= 32; + + /* Set line to GPIO */ + tmp = INL(base + 0x30); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x30); + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x34); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x34); + + /* Raise GPIO line */ + tmp = INL(base + 0x38); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x38); + } +} + +/** + * Suited for ASUS P4B266: socket478 + intel 845D + ICH2. */ -static int ich_gpio_raise(const char *name, uint16_t ich_vendor, - uint16_t ich_device, uint8_t gpiobase_reg, - uint8_t gp_lvl, uint32_t gp_lvl_bitmask, - unsigned int gpio_bit) +static int board_asus_p4b266(const char *name) { struct pci_dev *dev; - uint16_t gpiobar; - uint32_t reg32; - dev = pci_dev_find(ich_vendor, ich_device); /* Intel ICHx LPC */ + dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 ISA Bridge */ if (!dev) { - fprintf(stderr, "\nERROR: ICHx LPC dev %4x:%4x not found.\n", - ich_vendor, ich_device); + fprintf(stderr, "\nERROR: Intel ICH2 ISA Bridge not found.\n"); return -1; } - /* Use GPIOBASE register to find the I/O space for GPIO. */ - gpiobar = pci_read_word(dev, gpiobase_reg) & gp_lvl_bitmask; + intel_ich_gpio_raise(dev, 22); + + return 0; +} - /* Set specified GPIO to high. */ - reg32 = INL(gpiobar + gp_lvl); - reg32 |= (1 << gpio_bit); - OUTL(reg32, gpiobar + gp_lvl); +/** + * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. + */ +static int board_acorp_6a815epd(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH2 ISA bridge not found.\n"); + return -1; + } + + intel_ich_gpio_raise(dev, 22); /* Lower Blocks Lock -- pin 7 of PLCC32 */ + intel_ich_gpio_raise(dev, 23); /* Top Block Lock -- pin 8 of PLCC32 */ return 0; } /** - * Suited for ASUS P4B266. + * Suited for Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ -static int ich2_gpio22_raise(const char *name) +static int board_asus_p4p800(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x2440, 0x58, 0x0c, 0xffc0, 22); + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x24D0); /* Intel ICH5R ISA Bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH5 ISA Bridge not found.\n"); + return -1; + } + + intel_ich_gpio_raise(dev, 21); + + return 0; } /** - * Suited for the Dell PowerEdge 1850. All parameters except the last one are - * documented in the public Intel 82801EB ICH5 / 82801ER ICH5R datasheet. The - * last parameter (GPIO number) has to be in the range [16,31] according to - * said Intel datasheet and was found by exhaustive search. + * Suited for Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + * + * The GPIO number has to be in the range [16,31] according to the public Intel + * 82801EB ICH5 / 82801ER ICH5R datasheet and was found by exhaustive search. */ -static int ich5_gpio23_raise(const char *name) +static int board_dell_pe_1850(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, 23); + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x24D0); /* Intel ICH5R ISA Bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH5 ISA Bridge not found.\n"); + return -1; + } + + intel_ich_gpio_raise(dev, 23); + + return 0; } /** - * Suited for MSI MS-7046. + * Suited for MSI MS-7046: LGA775 + 915P + ICH6. */ -static int ich6_gpio19_raise(const char *name) +static int board_msi_ms7046(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x2640, 0x48, 0x0c, 0xffc0, 19); + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x2640); /* Intel ICH6 LPC Interface */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); + return -1; + } + + intel_ich_gpio_raise(dev, 19); + + return 0; } +/** + * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R. + */ static int board_kontron_986lcd_m(const char *name) { struct pci_dev *dev; - uint16_t gpiobar; - uint32_t val; - -#define ICH7_GPIO_LVL2 0x38 dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC */ if (!dev) { - // This will never happen on this board - fprintf(stderr, "\nERROR: ICH7 LPC bridge not found.\n"); + fprintf(stderr, "\nERROR: Intel ICH7 LPC bridge not found.\n"); return -1; } - /* Use GPIOBASE register to find where the GPIO is mapped. */ - gpiobar = pci_read_word(dev, 0x48) & 0xfffc; + intel_ich_gpio_raise(dev, 34); /* #TBL */ + intel_ich_gpio_raise(dev, 35); /* #WP */ - val = INL(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ - printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val); + return 0; +} - /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1 - * bit 2 (0x04) = 1 #TBL --> bootblock locking = 0 - * bit 3 (0x08) = 0 #WP --> block locking = 1 - * bit 3 (0x08) = 1 #WP --> block locking = 0 - * - * To enable full block locking, you would do: - * val &= ~ ((1 << 2) | (1 << 3)); - */ - val |= (1 << 2) | (1 << 3); +/** + * Suited for Abit IP35: Intel P35 + ICH9R. + */ +static int board_abit_ip35(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x2916); /* Intel ICH9R LPC Interface */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); + return -1; + } - OUTL(val, gpiobar + ICH7_GPIO_LVL2); + intel_ich_gpio_raise(dev, 16); return 0; } @@ -881,32 +985,6 @@ static int board_mitac_6513wu(const char *name) } /** - * Suited for Abit IP35: Intel P35 + ICH9R. - */ -static int board_abit_ip35(const char *name) -{ - struct pci_dev *dev; - uint16_t base; - uint8_t tmp; - - dev = pci_dev_find(0x8086, 0x2916); /* Intel ICH9R LPC Interface */ - if (!dev) { - fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); - return -1; - } - - /* get LPC GPIO base */ - base = pci_read_long(dev, 0x48) & 0x0000FFC0; - - /* Raise GPIO 16 */ - tmp = INB(base + 0x0E); - tmp |= 0x01; - OUTB(tmp, base + 0x0E); - - return 0; -} - -/** * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A */ static int board_asus_a7v8x(const char *name) @@ -1009,32 +1087,6 @@ static int board_asus_a7v600x(const char *name) } /** - * Suited for Asus P4P800-E Deluxe: Intel Intel 865PE + ICH5R. - */ -static int board_asus_p4p800(const char *name) -{ - struct pci_dev *dev; - uint16_t base; - uint8_t tmp; - - dev = pci_dev_find(0x8086, 0x24D0); /* Intel ICH5R ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: Intel ICH5R ISA Bridge not found.\n"); - return -1; - } - - /* get PM IO base */ - base = pci_read_long(dev, 0x58) & 0x0000FFC0; - - /* Raise GPIO 21 */ - tmp = INB(base + 0x0E); - tmp |= 0x20; - OUTB(tmp, base + 0x0E); - - return 0; -} - -/** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. * @@ -1073,12 +1125,12 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, - {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, + {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", board_asus_p4b266}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, - {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", ich5_gpio23_raise}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", board_dell_pe_1850}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, @@ -1103,7 +1155,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, - {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, + {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", board_msi_ms7046}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, -- 1.6.0.2 --KsGdsel6WgEHnImy--

1 0

Remove board enable for Asus P5A.
by Luc Verhaegen 23 Oct '09

23 Oct '09

A first: removal of what might be a working board enable still. Long story short; it's horrible and i do not want to spend any time on cleaning it up. We have better things to do. Luc Verhaegen.

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