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[commit] r1266 - trunk
by repository service 06 Mar '11

06 Mar '11

Author: mkarcher Date: Sun Mar 6 13:09:05 2011 New Revision: 1266 URL: http://flashrom.org/trac/flashrom/changeset/1266 Log: Board-enable for GA-K8N51GMF Gigabyte is not really helpful with their PCI IDs for us, the subsystem IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". We should investigate whether autodetection of this board is causing interference with other boards. real version 2: Extend list of PCI IDs for nvidia southbridges. flashrom -V: http://paste.flashrom.org/view.php?id=326 lspic: http://paste.flashrom.org/view.php?id=328 superiotool: http://paste.flashrom.org/view.php?id=329 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Mar 6 13:07:19 2011 (r1265) +++ trunk/board_enable.c Sun Mar 6 13:09:05 2011 (r1266) @@ -869,6 +869,7 @@ case 0x00E0: /* CK8 */ break; case 0x0260: /* MCP51 */ + case 0x0261: /* MCP51 */ case 0x0364: /* MCP55 */ /* find SMBus controller on *this* southbridge */ /* The infamous Tyan S2915-E has two south bridges; they are @@ -1029,7 +1030,8 @@ /* * Suited for: - * - GIGABYTE GA-K8N51GMF-9 + * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 + * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 */ static int nvidia_mcp_gpio3b_raise(void) { @@ -1954,6 +1956,7 @@ {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Mar 6 13:07:19 2011 (r1265) +++ trunk/print.c Sun Mar 6 13:09:05 2011 (r1266) @@ -482,6 +482,7 @@ B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), + B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL),

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[commit] r1265 - trunk
by repository service 06 Mar '11

06 Mar '11

Author: mkarcher Date: Sun Mar 6 13:07:19 2011 New Revision: 1265 URL: http://flashrom.org/trac/flashrom/changeset/1265 Log: Add HP e-Vectra P2706T Reported by: Michal Janke <jankeso(a)gmail.com> flashrom -V: http://paste.flashrom.org/view.php?id=370 lspci: http://paste.flashrom.org/view.php?id=371 superiotool: http://paste.flashrom.org/view.php?id=372 and http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Mar 5 17:31:57 2011 (r1264) +++ trunk/board_enable.c Sun Mar 6 13:07:19 2011 (r1265) @@ -543,7 +543,10 @@ return it8707f_write_enable(0x2e); } -static int pc87360_gpio_set(uint8_t gpio, int raise) +#define PC87360_ID 0xE1 +#define PC87364_ID 0xE4 + +static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise) { static const int bankbase[] = {0, 4, 8, 10, 12}; int gpio_bank = gpio / 8; @@ -552,13 +555,13 @@ uint8_t id, val; if (gpio_bank > 4) { - msg_perr("PC87360: Invalid GPIO %d\n", gpio); + msg_perr("PC8736x: Invalid GPIO %d\n", gpio); return -1; } id = sio_read(0x2E, 0x20); - if (id != 0xE1) { - msg_perr("PC87360: unexpected ID %02x\n", id); + if (id != chipid) { + msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n", id, chipid); return -1; } @@ -1483,9 +1486,22 @@ int ret; ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ if (!ret) - ret = pc87360_gpio_set(0x09, 1); /* #WP ? */ + ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */ + if (!ret) + ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */ + return ret; +} + +/* + * Suited for: + * - HP e-Vectra P2706T: 810E + ICH + PC87364 + */ +static int board_hp_p2706t(void) +{ + int ret; + ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1); if (!ret) - ret = pc87360_gpio_set(0x27, 1); /* #TBL */ + ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1); return ret; } @@ -1940,6 +1956,7 @@ {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, + {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable}, {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Mar 5 17:31:57 2011 (r1264) +++ trunk/print.c Sun Mar 6 13:07:19 2011 (r1265) @@ -493,6 +493,7 @@ B("GIGABYTE", "GA-MA78GPM-DS2H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2859", NULL), B("GIGABYTE", "GA-MA790FX-DQ6", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), B("GIGABYTE", "GA-MA790GP-DS4H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), + B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-33…", NULL), B("HP", "Puffer2-UL8E", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00300023", NULL),

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Re: [flashrom] [PATCH] kill central list of SPI programmers
by Carl-Daniel Hailfinger 06 Mar '11

06 Mar '11

Auf 18.07.2010 17:20, Michael Karcher schrieb: > This version really compiles. Forgot the forward declaration after > moving code initially. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > I like most ideas in there, and have some minor nitpicks. Using a registration function would allow us to handle multiple SPI programmers on one board (e.g. one in the EC and one in the southbridge), but some infrastructure changes elsewhere would be needed. We need that to handle stuff like the Google Cr-48 netbook sanely. One of my post-0.9.4 goals is to register programmer drivers for every bus, not just SPI. The idea is to be able to handle multiple flash chips behind LPC as well, e.g. if they have different base addresses. And stuff like switching between Dual BIOS chips with a GPIO line could be implemented under that scheme as well. > diff --git a/buspirate_spi.c b/buspirate_spi.c > index 55e71c2..36eaa9a 100644 > --- a/buspirate_spi.c > +++ b/buspirate_spi.c > @@ -44,6 +44,8 @@ static int buspirate_serialport_setup(char *dev) > #define sp_flush_incoming(...) 0 > #endif > > +static const struct spi_programmer spi_programmer_buspirate; > + > static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) > { > int i, ret = 0; > @@ -210,7 +212,7 @@ int buspirate_spi_init(void) > } > > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_BUSPIRATE; > + spi_programmer = &spi_programmer_buspirate; > You assign the spi_programmer variable directly. While that is a straightforward replacement of the current code, it would be cool if you could use a registration function instead: register_spi_programmer(&spi_programmer_buspirate); Depending on whether modification of the programmer-specific info is desired, it may also be possible to have that registration function copy the struct so later calls can make changes even if the original parameter is const. > > return 0; > } > @@ -250,7 +252,7 @@ int buspirate_spi_shutdown(void) > return 0; > } > > -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > static unsigned char *buf = NULL; > @@ -304,12 +306,20 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return ret; > } > > -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_read_chunked(flash, buf, start, len, 12); > } > > -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, 12); > } > + > +static const struct spi_programmer spi_programmer_buspirate = { > + .type = SPI_CONTROLLER_BUSPIRATE, > + .command = buspirate_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = buspirate_spi_read, > + .write_256 = buspirate_spi_write_256, > +}; > diff --git a/dediprog.c b/dediprog.c > index 0b92983..c21c801 100644 > --- a/dediprog.c > +++ b/dediprog.c > @@ -25,6 +25,7 @@ > > #define DEFAULT_TIMEOUT 3000 > static usb_dev_handle *dediprog_handle; > +static const struct spi_programmer spi_programmer_dediprog; > > #if 0 > /* Might be useful for other pieces of code as well. */ > @@ -145,14 +146,14 @@ static int dediprog_set_spi_speed(uint16_t speed) > } > #endif > > -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > msg_pspew("%s, start=0x%x, len=0x%x\n", __func__, start, len); > /* Chosen read length is 16 bytes for now. */ > return spi_read_chunked(flash, buf, start, len, 16); > } > > -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int ret; > @@ -318,7 +319,7 @@ int dediprog_init(void) > return 1; > > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_DEDIPROG; > + spi_programmer = &spi_programmer_dediprog; > Registration function. Same for all subsequent occurences. > > /* RE leftover, leave in until the driver is complete. */ > #if 0 > @@ -394,3 +395,11 @@ int dediprog_shutdown(void) > } > return 0; > } > + > +static const struct spi_programmer spi_programmer_dediprog = { > + .type = SPI_CONTROLLER_DEDIPROG, > + .command = dediprog_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = dediprog_spi_read, > + .write_256 = spi_chip_write_1_new, > +}; > diff --git a/dummyflasher.c b/dummyflasher.c > index 241dcee..b1bbcf2 100644 > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -25,6 +25,8 @@ > #include "flash.h" > #include "chipdrivers.h" > > +static const struct spi_programmer spi_programmer_dummy; > + > static void tolower_string(char *str) > { > for (; *str != '\0'; str++) > @@ -59,7 +61,7 @@ int dummy_init(void) > } > if (strstr(bustext, "spi")) { > buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_DUMMY; > + spi_programmer = &spi_programmer_dummy; > msg_pdbg("Enabling support for %s flash.\n", "SPI"); > } > if (buses_supported == CHIP_BUSTYPE_NONE) > @@ -140,7 +142,7 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) > return; > } > > -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -161,7 +163,7 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > /* Maximum read length is unlimited, use 64kB. */ > return spi_read_chunked(flash, buf, start, len, 64 * 1024); > @@ -171,7 +173,15 @@ int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > * never be successful, and the current frontend refuses to write in that case. > * Other frontends may allow writing even for non-detected chips, though. > */ > -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, 256); > } > + > +static const struct spi_programmer spi_programmer_dummy = { > + .type = SPI_CONTROLLER_DUMMY, > + .command = dummy_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = dummy_spi_read, > + .write_256 = dummy_spi_write_256, > +}; > diff --git a/flash.h b/flash.h > index 8ebea29..fb06207 100644 > --- a/flash.h > +++ b/flash.h > @@ -452,10 +452,6 @@ uint8_t dummy_chip_readb(const chipaddr addr); > uint16_t dummy_chip_readw(const chipaddr addr); > uint32_t dummy_chip_readl(const chipaddr addr); > void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); > -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > #endif > > /* nic3com.c */ > @@ -527,9 +523,6 @@ extern const struct pcidev_status ata_hpt[]; > #define FTDI_FT2232H 0x6010 > #define FTDI_FT4232H 0x6011 > int ft2232_spi_init(void); > -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); > -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* bitbang_spi.c */ > int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); > @@ -544,15 +537,10 @@ struct buspirate_spispeeds { > }; > int buspirate_spi_init(void); > int buspirate_spi_shutdown(void); > -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); > -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* dediprog.c */ > int dediprog_init(void); > int dediprog_shutdown(void); > -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); > -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* flashrom.c */ > enum write_granularity { > @@ -627,32 +615,18 @@ int handle_romentries(uint8_t *buffer, struct flashchip *flash); > > /* spi.c */ > enum spi_controller { > - SPI_CONTROLLER_NONE, > -#if CONFIG_INTERNAL == 1 > -#if defined(__i386__) || defined(__x86_64__) > SPI_CONTROLLER_ICH7, > SPI_CONTROLLER_ICH9, > SPI_CONTROLLER_IT87XX, > SPI_CONTROLLER_SB600, > SPI_CONTROLLER_VIA, > SPI_CONTROLLER_WBSIO, > -#endif > -#endif > -#if CONFIG_FT2232_SPI == 1 > SPI_CONTROLLER_FT2232, > -#endif > -#if CONFIG_DUMMY == 1 > SPI_CONTROLLER_DUMMY, > -#endif > -#if CONFIG_BUSPIRATE_SPI == 1 > SPI_CONTROLLER_BUSPIRATE, > -#endif > -#if CONFIG_DEDIPROG == 1 > SPI_CONTROLLER_DEDIPROG, > -#endif > - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ > Could you leave the #ifdefs in place for now? > }; > -extern const int spi_programmer_count; > + > struct spi_command { > unsigned int writecnt; > unsigned int readcnt; > @@ -660,6 +634,7 @@ struct spi_command { > unsigned char *readarr; > }; > struct spi_programmer { > + enum spi_controller type; > int (*command)(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int (*multicommand)(struct spi_command *cmds); > @@ -669,8 +644,8 @@ struct spi_programmer { > int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); > }; > > -extern enum spi_controller spi_controller; > -extern const struct spi_programmer spi_programmer[]; > +const struct spi_programmer *spi_programmer; > + > int spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int spi_send_multicommand(struct spi_command *cmds); > @@ -684,11 +659,6 @@ extern uint32_t ichspi_bbar; > void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > int ich_generation); > int via_init_spi(struct pci_dev * dev); > -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); > -int ich_spi_send_multicommand(struct spi_command *cmds); > > /* it87spi.c */ > void enter_conf_mode_ite(uint16_t port); > @@ -696,23 +666,12 @@ void exit_conf_mode_ite(uint16_t port); > struct superio probe_superio_ite(void); > int init_superio_ite(void); > int it87spi_init(void); > -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* sb600spi.c */ > void sb600_probe_spi(struct pci_dev * dev); > -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* wbsio_spi.c */ > int wbsio_check_for_spi(void); > -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* serprog.c */ > int serprog_init(void); > diff --git a/flashrom.c b/flashrom.c > index fe173a7..dc262d5 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1354,10 +1354,6 @@ int selfcheck(void) > msg_gerr("Programmer table miscompilation!\n"); > ret = 1; > } > - if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { > - msg_gerr("SPI programmer table miscompilation!\n"); > - ret = 1; > - } > for (flash = flashchips; flash && flash->name; flash++) > if (selfcheck_eraseblocks(flash)) > ret = 1; > diff --git a/ft2232_spi.c b/ft2232_spi.c > index c8711e9..b45ba42 100644 > --- a/ft2232_spi.c > +++ b/ft2232_spi.c > @@ -45,6 +45,7 @@ > #define BITMODE_BITBANG_NORMAL 1 > #define BITMODE_BITBANG_SPI 2 > > +static const struct spi_programmer spi_programmer_ft2232; > static struct ftdi_context ftdic_context; > > static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) > @@ -192,7 +193,7 @@ int ft2232_spi_init(void) > // msg_pdbg("\nft2232 chosen\n"); > > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_FT2232; > + spi_programmer = &spi_programmer_ft2232; > > return 0; > } > @@ -293,4 +294,12 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int l > return spi_write_chunked(flash, buf, start, len, 256); > } > > +static const struct spi_programmer spi_programmer_ft2232 = { > + .type = SPI_CONTROLLER_FT2232, > + .command = ft2232_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = ft2232_spi_read, > + .write_256 = ft2232_spi_write_256, > +}; > + > #endif > diff --git a/ichspi.c b/ichspi.c > index 246f3ae..ae9a5f4 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -106,6 +106,9 @@ static int ichspi_lock = 0; > uint32_t ichspi_bbar = 0; > > static void *ich_spibar = NULL; > +static const struct spi_programmer spi_programmer_ich7; > +static const struct spi_programmer spi_programmer_ich9; > +static const struct spi_programmer spi_programmer_via; > > typedef struct _OPCODE { > uint8_t opcode; //This commands spi opcode > @@ -234,7 +237,7 @@ static int generate_opcodes(OPCODES * op) > return -1; > } > > - switch (spi_controller) { > + switch (spi_programmer->type) { > We need to decide whether we want to access spi_programmer directly. It works in your patch, but if we go the route towards multiple SPI programmers on one board, we have to be sure to access the correct spi_programmer (maybe array member, maybe something else). If you have any neat ideas, please come forward. Otherwise I'd say your code is a good solution for now, and once we add support for registering multiple programmers, we'll notice this location because compilation will fail. > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_VIA: > preop = REGREAD16(ICH7_REG_PREOP); > @@ -309,7 +312,7 @@ int program_opcodes(OPCODES * op) > } > > msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_VIA: > REGWRITE16(ICH7_REG_PREOP, preop); > @@ -337,7 +340,7 @@ int program_opcodes(OPCODES * op) > */ > void ich_set_bbar(uint32_t minaddr) > { > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > mmio_writel(minaddr, ich_spibar + 0x50); > ichspi_bbar = mmio_readl(ich_spibar + 0x50); > @@ -448,19 +451,19 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > switch (ich_generation) { > case 7: > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH7; > + spi_programmer = &spi_programmer_ich7; > spibar_offset = 0x3020; > break; > case 8: > buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH9; > + spi_programmer = &spi_programmer_ich9; > spibar_offset = 0x3020; > break; > case 9: > case 10: > default: /* Future version might behave the same */ > buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH9; > + spi_programmer = &spi_programmer_ich9; > spibar_offset = 0x3800; > break; > } > @@ -471,7 +474,7 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > /* Assign Virtual Address */ > ich_spibar = rcrb + spibar_offset; > > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > msg_pdbg("0x00: 0x%04x (SPIS)\n", > mmio_readw(ich_spibar + 0)); > @@ -600,7 +603,7 @@ int via_init_spi(struct pci_dev * dev) > > /* Not sure if it speaks all these bus protocols. */ > buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_VIA; > + spi_programmer = &spi_programmer_via; > ich_init_opcodes(); > > return 0; > @@ -848,7 +851,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > static int run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data) > { > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_VIA: > if (datalength > 16) { > msg_perr("%s: Internal command size error for " > @@ -881,27 +884,27 @@ static int run_opcode(OPCODE op, uint32_t offset, > return -1; > } > > -int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) > +static int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) > { > int maxdata = 64; > > - if (spi_controller == SPI_CONTROLLER_VIA) > + if (spi_programmer->type == SPI_CONTROLLER_VIA) > maxdata = 16; > > return spi_read_chunked(flash, buf, start, len, maxdata); > } > > -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) > +static int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) > { > int maxdata = 64; > > - if (spi_controller == SPI_CONTROLLER_VIA) > + if (spi_programmer->type == SPI_CONTROLLER_VIA) > maxdata = 16; > > return spi_write_chunked(flash, buf, start, len, maxdata); > } > > -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int result; > @@ -966,7 +969,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { > addr = (writearr[1] << 16) | > (writearr[2] << 8) | (writearr[3] << 0); > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_ICH9: > if (addr < ichspi_bbar) { > @@ -1001,7 +1004,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return result; > } > > -int ich_spi_send_multicommand(struct spi_command *cmds) > +static int ich_spi_send_multicommand(struct spi_command *cmds) > { > int ret = 0; > int i; > @@ -1071,4 +1074,28 @@ int ich_spi_send_multicommand(struct spi_command *cmds) > return ret; > } > > +static const struct spi_programmer spi_programmer_ich7 = { > + .type = SPI_CONTROLLER_ICH7, > + .command = ich_spi_send_command, > + .multicommand = ich_spi_send_multicommand, > + .read = ich_spi_read, > + .write_256 = ich_spi_write_256, > +}; > + > +static const struct spi_programmer spi_programmer_ich9 = { > + .type = SPI_CONTROLLER_ICH9, > + .command = ich_spi_send_command, > + .multicommand = ich_spi_send_multicommand, > + .read = ich_spi_read, > + .write_256 = ich_spi_write_256, > +}; > + > +static const struct spi_programmer spi_programmer_via = { > + .type = SPI_CONTROLLER_VIA, > + .command = ich_spi_send_command, > + .multicommand = ich_spi_send_multicommand, > + .read = ich_spi_read, > + .write_256 = ich_spi_write_256, > +}; > + > #endif > diff --git a/it87spi.c b/it87spi.c > index cf3d3b9..dddb5a9 100644 > --- a/it87spi.c > +++ b/it87spi.c > @@ -34,6 +34,8 @@ > #define ITE_SUPERIO_PORT1 0x2e > #define ITE_SUPERIO_PORT2 0x4e > > +static const struct spi_programmer spi_programmer_it87xx; > + > uint16_t it8716f_flashport = 0; > /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ > static int fast_spi = 1; > @@ -175,7 +177,7 @@ static uint16_t it87spi_probe(uint16_t port) > it8716f_flashport = flashport; > if (buses_supported & CHIP_BUSTYPE_SPI) > msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); > - spi_controller = SPI_CONTROLLER_IT87XX; > + spi_programmer = &spi_programmer_it87xx; > buses_supported |= CHIP_BUSTYPE_SPI; > return 0; > } > @@ -227,7 +229,7 @@ int it87spi_init(void) > * commands with the address in inverse wire order. That's why the register > * ordering in case 4 and 5 may seem strange. > */ > -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > uint8_t busy, writeenc; > @@ -320,7 +322,7 @@ static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int s > * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles > * Need to read this big flash using firmware cycles 3 byte at a time. > */ > -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > int total_size = 1024 * flash->total_size; > fast_spi = 0; > @@ -334,7 +336,7 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int > return 0; > } > > -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > /* > * IT8716F only allows maximum of 512 kb SPI chip size for memory > @@ -371,4 +373,12 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, > return 0; > } > > +static const struct spi_programmer spi_programmer_it87xx = { > + .type = SPI_CONTROLLER_IT87XX, > + .command = it8716f_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = it8716f_spi_chip_read, > + .write_256 = it8716f_spi_chip_write_256, > +}; > + > #endif > diff --git a/sb600spi.c b/sb600spi.c > index e42b20b..866e309 100644 > --- a/sb600spi.c > +++ b/sb600spi.c > @@ -41,6 +41,7 @@ > */ > > static uint8_t *sb600_spibar = NULL; > +static const struct spi_programmer spi_programmer_sb600; > > void sb600_probe_spi(struct pci_dev * dev) > { > @@ -114,16 +115,16 @@ void sb600_probe_spi(struct pci_dev * dev) > return; > > buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_SB600; > + spi_programmer = &spi_programmer_sb600; > } > > -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > /* Maximum read length is 8 bytes. */ > return spi_read_chunked(flash, buf, start, len, 8); > } > > -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, 5); > } > @@ -144,7 +145,7 @@ static void execute_command(void) > ; > } > > -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int count; > @@ -227,4 +228,12 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > +static const struct spi_programmer spi_programmer_sb600 = { > + .type = SPI_CONTROLLER_SB600, > + .command = sb600_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = sb600_spi_read, > + .write_256 = sb600_spi_write_256, > +}; > + > #endif > diff --git a/spi.c b/spi.c > index 2b64463..dc4da9f 100644 > --- a/spi.c > +++ b/spi.c > @@ -27,129 +27,34 @@ > #include "chipdrivers.h" > #include "spi.h" > > -enum spi_controller spi_controller = SPI_CONTROLLER_NONE; > - > void spi_prettyprint_status_register(struct flashchip *flash); > > -const struct spi_programmer spi_programmer[] = { > - { /* SPI_CONTROLLER_NONE */ > - .command = NULL, > - .multicommand = NULL, > - .read = NULL, > - .write_256 = NULL, > - }, > - > -#if CONFIG_INTERNAL == 1 > -#if defined(__i386__) || defined(__x86_64__) > - { /* SPI_CONTROLLER_ICH7 */ > - .command = ich_spi_send_command, > - .multicommand = ich_spi_send_multicommand, > - .read = ich_spi_read, > - .write_256 = ich_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_ICH9 */ > - .command = ich_spi_send_command, > - .multicommand = ich_spi_send_multicommand, > - .read = ich_spi_read, > - .write_256 = ich_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_IT87XX */ > - .command = it8716f_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = it8716f_spi_chip_read, > - .write_256 = it8716f_spi_chip_write_256, > - }, > - > - { /* SPI_CONTROLLER_SB600 */ > - .command = sb600_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = sb600_spi_read, > - .write_256 = sb600_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_VIA */ > - .command = ich_spi_send_command, > - .multicommand = ich_spi_send_multicommand, > - .read = ich_spi_read, > - .write_256 = ich_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_WBSIO */ > - .command = wbsio_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = wbsio_spi_read, > - .write_256 = spi_chip_write_1_new, > - }, > -#endif > -#endif > - > -#if CONFIG_FT2232_SPI == 1 > - { /* SPI_CONTROLLER_FT2232 */ > - .command = ft2232_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = ft2232_spi_read, > - .write_256 = ft2232_spi_write_256, > - }, > -#endif > - > -#if CONFIG_DUMMY == 1 > - { /* SPI_CONTROLLER_DUMMY */ > - .command = dummy_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = dummy_spi_read, > - .write_256 = dummy_spi_write_256, > - }, > -#endif > - > -#if CONFIG_BUSPIRATE_SPI == 1 > - { /* SPI_CONTROLLER_BUSPIRATE */ > - .command = buspirate_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = buspirate_spi_read, > - .write_256 = buspirate_spi_write_256, > - }, > -#endif > - > -#if CONFIG_DEDIPROG == 1 > - { /* SPI_CONTROLLER_DEDIPROG */ > - .command = dediprog_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = dediprog_spi_read, > - .write_256 = spi_chip_write_1_new, > - }, > -#endif > - > - {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ > -}; > - > -const int spi_programmer_count = ARRAY_SIZE(spi_programmer); > +const struct spi_programmer *spi_programmer; > If someone forces a SPI access on a programmer which does not support SPI, this will explode AFAICS because it means following an uninitialized pointer to check for NULL in a struct member which does not exist. > > int spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > - if (!spi_programmer[spi_controller].command) { > + if (!spi_programmer->command) { > msg_perr("%s called, but SPI is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].command(writecnt, readcnt, > + return spi_programmer->command(writecnt, readcnt, > writearr, readarr); > } > > int spi_send_multicommand(struct spi_command *cmds) > { > - if (!spi_programmer[spi_controller].multicommand) { > + if (!spi_programmer->multicommand) { > msg_perr("%s called, but SPI is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].multicommand(cmds); > + return spi_programmer->multicommand(cmds); > } > > int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, > @@ -183,14 +88,14 @@ int default_spi_send_multicommand(struct spi_command *cmds) > > int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > - if (!spi_programmer[spi_controller].read) { > + if (!spi_programmer->read) { > msg_perr("%s called, but SPI read is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].read(flash, buf, start, len); > + return spi_programmer->read(flash, buf, start, len); > } > > /* > @@ -202,14 +107,14 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > /* real chunksize is up to 256, logical chunksize is 256 */ > int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len) > { > - if (!spi_programmer[spi_controller].write_256) { > + if (!spi_programmer->write_256) { > msg_perr("%s called, but SPI page write is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].write_256(flash, buf, start, len); > + return spi_programmer->write_256(flash, buf, start, len); > } > > /* Wrapper function until the generic code is converted to partial writes. */ > @@ -239,7 +144,7 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) > */ > uint32_t spi_get_valid_read_addr(void) > { > - switch (spi_controller) { > + switch (spi_programmer->type) { > #if CONFIG_INTERNAL == 1 > #if defined(__i386__) || defined(__x86_64__) > case SPI_CONTROLLER_ICH7: > diff --git a/spi25.c b/spi25.c > index 32bb73c..d9dae35 100644 > --- a/spi25.c > +++ b/spi25.c > @@ -177,7 +177,7 @@ int probe_spi_rdid4(struct flashchip *flash) > /* Some SPI controllers do not support commands with writecnt=1 and > * readcnt=4. > */ > - switch (spi_controller) { > + switch (spi_programmer->type) { > #if CONFIG_INTERNAL == 1 > #if defined(__i386__) || defined(__x86_64__) > case SPI_CONTROLLER_IT87XX: > @@ -1019,7 +1019,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) > .readarr = NULL, > }}; > > - switch (spi_controller) { > + switch (spi_programmer->type) { > #if CONFIG_INTERNAL == 1 > #if defined(__i386__) || defined(__x86_64__) > case SPI_CONTROLLER_IT87XX: > diff --git a/wbsio_spi.c b/wbsio_spi.c > index b8f8b38..6288340 100644 > --- a/wbsio_spi.c > +++ b/wbsio_spi.c > @@ -28,6 +28,7 @@ > #define WBSIO_PORT2 0x4e > > static uint16_t wbsio_spibase = 0; > +static const struct spi_programmer spi_programmer_wbsio; > > static uint16_t wbsio_get_spibase(uint16_t port) > { > @@ -68,7 +69,7 @@ int wbsio_check_for_spi(void) > msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); > > buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_WBSIO; > + spi_programmer = &spi_programmer_wbsio; > msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " > "1024 KB!\n", __func__); > max_rom_decode.spi = 1024 * 1024; > @@ -96,7 +97,7 @@ int wbsio_check_for_spi(void) > * Would one more byte of RAM in the chip (to get all 24 bits) really make > * such a big difference? > */ > -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -180,9 +181,18 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return read_memmapped(flash, buf, start, len); > } > > +static const struct spi_programmer spi_programmer_wbsio = { > + .type = SPI_CONTROLLER_WBSIO, > + .command = wbsio_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = wbsio_spi_read, > + .write_256 = spi_chip_write_1_new, > +}; > + > + > #endif > Looks good otherwise. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

SUCCESS: Gigabyte GA-M61P-S3
by Simon Elsbrock 05 Mar '11

05 Mar '11

http://paste.flashrom.org/view.php?id=384 http://paste.flashrom.org/view.php?id=385 http://paste.flashrom.org/view.php?id=386

1 0

[PATCH] Add mainboards to print.c and mark writing as tested on Winbond W25x80
by Yul Rottmann 05 Mar '11

05 Mar '11

Hello List, I successfully tested flashrom on my MSI MS-7596 (785GM-E51). Here is the patch to add it to the list of supported mainboards. Also I marked writing as tested on the flashchip that belongs to it. Earlier I reported the success of flashing my GIGABYTE GA-MA78G-DS3H. This patch makes clear that it is about the revision 1.0. I also tested flashing an ASRock 890GX Extreme3, which worked. I also added it to print.c. If you have questions, please contact me on my private e-mail adress since I haven't subscribed to the mailinglist. Thanks! Signed-off-by: Yul Rottmann <yulrottmann(a)bitel.net>

2 1

[commit] r1264 - trunk
by repository service 05 Mar '11

05 Mar '11

Author: hailfinger Date: Sat Mar 5 17:31:57 2011 New Revision: 1264 URL: http://flashrom.org/trac/flashrom/changeset/1264 Log: I tested a few mainboards and flash chips. Successfully tested MSI MS-7596 (785GM-E51). Successfully tested ASRock 890GX Extreme3. Successfully tested Winbond W25x80. Mention which GIGABYTE GA-MA78G-DS3H board revision was tested. Signed-off-by: Yul Rottmann <yulrottmann(a)bitel.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/print.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Mar 1 00:58:15 2011 (r1263) +++ trunk/flashchips.c Sat Mar 5 17:31:57 2011 (r1264) @@ -7597,7 +7597,7 @@ .total_size = 1024, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Mar 1 00:58:15 2011 (r1263) +++ trunk/print.c Sat Mar 5 17:31:57 2011 (r1264) @@ -358,6 +358,7 @@ B("Artec Group","DBE62", 1, "http://wiki.thincan.org/DBE62", NULL), B("ASI", "MB-5BLMP", 1, "http://www.hojerteknik.com/winnet.htm", "Used in the IGEL WinNET III thin client."), B("ASRock", "775i65G", 1, "http://www.asrock.com/mb/overview.asp?Model=775i65G", NULL), + B("ASRock", "890GX Extreme3", 1, "http://www.asrock.com/mb/overview.asp?Model=890GX%20Extreme3", NULL), B("ASRock", "939A785GMH/128M", 1, "http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939", NULL), B("ASRock", "A330GC", 1, "http://www.asrock.com/mb/overview.asp?Model=A330GC", NULL), B("ASRock", "A770CrossFire", 1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2%%2b", NULL), @@ -487,7 +488,7 @@ B("GIGABYTE", "GA-MA69VM-S2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2500", NULL), B("GIGABYTE", "GA-MA74GM-S2H (rev. 3.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3152", NULL), B("GIGABYTE", "GA-MA770T-UD3P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3096", NULL), - B("GIGABYTE", "GA-MA78G-DS3H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2800", NULL), /* TODO: Rev 1.x or 2.x? */ + B("GIGABYTE", "GA-MA78G-DS3H (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2800", NULL), B("GIGABYTE", "GA-MA78GM-S2H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2758", NULL), /* TODO: Rev. 1.0, 1.1, or 2.x? */ B("GIGABYTE", "GA-MA78GPM-DS2H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2859", NULL), B("GIGABYTE", "GA-MA790FX-DQ6", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), @@ -541,6 +542,7 @@ B("MSI", "MS-7345 (P35 Neo2-FIR)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1261", NULL), B("MSI", "MS-7368 (K9AG Neo2-Digital)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1241", NULL), B("MSI", "MS-7376 (K9A2 Platinum)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1332", NULL), + B("MSI", "MS-7596 (785GM-E51)", 1, "http://eu.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1866", NULL), B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=2012", NULL), B("NEC", "PowerMate 2000", 1, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), B("Nokia", "IP530", 1, NULL, NULL),

1 0

FAILED: Asus P5N-E SLI
by Segfault 04 Mar '11

04 Mar '11

Hi, I cannot flash the BIOS on my Asus P5N-E SLI. I am confident that I could reboot the computer without issues, as I have dumped before and after the error and the flash is unchanged. I still would like to have support for this motherboard. Here is the output of flashrom -V flashrom v0.9.3-r1262 on Linux 2.6.32-5-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1866M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1006 us, 10000 myus = 10003 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5N-E SLI" DMI string baseboard-version: "1.XX " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8718. Found chipset "NVIDIA MCP51", enabling flash write... chipset PCI ID is 10de:0260, OK. This chipset supports the following protocols: Non-SPI. No IT87* serial flash segment enabled. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A25L512, 64 KB: skipped. Probing for AMIC A25L010, 128 KB: skipped. Probing for AMIC A25L020, 256 KB: skipped. Probing for AMIC A25L040, 512 KB: skipped. Probing for AMIC A25L080, 1024 KB: skipped. Probing for AMIC A25L016, 2048 KB: skipped. Probing for AMIC A25L032, 4096 KB: skipped. Probing for AMIC A25LQ032, 4096 KB: skipped. Probing for AMIC A29002B, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF081A, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25DQ161, 2048 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49F020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Bright BM29F040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for EMST F25L008A, 1024 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for Hyundai HY29F002T, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Hyundai HY29F002B, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Hyundai HY29F040A, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Intel 28F001BN/BX-T, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: probe_82802ab: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: probe_82802ab: id1 0x21, id2 0x2d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: probe_82802ab: id1 0x21, id2 0x2d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L1635E, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29C51000T, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29C51400B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29C51400T, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29LC51000, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29LC51001, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29LC51002, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for Spansion S25FL032A, 4096 KB: skipped. Probing for Spansion S25FL064A, 8192 KB: skipped. Probing for SST SST25VF010.REMS, 128 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M25PX32, 4096 KB: skipped. Probing for ST M25PX64, 8192 KB: skipped. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0xe9, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W29C020(C)/W29C022, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W29C040/P, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040C, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Found chip "Winbond W39V040C" (512 KB, LPC) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is active. Hardware remaining chip locking (#WP) is active.. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FB, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FC, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Found chip "Winbond W39V040FC" (512 KB, FWH) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is active. Hardware remaining chip locking (#WP) is active.. Lock status of block at 0x00000000 is Full Access. Lock status of block at 0x00010000 is Full Access. Lock status of block at 0x00020000 is Full Access. Lock status of block at 0x00030000 is Full Access. Lock status of block at 0x00040000 is Full Access. Lock status of block at 0x00050000 is Full Access. Lock status of block at 0x00060000 is Full Access. Lock status of block at 0x00070000 is Full Access. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W49F020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V080FA, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for Eon unknown Eon SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Multiple flash chips were detected: W39V040C W39V040FC Please specify which chip to use with the -c <chipname> option. Restoring PCI config space for 00:0a:0 reg 0x6d Here is the output when I specify either chip name: flashrom v0.9.3-r1262 on Linux 2.6.32-5-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1866M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1005 us, 10000 myus = 10003 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5N-E SLI" DMI string baseboard-version: "1.XX " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8718. Found chipset "NVIDIA MCP51", enabling flash write... chipset PCI ID is 10de:0260, OK. This chipset supports the following protocols: Non-SPI. No IT87* serial flash segment enabled. Probing for Winbond W39V040C, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Found chip "Winbond W39V040C" (512 KB, LPC) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is active. Hardware remaining chip locking (#WP) is active.. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling checks. Reading old flash chip contents... Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x00ffff:E Looking at blockwise erase function 1... trying... 0x000000-0x07ffff:E Looking at blockwise erase function 2... not defined. trying... Done. Verifying flash... Restoring PCI config space for 00:0a:0 reg 0x6d

2 3

FIXMEs
by Carl-Daniel Hailfinger 04 Mar '11

04 Mar '11

Hi, you may have noticed that many of my recent patches added FIXME comments to existing and new code. My goals related to those FIXMEs are threefold: - Give others a chance to grep for FIXME if they don't know what to contribute. - Mark places which either need bugfixes, design changes or which make assumptions which are not guaranteed to be valid in the future. - Provide hints for people refactoring code related to the snippet with FIXME. While I could probably fix most of the places instead of adding FIXMEs, my patches would grow to an unmanageable and unreviewable size. If you spot some problem and think fixing it is not super urgent, feel free to add a FIXME yourself. What do you think? Should I stop adding FIXMEs or are they valuable hints? Regards, Carl-Daniel -- http://www.hailfinger.org/

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UBW32 flashing LPC/FWH in 20us
by Joseph Smith 03 Mar '11

03 Mar '11

Hey the UBW32 (http://www.schmalzhaus.com/UBW32/) has enough I/O (78) pins to be able to flash LPC/FWH chips in programming mode or A/A Mux mode. In this mode you are able to flash in 8bit bytes instead of 4bit nibbles. A few of the datasheets I have seen says in this mode a 256K chip could be flashed in approx 20us. That is friggin fast!!! The only thing that would some what slow it down is USB. But, the UBW32 is detected as a USB HID device and you can do data transfers over serial console. I think this is a major discovery I will be looking into. Thoughts? Comments? FWI the UBW32 dev board from SparFun is $40 and has a built in 3.3v voltage regulator, mount it on a daughter board with a socket you would have a smoking fast programmer for about $50 :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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Re: [flashrom] Hmmm UBW?
by Joseph Smith 01 Mar '11

01 Mar '11

On Mon, 28 Feb 2011 22:12:37 -0600, Марко Краљевић <krasnaya.zvezda(a)gmail.com> wrote: > On Mon, Feb 28, 2011 at 17:08, Joseph Smith <joe(a)settoplinux.org> wrote: > >> http://www.schmalzhaus.com/UBW/ >> >> > This is probably pretty pokey? I was thinking of making something similar > with an AVR. I can't seem to find much information on speed capability of > USB CDC / ACM devices though? > If they only support 115k or whatnot as the top end, it'll be pretty > painful, I'd think. > > curious. I was looking at some of the UBW tutorials and it appears you can set the baudrate to pretty much what ever you want. It is set in the PIC's "bootloader" / firmware and of course your PC (that is what you mean by 115k correct?). The PIC18 runs at 48 MHz. There is also a UBW32 project that runs a PIC32 at 80 MHz but I am not sure if that would be a overkill and it costs more. Any ways there are sparkfun modules for both versions and the PIC18 chip itself only goes for around $6-7 dollars. I just think it is really cool that the UBW was orriginally designed as a parallel replacement for bit-banging over USB-> serial. I think it would be very easy to add flashrom support for this device and there is enough GPIO's on the PIC18 so you could support both LPC/FWH and SPI on the same device. I also like how "open" Microchip is with their products :-) Anyways I don't know alot about PIC devices but I thought I would throw it out there that it seems like 75% of the work has already been done on the UBW to make it a neat little cost effective external USB flashrom programmer. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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[commit] r1263 - trunk
by repository service 01 Mar '11

01 Mar '11

Author: hailfinger Date: Tue Mar 1 00:58:15 2011 New Revision: 1263 URL: http://flashrom.org/trac/flashrom/changeset/1263 Log: Update the ITE IT8500 EC support to match the current state of the flashrom-chromium tree. This code has been deployed and tested to work on the Cr-48. There are a few caveats, though: - The boot BIOS straps register must be modified to select LPC. This can be done with the "select_bbs.sh" script (Install iotools at http://code.google.com/p/iotools/ before using select_bbs). - It is very important to disable power management daemons before running flashrom on this EC. I commented out the brute force method we use in the Chromium OS branch that disables powerd, since IIRC Carl-Daniel has a better approach in the works. - Due to dependencies which may be introduced by the OEM/ODM EC firmware, the code is not guaranteed to work for anything other than the Cr-48. Signed-off-by: David Hendricks <dhendrix(a)google.com> Carl-Daniel comments: Code is not hooked up yet because probing needs to be sorted out. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile trunk/it85spi.c trunk/programmer.h trunk/spi.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Feb 22 18:16:34 2011 (r1262) +++ trunk/Makefile Tue Mar 1 00:58:15 2011 (r1263) @@ -184,7 +184,7 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o # FIXME: The PROGRAMMER_OBJS below should only be included on x86. -PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o NEED_PCI := yes endif Modified: trunk/it85spi.c ============================================================================== --- trunk/it85spi.c Tue Feb 22 18:16:34 2011 (r1262) +++ trunk/it85spi.c Tue Mar 1 00:58:15 2011 (r1263) @@ -27,18 +27,23 @@ #if defined(__i386__) || defined(__x86_64__) #include <string.h> +#include <stdio.h> #include <stdlib.h> #include "flash.h" #include "chipdrivers.h" #include "spi.h" #include "programmer.h" +#define MAX_TIMEOUT 100000 +#define MAX_TRY 5 + /* Constans for I/O ports */ #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e /* Legacy I/O */ -#define LEGACY_KBC_PORT 0x64 +#define LEGACY_KBC_PORT_DATA 0x60 +#define LEGACY_KBC_PORT_CMD 0x64 /* Constants for Logical Device registers */ #define LDNSEL 0x07 @@ -50,6 +55,13 @@ #define SHM_IO_BAD0 0x60 /* big-endian, this is high bits */ #define SHM_IO_BAD1 0x61 +/* 8042 keyboard controller uses an input buffer and an output buffer to + * communicate with host CPU. Both buffers are 1-byte depth. That means the + * IBF is set to 1 when host CPU sends a command to input buffer (standing on + * the EC side). IBF is cleared to 0 once the command is read by EC. */ +#define KB_IBF (1 << 1) /* Input Buffer Full */ +#define KB_OBF (1 << 0) /* Output Buffer Full */ + /* IT8502 supports two access modes: * LPC_MEMORY: through the memory window in 0xFFFFFxxx (follow mode) * LPC_IO: through I/O port (so called indirect memory) @@ -95,11 +107,11 @@ ret.model = probe_id_ite85(ret.port); switch (ret.model >> 8) { case 0x85: - msg_pinfo("Found EC: ITE85xx (Vendor:0x%02x,ID:0x%02x," - "Rev:0x%02x) on sio_port:0x%x.\n", - ret.model >> 8, ret.model & 0xff, - sio_read(ret.port, CHIP_CHIP_VER_REG), - ret.port); + msg_pdbg("Found EC: ITE85xx (Vendor:0x%02x,ID:0x%02x," + "Rev:0x%02x) on sio_port:0x%x.\n", + ret.model >> 8, ret.model & 0xff, + sio_read(ret.port, CHIP_CHIP_VER_REG), + ret.port); return ret; } } @@ -111,20 +123,147 @@ return ret; } -/* IT8502 employs a scratch rom when flash is updating. Call the following two - * functions before/after flash erase/program. */ +/* This function will poll the keyboard status register until either + * an expected value shows up, or + * timeout reaches. + * + * Returns: 0 -- the expected value has shown. + * 1 -- timeout reached. + */ +static int wait_for( + const unsigned int mask, + const unsigned int expected_value, + const int timeout, /* in usec */ + const char* error_message, + const char* function_name, + const int lineno +) { + int time_passed; + + for (time_passed = 0;; ++time_passed) { + if ((INB(LEGACY_KBC_PORT_CMD) & mask) == expected_value) + return 0; + if (time_passed >= timeout) + break; + programmer_delay(1); + } + if (error_message) + msg_perr("%s():%d %s", function_name, lineno, error_message); + return 1; +} + +/* IT8502 employs a scratch ram when flash is being updated. Call the following + * two functions before/after flash erase/program. */ void it85xx_enter_scratch_rom() { + int ret; + int tries; + + msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__); if (it85xx_scratch_rom_reenter > 0) return; - it85xx_scratch_rom_reenter++; - OUTB(0xb4, LEGACY_KBC_PORT); + +#if 0 + /* FIXME: this a workaround for the bug that SMBus signal would + * interfere the EC firmware update. Should be removed if + * we find out the root cause. */ + ret = system("stop powerd >&2"); + if (ret) { + msg_perr("Cannot stop powerd.\n"); + } +#endif + + for (tries = 0; tries < MAX_TRY; ++tries) { + /* Wait until IBF (input buffer) is not full. */ + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + "* timeout at waiting for IBF==0.\n", + __FUNCTION__, __LINE__)) + continue; + + /* Copy EC firmware to SRAM. */ + OUTB(0xb4, LEGACY_KBC_PORT_CMD); + + /* Confirm EC has taken away the command. */ + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + "* timeout at taking command.\n", + __FUNCTION__, __LINE__)) + continue; + + /* Waiting for OBF (output buffer) has data. + * Note sometimes the replied command might be stolen by kernel + * ISR so that it is okay as long as the command is 0xFA. */ + if (wait_for(KB_OBF, KB_OBF, MAX_TIMEOUT, NULL, NULL, 0)) + msg_pdbg("%s():%d * timeout at waiting for OBF.\n", + __FUNCTION__, __LINE__); + if ((ret = INB(LEGACY_KBC_PORT_DATA)) == 0xFA) { + break; + } else { + msg_perr("%s():%d * not run on SRAM ret=%d\n", + __FUNCTION__, __LINE__, ret); + continue; + } + } + + if (tries < MAX_TRY) { + /* EC already runs on SRAM */ + it85xx_scratch_rom_reenter++; + msg_pdbg("%s():%d * SUCCESS.\n", __FUNCTION__, __LINE__); + } else { + msg_perr("%s():%d * Max try reached.\n", + __FUNCTION__, __LINE__); + } } void it85xx_exit_scratch_rom() { +#if 0 + int ret; +#endif + int tries; + + msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__); if (it85xx_scratch_rom_reenter <= 0) return; - it85xx_scratch_rom_reenter = 0; - OUTB(0xfe, LEGACY_KBC_PORT); + + for (tries = 0; tries < MAX_TRY; ++tries) { + /* Wait until IBF (input buffer) is not full. */ + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + "* timeout at waiting for IBF==0.\n", + __FUNCTION__, __LINE__)) + continue; + + /* Exit SRAM. Run on flash. */ + OUTB(0xFE, LEGACY_KBC_PORT_CMD); + + /* Confirm EC has taken away the command. */ + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + "* timeout at taking command.\n", + __FUNCTION__, __LINE__)) { + /* We cannot ensure if EC has exited update mode. + * If EC is in normal mode already, a further 0xFE + * command will reboot system. So, exit loop here. */ + tries = MAX_TRY; + break; + } + + break; + } + + if (tries < MAX_TRY) { + it85xx_scratch_rom_reenter = 0; + msg_pdbg("%s():%d * SUCCESS.\n", __FUNCTION__, __LINE__); + } else { + msg_perr("%s():%d * Max try reached.\n", + __FUNCTION__, __LINE__); + } + +#if 0 + /* FIXME: this a workaround for the bug that SMBus signal would + * interfere the EC firmware update. Should be removed if + * we find out the root cause. */ + ret = system("start powerd >&2"); + if (ret) { + msg_perr("Cannot start powerd again.\n"); + } +#endif } int it85xx_spi_common_init(void) @@ -256,6 +395,14 @@ readarr[i] = *ce_low; #endif } +#ifdef LPC_IO + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); + INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ +#endif +#ifdef LPC_MEMORY + *ce_high = 0; +#endif + return 0; } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Tue Feb 22 18:16:34 2011 (r1262) +++ trunk/programmer.h Tue Mar 1 00:58:15 2011 (r1263) @@ -523,6 +523,7 @@ #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, @@ -583,6 +584,14 @@ int ich_spi_send_multicommand(struct spi_command *cmds); #endif +/* it85spi.c */ +struct superio probe_superio_ite85xx(void); +int it85xx_spi_init(void); +int it85xx_shutdown(void); +int it85xx_probe_spi_flash(const char *name); +int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Tue Feb 22 18:16:34 2011 (r1262) +++ trunk/spi.c Tue Mar 1 00:58:15 2011 (r1263) @@ -55,6 +55,13 @@ .write_256 = ich_spi_write_256, }, + { /* SPI_CONTROLLER_IT85XX */ + .command = it85xx_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, + }, + { /* SPI_CONTROLLER_IT87XX */ .command = it8716f_spi_send_command, .multicommand = default_spi_send_multicommand,

1 0

Hmmm
by Joseph Smith 01 Mar '11

01 Mar '11

http://www.schmalzhaus.com/UBW/ -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

1 0

LPC programmer over serial port
by Joseph Smith 28 Feb '11

28 Feb '11

I found this interesting... LPC programmer over serial port... http://interesting-devices.com/asp/product.asp?recorprod=1&product=318&cat=… -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

1 0

[patch] make EPoX EP-8NPA7I board enable actually work
by Jonathan A. Kollasch 27 Feb '11

27 Feb '11

The OEM BIOS on the EPoX EP-8PA7I clears byte 0x92 in the LPC bridge configuration space. Do the same for all CK804 chips, assuming this to be some sort of chipset-generic write-enable. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ---

3 2

intel 845grg (rebranded gateway)
by Jason Dravet 22 Feb '11

22 Feb '11

I have used flashrom on an intel 845grg motherboard. I had flashed it to an intel bios from a gateway bios, but I had to change it back and flashrom was the only program able to do the job. Here is the data that was requested. I used the -r option on one pc and -w on a second pc. If I could make a feature request: is there any way to change the serial number of the system and motherboard? I read the current bios from one pc and flashed it another unit and the old pc's serial number and serial number of the motherboard are in the new pc. The good news is the mac address didn't change. Thanks, Jason Dravet

1 0

Re: [flashrom] [PATCH] Initial ITE IT8500 EC support
by Carl-Daniel Hailfinger 22 Feb '11

22 Feb '11

Dear Donald, thanks a lot for your patch. I will review it as soon as possible, and I will work with you to ensure a speedy integration of the patch. Right now we are in the process of finalizing the flashrom 0.9.3 release, and such a big new feature needs to be reviewed in depth before being merged, so it won't be part of 0.9.3. I'm very confident this patch will be fully integrated before flashrom 0.9.4. On 09.08.2010 05:06, Donald.Huang(a)ite.com.tw wrote: > The attached patch adds generalized support for IT8500/IT8502 embedded controllers. > The patch was developed by Google for Flashrom r1082, but applies cleanly against r1130. > It was tested for IT8500E on a Chrome OS platform and may require modification > depending on ODM/OEM customization and EC firmware version. > > Signed-off by: Donald Huang (donald.huang(a)ite.com.tw) > Signed-off by: Yung-chieh Lo (yjlou(a)google.com) > Signed-off by: David Hendricks (dhendrix(a)google.com) > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

[commit] r1262 - trunk
by repository service 22 Feb '11

22 Feb '11

Author: hailfinger Date: Tue Feb 22 18:16:34 2011 New Revision: 1262 URL: http://flashrom.org/trac/flashrom/changeset/1262 Log: Add generalized support for ITE IT8500/IT8502 embedded controllers. The patch was developed by Google. It was tested for IT8500E on a Chrome OS platform and may require modification depending on ODM/OEM customization and EC firmware version. This patch is not officially supported by ITE Tech Inc. Signed-off-by: Donald Huang <donald.huang(a)ite.com.tw> Signed-off-by: Yung-chieh Lo <yjlou(a)google.com> Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/it85spi.c Added: trunk/it85spi.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/it85spi.c Tue Feb 22 18:16:34 2011 (r1262) @@ -0,0 +1,262 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger + * Copyright (C) 2008 Ronald Hoogenboom <ronald(a)zonnet.nl> + * Copyright (C) 2008 coresystems GmbH + * Copyright (C) 2010 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Contains the ITE IT85* SPI specific routines + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include <string.h> +#include <stdlib.h> +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" +#include "programmer.h" + +/* Constans for I/O ports */ +#define ITE_SUPERIO_PORT1 0x2e +#define ITE_SUPERIO_PORT2 0x4e + +/* Legacy I/O */ +#define LEGACY_KBC_PORT 0x64 + +/* Constants for Logical Device registers */ +#define LDNSEL 0x07 +#define CHIP_ID_BYTE1_REG 0x20 +#define CHIP_ID_BYTE2_REG 0x21 +#define CHIP_CHIP_VER_REG 0x22 + +/* These are standard Super I/O 16-bit base address registers */ +#define SHM_IO_BAD0 0x60 /* big-endian, this is high bits */ +#define SHM_IO_BAD1 0x61 + +/* IT8502 supports two access modes: + * LPC_MEMORY: through the memory window in 0xFFFFFxxx (follow mode) + * LPC_IO: through I/O port (so called indirect memory) + */ +#undef LPC_MEMORY +#define LPC_IO + +#ifdef LPC_IO +/* macro to fill in indirect-access registers. */ +#define INDIRECT_A0(base, value) OUTB(value, (base) + 0) /* little-endian */ +#define INDIRECT_A1(base, value) OUTB(value, (base) + 1) +#define INDIRECT_A2(base, value) OUTB(value, (base) + 2) +#define INDIRECT_A3(base, value) OUTB(value, (base) + 3) +#define INDIRECT_READ(base) INB((base) + 4) +#define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4) +#endif /* LPC_IO */ + +#ifdef LPC_IO +unsigned int shm_io_base; +#endif +unsigned char *ce_high, *ce_low; +static int it85xx_scratch_rom_reenter = 0; + +uint16_t probe_id_ite85(uint16_t port) +{ + uint16_t id; + + id = sio_read(port, CHIP_ID_BYTE1_REG) << 8 | + sio_read(port, CHIP_ID_BYTE2_REG); + + return id; +} + +struct superio probe_superio_ite85xx(void) +{ + struct superio ret = {}; + uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0}; + uint16_t *i = ite_ports; + + ret.vendor = SUPERIO_VENDOR_ITE; + for (; *i; i++) { + ret.port = *i; + ret.model = probe_id_ite85(ret.port); + switch (ret.model >> 8) { + case 0x85: + msg_pinfo("Found EC: ITE85xx (Vendor:0x%02x,ID:0x%02x," + "Rev:0x%02x) on sio_port:0x%x.\n", + ret.model >> 8, ret.model & 0xff, + sio_read(ret.port, CHIP_CHIP_VER_REG), + ret.port); + return ret; + } + } + + /* No good ID found. */ + ret.vendor = SUPERIO_VENDOR_NONE; + ret.port = 0; + ret.model = 0; + return ret; +} + +/* IT8502 employs a scratch rom when flash is updating. Call the following two + * functions before/after flash erase/program. */ +void it85xx_enter_scratch_rom() +{ + if (it85xx_scratch_rom_reenter > 0) return; + it85xx_scratch_rom_reenter++; + OUTB(0xb4, LEGACY_KBC_PORT); +} + +void it85xx_exit_scratch_rom() +{ + if (it85xx_scratch_rom_reenter <= 0) return; + it85xx_scratch_rom_reenter = 0; + OUTB(0xfe, LEGACY_KBC_PORT); +} + +int it85xx_spi_common_init(void) +{ + chipaddr base; + + msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__, + superio.vendor); + if (superio.vendor != SUPERIO_VENDOR_ITE) + return 1; + +#ifdef LPC_IO + /* Get LPCPNP of SHM. That's big-endian */ + sio_write(superio.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */ + shm_io_base = (sio_read(superio.port, SHM_IO_BAD0) << 8) + + sio_read(superio.port, SHM_IO_BAD1); + msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__, + shm_io_base); + + /* These pointers are not used directly. They will be send to EC's + * register for indirect access. */ + base = 0xFFFFF000; + ce_high = ((unsigned char*)base) + 0xE00; /* 0xFFFFFE00 */ + ce_low = ((unsigned char*)base) + 0xD00; /* 0xFFFFFD00 */ + + /* pre-set indirect-access registers since in most of cases they are + * 0xFFFFxx00. */ + INDIRECT_A0(shm_io_base, base & 0xFF); + INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF); + INDIRECT_A3(shm_io_base, (base >> 24)); +#endif +#ifdef LPC_MEMORY + base = (chipaddr)programmer_map_flash_region("flash base", 0xFFFFF000, + 0x1000); + msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, + (unsigned int)base); + ce_high = (unsigned char*)(base + 0xE00); /* 0xFFFFFE00 */ + ce_low = (unsigned char*)(base + 0xD00); /* 0xFFFFFD00 */ +#endif + + /* Set this as spi controller. */ + spi_controller = SPI_CONTROLLER_IT85XX; + + return 0; +} + +/* Called by programmer_entry .init */ +int it85xx_spi_init(void) +{ + int ret; + + get_io_perms(); + /* Probe for the Super I/O chip and fill global struct superio. */ + probe_superio(); + ret = it85xx_spi_common_init(); + if (!ret) { + buses_supported = CHIP_BUSTYPE_SPI; + } else { + buses_supported = CHIP_BUSTYPE_NONE; + } + return ret; +} + +/* Called by internal_init() */ +int it85xx_probe_spi_flash(const char *name) +{ + int ret; + + if (!(buses_supported & CHIP_BUSTYPE_FWH)) { + msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); + return 1; + } + ret = it85xx_spi_common_init(); + msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); + if (!ret) { + msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__, + buses_supported); + if (buses_supported & CHIP_BUSTYPE_FWH) + msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); + buses_supported |= CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + } + return ret; +} + +int it85xx_shutdown(void) +{ + msg_pdbg("%s():%d\n", __func__, __LINE__); + it85xx_exit_scratch_rom(); + return 0; +} + +/* According to ITE 8502 document, the procedure to follow mode is following: + * 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high) + * 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI + * with data) + * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get + * data from MISO) + */ +int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + int i; + + it85xx_enter_scratch_rom(); + /* exit scratch rom ONLY when programmer shuts down. Otherwise, the + * temporary flash state may halt EC. */ + +#ifdef LPC_IO + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); + INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); +#endif +#ifdef LPC_MEMORY + *ce_high = 0; +#endif + for (i = 0; i < writecnt; ++i) { +#ifdef LPC_IO + INDIRECT_WRITE(shm_io_base, writearr[i]); +#endif +#ifdef LPC_MEMORY + *ce_low = writearr[i]; +#endif + } + for (i = 0; i < readcnt; ++i) { +#ifdef LPC_IO + readarr[i] = INDIRECT_READ(shm_io_base); +#endif +#ifdef LPC_MEMORY + readarr[i] = *ce_low; +#endif + } + return 0; +} + +#endif

1 0

flashrom -V for N61PA-M2S
by Igor Murzich 22 Feb '11

22 Feb '11

info about chipset: DMI string system-manufacturer: "BIOSTAR Group" DMI string system-product-name: "N61PA-M2S" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "BIOSTAR Group" DMI string baseboard-product-name: "N61PA-M2S" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" -- Игорь. ICQ: 97236673 Home / 278240848 Work MailTo:IMurzich_NoSpam At GMail.com Не восхищайся прошлогодним небом, - Не возвращайся - где был рай когда-то, И брось дурить - иди туда, где не был! (С) Высоцкий "Цунами"

1 0

GIGABYTE GA-M565-S3: flashrom -Vr/VE/Vw
by Thomas Schneider 21 Feb '11

21 Feb '11

root@nataschaspc:~/work/flashrom-0.9.3# ./flashrom -Vr ~/bios > flashromVr root@nataschaspc:~/work/flashrom-0.9.3# ./flashrom -VE > flashromVE root@nataschaspc:~/work/flashrom-0.9.3# ./flashrom -Vw ~/bios > flashromVw

1 0

GIGABYTE GA-M565-S3: flashrom -V
by Thomas Schneider 21 Feb '11

21 Feb '11

flashrom v0.9.3-r1205 on Linux 2.6.32-28-generic (i686), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 2 usecs, 668M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 999 us, 10000 myus = 9996 us, 8 myus = 9 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." DMI string system-product-name: "M56S-S3" DMI string system-version: " " DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." DMI string baseboard-product-name: "GA-M56S-S3" DMI string baseboard-version: "x.x" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8716. Found chipset "NVIDIA MCP65", enabling flash write... chipset PCI ID is 10de:0441, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:0446 at 00:01:1 MCP SPI BAR is at 0xfec80000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled Serial flash pin 29 Serial flash port 0x0820 Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L05PU, 64 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L10PT, 128 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L10PU, 128 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L20PT, 256 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L20PU, 256 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L40PT, 512 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L40PU, 512 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L80P, 1024 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L16PT, 2048 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L16PU, 2048 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L4005" (512 KB, SPI) at physical address 0xfff80000. Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x12 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x12, id2 0x12 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x12 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040(F)B, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040(F)C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: 4 byte RDID not supported on this SPI controller Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xc2, id2 0x12 === This flash part has status UNTESTED for operations: ERASE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified.

1 0

Re: [flashrom] MS-7250
by Idwer Vollering 20 Feb '11

20 Feb '11

2011/2/20 Raymond Hoogerdijk <raymond(a)hoogerdijk.org>: > Hello, > > I would like to flash my BIOS with Flashrom. However I noticed that for the chip on my mainboard write has a '?'. Will it not work then? > > I have enclosed the -Vr output for more information about my system. flashrom v0.9.3-r1250 on Linux 2.6.18-194.32.1.el5 (x86_64), built with > libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48), little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 2 usecs, 1196M loops per > second, 10 myus = 12 us, 100 myus = 101 us, 1000 myus = 997 us, 10000 myus = > 10143 us, 8 myus = 10 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "MSI" > DMI string system-product-name: "MS-7250" > DMI string system-version: "2.1" > DMI string baseboard-manufacturer: "MSI" > DMI string baseboard-product-name: "MS-7250" > DMI string baseboard-version: "2.1" > DMI string chassis-type: "Desktop" > Found chipset "NVIDIA MCP55", enabling flash write... chipset PCI ID is > 10de:0360, OK. > This chipset supports the following protocols: Non-SPI. > <snip> > Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e > Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address > 0xfff80000. > Works for me (I've just sent a patch too): flashrom v0.9.3-r1261 on Linux 2.6.37-ARCH (i686), built with libpci 3.1.7, GCC 4.5.2 20110127 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: FWH. Disabling flash write protection for board "ASUS P4P800-VM"... OK. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling checks. Erasing and writing flash chip... Done. Verifying flash... VERIFIED. > <snip> > === > This flash part has status UNTESTED for operations: WRITE > The test status of this chip may have been updated in the latest > development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above > operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, > -Vr, > -Vw, -VE), and mention which mainboard or programmer you tested. > Please mention your board in the subject line. Thanks for your help! > Reading flash... done. > Restoring PCI config space for 00:01:0 reg 0x6d > Restoring PCI config space for 00:01:0 reg 0x90 > Restoring PCI config space for 00:01:0 reg 0x8c > Restoring PCI config space for 00:01:0 reg 0x88 > > > Thanks for your help! > > Kind regards, > > Raymond > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

1 0

MS-7250
by Raymond Hoogerdijk 20 Feb '11

20 Feb '11

Hello, I would like to flash my BIOS with Flashrom. However I noticed that for the chip on my mainboard write has a '?'. Will it not work then? I have enclosed the -Vr output for more information about my system. Thanks for your help! Kind regards, Raymond

1 0

oops ! - everything went fine, until...
by Jules Gosnell 20 Feb '11

20 Feb '11

late night session... feeling a little cavalier with some old hardware... ran 'flashrom' - seemed to be happy... made a backup of my existing bios - still happy... wrote my new bios - flashrom reported job done no problems...still happy... I reboot, kicking myself for hours of messing around with various versions of windows trying and failing to update my bios that way... suddenly - box NOT happy :-( three short beeps, pause, three short beeps... I power down, power up - three short beeps repeating - argh !!! M/B is/was? a Tyan Thunder, with a pair of old opterons on it. New bios version, carefully hunted down online was - 2885V208.rom. flashrom worked flawlessly, so no doubt this is pilot error - most likely I have installed the wrong image. Do I chuck the m/b and get another on eBay, or is it salvageable ? I think I saw someone online selling BIOS chips - maybe, if I knew which chip it was, I could unplug mine and plug a new one in - if it's not all soldered down... I'm afraid I don't know much about BIOSes. They are not something I play with every day. I was just trying to persuade my old box to see a new 2TB SATA drive so it could retire into my loft to run mythtvbackend... any help appreciated, regards. Jules

2 4

ABIT AN8-SLI
by Gerad Munsch 19 Feb '11

19 Feb '11

Hello, This is unforgiven512 from #flashrom on irc.freenode.net. My board is an ABIT AN8-SLI. Here are the links with the relevant information for my board: http://paste.flashrom.org/view.php?id=357 < flashrom http://paste.flashrom.org/view.php?id=358 < lspci http://paste.flashrom.org/view.php?id=357 < superiotool If you require anymore information, please let me know. Thanks, Gerad Munsch

2 1

As instructed by flashrom_bot
by Schnittchen 18 Feb '11

18 Feb '11

See pastie links. Hope it helps. Keep up the good work! Schnittchen Your paste can be seen at http://paste.flashrom.org/view.php?id=355 Your upload can be seen at http://paste.flashrom.org/view.php?id=356

2 1

Re: [flashrom] [coreboot] Tester devices [was: QA contribution]
by Carl-Daniel Hailfinger 17 Feb '11

17 Feb '11

Hi Juhana, I've added the flashrom mailing list to CC. Auf 12.02.2011 19:55, Juhana Helovuo schrieb: > Now there is more progress. After some building, coding, and debugging > I have the tester sort-of-working. > > The first version of the hardware works. > > In this image you can see the tester plugged into an Asus mainboard: > > http://alpskari.asiantuntijat.org/~juhe/in-system-flasher/DSC08430.jpg > > Today I successfully used this setup to reflash the mainboard from the > host PC via flashrom. > > The USB cable goes to a host computer, which is running a modified > flashrom program. The flashrom is extended with a serprog_spi module, > which can transfer SPI over the serprog protocol, and additionally > toggle SPI bus multiplexer between the MCU and mainboard at the > beginning and end of programming. > > The tester hardware has the following features: > > * Tester can access the ROM also when disconnected from the target > mainboard. > > The work is still quite incomplete: > > * Currently there is no tester firmware that could operate both the > SPI and RS-232. The main problem is that the AT90USB162 > microcontroller supports only up to five USB endpoints (including > default control EP). I do not know if it is possible to implement two > USB CDC class virtual serial ports with less than seven EPs. With two > serial ports, one could represent the RS-232 interface, and other be > used to control the programmer without writing any custom USB drivers. > > This could be solved either in software by writing a custom USB driver > for both the tester and the host, or in hardware by replacing the > microcontroller with a more capable model. If anyone on the list can > suggest any easier solutions, I'd be glad to hear about them. > > * The handling of SPI ROM is horribly slow. Programming and verifying > 1 MByte ROM takes about half an hour. The main suspect is nonexistent > USB data buffering in the tester firmware. There are a few tricks we could use to speed up SPI programming with your hardware. flashrom already supports the Dediprog SF100 USB-based SPI programmer, and that works well. Maybe we could use a similar communication protocol, and/or use a serprog-like protocol directly on top of libusb without the need of serial port emulation. The serial port emulation is probably the biggest reason why anything is slow. If you tell me about the design constraints of your device, I can probably come up with a flashrom driver which can reflash an 1 MByte ROM in ~5 minutes or so. That will require some cooperation from your device, but should be doable with ~270 bytes of RAM. Even with ~140 bytes of RAM we should be able to get some decent performance. As long as we can optimize the protocol, it should be possible to get acceptable performance even with only 50 bytes of RAM, but generally more RAM will give you better performance. Side note: I think there once was a SPI-serprog design on the flashrom mailing list, but I can't find it right now. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[PATCH] Support 64-bit MEM BARs
by Carl-Daniel Hailfinger 15 Feb '11

15 Feb '11

Support 64-bit MEM BARs wherever possible. Add more sanity checks for BARs and abort if resources are unreachable. Undecoded resources are reported, but flashrom will proceed anyway just in case the BIOS screwed up the configuration. (The empty CardBus handler is intentional, according to the spec no BARs in PCI config space are used by CardBus.) Verbose logs (and tests) with PCI-based external programmers would be highly appreciated. I spotted this while working on a driver for a PCIe-based SSD which has 64-bit capable MEM BARs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-64bit_membar/pcidev.c =================================================================== --- flashrom-64bit_membar/pcidev.c (Revision 1257) +++ flashrom-64bit_membar/pcidev.c (Arbeitskopie) @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2010, 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,43 +28,151 @@ struct pci_access *pacc; struct pci_dev *pcidev_dev = NULL; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, +enum pci_bartype { + TYPE_MEMBAR, + TYPE_IOBAR, + TYPE_ROMBAR, + TYPE_UNKNOWN +}; + +uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs) { int i; - /* FIXME: 64 bit memory BARs need a 64 bit addr. */ - uint32_t addr; + uint64_t addr; + uint32_t upperaddr; + uint8_t headertype; + uint16_t supported_cycles; + enum pci_bartype bartype = TYPE_UNKNOWN; for (i = 0; devs[i].device_name != NULL; i++) { if (dev->device_id != devs[i].device_id) continue; + msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", + devs[i].vendor_name, devs[i].device_name, + dev->vendor_id, dev->device_id, dev->bus, dev->dev, + dev->func); + + headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; + msg_pspew("PCI header type 0x%02x\n", headertype); + /* * Don't use dev->base_addr[x] (as value for 'bar'), won't * work on older libpci. */ addr = pci_read_long(dev, bar); - - msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", - devs[i].vendor_name, devs[i].device_name, - dev->vendor_id, dev->device_id, dev->bus, dev->dev, - dev->func); - msg_pdbg("Requested BAR is %s", (addr & 0x1) ? "IO" : "MEM"); - if (addr & 0x1) { - /* Mask off IO space indicator and reserved bit. */ - msg_pdbg("\n"); - addr &= ~0x3; - } else { + + /* Sanity checks. */ + switch (headertype) { + case PCI_HEADER_TYPE_NORMAL: + switch (bar) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + case PCI_BASE_ADDRESS_4: + case PCI_BASE_ADDRESS_5: + if ((addr & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_IO) + bartype = TYPE_IOBAR; + else + bartype = TYPE_MEMBAR; + break; + case PCI_ROM_ADDRESS: + bartype = TYPE_ROMBAR; + break; + } + break; + case PCI_HEADER_TYPE_BRIDGE: + switch (bar) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + if ((addr & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_IO) + bartype = TYPE_IOBAR; + else + bartype = TYPE_MEMBAR; + break; + case PCI_ROM_ADDRESS1: + bartype = TYPE_ROMBAR; + break; + } + break; + case PCI_HEADER_TYPE_CARDBUS: + break; + default: + msg_perr("Unknown PCI header type 0x%02x, BAR type " + "cannot be determined reliably.\n", headertype); + break; + } + + supported_cycles = pci_read_word(dev, PCI_COMMAND); + + msg_pdbg("Requested BAR is "); + switch (bartype) { + case TYPE_MEMBAR: + msg_pdbg("MEM"); + if (!(supported_cycles & PCI_COMMAND_MEMORY)) { + msg_perr("MEM BAR access requested, but device " + "has MEM space accesses disabled.\n"); + /* TODO: Abort here? */ + } msg_pdbg(", %sbit, %sprefetchable\n", ((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"), (addr & 0x8) ? "" : "not "); - /* Mask off Mem space indicator, 32/64bit type indicator - * and Prefetchable indicator. - */ - addr &= ~0xf; + if ((addr & 0x6) == 0x4) { + /* The spec says that a 64-bit register consumes + * two subsequent dword locations. + */ + upperaddr = pci_read_long(dev, bar + 4); + if (upperaddr != 0x00000000) { + /* Fun! A real 64-bit resource. */ + if (sizeof(uintptr_t) != sizeof(uint64_t)) { + msg_perr("BAR unreachable!"); + /* TODO: Really abort here? If + * multiple PCI devices match, + * we might never tell the user + * about the other devices. + */ + return 0; + } + addr |= (uint64_t)upperaddr << 32; + } + } + addr &= PCI_BASE_ADDRESS_MEM_MASK; + break; + case TYPE_IOBAR: + msg_pdbg("I/O\n"); +#if __FLASHROM_HAVE_OUTB__ + if (!(supported_cycles & PCI_COMMAND_IO)) { + msg_perr("I/O BAR access requested, but device " + "has I/O space accesses disabled.\n"); + /* TODO: Abort here? */ + } +#else + msg_perr("I/O BAR access requested, but flashrom does " + "not support I/O BAR access on this platform " + "(yet).\n"); +#endif + addr &= PCI_BASE_ADDRESS_IO_MASK; + break; + case TYPE_ROMBAR: + msg_pdbg("ROM\n"); + /* Not sure if this check is needed. */ + if (!(supported_cycles & PCI_COMMAND_MEMORY)) { + msg_perr("MEM BAR access requested, but device " + "has MEM space accesses disabled.\n"); + /* TODO: Abort here? */ + } + addr &= PCI_ROM_ADDRESS_MASK; + break; + case TYPE_UNKNOWN: + msg_perr("BAR type unknown, please report a bug at " + "flashrom(a)flashrom.org\n"); } - + if (devs[i].status == NT) { msg_pinfo("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" @@ -73,13 +182,13 @@ "your help!\n===\n"); } - return addr; + return (uintptr_t)addr; } return 0; } -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, +uintptr_t pcidev_init(uint16_t vendor_id, int bar, const struct pcidev_status *devs) { struct pci_dev *dev; @@ -87,7 +196,7 @@ char *pcidev_bdf; char *msg = NULL; int found = 0; - uint32_t addr = 0, curaddr = 0; + uintptr_t addr = 0, curaddr = 0; pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ Index: flashrom-64bit_membar/programmer.h =================================================================== --- flashrom-64bit_membar/programmer.h (Revision 1257) +++ flashrom-64bit_membar/programmer.h (Arbeitskopie) @@ -216,8 +216,8 @@ const char *vendor_name; const char *device_name; }; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs); +uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs); +uintptr_t pcidev_init(uint16_t vendor_id, int bar, const struct pcidev_status *devs); /* rpci_write_* are reversible writes. The original PCI config space register * contents will be restored on shutdown. */ -- http://www.hailfinger.org/

2 2

[commit] r1261 - trunk
by repository service 15 Feb '11

15 Feb '11

Author: hailfinger Date: Tue Feb 15 23:44:27 2011 New Revision: 1261 URL: http://flashrom.org/trac/flashrom/changeset/1261 Log: Support 64-bit MEM BARs wherever possible. Add more sanity checks for BARs and abort if resources are unreachable. Undecoded resources are reported, but flashrom will proceed anyway just in case the BIOS screwed up the configuration. (The empty CardBus handler is intentional, according to the spec no BARs in PCI config space are used by CardBus.) Found while working on a driver for the Angelbird PCIe-based SSD which has 64-bit capable MEM BARs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/pcidev.c trunk/programmer.h Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Sat Feb 5 13:11:17 2011 (r1260) +++ trunk/pcidev.c Tue Feb 15 23:44:27 2011 (r1261) @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2010, 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,43 +28,151 @@ struct pci_access *pacc; struct pci_dev *pcidev_dev = NULL; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, +enum pci_bartype { + TYPE_MEMBAR, + TYPE_IOBAR, + TYPE_ROMBAR, + TYPE_UNKNOWN +}; + +uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs) { int i; - /* FIXME: 64 bit memory BARs need a 64 bit addr. */ - uint32_t addr; + uint64_t addr; + uint32_t upperaddr; + uint8_t headertype; + uint16_t supported_cycles; + enum pci_bartype bartype = TYPE_UNKNOWN; for (i = 0; devs[i].device_name != NULL; i++) { if (dev->device_id != devs[i].device_id) continue; + msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", + devs[i].vendor_name, devs[i].device_name, + dev->vendor_id, dev->device_id, dev->bus, dev->dev, + dev->func); + + headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; + msg_pspew("PCI header type 0x%02x\n", headertype); + /* * Don't use dev->base_addr[x] (as value for 'bar'), won't * work on older libpci. */ addr = pci_read_long(dev, bar); - - msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", - devs[i].vendor_name, devs[i].device_name, - dev->vendor_id, dev->device_id, dev->bus, dev->dev, - dev->func); - msg_pdbg("Requested BAR is %s", (addr & 0x1) ? "IO" : "MEM"); - if (addr & 0x1) { - /* Mask off IO space indicator and reserved bit. */ - msg_pdbg("\n"); - addr &= ~0x3; - } else { + + /* Sanity checks. */ + switch (headertype) { + case PCI_HEADER_TYPE_NORMAL: + switch (bar) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + case PCI_BASE_ADDRESS_4: + case PCI_BASE_ADDRESS_5: + if ((addr & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_IO) + bartype = TYPE_IOBAR; + else + bartype = TYPE_MEMBAR; + break; + case PCI_ROM_ADDRESS: + bartype = TYPE_ROMBAR; + break; + } + break; + case PCI_HEADER_TYPE_BRIDGE: + switch (bar) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + if ((addr & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_IO) + bartype = TYPE_IOBAR; + else + bartype = TYPE_MEMBAR; + break; + case PCI_ROM_ADDRESS1: + bartype = TYPE_ROMBAR; + break; + } + break; + case PCI_HEADER_TYPE_CARDBUS: + break; + default: + msg_perr("Unknown PCI header type 0x%02x, BAR type " + "cannot be determined reliably.\n", headertype); + break; + } + + supported_cycles = pci_read_word(dev, PCI_COMMAND); + + msg_pdbg("Requested BAR is "); + switch (bartype) { + case TYPE_MEMBAR: + msg_pdbg("MEM"); + if (!(supported_cycles & PCI_COMMAND_MEMORY)) { + msg_perr("MEM BAR access requested, but device " + "has MEM space accesses disabled.\n"); + /* TODO: Abort here? */ + } msg_pdbg(", %sbit, %sprefetchable\n", ((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"), (addr & 0x8) ? "" : "not "); - /* Mask off Mem space indicator, 32/64bit type indicator - * and Prefetchable indicator. - */ - addr &= ~0xf; + if ((addr & 0x6) == 0x4) { + /* The spec says that a 64-bit register consumes + * two subsequent dword locations. + */ + upperaddr = pci_read_long(dev, bar + 4); + if (upperaddr != 0x00000000) { + /* Fun! A real 64-bit resource. */ + if (sizeof(uintptr_t) != sizeof(uint64_t)) { + msg_perr("BAR unreachable!"); + /* TODO: Really abort here? If + * multiple PCI devices match, + * we might never tell the user + * about the other devices. + */ + return 0; + } + addr |= (uint64_t)upperaddr << 32; + } + } + addr &= PCI_BASE_ADDRESS_MEM_MASK; + break; + case TYPE_IOBAR: + msg_pdbg("I/O\n"); +#if __FLASHROM_HAVE_OUTB__ + if (!(supported_cycles & PCI_COMMAND_IO)) { + msg_perr("I/O BAR access requested, but device " + "has I/O space accesses disabled.\n"); + /* TODO: Abort here? */ + } +#else + msg_perr("I/O BAR access requested, but flashrom does " + "not support I/O BAR access on this platform " + "(yet).\n"); +#endif + addr &= PCI_BASE_ADDRESS_IO_MASK; + break; + case TYPE_ROMBAR: + msg_pdbg("ROM\n"); + /* Not sure if this check is needed. */ + if (!(supported_cycles & PCI_COMMAND_MEMORY)) { + msg_perr("MEM BAR access requested, but device " + "has MEM space accesses disabled.\n"); + /* TODO: Abort here? */ + } + addr &= PCI_ROM_ADDRESS_MASK; + break; + case TYPE_UNKNOWN: + msg_perr("BAR type unknown, please report a bug at " + "flashrom(a)flashrom.org\n"); } - + if (devs[i].status == NT) { msg_pinfo("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" @@ -73,13 +182,13 @@ "your help!\n===\n"); } - return addr; + return (uintptr_t)addr; } return 0; } -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, +uintptr_t pcidev_init(uint16_t vendor_id, int bar, const struct pcidev_status *devs) { struct pci_dev *dev; @@ -87,7 +196,7 @@ char *pcidev_bdf; char *msg = NULL; int found = 0; - uint32_t addr = 0, curaddr = 0; + uintptr_t addr = 0, curaddr = 0; pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Feb 5 13:11:17 2011 (r1260) +++ trunk/programmer.h Tue Feb 15 23:44:27 2011 (r1261) @@ -219,8 +219,8 @@ const char *vendor_name; const char *device_name; }; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs); +uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs); +uintptr_t pcidev_init(uint16_t vendor_id, int bar, const struct pcidev_status *devs); /* rpci_write_* are reversible writes. The original PCI config space register * contents will be restored on shutdown. */

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Intel NIC flashrom fail
by Антон Кочков 15 Feb '11

15 Feb '11

flashrom -r INTEL.ROM -p nicintel_spi:pci=02:0B.0 -VV flashrom v0.9.3-r1250 on MS-DOS 8 (i786), built with libpci 3.1.5, GCC 4.3.2, little endian flashrom is free software, get the source code at flashrom.org Calibrating delay loop... OS timer resolution is 50000 usecs, 1589M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 0 us, 10000 myus = 0 us, 200000 myus = 220000 us, OK. Initializing nicintel_spi programmer ERROR: No supported PCI device found lspci output: http://paste.flashrom.org/view.php?id=347 vendor flash tool: http://paste.flashrom.org/view.php?id=348 Best regards, Anton Kochkov.

2 1

Read/Fast Read chip status sheet (re-send)
by Steven Zakulec 12 Feb '11

12 Feb '11

(I'm re-sending this now because carldani asked if I could re-send it after FOSDEM). Hi, here's a copy of the sheet I created covering most of the chips (it's the same chip list as in my previous list- the form factor & voltage one). If I couldn't figure out whether the chip had read/fast read, I left it blank. Otherwise, I filled in on the sheet the instruction code, any notes, and whether the mode(s) on the datasheet were the ones Flashrom wanted.

3 3

mx25l8005 write report
by Alec Wright 12 Feb '11

12 Feb '11

Apparently it's been marked as untested again

1 0

EVGA nForce 780i Revised
by Brandon Dowdy 10 Feb '11

10 Feb '11

Manufacturer: EVGA Model: nForce 780i Super I/O: Winbond W83627DHG Flash chip: SST SST49LF080A Southbridge: NVIDIA MCP55 I don't know what the northbridge for the board is, so that's one more thing to find before coreboot fully supports it. acpidump output included. P.S. Sorry if the email is too big like the last one. And also, The only difference is that the logs are updated and some more logs are added.

1 0

Re: [flashrom] Vortex86 based machines
by Антон Кочков 10 Feb '11

10 Feb '11

Full developer manual and additional information available here http://www.dmp.com.tw/tech/vortex86dx/ 2011/2/10 Антон Кочков <anton.kochkov(a)gmail.com>: > Here an suggestion of some cheap nettop. > It use SPI flash and winbond super i/o. > Attached log of proprietary utility and documentation (software > reference manual) > > original spiflash utility (for DOS) can be downloaded here > http://rghost.net/4282595 > > -- > Best regards, > Anton Kochkov. > -- Best regards, Anton Kochkov.

1 0

FAILED: Asus P5NSLI
by Alvaro Aguilera 06 Feb '11

06 Feb '11

Hello, I'm trying to update the BIOS of a P5NSLI board but the procedure failed. Any hints on how to correct this? Thanks, Alvaro.

2 2

Flashrom Winbond W25Q64 Erase and write support works
by Юшаков Дмитрий 06 Feb '11

06 Feb '11

Hello, flashrom team. I just flashed on my P5Q deluxe motherboard with ICH10R SB EPPROM from my new ASRock p67 extreme4 board, it's Winbond W25Q64. In your support table it's '?' for erase and write, so it works greatly. Thank you for your util. But some binaries for dos can save time for users and increase popularity for you utility. That was too hard for me to install latest version on Ubuntu live USB. Best regards!

1 0

[PATCH] Add support for AMD Am29LV00*
by Carl-Daniel Hailfinger 05 Feb '11

05 Feb '11

Add support for AMD Am29LV001BB, Am29LV001BT, Am29LV002BB, Am29LV002BT, Am29LV004BB, Am29LV004BT, Am29LV008BB, Am29LV008BT Mark, could you please update a clean tree to latest flashrom (which has the Angelbird SSD support) and apply this patch on top? It should recognize your flash chip, and allow read/write/erase without the need to specify -f. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-am29lv00x/flashchips.c =================================================================== --- flashrom-am29lv00x/flashchips.c (Revision 1258) +++ flashrom-am29lv00x/flashchips.c (Arbeitskopie) @@ -224,6 +224,252 @@ { .vendor = "AMD", + .name = "Am29LV001BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV001BB, + .total_size = 128, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 1}, + {4 * 1024, 2}, + {16 * 1024, 7}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV001BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV001BT, + .total_size = 128, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 7}, + {4 * 1024, 2}, + {8 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV002BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV002BB, + .total_size = 256, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 3}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV002BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV002BT, + .total_size = 256, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV004BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV004BB, + .total_size = 512, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 7}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV004BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV004BT, + .total_size = 512, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 7}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV008BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV008BB, + .total_size = 1024, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 15}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV008BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV008BT, + .total_size = 1024, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 15}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", .name = "Am29LV040B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, Index: flashrom-am29lv00x/flashchips.h =================================================================== --- flashrom-am29lv00x/flashchips.h (Revision 1258) +++ flashrom-am29lv00x/flashchips.h (Arbeitskopie) @@ -70,6 +70,8 @@ #define AMD_AM29F400BT 0x23 #define AMD_AM29F800BB 0x58 #define AMD_AM29F800BT 0xD6 +#define AMD_AM29LV001BB 0x6D +#define AMD_AM29LV001BT 0xED #define AMD_AM29LV002BB 0xC2 #define AMD_AM29LV002BT 0x40 #define AMD_AM29LV004BB 0xB6 -- http://www.hailfinger.org/

2 2

[commit] r1260 - trunk
by repository service 05 Feb '11

05 Feb '11

Author: hailfinger Date: Sat Feb 5 13:11:17 2011 New Revision: 1260 URL: http://flashrom.org/trac/flashrom/changeset/1260 Log: Add support for AMD Am29LV001BB, Am29LV001BT, Am29LV002BB, Am29LV002BT, Am29LV004BB, Am29LV004BT, Am29LV008BB, Am29LV008BT Thanks to Mark Pustjens for testing the Am29LV001BB. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Fri Feb 4 23:52:04 2011 (r1259) +++ trunk/flashchips.c Sat Feb 5 13:11:17 2011 (r1260) @@ -224,6 +224,252 @@ { .vendor = "AMD", + .name = "Am29LV001BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV001BB, + .total_size = 128, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 1}, + {4 * 1024, 2}, + {16 * 1024, 7}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV001BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV001BT, + .total_size = 128, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 7}, + {4 * 1024, 2}, + {8 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV002BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV002BB, + .total_size = 256, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 3}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV002BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV002BT, + .total_size = 256, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV004BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV004BB, + .total_size = 512, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 7}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV004BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV004BT, + .total_size = 512, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 7}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV008BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV008BB, + .total_size = 1024, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 15}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV008BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV008BT, + .total_size = 1024, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 15}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", .name = "Am29LV040B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Fri Feb 4 23:52:04 2011 (r1259) +++ trunk/flashchips.h Sat Feb 5 13:11:17 2011 (r1260) @@ -70,6 +70,8 @@ #define AMD_AM29F400BT 0x23 #define AMD_AM29F800BB 0x58 #define AMD_AM29F800BT 0xD6 +#define AMD_AM29LV001BB 0x6D +#define AMD_AM29LV001BT 0xED #define AMD_AM29LV002BB 0xC2 #define AMD_AM29LV002BT 0x40 #define AMD_AM29LV004BB 0xB6

1 0

Giada N3, flashrom -Vr
by Tristan Plumb 05 Feb '11

05 Feb '11

Note, I have a few of these and soldering skills, and will happily test writing to the flash if so desired. The dumped rom is valid. flashrom v0.9.3-r1258 on Linux 2.6.27.8 (i686), built with libpci 2.2.10, GCC 4.2.4, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 3 usecs, 798M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 999 us, 10000 myus = 10021 us, 12 myus = 14 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "To Be Filled By O.E.M." DMI string system-product-name: "To Be Filled By O.E.M." DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: "ASL" DMI string baseboard-product-name: "MCP7A-ION" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP79", enabling flash write... chipset PCI ID is 10de:0aad, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI Found SMBus device 10de:0aa2 at 00:03:2 MCP SPI BAR is at 0xfae80000 SPI control is 0xc052, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL004A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL032A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL064A, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF010.REMS, 128 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Chip status register is 00 Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000. Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V040FB, 512 KB: skipped. Probing for Winbond W39V040FC, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xef, id2 0x13 === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading flash... done.

1 0

[commit] r1259 - trunk
by repository service 04 Feb '11

04 Feb '11

Author: hailfinger Date: Fri Feb 4 23:52:04 2011 New Revision: 1259 URL: http://flashrom.org/trac/flashrom/changeset/1259 Log: Improve debugging for unaligned erase in the flash chip emulator. Fix out-of-bounds access for chip erase in the flash chip emulator. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/dummyflasher.c Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Fri Feb 4 22:37:59 2011 (r1258) +++ trunk/dummyflasher.c Fri Feb 4 23:52:04 2011 (r1259) @@ -395,7 +395,7 @@ } offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; if (offs & (emu_jedec_se_size - 1)) - msg_pdbg("Unaligned SECTOR ERASE 0x20\n"); + msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs); offs &= ~(emu_jedec_se_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_se_size); break; @@ -412,7 +412,7 @@ } offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; if (offs & (emu_jedec_be_52_size - 1)) - msg_pdbg("Unaligned BLOCK ERASE 0x52\n"); + msg_pdbg("Unaligned BLOCK ERASE 0x52: 0x%x\n", offs); offs &= ~(emu_jedec_be_52_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_be_52_size); break; @@ -429,7 +429,7 @@ } offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; if (offs & (emu_jedec_be_d8_size - 1)) - msg_pdbg("Unaligned BLOCK ERASE 0xd8\n"); + msg_pdbg("Unaligned BLOCK ERASE 0xd8: 0x%x\n", offs); offs &= ~(emu_jedec_be_d8_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_be_d8_size); break; @@ -444,12 +444,9 @@ msg_perr("CHIP ERASE 0x60 insize invalid!\n"); return 1; } - offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; - if (offs & (emu_jedec_ce_60_size - 1)) - msg_pdbg("Unaligned CHIP ERASE 0x60\n"); - offs &= ~(emu_jedec_ce_60_size - 1); + /* JEDEC_CE_60_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_60_size is emu_chip_size. */ - memset(flashchip_contents + offs, 0xff, emu_jedec_ce_60_size); + memset(flashchip_contents, 0xff, emu_jedec_ce_60_size); break; case JEDEC_CE_C7: if (!emu_jedec_ce_c7_size) @@ -462,10 +459,7 @@ msg_perr("CHIP ERASE 0xc7 insize invalid!\n"); return 1; } - offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; - if (offs & (emu_jedec_ce_c7_size - 1)) - msg_pdbg("Unaligned CHIP ERASE 0xc7\n"); - offs &= ~(emu_jedec_ce_c7_size - 1); + /* JEDEC_CE_C7_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_c7_size is emu_chip_size. */ memset(flashchip_contents, 0xff, emu_jedec_ce_c7_size); break;

1 0

[PATCH] Support for Angelbird Wings PCIe SSD, Marvell 88SX7042
by Carl-Daniel Hailfinger 04 Feb '11

04 Feb '11

Support for Angelbird Wings PCIe SSD (solid-state drive). It uses a Marvell 88SX7042 SATA controller internally which has access to a separate flash chip hosting the option ROM. Thanks to Angelbird Ltd for sponsoring development of this driver! I expect the code to work for that SATA controller even if it is not part of the Angelbird SSD. Note: The controller has 64-bit BARs which may be mapped outside the 32-bit (4 GB) address space. A separate patch has been sent to fix that code. Tested on hardware. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-marvell/satamv.c =================================================================== --- flashrom-marvell/satamv.c (Revision 0) +++ flashrom-marvell/satamv.c (Revision 0) @@ -0,0 +1,183 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010,2011 Carl-Daniel Hailfinger + * Written by Carl-Daniel Hailfinger for Angelbird Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Datasheets are not public (yet?) */ + +#include <stdlib.h> +#include "flash.h" +#include "programmer.h" + +uint8_t *mv_bar; +uint16_t mv_iobar; + +const struct pcidev_status satas_mv[] = { + /* 88SX6041 and 88SX6042 are the same according to the datasheet. */ + {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"}, + + {}, +}; + +#define NVRAM_PARAM 0x1045c +#define FLASH_PARAM 0x1046c +#define EXPANSION_ROM_BAR_CONTROL 0x00d2c +#define PCI_BAR2_CONTROL 0x00c08 +#define GPIO_PORT_CONTROL 0x104f0 + +/* + * Random notes: + * FCE# Flash Chip Enable + * FWE# Flash Write Enable + * FOE# Flash Output Enable + * FALE[1:0] Flash Address Latch Enable + * FAD[7:0] Flash Multiplexed Address/Data Bus + * FA[2:0] Flash Address Low + * + * GPIO[15,2] GPIO Port Mode + * GPIO[4:3] Flash Size + * + * 0xd2c Expansion ROM BAR Control + * 0xc08 PCI BAR2 (Flash/NVRAM) Control + * 0x1046c Flash Parameters + */ +int satamv_init(void) +{ + uintptr_t addr; + uint32_t tmp; + + get_io_perms(); + + /* BAR0 has all internal registers memory mapped. */ + /* No need to check for errors, pcidev_init() will not return in case + * of errors. + */ + addr = pcidev_init(0x11ab, PCI_BASE_ADDRESS_0, satas_mv); + + mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); + if (mv_bar == ERROR_PTR) + goto error_out; + + tmp = pci_mmio_readl(mv_bar + FLASH_PARAM); + msg_pspew("Flash Parameters:\n"); + msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7); + msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf); + msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf); + msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7); + msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7); + msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7); + msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3); + msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1); + msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1); + msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1); + msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1); + msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1); + msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1); + msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf); + + tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL); + msg_pspew("Expansion ROM BAR Control:\n"); + msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7); + + /* Enable BAR2 mapping to flash */ + tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL); + msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n"); + msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1); + msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f); + msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7); + tmp &= 0xffffffc0; + tmp |= 0x0000001f; + /* FIXME: This needs to be an auto-reversible write. */ + pci_mmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL); + + /* Enable flash: GPIO Port Control Register 0x104f0 */ + tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL); + msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3); + if (((tmp >> 0) & 0x3) != 0x2) + msg_pinfo("Warning! Either the straps are incorrect or you " + "have no flash or someone overwrote the strap " + "values!\n"); + tmp &= 0xfffffffc; + tmp |= 0x2; + /* FIXME: This needs to be an auto-reversible write. */ + pci_mmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL); + + /* Get I/O BAR location. */ + tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) & + PCI_BASE_ADDRESS_IO_MASK; + /* Truncate to reachable range. + * FIXME: Check if the I/O BAR is actually reachable. + * This is an arch specific check. + */ + mv_iobar = tmp & 0xffff; + msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + /* 512 kByte with two 8-bit latches, and + * 4 MByte with additional 3-bit latch. */ + max_rom_decode.parallel = 4 * 1024 * 1024; + + return 0; + +error_out: + pci_cleanup(pacc); + release_io_perms(); + return 1; +} + +int satamv_shutdown(void) +{ + physunmap(mv_bar, 0x20000); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. + * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O). + * This code only supports indirect accesses for now. + */ + +/* Indirect access to via the I/O BAR1. */ +static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + OUTB(val, mv_iobar + 0x80 + (addr & 0x3)); +} + +/* Indirect access to via the I/O BAR1. */ +static uint8_t satamv_indirect_chip_readb(const chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + return INB(mv_iobar + 0x80 + (addr & 0x3)); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ +void satamv_chip_writeb(uint8_t val, chipaddr addr) +{ + satamv_indirect_chip_writeb(val, addr); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ +uint8_t satamv_chip_readb(const chipaddr addr) +{ + return satamv_indirect_chip_readb(addr); +} Index: flashrom-marvell/Makefile =================================================================== --- flashrom-marvell/Makefile (Revision 1257) +++ flashrom-marvell/Makefile (Arbeitskopie) @@ -155,6 +155,9 @@ # Disable Dediprog SF100 until support is complete and tested. CONFIG_DEDIPROG ?= no +# Always enable Marvell SATA controllers for now. +CONFIG_SATAMV ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -283,6 +286,12 @@ PROGRAMMER_OBJS += dediprog.o endif +ifeq ($(CONFIG_SATAMV), yes) +FEATURE_CFLAGS += -D'CONFIG_SATAMV=1' +PROGRAMMER_OBJS += satamv.o +NEED_PCI := yes +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif Index: flashrom-marvell/print_wiki.c =================================================================== --- flashrom-marvell/print_wiki.c (Revision 1257) +++ flashrom-marvell/print_wiki.c (Arbeitskopie) @@ -302,6 +302,9 @@ #if CONFIG_OGP_SPI == 1 print_supported_pcidevs_wiki(ogp_spi); #endif +#if CONFIG_SATAMV == 1 + print_supported_pcidevs_wiki(satas_mv); +#endif printf("\n|}\n"); } Index: flashrom-marvell/flashrom.c =================================================================== --- flashrom-marvell/flashrom.c (Revision 1257) +++ flashrom-marvell/flashrom.c (Arbeitskopie) @@ -52,7 +52,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif enum programmer programmer = @@ -99,6 +99,9 @@ #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI #endif +#if CONFIG_SATAMV == 1 + PROGRAMMER_SATAMV +#endif ; #endif @@ -461,6 +464,25 @@ }, #endif +#if CONFIG_SATAMV == 1 + { + .name = "satamv", + .init = satamv_init, + .shutdown = satamv_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = satamv_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satamv_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Index: flashrom-marvell/programmer.h =================================================================== --- flashrom-marvell/programmer.h (Revision 1257) +++ flashrom-marvell/programmer.h (Arbeitskopie) @@ -79,6 +79,9 @@ #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif +#if CONFIG_SATAMV == 1 + PROGRAMMER_SATAMV, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -415,6 +418,15 @@ extern const struct pcidev_status ogp_spi[]; #endif +/* satamv.c */ +#if CONFIG_SATAMV == 1 +int satamv_init(void); +int satamv_shutdown(void); +void satamv_chip_writeb(uint8_t val, chipaddr addr); +uint8_t satamv_chip_readb(const chipaddr addr); +extern const struct pcidev_status satas_mv[]; +#endif + /* satasii.c */ #if CONFIG_SATASII == 1 int satasii_init(void); Index: flashrom-marvell/print.c =================================================================== --- flashrom-marvell/print.c (Revision 1257) +++ flashrom-marvell/print.c (Arbeitskopie) @@ -317,6 +317,11 @@ programmer_table[PROGRAMMER_OGP_SPI].name); print_supported_pcidevs(ogp_spi); #endif +#if CONFIG_SATAMV == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_SATAMV].name); + print_supported_pcidevs(satas_mv); +#endif } #if CONFIG_INTERNAL == 1 -- http://www.hailfinger.org/

3 5

[commit] r1258 - trunk
by repository service 04 Feb '11

04 Feb '11

Author: hailfinger Date: Fri Feb 4 22:37:59 2011 New Revision: 1258 URL: http://flashrom.org/trac/flashrom/changeset/1258 Log: Support for Angelbird Wings PCIe SSD (solid-state drive). It uses a Marvell 88SX7042 SATA controller internally which has access to a separate flash chip hosting the option ROM. Thanks to Angelbird Ltd for sponsoring development of this driver! I expect the code to work for that SATA controller even if it is not part of the Angelbird SSD. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Added: trunk/satamv.c Modified: trunk/Makefile trunk/flashrom.c trunk/print.c trunk/print_wiki.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Jan 28 10:00:15 2011 (r1257) +++ trunk/Makefile Fri Feb 4 22:37:59 2011 (r1258) @@ -155,6 +155,9 @@ # Disable Dediprog SF100 until support is complete and tested. CONFIG_DEDIPROG ?= no +# Always enable Marvell SATA controllers for now. +CONFIG_SATAMV ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -283,6 +286,12 @@ PROGRAMMER_OBJS += dediprog.o endif +ifeq ($(CONFIG_SATAMV), yes) +FEATURE_CFLAGS += -D'CONFIG_SATAMV=1' +PROGRAMMER_OBJS += satamv.o +NEED_PCI := yes +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Fri Jan 28 10:00:15 2011 (r1257) +++ trunk/flashrom.c Fri Feb 4 22:37:59 2011 (r1258) @@ -52,7 +52,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif enum programmer programmer = @@ -99,6 +99,9 @@ #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI #endif +#if CONFIG_SATAMV == 1 + PROGRAMMER_SATAMV +#endif ; #endif @@ -461,6 +464,25 @@ }, #endif +#if CONFIG_SATAMV == 1 + { + .name = "satamv", + .init = satamv_init, + .shutdown = satamv_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = satamv_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satamv_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Modified: trunk/print.c ============================================================================== --- trunk/print.c Fri Jan 28 10:00:15 2011 (r1257) +++ trunk/print.c Fri Feb 4 22:37:59 2011 (r1258) @@ -317,6 +317,11 @@ programmer_table[PROGRAMMER_OGP_SPI].name); print_supported_pcidevs(ogp_spi); #endif +#if CONFIG_SATAMV == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_SATAMV].name); + print_supported_pcidevs(satas_mv); +#endif } #if CONFIG_INTERNAL == 1 Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Fri Jan 28 10:00:15 2011 (r1257) +++ trunk/print_wiki.c Fri Feb 4 22:37:59 2011 (r1258) @@ -302,6 +302,9 @@ #if CONFIG_OGP_SPI == 1 print_supported_pcidevs_wiki(ogp_spi); #endif +#if CONFIG_SATAMV == 1 + print_supported_pcidevs_wiki(satas_mv); +#endif printf("\n|}\n"); } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Fri Jan 28 10:00:15 2011 (r1257) +++ trunk/programmer.h Fri Feb 4 22:37:59 2011 (r1258) @@ -79,6 +79,9 @@ #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif +#if CONFIG_SATAMV == 1 + PROGRAMMER_SATAMV, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -415,6 +418,15 @@ extern const struct pcidev_status ogp_spi[]; #endif +/* satamv.c */ +#if CONFIG_SATAMV == 1 +int satamv_init(void); +int satamv_shutdown(void); +void satamv_chip_writeb(uint8_t val, chipaddr addr); +uint8_t satamv_chip_readb(const chipaddr addr); +extern const struct pcidev_status satas_mv[]; +#endif + /* satasii.c */ #if CONFIG_SATASII == 1 int satasii_init(void); Added: trunk/satamv.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/satamv.c Fri Feb 4 22:37:59 2011 (r1258) @@ -0,0 +1,183 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010,2011 Carl-Daniel Hailfinger + * Written by Carl-Daniel Hailfinger for Angelbird Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Datasheets are not public (yet?) */ + +#include <stdlib.h> +#include "flash.h" +#include "programmer.h" + +uint8_t *mv_bar; +uint16_t mv_iobar; + +const struct pcidev_status satas_mv[] = { + /* 88SX6041 and 88SX6042 are the same according to the datasheet. */ + {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"}, + + {}, +}; + +#define NVRAM_PARAM 0x1045c +#define FLASH_PARAM 0x1046c +#define EXPANSION_ROM_BAR_CONTROL 0x00d2c +#define PCI_BAR2_CONTROL 0x00c08 +#define GPIO_PORT_CONTROL 0x104f0 + +/* + * Random notes: + * FCE# Flash Chip Enable + * FWE# Flash Write Enable + * FOE# Flash Output Enable + * FALE[1:0] Flash Address Latch Enable + * FAD[7:0] Flash Multiplexed Address/Data Bus + * FA[2:0] Flash Address Low + * + * GPIO[15,2] GPIO Port Mode + * GPIO[4:3] Flash Size + * + * 0xd2c Expansion ROM BAR Control + * 0xc08 PCI BAR2 (Flash/NVRAM) Control + * 0x1046c Flash Parameters + */ +int satamv_init(void) +{ + uintptr_t addr; + uint32_t tmp; + + get_io_perms(); + + /* BAR0 has all internal registers memory mapped. */ + /* No need to check for errors, pcidev_init() will not return in case + * of errors. + */ + addr = pcidev_init(0x11ab, PCI_BASE_ADDRESS_0, satas_mv); + + mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); + if (mv_bar == ERROR_PTR) + goto error_out; + + tmp = pci_mmio_readl(mv_bar + FLASH_PARAM); + msg_pspew("Flash Parameters:\n"); + msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7); + msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf); + msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf); + msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7); + msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7); + msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7); + msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3); + msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1); + msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1); + msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1); + msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1); + msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1); + msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1); + msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf); + + tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL); + msg_pspew("Expansion ROM BAR Control:\n"); + msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7); + + /* Enable BAR2 mapping to flash */ + tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL); + msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n"); + msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1); + msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f); + msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7); + tmp &= 0xffffffc0; + tmp |= 0x0000001f; + /* FIXME: This needs to be an auto-reversible write. */ + pci_mmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL); + + /* Enable flash: GPIO Port Control Register 0x104f0 */ + tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL); + msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3); + if (((tmp >> 0) & 0x3) != 0x2) + msg_pinfo("Warning! Either the straps are incorrect or you " + "have no flash or someone overwrote the strap " + "values!\n"); + tmp &= 0xfffffffc; + tmp |= 0x2; + /* FIXME: This needs to be an auto-reversible write. */ + pci_mmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL); + + /* Get I/O BAR location. */ + tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) & + PCI_BASE_ADDRESS_IO_MASK; + /* Truncate to reachable range. + * FIXME: Check if the I/O BAR is actually reachable. + * This is an arch specific check. + */ + mv_iobar = tmp & 0xffff; + msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + /* 512 kByte with two 8-bit latches, and + * 4 MByte with additional 3-bit latch. */ + max_rom_decode.parallel = 4 * 1024 * 1024; + + return 0; + +error_out: + pci_cleanup(pacc); + release_io_perms(); + return 1; +} + +int satamv_shutdown(void) +{ + physunmap(mv_bar, 0x20000); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. + * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O). + * This code only supports indirect accesses for now. + */ + +/* Indirect access to via the I/O BAR1. */ +static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + OUTB(val, mv_iobar + 0x80 + (addr & 0x3)); +} + +/* Indirect access to via the I/O BAR1. */ +static uint8_t satamv_indirect_chip_readb(const chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + return INB(mv_iobar + 0x80 + (addr & 0x3)); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ +void satamv_chip_writeb(uint8_t val, chipaddr addr) +{ + satamv_indirect_chip_writeb(val, addr); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ +uint8_t satamv_chip_readb(const chipaddr addr) +{ + return satamv_indirect_chip_readb(addr); +}

1 0

[PATCH 1/1] Board-enable for GA-K8N51GMF
by Michael Karcher 04 Feb '11

04 Feb '11

(VERIFIED to contain the right patch) Gigabyte is not really helpful with their PCI IDs for us, the subsystem IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". We should investigate whether autodetection of this board is causing interference with other boards. real version 2: Extend list of PCI IDs for nvidia southbridges. flashrom -V: http://paste.flashrom.org/view.php?id=326 lspic: http://paste.flashrom.org/view.php?id=328 superiotool: http://paste.flashrom.org/view.php?id=329 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 5 ++++- print.c | 1 + 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 5776bf5..75adc9e 100644 --- a/board_enable.c +++ b/board_enable.c @@ -866,6 +866,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) case 0x00E0: /* CK8 */ break; case 0x0260: /* MCP51 */ + case 0x0261: /* MCP51 */ case 0x0364: /* MCP55 */ /* find SMBus controller on *this* southbridge */ /* The infamous Tyan S2915-E has two south bridges; they are @@ -1026,7 +1027,8 @@ static int nvidia_mcp_gpio31_raise(void) /* * Suited for: - * - GIGABYTE GA-K8N51GMF-9 + * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 + * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 */ static int nvidia_mcp_gpio3b_raise(void) { @@ -1938,6 +1940,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, diff --git a/print.c b/print.c index 7ba2801..01a32c6 100644 --- a/print.c +++ b/print.c @@ -476,6 +476,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), + B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL), -- 1.7.2.3

1 0

[PATCH 1/1] Board-enable for GA-K8N51GMF
by Michael Karcher 04 Feb '11

04 Feb '11

(this time *really* the updated patch!) Gigabyte is not really helpful with their PCI IDs for us, the subsystem IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". We should investigate whether autodetection of this board is causing interference with other boards. version 2: Extend list of PCI IDs for nvidia southbridges. flashrom -V: http://paste.flashrom.org/view.php?id=326 lspic: http://paste.flashrom.org/view.php?id=328 superiotool: http://paste.flashrom.org/view.php?id=329 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 4 +++- print.c | 1 + 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 5776bf5..4b9c515 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1026,7 +1026,8 @@ static int nvidia_mcp_gpio31_raise(void) /* * Suited for: - * - GIGABYTE GA-K8N51GMF-9 + * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 + * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 */ static int nvidia_mcp_gpio3b_raise(void) { @@ -1938,6 +1939,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, diff --git a/print.c b/print.c index 7ba2801..01a32c6 100644 --- a/print.c +++ b/print.c @@ -476,6 +476,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), + B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL), -- 1.7.2.3

1 0

CR-48 help
by Brian Davis 04 Feb '11

04 Feb '11

Do you have any experience with the cr-48 and hexxeh's script?

2 1

MICRO-STAR MS-6378(VT8361) write success
by Michael Kotschi 04 Feb '11

04 Feb '11

root@wopr:~/tmp# flashrom -Vw W6378VMS.350 flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "MICRO-STAR INTERNATIONAL CO., LTD" DMI string system-product-name: "MS-6378" DMI string system-version: " " DMI string baseboard-manufacturer: "MICRO-STAR INTERNATIONAL CO., LTD" DMI string baseboard-product-name: "MS-6378(VT8361)" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found chipset "VIA VT82C686A/B", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 315M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for Intel 28F001BX-B, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Intel 28F001BX-T, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Intel 28F004S5, 512 KB: probe_82802ab: id1 0x25, id2 0x3e Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x25, id2 0x3e Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Found chip "PMC Pm29F002T" (256 KB, Parallel) at physical address 0xfffc0000. Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0x25, id2 0x3e Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x25, id2 0x3e Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x25, id2 0x3e Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x25, id2 0x3e Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x25, id2 0x3e Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x25, id2 0x3e Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SyncMOS S29C31004T, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SyncMOS S29C51001T, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SyncMOS S29C51002T, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for SyncMOS S29C51004T, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W29C020C, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W29C040P, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0x9d, id2 0x1d Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x1d Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x01ffff, 0x020000-0x037fff, 0x038000-0x039fff, 0x03a000-0x03bfff, 0x03c000-0x03ffff, SUCCESS. Programming page: address: 0x0003f000 COMPLETE. -- ========================================================= |Michael Kotschi |Internet: mkotschi(a)voxmicro.net| |VoxMicro LLC |Phone: (321) 473-6379 ext 101 | |Managing Partner | | =========================================================

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[PATCH 1/1] Board-enable for GA-K8N51GMF
by Michael Karcher 03 Feb '11

03 Feb '11

Gigabyte is not really helpful with their PCI IDs for us, the subsystem IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". We should investigate whether autodetection of this board is causing interference with other boards. version 2: Extend list of PCI IDs for nvidia southbridges. flashrom -V: http://paste.flashrom.org/view.php?id=326 lspic: http://paste.flashrom.org/view.php?id=328 superiotool: http://paste.flashrom.org/view.php?id=329 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 4 +++- print.c | 1 + 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 5776bf5..4b9c515 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1026,7 +1026,8 @@ static int nvidia_mcp_gpio31_raise(void) /* * Suited for: - * - GIGABYTE GA-K8N51GMF-9 + * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 + * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 */ static int nvidia_mcp_gpio3b_raise(void) { @@ -1938,6 +1939,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, diff --git a/print.c b/print.c index 7ba2801..01a32c6 100644 --- a/print.c +++ b/print.c @@ -476,6 +476,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), + B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL), -- 1.7.2.3

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Asus P3V4x flashrom cant found flash chip
by XVilka Haos of System 03 Feb '11

03 Feb '11

Asus P3V4x VIA Apollo Pro 133A chipset VT82C694X & VT82C596B This board have Mosel Vitelic V29C51002T flash Output of flashrom: http://paste.flashrom.org/view.php?id=335 Output of lspci http://paste.flashrom.org/view.php?id=337 Original BIOS image ftp://ftp.asus.com/pub/ASUS/mb/slot1/pro133a/p3v4x/pv4x1064.zip 13:11:39.29: Chipset detected: VIA Apollo Pro (Plus/133(A|T)) [ASUS FLASH] 13:11:40.50: CMOS size detected: 256b 13:11:40.66: Found DMI 2.3 board info: ASUSTeK Computer INC. P3V4X REV 1.xx 13:11:41.10: Detected Award BIOS ID: P3V4X -- Best regards, XVilka.

1 1

MSI Speedster A4R/V MS-9632 write success
by Julian Scheel 02 Feb '11

02 Feb '11

$ sudo flashrom -Vw Downloads/w9632ims140/w9632ims.140 flashrom v0.9.3-r1257 on Linux 2.6.37-ARCH (x86_64), built with libpci 3.1.7, GCC 4.5.2 20110127 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1966M loops per second, 10 myus = 10 us, 100 myus = 98 us, 1000 myus = 987 us, 10000 myus = 10946 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "MICRO-STAR INTERNATIONAL CO., LTD" DMI string system-product-name: "MS-9632" DMI string system-version: "1.3" DMI string baseboard-manufacturer: "MICRO-STAR INTERNATIONAL CO., LTD" DMI string baseboard-product-name: "MS-9632" DMI string baseboard-version: "1.3" DMI string chassis-type: "Desktop" Found chipset "Intel ICH7/ICH7R", enabling flash write... chipset PCI ID is 8086:27b8, 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 Root Complex Register Block address = 0xfed1c000 GCS = 0x400c64: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled OK. This chipset supports the following protocols: FWH. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A25L512, 64 KB: skipped. Probing for AMIC A25L010, 128 KB: skipped. Probing for AMIC A25L020, 256 KB: skipped. Probing for AMIC A25L040, 512 KB: skipped. Probing for AMIC A25L080, 1024 KB: skipped. Probing for AMIC A25L016, 2048 KB: skipped. Probing for AMIC A25L032, 4096 KB: skipped. Probing for AMIC A25LQ032, 4096 KB: skipped. Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF081A, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25DQ161, 2048 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L1635E, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for Spansion S25FL032A, 4096 KB: skipped. Probing for Spansion S25FL064A, 8192 KB: skipped. Probing for SST SST25VF010.REMS, 128 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M25PX32, 4096 KB: skipped. Probing for ST M25PX64, 8192 KB: skipped. Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x43, id2 0x9f, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x1d, id2 0xa6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for Winbond W39V040FB, 512 KB: probe_jedec_common: id1 0xda, id2 0x54 Found chip "Winbond W39V040FB" (512 KB, FWH) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Lock status of block at 0x00000000 is Full Access. Lock status of block at 0x00010000 is Full Access. Lock status of block at 0x00020000 is Full Access. Lock status of block at 0x00030000 is Full Access. Lock status of block at 0x00040000 is Full Access. Lock status of block at 0x00050000 is Full Access. Lock status of block at 0x00060000 is Full Access. Lock status of block at 0x00070000 is Full Access. Probing for Winbond W39V040FC, 512 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for Winbond W39V080FA, 1024 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for Winbond W39V080FA (dual mode), 512 KB: probe_jedec_common: id1 0xda, id2 0x54 Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for Eon unknown Eon SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Flash image seems to be a legacy BIOS. Disabling checks. Reading old flash chip contents... Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x00ffff:S, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:S Done. Verifying flash... VERIFIED.

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[RFC + PATCH] lock command for flashrom
by Mathias Krause 02 Feb '11

02 Feb '11

Hi, flashrom currently tries to unlock the chip before each read/write/erase command. To prevent further modifications of the chip content, e.g. for security reasons, it would be helpful if flashrom would also be capable of the opposite operation. I talked with Carl-Daniel a little about it and he mentioned problems like having to implement features like partial locks, chips that cannot be unlocked after being locked, etc. To support those features and handle the problematic chips something more than this little patch can do must be implemented. But for now it would be nice to have *something*. See it as a starting point to solve the much bigger problem. This patch adds a function pointer to struct flashchip and a command line option to trigger this function to enable full flash chip write protection. It's currently only implemented for the Atmel AT26DF081A since this is the chip I'm currently working with and which I can test easily. ToDo: Add man page documentation. Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com>

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[PATCH] Board-enable for GA-K8N51GMF
by Michael Karcher 02 Feb '11

02 Feb '11

Gigabyte is not really helpful with their PCI IDs for us, the subsystem IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". We should investigate whether autodetection of this board is causing interference with other boards. flashrom -V: http://paste.flashrom.org/view.php?id=326 lspic: http://paste.flashrom.org/view.php?id=328 superiotool: http://paste.flashrom.org/view.php?id=329 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 4 +++- print.c | 1 + 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 5776bf5..4b9c515 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1026,7 +1026,8 @@ static int nvidia_mcp_gpio31_raise(void) /* * Suited for: - * - GIGABYTE GA-K8N51GMF-9 + * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 + * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 */ static int nvidia_mcp_gpio3b_raise(void) { @@ -1938,6 +1939,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, diff --git a/print.c b/print.c index 7ba2801..01a32c6 100644 --- a/print.c +++ b/print.c @@ -476,6 +476,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), + B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL), -- 1.7.2.3

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