- flashrom - mail.coreboot.org

[PATCH] Manpage improvements.
by Stefan Tauner 15 Feb '12

15 Feb '12

The sections describing the various options of the internal and dummy programmers have grown out of proportions. This patch adds some headlines to devide the unrelated topics a bit (with .TP commands). The previous indented paragraphs for the various programmers were transformed to subsections (.SS). Also, rephrase the documention related to laptops completely to make it less redundant and more informative. Document the laptop=this_is_not_a_laptop internal programmer parameter Change the contact info in the bugs section by removing the trac reference and adding IRC (and the pastebin) instead. Remove some superfluous white space. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.8 | 111 +++++++++++++++++++++++++++++++++++++++++------------------ 1 files changed, 77 insertions(+), 34 deletions(-) diff --git a/flashrom.8 b/flashrom.8 index 2f23cb8..c4356f8 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -1,4 +1,4 @@ -.TH FLASHROM 8 "Jul 25, 2011" +.TH FLASHROM 8 "Feb 15, 2012" .SH NAME flashrom \- detect, read, write, verify and erase flash chips .SH SYNOPSIS @@ -223,8 +223,11 @@ parameters. These parameters are separated from the programmer name by a colon. While some programmers take arguments at fixed positions, other programmers use a key/value interface in which the key and value is separated by an equal sign and different pairs are separated by a comma or a colon. -.TP +.SS .BR "internal " programmer +.TP +.B Board Enables +.sp Some mainboards require to run mainboard specific code to enable flash erase and write support (and probe support on old systems with parallel flash). The mainboard brand and model (if it requires specific code) is usually @@ -275,17 +278,22 @@ has been written because it is known that writing/erasing without the board enable is going to fail. In any case (success or failure), please report to the flashrom mailing list, see below. .sp +.TP +.B Coreboot +.sp On systems running coreboot, flashrom checks whether the desired image matches your mainboard. This needs some special board ID to be present in the image. If flashrom detects that the image you want to write and the current board do not match, it will refuse to write the image unless you specify .sp .B " flashrom \-p internal:boardmismatch=force" +.TP +.B ITE IT87 Super I/O .sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, flashrom should autodetect that configuration. If you want to set the I/O base port of the IT87 series SPI controller manually instead of -using the value provided by the BIOS, use the +using the value provided by the BIOS, use the .sp .B " flashrom \-p internal:it87spiport=portnum" .sp @@ -295,6 +303,9 @@ is the I/O port number (must be a multiple of 8). In the unlikely case flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem. .sp +.TP +.B Intel chipsets +.sp If you have an Intel chipset with an ICH8 or later southbridge with SPI flash attached, and if a valid descriptor was written to it (e.g. by the vendor), the chipset provides an alternative way to access the flash chip(s) named @@ -331,6 +342,8 @@ settings. The default value for ICH7 is given in the example below. .sp Example: .B "flashrom \-p internal:fwh_idsel=0x001122334567" +.TP +.B Laptops .sp Using flashrom on laptops is dangerous and may easily make your hardware unusable (see also the @@ -338,21 +351,31 @@ unusable (see also the section). The embedded controller (EC) in these machines often interacts badly with flashing. .B http://www.flashrom.org/Laptops -has more information. If flash is shared with the EC, erase is guaranteed to -brick your laptop and write is very likely to brick your laptop. -Chip read and probe may irritate your EC and cause fan failure, backlight -failure, sudden poweroff, and other nasty effects. -flashrom will attempt to detect laptops and abort immediately for safety -reasons. -If you want to proceed anyway at your own risk, use +has more information. For example the EC firmware sometimes resides on the same +flash chip as the host firmware. While flashrom tries to change the contents of +that memory the EC might need to fetch new instructions or data from it and +could stop working correctly. Probing for and reading from the chip may also +irritate your EC and cause fan failure, backlight failure, sudden poweroff, and +other nasty effects. flashrom will attempt to detect if it is running on a +laptop and abort immediately for safety reasons if it clearly identifies the +host computer as one. If you want to proceed anyway at your own risk, use .sp .B " flashrom \-p internal:laptop=force_I_want_a_brick" .sp -You have been warned. -.sp We will not help you if you force flashing on a laptop because this is a really dumb idea. -.TP +.sp +You have been warned. +.sp +Currently we rely on the chassis type encoded in the DMI/SMBIOS data to detect +laptops. Some vendors did not implement those bits correctly or set them to +generic and/or dummy values. flashrom will then issue a warning and bail out +like above. In this case you can use +.sp +.B " flashrom \-p internal:laptop=this_is_not_a_laptop" +.sp +to tell flashrom (at your own risk) that it does not running on a laptop. +.SS .BR "dummy " programmer The dummy programmer operates on a buffer in memory only. It provides a safe and fast way to test various aspects of flashrom and is mainly used in @@ -394,6 +417,8 @@ vendor): .sp Example: .B "flashrom -p dummy:emulate=SST25VF040.REMS" +.TP +.B Persistent images .sp If you use flash chip emulation, flash image persistence is available as well by using the @@ -407,6 +432,8 @@ where the chip contents on flashrom shutdown are written to. .sp Example: .B "flashrom -p dummy:emulate=M25P10.RES,image=dummy.bin" +.TP +.B SPI write chunk size .sp If you use SPI flash chip emulation for a chip which supports SPI page write with the default opcode, you can set the maximum allowed write chunk size with @@ -421,6 +448,8 @@ is the number of bytes (min. 1, max. 256). Example: .sp .B " flashrom -p dummy:emulate=M25P10.RES,spi_write_256_chunksize=5" +.TP +.B SPI blacklist .sp To simulate a programmer which refuses to send certain SPI commands to the flash chip, you can specify a blacklist of SPI commands with the @@ -433,6 +462,9 @@ controller refuses to run command 0x03 (READ) and command 0x02 (WRITE). commandlist may be up to 512 characters (256 commands) long. Implementation note: flashrom will detect an error during command execution. .sp +.TP +.B SPI ignorelist +.sp To simulate a flash chip which ignores (doesn't support) certain SPI commands, you can specify an ignorelist of SPI commands with the .sp @@ -443,7 +475,7 @@ SPI commands. If commandlist is e.g. 0302, the emulated flash chip will ignore command 0x03 (READ) and command 0x02 (WRITE). commandlist may be up to 512 characters (256 commands) long. Implementation note: flashrom won't detect an error during command execution. -.TP +.SS .BR "nic3com" , " nicrealtek" , " nicsmc1211" , " nicnatsemi" , " nicintel\ " , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\ " , " satamv" ", and " atahpt " programmers @@ -465,7 +497,7 @@ is the PCI function number of the desired device. .sp Example: .B "flashrom \-p nic3com:pci=05:04.0" -.TP +.SS .BR "ft2232_spi " programmer An optional parameter specifies the controller type and interface/port it should support. For that you have to use the @@ -486,7 +518,7 @@ The default model is .B 4232H and the default interface is .BR B . -.TP +.SS .BR "serprog " programmer A mandatory parameter specifies either a serial device/baud combination or an IP/port combination for communication with the @@ -502,7 +534,7 @@ syntax and for IP, you have to use instead. More information about serprog is available in .B serprog-protocol.txt in the source distribution. -.TP +.SS .BR "buspirate_spi " programmer A required .B dev @@ -518,7 +550,7 @@ where can be .BR 30k ", " 125k ", " 250k ", " 1M ", " 2M ", " 2.6M ", " 4M " or " 8M (in Hz). The default is the maximum frequency of 8 MHz. -.TP +.SS .BR "dediprog " programmer An optional .B voltage @@ -534,7 +566,7 @@ where can be .BR 0V ", " 1.8V ", " 2.5V ", " 3.5V or the equivalent in mV. -.TP +.SS .BR "rayer_spi " programmer The default I/O base address used for the parallel port is 0x378 and you can use the optional @@ -564,9 +596,9 @@ More information about the RayeR hardware is available at .BR "http://rayer.ic.cz/elektro/spipgm.htm " . The schematic of the Xilinx DLC 5 was published at .BR "http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html " . -.TP +.SS .BR "ogp_spi " programmer -The flash ROM chip to access must be specified with the +The flash ROM chip to access must be specified with the .B rom parameter. .sp @@ -650,26 +682,37 @@ in .B "/etc/rc.securelevel" and rebooting, or rebooting into single user mode. .SH BUGS -Please report any bugs at -.sp -.B " http://www.flashrom.org/trac/flashrom/newticket" -.sp -or on the flashrom mailing list at +Please report any bugs to the flashrom mailing list at .B "<flashrom(a)flashrom.org>" .sp We recommend to subscribe first at .sp .B " http://www.flashrom.org/mailman/listinfo/flashrom" .sp -Using flashrom on laptops is dangerous and may easily make your hardware -unusable unless you can desolder the flash chip and have a full flash chip -backup. This is caused by the embedded controller (EC) present in many laptops, -which interacts badly with any flash attempts. This is a hardware limitation -and flashrom will attempt to detect it and abort immediately for safety reasons. -.sp -More information about flashrom on laptops is available from +Many of the developers communicate via the +.B "#flashrom" +IRC channel on +.BR chat.freenode.net . +You are welcome to join and ask questions, send us bug and success reports there +too. Please provide a way to contact you later (e.g. a mail address) and be +patient if there is no immediate reaction. Also, we provide a pastebin service +at +.B http://paste.flashrom.org +that is very useful when you want to share logs etc. without spamming the +channel. +.SS +.B Laptops .sp -.B " http://www.flashrom.org/Laptops" +Using flashrom on laptops is dangerous and may easily make your hardware +unusable. flashrom will attempt to detect if it is running on a laptop and abort +immediately for safety reasons. Please see the detailed discussion of this topic +and associated flashrom options in the +.B Laptops +paragraph in the +.B internal programmer +subsection of the +.B PROGRAMMER SPECIFIC INFO +section. .SH LICENSE .B flashrom is covered by the GNU General Public License (GPL), version 2. Some files are -- 1.7.1

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Re: [flashrom] Just asking some basic advice before I flash the BIOS.
by Joshua Roys 15 Feb '12

15 Feb '12

On 02/15/2012 08:59 AM, Sergio Cipolla wrote: > unzip worked then flashing seems to have gone well too: > http://paste.flashrom.org/view.php?id=1079 > > I'll reboot just to check if everything is fine (and setup the BIOS) > then if it's all OK, should I report 'lspci -nnvvvxxx' and > 'superiotool -deV' ? > Should I add 'flashrom -V' again to the report? > I didn't understand what 'file read with 'flashrom -r readout.rom'' is > ( http://flashrom.org/IRC/Bot#.21summary ). > Hello, Great! It looks like your board already has the lspci output provided by someone else, and the flashrom -Vw output you put on paste.flashrom.org is good enough. The "readout.rom" part, along with the rest of that description, is actually for people who we'll need to do some reverse engineering for in order to support flashing. Since your board works, you don't need to upload it. If you like you can paste a suprtiotool output, but again, since flashing works, it is not necessary. Thanks, Josh

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Re: [flashrom] Just asking some basic advice before I flash the BIOS.
by Joshua Roys 15 Feb '12

15 Feb '12

On 02/15/2012 07:58 AM, Sergio Cipolla wrote: > Hello. First of all, thank you for flashrom. > I have an ECS k7vta3 mobo with VT8233A southbridge. > > # flashrom -r bios.old First, save this backup somewhere. If you want to be really paranoid/safe also save it on external media. > I have the latest BIOS (k7vta330d.exe) here. To write it I would simply run > > # flashrom -wv k7vta330d.exe > > right? > Should I add any -V just in case too? > You'll need to get the bios out of the exe. Try all of these: unzip cabextract unshield 7za Then find the file with an appropriate size. It will be the exact number of bytes as the backup you have made. Then, recent versions of flashrom automatically verify after writing so you do not need a little v. A big V would be nice for debugging any issues that occur. Now, make sure that you have time (at least a day, maybe more) to leave the machine running in case the flash fails. If it does fail, it is likely some software protection that can be disabled with some investigation (some reverse engineering by a developer, a patch being written, applied by you and a new flashrom being compiled by you). Also keep in mind that all flash updates have some amount of risk. So the command you'll want to run is: # flashrom -Vw $newfile where $newfile is the image you find after uncompressing/extracting the .exe provided by the bios vendor. Good luck (and please send success/failure reports to this list), Josh

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Re: [flashrom] Just asking some basic advice before I flash the BIOS.
by Idwer Vollering 15 Feb '12

15 Feb '12

2012/2/15 Sergio Cipolla <secipolla(a)gmail.com>: > Hello. First of all, thank you for flashrom. > I have an ECS k7vta3 mobo with VT8233A southbridge. It looks like your board is supported: http://www.coreboot.org/pipermail/coreboot/2009-June/050002.html http://www.coreboot.org/pipermail/coreboot/2009-June/050004.html Note that there seem to be several PCB revisions: v3.1, v5.0, v6.0, v8.0: http://www.google.nl/search?&q=site:ecs.com.tw+ECS+k7vta3 > > # flashrom -r bios.old > flashrom v0.9.4-r1394 on Linux 3.2.0-1-686-pae (i686), built with > libpci 3.1.7, GCC 4.6.1, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found chipset "VIA VT8233A". Enabling flash write... OK. > This chipset supports the following protocols: Non-SPI. > Found PMC flash chip "Pm29F002T" (256 kB, Parallel) at physical > address 0xfffc0000. > === > This flash part has status UNTESTED for operations: WRITE > The test status of this chip may have been updated in the latest development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, -Vr, > -Vw, -VE), and mention which mainboard or programmer you tested. > Please mention your board in the subject line. Thanks for your help! > > I have the latest BIOS (k7vta330d.exe) here. To write it I would simply run > > # flashrom -wv k7vta330d.exe > > right? No: 1) that file isn't a BIOS file and 2) the filesize won't match the chip's size. Unzip that .exe file and write "K7V330D.BIN" instead. The "-v" parameter is for verifying chip content against files (on any filesystem). > Should I add any -V just in case too? Adding "-V" and saving the output would be helpful, yes. > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom

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Just asking some basic advice before I flash the BIOS.
by Sergio Cipolla 15 Feb '12

15 Feb '12

Hello. First of all, thank you for flashrom. I have an ECS k7vta3 mobo with VT8233A southbridge. # flashrom -r bios.old flashrom v0.9.4-r1394 on Linux 3.2.0-1-686-pae (i686), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "VIA VT8233A". Enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Found PMC flash chip "Pm29F002T" (256 kB, Parallel) at physical address 0xfffc0000. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! I have the latest BIOS (k7vta330d.exe) here. To write it I would simply run # flashrom -wv k7vta330d.exe right? Should I add any -V just in case too?

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Re: [flashrom] [PATCH] Reformat the internal programmer section in the man page.
by Carl-Daniel Hailfinger 15 Feb '12

15 Feb '12

Am 14.02.2012 15:51 schrieb Stefan Tauner: > The section describing the various options of the internal programmer has grown > out of proportions and it has become confusing. This patch adds some headlines > to devide the unrelated topics a bit. > --- > I would also like to make the syntax examples non-bold so that the headlines > stick out more (TBH i don't see the point in making the examples stick out that > much by making them bold and reside on their own line at all). I don't really care about whether we make examples bold or not, but they must (in the RFC sense) be on their own line to avoid catastropical word wrapping and automatic hyphenation as much as possible. > The dummy programmer probably needs something similar rather > sooner than later. > > Opinions and other format command suggestions are very welcome! > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] dummyflasher: Add a status register to SPI chips.
by Carl-Daniel Hailfinger 15 Feb '12

15 Feb '12

Am 31.01.2012 06:51 schrieb Stefan Tauner: > This is just a quick hack, that could be expanded. What do you think? > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Very good idea! > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -55,6 +55,7 @@ static unsigned int emu_jedec_be_52_size = 0; > static unsigned int emu_jedec_be_d8_size = 0; > static unsigned int emu_jedec_ce_60_size = 0; > static unsigned int emu_jedec_ce_c7_size = 0; > +static uint8_t emu_status = 0; > #endif > #endif > > @@ -126,6 +127,9 @@ int dummy_init(void) > { > char *bustext = NULL; > char *tmp = NULL; > +#if EMULATE_SPI_CHIP > + char *status = NULL; > +#endif > #if EMULATE_CHIP > struct stat image_stat; > #endif > @@ -178,6 +182,14 @@ int dummy_init(void) > goto dummy_init_out; > } > #if EMULATE_SPI_CHIP > + status = extract_programmer_param("status"); > + if (status) { > + emu_status = atoi(status); > + msg_pdbg("Initial status register is set to 0x%02x.\n", > + emu_status); > + free(status); > + } > + > if (!strcmp(tmp, "M25P10.RES")) { > emu_chip = EMULATE_ST_M25P10_RES; > emu_chip_size = 128 * 1024; > @@ -385,10 +397,26 @@ static int emulate_spi_chip_response(unsigned int writecnt, > if (readcnt > 2) > readarr[2] = 0x4a; > break; > - case JEDEC_RDSR: > - memset(readarr, 0, readcnt); > + case JEDEC_RDSR: { > + uint8_t tmp_status = emu_status; > if (aai_active) > - memset(readarr, 1 << 6, readcnt); > + tmp_status |= 1 << 6; The WIP (write in progress) / WEL (write enable latch) /AIP (AAI in progress) logic should be moved to the respective commands so RDSR just does memset(readarr, emu_status, readcnt); > + memset(readarr, tmp_status, readcnt); > + break; > + } > + case JEDEC_WREN: > + emu_status |= (1 << 1); > + break; > + case JEDEC_WRSR: > + if (!(emu_status & (1 << 1))) { > + msg_perr("WRSR attempted, but WEL is 0!\n"); > + return 1; Don't return 1 because a real chip wouldn't return an error either, it would just ignore the command. > + } > + if (aai_active) { > + msg_perr("WRSR attempted during AAI sequence!\n"); > + return 1; dito. > + } > + emu_status = writearr[1] & 0xFC; /* resets WEL and WIP */ > break; > case JEDEC_READ: > offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; After the end of the switch statement we should clear WEL if the command was not WREN/EWSR. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH 5/5] Add support for Atmel's AT25F series of SPI flash chips.
by Stefan Tauner 15 Feb '12

15 Feb '12

Besides the definitions of the the chips in flashchips.c this includes - a dedicated probing method (probe_spi_at25f) - a pretty printing method (spi_prettyprint_status_register_at25f), and - an unlocking method (spi_disable_blockprotect_at25f) Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- at25.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ chipdrivers.h | 3 ++ flashchips.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++ flashchips.h | 10 ++--- spi.h | 9 +++-- 5 files changed, 200 insertions(+), 10 deletions(-) diff --git a/at25.c b/at25.c index 803e7e4..d0761f7 100644 --- a/at25.c +++ b/at25.c @@ -63,6 +63,24 @@ static void spi_prettyprint_status_register_atmel_at25_swp(uint8_t status) } } +/* used for AT25F512(A), AT25F1024(A) */ +int spi_prettyprint_status_register_at25f(struct flashctx *flash) +{ + uint8_t status; + + status = spi_read_status_register(flash); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_atmel_at25_wpen(status); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_bit(status, 5); + spi_prettyprint_status_register_bit(status, 4); + /* FIXME: Bit 3 is undefined on AT25F512A */ + spi_prettyprint_status_register_bp(status, 1); + spi_prettyprint_status_register_welwip(status); + return 0; +} + int spi_prettyprint_status_register_at25df(struct flashctx *flash) { uint8_t status; @@ -154,6 +172,58 @@ int spi_prettyprint_status_register_atmel_at26df081a(struct flashctx *flash) return 0; } +int spi_disable_blockprotect_at25f(struct flashctx *flash) +{ + uint8_t status; + int result; + + status = spi_read_status_register(flash); + /* If block protection is disabled (BP0 and BP1 are 0), stop here. */ + if ((status & (3 << 2)) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling... "); + if (status & (1 << 7)) { + msg_cdbg("Need to disable Write Protect Enable (WPEN)\n"); + /* The following is used in spi_disable_blockprotect_at25df + * to check the state of the hardware lock pin. This is not + * possible with this chip, so we have to try. + if ((status & (1 << 4)) == 0) { + msg_cerr("WP# pin is active, disabling " + "write protection is impossible.\n"); + return 1; + } + */ + /* All bits except bit 7 (WPEN) are readonly. If the WP pin is + * low, WPEN is readonly and this will fail. */ + result = spi_write_status_register(flash, status & ~(1 << 7)); + if (result) { + msg_cerr("spi_write_status_register failed.\n"); + return result; + } + status = spi_read_status_register(flash); + if (status & (1 << 7)) { + msg_cerr("WP# pin is probably active, disabling " + "write protection is impossible.\n"); + return 1; + } + + } + /* Global unprotect. Make sure to mask WPEN as well. */ + result = spi_write_status_register(flash, status & ~0x8c); + if (result) { + msg_cerr("spi_write_status_register failed.\n"); + return result; + } + status = spi_read_status_register(flash); + if ((status & (3 << 2)) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } + msg_cdbg("done.\n"); + return 0; +} + int spi_disable_blockprotect_at25df(struct flashctx *flash) { uint8_t status; @@ -279,3 +349,31 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash) msg_cdbg("done.\n"); return 0; } + +int probe_spi_at25f(struct flashctx *flash) +{ + static const unsigned char cmd[AT25F_RDID_OUTSIZE] = { AT25F_RDID }; + unsigned char readarr[AT25F_RDID_INSIZE]; + uint32_t id1; + uint32_t id2; + + if (spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr)) { + msg_cdbg("\n"); + return 0; + } + id1 = readarr[0]; + id2 = readarr[1]; + + msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); + + if (id1 == flash->manufacture_id && id2 == flash->model_id) { + /* Print the status register to tell the + * user about possible write protection. + */ + spi_prettyprint_status_register_at25f(flash); + + return 1; + } + + return 0; +} diff --git a/chipdrivers.h b/chipdrivers.h index 44eca65..9996493 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -74,15 +74,18 @@ int spi_prettyprint_status_register_amic_a25lq032(struct flashctx *flash); /* at25.c */ int spi_prettyprint_status_register_at25df(struct flashctx *flash); int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash); +int spi_prettyprint_status_register_at25f(struct flashctx *flash); int spi_prettyprint_status_register_at25f512b(struct flashctx *flash); int spi_prettyprint_status_register_at25fs010(struct flashctx *flash); int spi_prettyprint_status_register_at25fs040(struct flashctx *flash); int spi_prettyprint_status_register_atmel_at26df081a(struct flashctx *flash); int spi_disable_blockprotect_at25df(struct flashctx *flash); int spi_disable_blockprotect_at25df_sec(struct flashctx *flash); +int spi_disable_blockprotect_at25f(struct flashctx *flash); int spi_disable_blockprotect_at25f512b(struct flashctx *flash); int spi_disable_blockprotect_at25fs010(struct flashctx *flash); int spi_disable_blockprotect_at25fs040(struct flashctx *flash); +int probe_spi_at25f(struct flashctx *flash); /* 82802ab.c */ uint8_t wait_82802ab(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index 80f29f6..b2d1fcc 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1651,6 +1651,65 @@ const struct flashchip flashchips[] = { { .vendor = "Atmel", + .name = "AT25F512", + .bustype = BUS_SPI, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT25F512, + .total_size = 64, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_at25f, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_62, + } + }, + .printlock = spi_prettyprint_status_register_at25f, + .unlock = spi_disable_blockprotect_at25f, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Atmel", + .name = "AT25F512A", + .bustype = BUS_SPI, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT25F512A, + .total_size = 64, + .page_size = 128, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_at25f, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_62, + } + }, + .printlock = spi_prettyprint_status_register_at25f, + /* Not correct to use this one, because the BP1 bit is N/A. */ + .unlock = spi_disable_blockprotect_at25f, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Atmel", .name = "AT25F512B", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, @@ -1693,6 +1752,37 @@ const struct flashchip flashchips[] = { { .vendor = "Atmel", + /* The A suffix indicates 33MHz instead of 20MHz clock rate. + * All other properties seem to be the same.*/ + .name = "AT25F1024(A)", + .bustype = BUS_SPI, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT25F1024, + .total_size = 128, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_at25f, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_62, + } + }, + .printlock = spi_prettyprint_status_register_at25f, + .unlock = spi_disable_blockprotect_at25f, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Atmel", .name = "AT25FS010", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, diff --git a/flashchips.h b/flashchips.h index 03efb86..888fd1a 100644 --- a/flashchips.h +++ b/flashchips.h @@ -134,13 +134,11 @@ #define ATMEL_AT25DF321A 0x4701 #define ATMEL_AT25DF641 0x4800 #define ATMEL_AT25DQ161 0x8600 -#define ATMEL_AT25F512 /* No device ID found in datasheet. Vendor ID - * can be read with AT25F512A_RDID */ -#define ATMEL_AT25F512A 0x65 /* Needs AT25F512A_RDID */ +#define ATMEL_AT25F512 0x65 /* guessed, no device ID in datasheet. + * Vendor ID can be read with AT25F_RDID */ +#define ATMEL_AT25F512A 0x65 /* Needs AT25F_RDID */ #define ATMEL_AT25F512B 0x6500 -#define ATMEL_AT25F1024 /* No device ID found in datasheet. Vendor ID - * can be read with AT25F512A_RDID */ -#define ATMEL_AT25F1024A 0x60 /* Needs AT25F512A_RDID */ +#define ATMEL_AT25F1024 0x60 /* Needs AT25F_RDID */ #define ATMEL_AT25FS010 0x6601 #define ATMEL_AT25FS040 0x6604 #define ATMEL_AT26DF041 0x4400 diff --git a/spi.h b/spi.h index adb9109..a5c3406 100644 --- a/spi.h +++ b/spi.h @@ -30,10 +30,11 @@ /* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03 -/* AT25F512A has bit 3 as don't care bit in commands */ -#define AT25F512A_RDID 0x15 /* 0x15 or 0x1d */ -#define AT25F512A_RDID_OUTSIZE 0x01 -#define AT25F512A_RDID_INSIZE 0x02 +/* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ +/* 0x15 or 0x1d */ +#define AT25F_RDID 0x15 +#define AT25F_RDID_OUTSIZE 0x01 +#define AT25F_RDID_INSIZE 0x02 /* Read Electronic Manufacturer Signature */ #define JEDEC_REMS 0x90 -- 1.7.1

1 0

[PATCH 4/5] Add spi_block_erase_62.
by Stefan Tauner 15 Feb '12

15 Feb '12

This is used by the AT25F series (only?), but is generic enough to reside in spi25.c. The only currently supported chip is the AT25F512B. Other members of that series need some additional infrastructure code, hence this patch adds the erase function to the AT25F512B only. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 1 + flashchips.c | 3 +++ spi.h | 5 +++++ spi25.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 0 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 420564d..44eca65 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -40,6 +40,7 @@ int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int b int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); diff --git a/flashchips.c b/flashchips.c index 3656794..80f29f6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1679,6 +1679,9 @@ const struct flashchip flashchips[] = { }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_62, } }, .printlock = spi_prettyprint_status_register_at25f512b, diff --git a/spi.h b/spi.h index b908603..adb9109 100644 --- a/spi.h +++ b/spi.h @@ -61,6 +61,11 @@ #define JEDEC_CE_60_OUTSIZE 0x01 #define JEDEC_CE_60_INSIZE 0x00 +/* Chip Erase 0x62 is supported by Atmel AT25F chips. */ +#define JEDEC_CE_62 0x62 +#define JEDEC_CE_62_OUTSIZE 0x01 +#define JEDEC_CE_62_INSIZE 0x00 + /* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */ #define JEDEC_CE_C7 0xc7 #define JEDEC_CE_C7_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index 5c5048d..0d02559 100644 --- a/spi25.c +++ b/spi25.c @@ -488,6 +488,43 @@ int spi_chip_erase_60(struct flashctx *flash) return 0; } +int spi_chip_erase_62(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_62_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_62 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", + __func__); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 2-5 s, so wait in 100 ms steps. + */ + /* FIXME: We assume spi_read_status_register will never fail. */ + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + int spi_chip_erase_c7(struct flashctx *flash) { int result; @@ -712,6 +749,16 @@ int spi_block_erase_60(struct flashctx *flash, unsigned int addr, return spi_chip_erase_60(flash); } +int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + if ((addr != 0) || (blocklen != flash->total_size * 1024)) { + msg_cerr("%s called with incorrect arguments\n", + __func__); + return -1; + } + return spi_chip_erase_62(flash); +} + int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { -- 1.7.1

1 0

[PATCH 3/5] Rename AT25F512B-specific code.
by Stefan Tauner 15 Feb '12

15 Feb '12

The AT25F512B is quite different from the other (older and yet unsupported) chips in the AT25F* familiy, hence rename 512B-specific stuff to make room for the generic AT25F* code Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- at25.c | 4 ++-- chipdrivers.h | 4 ++-- flashchips.c | 5 +++-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/at25.c b/at25.c index 817e769..803e7e4 100644 --- a/at25.c +++ b/at25.c @@ -86,7 +86,7 @@ int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash) return spi_prettyprint_status_register_at25df(flash); } -int spi_prettyprint_status_register_at25f(struct flashctx *flash) +int spi_prettyprint_status_register_at25f512b(struct flashctx *flash) { uint8_t status; @@ -202,7 +202,7 @@ int spi_disable_blockprotect_at25df_sec(struct flashctx *flash) return spi_disable_blockprotect_at25df(flash); } -int spi_disable_blockprotect_at25f(struct flashctx *flash) +int spi_disable_blockprotect_at25f512b(struct flashctx *flash) { /* spi_disable_blockprotect_at25df is not really the right way to do * this, but the side effects of said function work here as well. diff --git a/chipdrivers.h b/chipdrivers.h index b20030b..420564d 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -73,13 +73,13 @@ int spi_prettyprint_status_register_amic_a25lq032(struct flashctx *flash); /* at25.c */ int spi_prettyprint_status_register_at25df(struct flashctx *flash); int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash); -int spi_prettyprint_status_register_at25f(struct flashctx *flash); +int spi_prettyprint_status_register_at25f512b(struct flashctx *flash); int spi_prettyprint_status_register_at25fs010(struct flashctx *flash); int spi_prettyprint_status_register_at25fs040(struct flashctx *flash); int spi_prettyprint_status_register_atmel_at26df081a(struct flashctx *flash); int spi_disable_blockprotect_at25df(struct flashctx *flash); int spi_disable_blockprotect_at25df_sec(struct flashctx *flash); -int spi_disable_blockprotect_at25f(struct flashctx *flash); +int spi_disable_blockprotect_at25f512b(struct flashctx *flash); int spi_disable_blockprotect_at25fs010(struct flashctx *flash); int spi_disable_blockprotect_at25fs040(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index ca1c57f..3656794 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1657,6 +1657,7 @@ const struct flashchip flashchips[] = { .model_id = ATMEL_AT25F512B, .total_size = 64, .page_size = 256, + /* TODO: chip features 128-byte one-time programmable region */ .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, @@ -1680,8 +1681,8 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_at25f, - .unlock = spi_disable_blockprotect_at25f, + .printlock = spi_prettyprint_status_register_at25f512b, + .unlock = spi_disable_blockprotect_at25f512b, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, -- 1.7.1

1 0

[PATCH 2/5] Refine messages of SPI block protection disables.
by Stefan Tauner 15 Feb '12

15 Feb '12

Make them real progress indicators with a final "done" message on success. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- at25.c | 21 ++++++++++++--------- spi25.c | 5 +++-- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/at25.c b/at25.c index 8891e2b..817e769 100644 --- a/at25.c +++ b/at25.c @@ -164,7 +164,7 @@ int spi_disable_blockprotect_at25df(struct flashctx *flash) if ((status & (3 << 2)) == 0) return 0; - msg_cdbg("Some block protection in effect, disabling\n"); + msg_cdbg("Some block protection in effect, disabling... "); if (status & (1 << 7)) { msg_cdbg("Need to disable Sector Protection Register Lock\n"); if ((status & (1 << 4)) == 0) { @@ -175,7 +175,7 @@ int spi_disable_blockprotect_at25df(struct flashctx *flash) /* All bits except bit 7 (SPRL) are readonly. */ result = spi_write_status_register(flash, status & ~(1 << 7)); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } @@ -183,7 +183,7 @@ int spi_disable_blockprotect_at25df(struct flashctx *flash) /* Global unprotect. Make sure to mask SPRL as well. */ result = spi_write_status_register(flash, status & ~0xbc); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } status = spi_read_status_register(flash); @@ -191,6 +191,7 @@ int spi_disable_blockprotect_at25df(struct flashctx *flash) msg_cerr("Block protection could not be disabled!\n"); return 1; } + msg_cdbg("done.\n"); return 0; } @@ -219,20 +220,20 @@ int spi_disable_blockprotect_at25fs010(struct flashctx *flash) if ((status & 0x6c) == 0) return 0; - msg_cdbg("Some block protection in effect, disabling\n"); + msg_cdbg("Some block protection in effect, disabling... "); if (status & (1 << 7)) { msg_cdbg("Need to disable Status Register Write Protect\n"); /* Clear bit 7 (WPEN). */ result = spi_write_status_register(flash, status & ~(1 << 7)); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } } /* Global unprotect. Make sure to mask WPEN as well. */ result = spi_write_status_register(flash, status & ~0xec); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } status = spi_read_status_register(flash); @@ -240,6 +241,7 @@ int spi_disable_blockprotect_at25fs010(struct flashctx *flash) msg_cerr("Block protection could not be disabled!\n"); return 1; } + msg_cdbg("done.\n"); return 0; } @@ -253,20 +255,20 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash) if ((status & 0x7c) == 0) return 0; - msg_cdbg("Some block protection in effect, disabling\n"); + msg_cdbg("Some block protection in effect, disabling... "); if (status & (1 << 7)) { msg_cdbg("Need to disable Status Register Write Protect\n"); /* Clear bit 7 (WPEN). */ result = spi_write_status_register(flash, status & ~(1 << 7)); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } } /* Global unprotect. Make sure to mask WPEN as well. */ result = spi_write_status_register(flash, status & ~0xfc); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } status = spi_read_status_register(flash); @@ -274,5 +276,6 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash) msg_cerr("Block protection could not be disabled!\n"); return 1; } + msg_cdbg("done.\n"); return 0; } diff --git a/spi25.c b/spi25.c index eaae204..5c5048d 100644 --- a/spi25.c +++ b/spi25.c @@ -951,10 +951,10 @@ int spi_disable_blockprotect(struct flashctx *flash) if ((status & 0x3c) == 0) return 0; - msg_cdbg("Some block protection in effect, disabling\n"); + msg_cdbg("Some block protection in effect, disabling... "); result = spi_write_status_register(flash, status & ~0x3c); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } status = spi_read_status_register(flash); @@ -962,6 +962,7 @@ int spi_disable_blockprotect(struct flashctx *flash) msg_cerr("Block protection could not be disabled!\n"); return 1; } + msg_cdbg("done.\n"); return 0; } -- 1.7.1

1 0

[PATCH 1/5] Clean up a25.c, at25.c, spi25.c.
by Stefan Tauner 15 Feb '12

15 Feb '12

- introduce spi_prettyprint_status_register_atmel_at25_wpen() - use spi_prettyprint_status_register_bit() where possible - generify spi_prettyprint_status_register_bp3210 and use it in at25.c too Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- a25.c | 8 ++++---- at25.c | 31 +++++++++++-------------------- chipdrivers.h | 2 +- spi25.c | 15 +++++++++------ 4 files changed, 25 insertions(+), 31 deletions(-) diff --git a/a25.c b/a25.c index b0c6b90..8c38f87 100644 --- a/a25.c +++ b/a25.c @@ -40,7 +40,7 @@ int spi_prettyprint_status_register_amic_a25l05p(struct flashctx *flash) spi_prettyprint_status_register_bit(status, 6); spi_prettyprint_status_register_bit(status, 5); spi_prettyprint_status_register_bit(status, 4); - spi_prettyprint_status_register_bp3210(status, 1); + spi_prettyprint_status_register_bp(status, 1); spi_prettyprint_status_register_welwip(status); return 0; } @@ -55,7 +55,7 @@ int spi_prettyprint_status_register_amic_a25l40p(struct flashctx *flash) spi_prettyprint_status_register_amic_a25_srwd(status); spi_prettyprint_status_register_bit(status, 6); spi_prettyprint_status_register_bit(status, 5); - spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_bp(status, 2); spi_prettyprint_status_register_welwip(status); return 0; } @@ -72,7 +72,7 @@ int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash) "is %i KB\n", (status & (1 << 6)) ? 4 : 64); msg_cdbg("Chip status register: Top/Bottom (TB) " "is %s\n", (status & (1 << 5)) ? "bottom" : "top"); - spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_bp(status, 2); spi_prettyprint_status_register_welwip(status); msg_cdbg("Chip status register 2 is NOT decoded!\n"); return 0; @@ -90,7 +90,7 @@ int spi_prettyprint_status_register_amic_a25lq032(struct flashctx *flash) "is %i KB\n", (status & (1 << 6)) ? 4 : 64); msg_cdbg("Chip status register: Top/Bottom (TB) " "is %s\n", (status & (1 << 5)) ? "bottom" : "top"); - spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_bp(status, 2); spi_prettyprint_status_register_welwip(status); msg_cdbg("Chip status register 2 is NOT decoded!\n"); return 0; diff --git a/at25.c b/at25.c index ec9b4b6..8891e2b 100644 --- a/at25.c +++ b/at25.c @@ -23,6 +23,12 @@ /* Prettyprint the status register. Works for Atmel A25/A26 series. */ +static void spi_prettyprint_status_register_atmel_at25_wpen(uint8_t status) +{ + msg_cdbg("Chip status register: Write Protect Enable (WPEN) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); +} + static void spi_prettyprint_status_register_atmel_at25_srpl(uint8_t status) { msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) " @@ -91,10 +97,7 @@ int spi_prettyprint_status_register_at25f(struct flashctx *flash) spi_prettyprint_status_register_bit(status, 6); spi_prettyprint_status_register_atmel_at25_epewpp(status); spi_prettyprint_status_register_bit(status, 3); - msg_cdbg("Chip status register: Block Protect 0 (BP0) is " - "%sset, %s sectors are protected\n", - (status & (1 << 2)) ? "" : "not ", - (status & (1 << 2)) ? "all" : "no"); + spi_prettyprint_status_register_bp(status, 0); spi_prettyprint_status_register_welwip(status); return 0; } @@ -106,14 +109,12 @@ int spi_prettyprint_status_register_at25fs010(struct flashctx *flash) status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); - msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); + spi_prettyprint_status_register_atmel_at25_wpen(status); msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " "%sset\n", (status & (1 << 6)) ? "" : "not "); msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); + spi_prettyprint_status_register_bit(status, 4); msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " "%sset\n", (status & (1 << 3)) ? "" : "not "); msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " @@ -130,18 +131,8 @@ int spi_prettyprint_status_register_at25fs040(struct flashctx *flash) status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); - msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); + spi_prettyprint_status_register_atmel_at25_wpen(status); + spi_prettyprint_status_register_bp(status, 4); /* FIXME: Pretty-print detailed sector protection status. */ spi_prettyprint_status_register_welwip(status); return 0; diff --git a/chipdrivers.h b/chipdrivers.h index a1d0cd9..b20030b 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -47,7 +47,7 @@ int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, int uint8_t spi_read_status_register(struct flashctx *flash); int spi_write_status_register(struct flashctx *flash, int status); void spi_prettyprint_status_register_bit(uint8_t status, int bit); -void spi_prettyprint_status_register_bp3210(uint8_t status, int bp); +void spi_prettyprint_status_register_bp(uint8_t status, int bp); void spi_prettyprint_status_register_welwip(uint8_t status); int spi_prettyprint_status_register(struct flashctx *flash); int spi_disable_blockprotect(struct flashctx *flash); diff --git a/spi25.c b/spi25.c index 3ce7f08..eaae204 100644 --- a/spi25.c +++ b/spi25.c @@ -327,21 +327,24 @@ void spi_prettyprint_status_register_welwip(uint8_t status) } /* Prettyprint the status register. Common definitions. */ -void spi_prettyprint_status_register_bp3210(uint8_t status, int bp) +void spi_prettyprint_status_register_bp(uint8_t status, int bp) { switch (bp) { /* Fall through. */ + case 4: + msg_cdbg("Chip status register: Block Protect 4 (BP4) " + "is %sset\n", (status & (1 << 5)) ? "" : "not "); case 3: - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) " + msg_cdbg("Chip status register: Block Protect 3 (BP3) " "is %sset\n", (status & (1 << 5)) ? "" : "not "); case 2: - msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) " + msg_cdbg("Chip status register: Block Protect 2 (BP2) " "is %sset\n", (status & (1 << 4)) ? "" : "not "); case 1: - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) " + msg_cdbg("Chip status register: Block Protect 1 (BP1) " "is %sset\n", (status & (1 << 3)) ? "" : "not "); case 0: - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) " + msg_cdbg("Chip status register: Block Protect 0 (BP0) " "is %sset\n", (status & (1 << 2)) ? "" : "not "); } } @@ -355,7 +358,7 @@ void spi_prettyprint_status_register_bit(uint8_t status, int bit) static void spi_prettyprint_status_register_common(uint8_t status) { - spi_prettyprint_status_register_bp3210(status, 3); + spi_prettyprint_status_register_bp(status, 3); spi_prettyprint_status_register_welwip(status); } -- 1.7.1

1 0

[PATCH 0/5] AT25F* 3.0
by Stefan Tauner 15 Feb '12

15 Feb '12

Rebased this old series... 2/5 is new. The bunch of block protection disables may be valid target for refactoring because they share lots of code, but have slightly different constants… Stefan Tauner (5): Clean up a25.c, at25.c, spi25.c. Refine messages of SPI block protection disables. Rename AT25F512B-specific code. Add spi_block_erase_62. Add support for Atmel's AT25F series of SPI flash chips. a25.c | 8 ++-- at25.c | 154 +++++++++++++++++++++++++++++++++++++++++++++----------- chipdrivers.h | 6 ++- flashchips.c | 94 +++++++++++++++++++++++++++++++++++ flashchips.h | 10 ++-- spi.h | 14 ++++-- spi25.c | 67 ++++++++++++++++++++++--- 7 files changed, 299 insertions(+), 54 deletions(-)

1 0

Re: [flashrom] FAILED: FR597AA-AKD m9360.pl (FR597AA#AKD)
by Michael Karcher 15 Feb '12

15 Feb '12

Am Dienstag, den 14.02.2012, 11:39 +0100 schrieb Mariusz Cygan: >> Verifying flash... VERIFY FAILED at 0x00011a00! Expected=0x05, Read=0xff, >> failed byte count from 0x00000000-0x000fffff: 0x1f8 >> Your flash chip is in an unknown state. >> Get help on IRC at irc.freenode.net (channel #flashrom) or >> mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! > :( and now I have to pay for the reprogramming of bone BIOS. Restored > back however, and so does not work. I don't completely understand what you mean by "restore back", if it means "reboot", you are right, the chip likely needs to be reprogrammed outside of that mainboard. In case of a desktop, the chip is likely socketed (8-pin DIP) and easily replaceable. Also, as only a low amount of bytes failed to get reprogrammed, chances are good that some flash recovery mode (if supported by that BIOS) kicks in if you try to power on the machine. On the other hand, if "restore back" means restoring the old bios (a backup you did with flashrom) and the thus the upgrade didn't work, please give it a second try. As I read the error message, writing the new image *nearly* worked, only around 500 bytes mismatched, and at least the first byte mismatch is likely explained by missing programming of a "page" of 256 bytes. Many flash chips are quite picky on how the write instruction is issued, and it might be that flashrom is slightly unreliable in getting it completely right so the flash chip ignored the write instruction if something looks fishy. I have to admit I don't know what exactly might cause such a failure, though. If that theory is indeed right, just retrying to write NT35.bin a second time would likely have fixed the situation too, especially as flashrom detects what areas really need to be reprogrammed and leaves the correctly written areas alone. If restoring the old BIOS worked as I guessed in the three steps above, I would encourage you to try writing the new image again, please run flashrom in verbose mode (add -V) and send the output to the mailing list. If writing fails again, please retry with the same image, and attach the log of the write process to the mail, too. Regards, Michael Karcher

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Re: [flashrom] [PATCH] ichspi.c: warn user when a protected region is detected
by Stefan Tauner 14 Feb '12

14 Feb '12

On Sun, 27 Nov 2011 11:48:51 -0800 David Hendricks <david.hendricks(a)gmail.com> wrote: > On Sat, Nov 26, 2011 at 3:35 PM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > > > This includes the notorious read-only flash descriptors and locked ME > > regions. > > --- > > non-verbose sample output from my laptop: > > […] > > Found chipset "Intel QS57". Enabling flash write... WARNING: SPI > > Configuration Lockdown activated. > > WARNING: Flash Descriptor region is not fully accessible and flashrom can > > not deal with this correctly yet. Intel does not provide us the necessary > > documention to support this. > > > To be fair, I think Intel documents it fine. That depends on what 'it' is. The limitations and the influence of FDOPSS on that limitation are well defined in public documentation. But the unlocking process is not documented at all publicly. We know from different leaked documents and also from the fact that vendor tools exist, that unlocking can be done by software only and without touching the FDOPSS pin by sending the "HMRFPO Enable" command via HECI/MEI to the ME. The details are documented in the BIOS writer guide(s) (which are "restricted secret" level(?)) > I think what we've got to do > is checking the flash descriptor override pin strap status (FDOPSS). If it > is cleared then we can ignore the descriptor, otherwise if it is set then > we need to avoid locked regions. I would not call it 'ignoring'. We should be aware, that the limitation do not apply (we do print a message to the user already in that case), but we could and should use the regions where it makes sense (e.g. automatic creation of layout (file)s. > It's really just a pain in the ass and, as you pointed out, may leave the > BIOS/ME firmware blobs in an inconsistent or incompatible state. So the > onus is on the user to ensure a safe upgrade path if only part of the ROM > can be updated. It's probably worth displaying a warning and requiring > "--force" or something in that scenario. As a first step yes. IIRC i have sent a patch that does that when active PR protections are found(?), but i think it is not in/reviewed yet. I agree, we should set write_allowed = 0 (or whatever it was) and rephrase the warning to include that. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 2

[PATCH] Reformat the internal programmer section in the man page.
by Stefan Tauner 14 Feb '12

14 Feb '12

The section describing the various options of the internal programmer has grown out of proportions and it has become confusing. This patch adds some headlines to devide the unrelated topics a bit. --- I would also like to make the syntax examples non-bold so that the headlines stick out more (TBH i don't see the point in making the examples stick out that much by making them bold and reside on their own line at all). The dummy programmer probably needs something similar rather sooner than later. Opinions and other format command suggestions are very welcome! Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.8 | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/flashrom.8 b/flashrom.8 index 9ffd788..367a0a9 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -225,6 +225,9 @@ programmers use a key/value interface in which the key and value is separated by an equal sign and different pairs are separated by a comma or a colon. .TP .BR "internal " programmer +.sp +.B * Board Enables +.sp Some mainboards require to run mainboard specific code to enable flash erase and write support (and probe support on old systems with parallel flash). The mainboard brand and model (if it requires specific code) is usually @@ -275,6 +278,8 @@ has been written because it is known that writing/erasing without the board enable is going to fail. In any case (success or failure), please report to the flashrom mailing list, see below. .sp +.B * Coreboot +.sp On systems running coreboot, flashrom checks whether the desired image matches your mainboard. This needs some special board ID to be present in the image. If flashrom detects that the image you want to write and the current board @@ -282,6 +287,8 @@ do not match, it will refuse to write the image unless you specify .sp .B " flashrom \-p internal:boardmismatch=force" .sp +.B * ITE IT87 Super I/O +.sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, flashrom should autodetect that configuration. If you want to set the I/O base port of the IT87 series SPI controller manually instead of @@ -295,6 +302,8 @@ is the I/O port number (must be a multiple of 8). In the unlikely case flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem. .sp +.B * Intel chipsets +.sp If you have an Intel chipset with an ICH8 or later southbridge with SPI flash attached, and if a valid descriptor was written to it (e.g. by the vendor), the chipset provides an alternative way to access the flash chip(s) named @@ -332,6 +341,8 @@ settings. The default value for ICH7 is given in the example below. Example: .B "flashrom \-p internal:fwh_idsel=0x001122334567" .sp +.B * Laptops +.sp Using flashrom on laptops is dangerous and may easily make your hardware unusable (see also the .B BUGS -- 1.7.1

1 0

Re: [flashrom] FAILED: FR597AA-AKD m9360.pl (FR597AA#AKD)
by Stefan Tauner 14 Feb '12

14 Feb '12

On Tue, 14 Feb 2012 09:58:08 +0100 Mariusz Cygan <itcygan(a)gmail.com> wrote: > flashrom -c W25X80 -w NT35.bin > flashrom v0.9.4-r1394 on Linux 3.0.0-16-generic (x86_64), built with libpci > 3.1.7, GCC 4.6.1, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found chipset "NVIDIA MCP61". > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... This chipset is not really supported yet. > Guesswork... > SPI on this chipset is WIP. Please report any success or failure by mailing > us the verbose output to flashrom(a)flashrom.org, thanks! > Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. > Please send the output of "flashrom -V" to flashrom(a)flashrom.org with > your board name: flashrom -V as the subject to help us finish support for > your > chipset. Thanks. > OK. > This chipset supports the following protocols: SPI. > Found Winbond flash chip "W25X80" (1024 kB, SPI) at physical address > 0xfff00000. > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Erase/write done. > Verifying flash... VERIFY FAILED at 0x00011a00! Expected=0x05, Read=0xff, > failed byte count from 0x00000000-0x000fffff: 0x1f8 > Your flash chip is in an unknown state. > Get help on IRC at irc.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! > ------------------------------------------------------------------------------- > DO NOT REBOOT OR POWEROFF! > > Hello Mariusz, i am not very familiar with the chipset, so i cant really help by fixing the problem. It seems that the addressing is somehow broken: I know that because erase and write succeeds. It does only succeed, if it can verify the contents of every block it wrote to be correct. After the whole process it does read the whole chip again and checks if it equals the image. Now if the addressing of the blocks wraps somewhere then the erase/write code will overwrite some blocks without noticing it (the block itself looks correct to it), but verification will fail at the end. Someone will have to look at it later. They will probably want to look at least at a verbose log, so please post the output of flashrom -V (and additionally maybe even with -VVV). The output of lspci -nnvvxxx (run as root) may also be useful. To get your board back to a consistent state, you could try flashing the backup you made with the -r/--read option (you DID make a backup, right?). But i fear it may also fail... in that case or if you do not have a backup please join IRC and most importantly: DO NOT REBOOT OR POWER OFF! We really mean it. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

FAILED: FR597AA-AKD m9360.pl (FR597AA#AKD)
by Mariusz Cygan 14 Feb '12

14 Feb '12

flashrom -c W25X80 -w NT35.bin flashrom v0.9.4-r1394 on Linux 3.0.0-16-generic (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP61". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Found Winbond flash chip "W25X80" (1024 kB, SPI) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFY FAILED at 0x00011a00! Expected=0x05, Read=0xff, failed byte count from 0x00000000-0x000fffff: 0x1f8 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! -- Serdecznie pozdrawiam Mariusz Cygan Specjalista IT / Administrator / Help Desk

1 0

Re: [flashrom] HM65
by Stefan Tauner 13 Feb '12

13 Feb '12

On Mon, 13 Feb 2012 17:12:25 +0300 Tosoa Bacca <elsifaka(a)gmail.com> wrote: > Hello, > > as requested, here is a verbose output of flashrom on my P150HM. > > And I would like to ask if I have got the EC > (http://www.pcw.fr/bios/BIOS_P150HM_EC_13.zip) from the retailer, > can't I use flashrom to update my BIOS ? > 0x5C: 0x01ff0001 (FREG2: Management Engine) > 0x00001000-0x001fffff is locked Hello Tosoa, thanks for your report! Flashrom is currently not able to write the full image. The problem is the locked ME region as quoted above. We are working on unlocking it, but intel does not provide us any documentation so please do not expect a solution soon. I have added the board to our list of (un)supported laptops (with an appropriate note) and will commit that later together with other small changes. Please use the vendor tools to update your firmware. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

HM65
by Tosoa Bacca 13 Feb '12

13 Feb '12

Hello, as requested, here is a verbose output of flashrom on my P150HM. And I would like to ask if I have got the EC (http://www.pcw.fr/bios/BIOS_P150HM_EC_13.zip) from the retailer, can't I use flashrom to update my BIOS ? thank you, -- Mandrantosoa 'Ndrianiaina Project Manager http://jojopil.com +261 34 01 236 31 – +261 33 37 705 04

1 0

Verified working on Gigabyte 880GMA-USB3
by Shahar Or 13 Feb '12

13 Feb '12

Dear ones, I'm not subscribed to the list so please reply directly. I've tested read and write on Gigabyte GA-880GMA-USB3 (rev 3.1). Thanks so much for enabling me to flash my BIOS ROM from Linux! Here's the link to the mainboard's page in Gigabyte: http://www.gigabyte.com/products/product-page.aspx?pid=3817 Blessings, Shahar

1 0

[PATCH] selfcheck script using dummy programmer
by Carl-Daniel Hailfinger 13 Feb '12

13 Feb '12

This script attempts to test basic flashrom functionality with the help of the dummy programmer and builtin chip simulator. It does not need any hardware access and is ideal for post-compilation self checks, especially for package maintainers. FIXMEs: Should the path to flashrom be hardcoded as ./flashrom ? Can we really assume the script will always be called from the main flashrom directory? How do we make sure that nobody packages the script since it's useless for end users? How do we handle addition of new chips gracefully? Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-dummy_selfcheck_script/util/flashrom_dummy.log =================================================================== --- flashrom-dummy_selfcheck_script/util/flashrom_dummy.log (revision 0) +++ flashrom-dummy_selfcheck_script/util/flashrom_dummy.log (revision 0) @@ -0,0 +1,339 @@ +flashrom v0.9.4-r1492 on Linux 2.6.34.10-0.6-default (i686), built with LLVM Clang 3.0 (branches/release_30 145598), little endian +flashrom is free software, get the source code at http://www.flashrom.org + +Calibrating delay loop... OS timer resolution is 1 usecs, 530M loops per second, 10 myus = 10 us, 100 myus = 101 us, 1000 myus = 995 us, 10000 myus = 9994 us, 4 myus = 5 us, OK. +Initializing dummy programmer +Requested buses are: default +Enabling support for parallel flash. +Enabling support for LPC flash. +Enabling support for FWH flash. +Enabling support for SPI flash. +SPI blacklist is 20 , size 1 +SPI ignorelist is 52 , size 1 +Emulating SST SST25VF032B SPI flash chip (RDID, AAI write) +Filling fake flash chip with 0xff, size 4194304 +Found persistent image dummy_simulator.tmp, size 4194304 matches. +Reading dummy_simulator.tmp +The following protocols are supported: Parallel, LPC, FWH, SPI. +Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff +Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff +Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff +Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff +Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. +Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0xff, id2 0xff +Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0xff, id2 0xff +Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xff, id2 0xff +Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Chip status register is 00 +Chip status register: Block Protect Write Disable (BPL) is not set +Chip status register: Auto Address Increment Programming (AAI) is not set +Chip status register: Bit 5 / Block Protect 3 (BP3) is not set +Chip status register: Bit 4 / Block Protect 2 (BP2) is not set +Chip status register: Bit 3 / Block Protect 1 (BP1) is not set +Chip status register: Bit 2 / Block Protect 0 (BP0) is not set +Chip status register: Write Enable Latch (WEL) is not set +Chip status register: Write In Progress (WIP/BUSY) is not set +Found SST flash chip "SST25VF032B" (4096 kB, SPI) on dummy. +Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xff, id2 0xff +Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff +Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. +Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. +Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. +Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x254a +Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xff, id2 0xff +Found SST flash chip "SST25VF032B" (4096 kB, SPI). +Reading old flash chip contents... done. +Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:ERefusing blacklisted SPI command 0x20 +Invalid command sent to flash chip! +spi_block_erase_20 failed during command execution at address 0x0 +Reading current flash chip contents... done. Looking for another erase function. +Trying erase function 1... 0x000000-0x007fff:EIgnoring ignorelisted SPI command 0x52 +ERASE FAILED at 0x00000000! Expected=0xff, Read=0x00, failed byte count from 0x00000000-0x00007fff: 0x8000 +ERASE FAILED! +Reading current flash chip contents... done. Looking for another erase function. +Trying erase function 2... 0x000000-0x00ffff:EW, 0x010000-0x01ffff:EW, 0x020000-0x02ffff:EW, 0x030000-0x03ffff:EW, 0x040000-0x04ffff:EW, 0x050000-0x05ffff:EW, 0x060000-0x06ffff:EW, 0x070000-0x07ffff:EW, 0x080000-0x08ffff:EW, 0x090000-0x09ffff:EW, 0x0a0000-0x0affff:EW, 0x0b0000-0x0bffff:EW, 0x0c0000-0x0cffff:EW, 0x0d0000-0x0dffff:EW, 0x0e0000-0x0effff:EW, 0x0f0000-0x0fffff:EW, 0x100000-0x10ffff:EW, 0x110000-0x11ffff:EW, 0x120000-0x12ffff:EW, 0x130000-0x13ffff:EW, 0x140000-0x14ffff:EW, 0x150000-0x15ffff:EW, 0x160000-0x16ffff:EW, 0x170000-0x17ffff:EW, 0x180000-0x18ffff:EW, 0x190000-0x19ffff:EW, 0x1a0000-0x1affff:EW, 0x1b0000-0x1bffff:EW, 0x1c0000-0x1cffff:EW, 0x1d0000-0x1dffff:EW, 0x1e0000-0x1effff:EW, 0x1f0000-0x1fffff:EW, 0x200000-0x20ffff:EW, 0x210000-0x21ffff:EW, 0x220000-0x22ffff:EW, 0x230000-0x23ffff:EW, 0x240000-0x24ffff:EW, 0x250000-0x25ffff:EW, 0x260000-0x26ffff:EW, 0x270000-0x27ffff:EW, 0x280000-0x28ffff:EW, 0x290000-0x29ffff:EW, 0x2a0000-0x2affff:EW, 0x2b0000-0x2bffff:EW, 0x2c0000-0x2cffff:EW, 0x2d0000-0x2dffff:EW, 0x2e0000-0x2effff:EW, 0x2f0000-0x2fffff:EW, 0x300000-0x30ffff:EW, 0x310000-0x31ffff:EW, 0x320000-0x32ffff:EW, 0x330000-0x33ffff:EW, 0x340000-0x34ffff:EW, 0x350000-0x35ffff:EW, 0x360000-0x36ffff:EW, 0x370000-0x37ffff:EW, 0x380000-0x38ffff:EW, 0x390000-0x39ffff:EW, 0x3a0000-0x3affff:EW, 0x3b0000-0x3bffff:EW, 0x3c0000-0x3cffff:EW, 0x3d0000-0x3dffff:EW, 0x3e0000-0x3effff:EW, 0x3f0000-0x3fffff:EW +Erase/write done. +Verifying flash... VERIFIED. +Writing dummy_simulator.tmp Index: flashrom-dummy_selfcheck_script/util/flashrom_dummy_selfcheck.sh =================================================================== --- flashrom-dummy_selfcheck_script/util/flashrom_dummy_selfcheck.sh (revision 0) +++ flashrom-dummy_selfcheck_script/util/flashrom_dummy_selfcheck.sh (revision 0) @@ -0,0 +1,38 @@ +#!/bin/sh +# +# Copyright (C) 2012 Carl-Daniel Hailfinger +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# This script attempts to test basic flashrom functionality with the help of +# the dummy programmer and builtin chip simulator. +# It does not need any hardware access and is ideal for post-compilation +# self checks, especially for package maintainers. + +LANG=C +ret=0 +dd if=/dev/zero bs=1024k count=4 of=dummy_simulator.tmp 2>/dev/null || { echo "Image creation failed!" >&2 ; exit 1; } +dd if=/dev/urandom bs=1024k count=4 of=randomimage.tmp 2>/dev/null || { echo "Image creation failed!" >&2 ; exit 1; } +./flashrom -p dummy:emulate=SST25VF032B,image=dummy_simulator.tmp,spi_blacklist=20,spi_ignorelist=52 -w randomimage.tmp -V >flashrom_dummy.tmp 2>&1 +test $? -eq 0 || { ret=1; echo "flashrom returned an error!" >&2 ; } +echo "Checking for output message differences..." +diff flashrom_dummy.tmp util/flashrom_dummy.log +# Filter out version/architecture string and delay loop calibration +diff flashrom_dummy.tmp util/flashrom_dummy.log | grep "^[<>]" | grep -v "^[<>] flashrom v0\.9\.\|^[<>] Calibrating delay loop\.\.\..*OK.$" | wc -l | grep -q "^0$" +test $? -eq 0 && { echo "No significant message differences found."; } || { ret=1; echo "Significant message differences found!" >&2 ; } +cmp randomimage.tmp dummy_simulator.tmp +test $? -eq 0 || { ret=1; echo "Written image has wrong contents!" >&2 ; } +rm dummy_simulator.tmp randomimage.tmp flashrom_dummy.tmp +exit $ret Property changes on: flashrom-dummy_selfcheck_script/util/flashrom_dummy_selfcheck.sh ___________________________________________________________________ Added: svn:executable + * -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] ARM support
by Carl-Daniel Hailfinger 13 Feb '12

13 Feb '12

Am 13.02.2012 01:18 schrieb David Hendricks: > It's a step in the right direction, and compiles for (and runs) on my > Tegra2 test platform, so: > > Acked-by: David Hendricks <dhendrix(a)google.com> The other tests done by lindi- were reported on IRC in #debian-arm. >>> David: This is mostly your code (I only extracted it from the chromium >>> branch of flashrom), could you sign off on it? > All code in this patch ported from chromium.org is: > Signed-off-by: David Hendricks <dhendrix(a)google.com> The other tests done by lindi- were reported on IRC in #debian-arm. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> A small (almost trivial) addition to the chromium patch in hwaccess.h was done by me, for which I state Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Committed in r1492. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[commit] r1492 - trunk
by repository service 13 Feb '12

13 Feb '12

Author: hailfinger Date: Mon Feb 13 01:35:35 2012 New Revision: 1492 URL: http://flashrom.org/trac/flashrom/changeset/1492 Log: Support compilation for the ARM architecture (little-endian only). Note: The internal programmer will abort during processor check. This is intentional. The other hardware drivers (except those using port I/O) should work. Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: David Hendricks <dhendrix(a)google.com> Tested-by: Timo Juhani Lindfors <timo.lindfors(a)iki.fi> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile trunk/arch.h trunk/hwaccess.c trunk/hwaccess.h trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Feb 12 01:13:14 2012 (r1491) +++ trunk/Makefile Mon Feb 13 01:35:35 2012 (r1492) @@ -215,8 +215,9 @@ # below uses CC itself. override ARCH := $(strip $(shell LC_ALL=C $(CC) $(CPPFLAGS) -E arch.h 2>/dev/null | grep -v '^\#' | grep '"' | cut -f 2 -d'"')) -ifeq ($(ARCH), ppc) -# There's no PCI port I/O support on PPC/PowerPC, yet. +# PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. +# Right now this means the drivers below only work on x86. +ifneq ($(ARCH), x86) ifeq ($(CONFIG_NIC3COM), yes) UNSUPPORTED_FEATURES += CONFIG_NIC3COM=yes else Modified: trunk/arch.h ============================================================================== --- trunk/arch.h Sun Feb 12 01:13:14 2012 (r1491) +++ trunk/arch.h Mon Feb 13 01:35:35 2012 (r1492) @@ -27,5 +27,7 @@ #define __FLASHROM_ARCH__ "mips" #elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) #define __FLASHROM_ARCH__ "ppc" +#elif defined(__arm__) +#define __FLASHROM_ARCH__ "arm" #endif __FLASHROM_ARCH__ Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Sun Feb 12 01:13:14 2012 (r1491) +++ trunk/hwaccess.c Mon Feb 13 01:35:35 2012 (r1492) @@ -116,6 +116,20 @@ { } +#elif defined (__arm__) + +static inline void sync_primitive(void) +{ +} + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + #else #error Unknown architecture Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Sun Feb 12 01:13:14 2012 (r1491) +++ trunk/hwaccess.h Mon Feb 13 01:35:35 2012 (r1492) @@ -68,6 +68,13 @@ #error Little-endian PowerPC #defines are unknown #endif +#elif defined (__arm__) +#if defined (__ARMEL__) +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#else +#error Big-endian ARM #defines are unknown +#endif + #endif #if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) @@ -326,6 +333,10 @@ /* PCI port I/O is not yet implemented on MIPS. */ +#elif defined(__arm__) + +/* Non memory mapped I/O is not supported on ARM. */ + #else #error Unknown architecture, please check if it supports PCI port IO. Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sun Feb 12 01:13:14 2012 (r1491) +++ trunk/programmer.h Mon Feb 13 01:35:35 2012 (r1492) @@ -527,6 +527,7 @@ int register_spi_programmer(const struct spi_programmer *programmer); /* ichspi.c */ +#if CONFIG_INTERNAL == 1 enum ich_chipset { CHIPSET_ICH_UNKNOWN, CHIPSET_ICH7 = 7, @@ -538,7 +539,6 @@ CHIPSET_7_SERIES_PANTHER_POINT }; -#if CONFIG_INTERNAL == 1 extern uint32_t ichspi_bbar; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, enum ich_chipset ich_generation);

1 0

[PATCH] ARM support
by Carl-Daniel Hailfinger 13 Feb '12

13 Feb '12

Add the ability to compile for the ARM architecture. Note: The internal programmer will abort during processor check. This is intentional. The other hardware drivers (except those using port I/O) should work, though. My hope is to get this in before 0.9.5 so we can get a release with at least some ARM support. Compile and run tests appreciated. If you're afraid, you can just run dummy. That would at least prove that flashrom compiles and works somehow. David: This is mostly your code (I only extracted it from the chromium branch of flashrom), could you sign off on it? Regards, Carl-Daniel Index: flashrom-arm/hwaccess.c =================================================================== --- flashrom-arm/hwaccess.c (Revision 1491) +++ flashrom-arm/hwaccess.c (Arbeitskopie) @@ -116,6 +116,20 @@ { } +#elif defined (__arm__) + +static inline void sync_primitive(void) +{ +} + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + #else #error Unknown architecture Index: flashrom-arm/hwaccess.h =================================================================== --- flashrom-arm/hwaccess.h (Revision 1491) +++ flashrom-arm/hwaccess.h (Arbeitskopie) @@ -68,8 +68,15 @@ #error Little-endian PowerPC #defines are unknown #endif +#elif defined (__arm__) +#if defined (__ARMEL__) +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#else +#error Big-endian ARM #defines are unknown #endif +#endif + #if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) /* Nonstandard libc-specific macros for determining endianness. */ #if defined(__GLIBC__) @@ -326,6 +333,10 @@ /* PCI port I/O is not yet implemented on MIPS. */ +#elif defined(__arm__) + +/* Non memory mapped I/O is not supported on ARM. */ + #else #error Unknown architecture, please check if it supports PCI port IO. Index: flashrom-arm/Makefile =================================================================== --- flashrom-arm/Makefile (Revision 1491) +++ flashrom-arm/Makefile (Arbeitskopie) @@ -215,8 +215,9 @@ # below uses CC itself. override ARCH := $(strip $(shell LC_ALL=C $(CC) $(CPPFLAGS) -E arch.h 2>/dev/null | grep -v '^\#' | grep '"' | cut -f 2 -d'"')) -ifeq ($(ARCH), ppc) -# There's no PCI port I/O support on PPC/PowerPC, yet. +# PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. +# Right now this means the drivers below only work on x86. +ifneq ($(ARCH), x86) ifeq ($(CONFIG_NIC3COM), yes) UNSUPPORTED_FEATURES += CONFIG_NIC3COM=yes else Index: flashrom-arm/arch.h =================================================================== --- flashrom-arm/arch.h (Revision 1491) +++ flashrom-arm/arch.h (Arbeitskopie) @@ -27,5 +27,7 @@ #define __FLASHROM_ARCH__ "mips" #elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) #define __FLASHROM_ARCH__ "ppc" +#elif defined(__arm__) +#define __FLASHROM_ARCH__ "arm" #endif __FLASHROM_ARCH__ Index: flashrom-arm/programmer.h =================================================================== --- flashrom-arm/programmer.h (Revision 1491) +++ flashrom-arm/programmer.h (Arbeitskopie) @@ -527,6 +527,7 @@ int register_spi_programmer(const struct spi_programmer *programmer); /* ichspi.c */ +#if CONFIG_INTERNAL == 1 enum ich_chipset { CHIPSET_ICH_UNKNOWN, CHIPSET_ICH7 = 7, @@ -538,7 +539,6 @@ CHIPSET_7_SERIES_PANTHER_POINT }; -#if CONFIG_INTERNAL == 1 extern uint32_t ichspi_bbar; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, enum ich_chipset ich_generation); -- http://www.hailfinger.org/

2 2

[PATCH] Add a bunch of new/tested stuff and various small changes 10
by Stefan Tauner 13 Feb '12

13 Feb '12

Tested mainboards: OK: - ABIT A-S78H http://www.flashrom.org/pipermail/flashrom/2012-January/008603.html - ASRock AM2NF6G-VSTA http://www.flashrom.org/pipermail/flashrom/2012-January/008534.html - ASUS M2A-VM (HDMI variant) http://www.flashrom.org/pipermail/flashrom/2012-January/008509.html - ASUS M4N78 PRO http://www.flashrom.org/pipermail/flashrom/2012-January/008598.html - ASUS P5N7A-VM http://www.flashrom.org/pipermail/flashrom/2012-January/008508.html - ASUS P5KPL-CM http://www.flashrom.org/pipermail/flashrom/2012-January/008522.html - ASUS P5QPL-AM http://www.flashrom.org/pipermail/flashrom/2012-January/008557.html - ECS GF7100PVT-M3 http://www.flashrom.org/pipermail/flashrom/2011-December/008412.html - ECS K7SEM http://www.flashrom.org/pipermail/flashrom/2011-December/008362.html - ECS P4M800PRO-M V2.0 http://www.flashrom.org/pipermail/flashrom/2012-January/008478.html - Gigabyte GA-EP31-DS3L http://www.flashrom.org/pipermail/flashrom/2012-January/008601.html - Gigabyte GA-X58A-UDR3 http://www.flashrom.org/pipermail/flashrom/2012-January/008572.html - Gigabyte GA-Z68XP-UD3 http://paste.flashrom.org/view.php?id=1058 - HP ProLiant N40L http://www.flashrom.org/pipermail/flashrom/2012-February/008650.html - MSI MS-7309 (K9N6PGM2-V2) http://www.flashrom.org/pipermail/flashrom/2011-December/008441.html - MSI MS-7548 (Aspen-GL8E used in HP Pavilion a6750f) http://www.flashrom.org/pipermail/flashrom/2012-February/008666.html - MSI MS-7676 (H67MA-ED55(B3)) http://www.flashrom.org/pipermail/flashrom/2012-January/008547.html - PC Engines Alix.6f2 Reported by Philip Prindeville on IRC - Shuttle AV18E2 http://www.flashrom.org/pipermail/flashrom/2011-December/008459.html - Supermicro X8DTE-F http://www.flashrom.org/pipermail/flashrom/2011-November/008304.html - Supermicro X8DTT-HIBQF http://www.flashrom.org/pipermail/flashrom/2012-January/008520.html NOT OK: - ASUS P8H61-M LE/USB3 http://www.flashrom.org/pipermail/flashrom/2012-January/008491.html - ASUS P8H67-M PRO http://www.flashrom.org/pipermail/flashrom/2011-December/008321.html - ASUS P8Z68-V PRO http://www.flashrom.org/pipermail/flashrom/2012-January/008469.html - Intel D425KT http://www.flashrom.org/pipermail/flashrom/2012-January/008600.html - Supermicro X9SCA-F http://www.flashrom.org/pipermail/flashrom/2011-December/008313.html Tested flash chips: - mark AT29C512 as TEST_OK_PREW http://paste.flashrom.org/view.php?id=977 - mark M25P40 as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-December/008351.html - mark M25PE80 as TEST_OK_PREW http://paste.flashrom.org/view.php?id=1061 - mark MX25L6405 as TEST_OK_PREW tested myself with an MX25L6436E variant on serprog - mark W39V080A as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2012-January/008509.html Tested chipsets: - SiS 730 (:0730) http://www.flashrom.org/pipermail/flashrom/2011-December/008362.html - NVIDIA MCP61 (:03e0) http://www.flashrom.org/pipermail/flashrom/2012-January/008534.html - NVIDIA MCP73 (:07d7) http://www.flashrom.org/pipermail/flashrom/2011-December/008412.html - NVIDIA MCP79 (:0aac) http://www.flashrom.org/pipermail/flashrom/2012-January/008508.html - VIA VT82C69x (0691) and VT82C686A/B (:0686) http://www.flashrom.org/pipermail/flashrom/2011-December/008459.html - AMD's SB950 (and presumably also SB920) have the same PCI ID as previous generations, hence change the chipset enable device string. Thanks to Christian Ruppert for the suggestion. - Fix the board enable of the abit NF-M2 nView which had the IDs of its onboard graphics card in its pattern. Change this to the LPC controller. - Intel X79 SPI registers are identical to 6 Series', so use the chipsetenable wrapper of it (enable_flash_pch6). - Fix two paranoid checks for address < 0 in ichspi.c which became futile (and generate clang warnings) with the unsignify patch committed in r1470. - Rename AT25DF641 to AT25DF641(A). They are almost idencical, but could be distinguished by an extended RDID probe (Atmel's patented EDI procedure), which we do not support yet, hence handle them as one model for now. - Remove trac reference from man page - Source format fixes and typos the addition of the ASRock AM2NF6G-VSTA to print.c is Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> everything else is Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- board_enable.c | 4 ++-- chipset_enable.c | 18 +++++++++--------- dediprog.c | 2 +- flashchips.c | 14 +++++++------- flashchips.h | 2 +- flashrom.8 | 8 +++----- ichspi.c | 4 ++-- print.c | 32 ++++++++++++++++++++++++++++---- 8 files changed, 53 insertions(+), 31 deletions(-) diff --git a/board_enable.c b/board_enable.c index 1c5024f..d4f14bb 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1562,7 +1562,7 @@ static int intel_ich_gpio34_raise(void) /* * Suited for: * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ... - * - FCS ESPRIMO Q5010 (SMBIOS: D2544-B1) + * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1) */ static int intel_ich_gpio38_raise(void) { @@ -2114,7 +2114,7 @@ const struct board_match board_matches[] = { {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, - {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower}, + {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, diff --git a/chipset_enable.c b/chipset_enable.c index 33b32ef..0aba1e0 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1155,7 +1155,7 @@ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750/SB850", enable_flash_sb600}, + {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, @@ -1178,7 +1178,7 @@ const struct penable chipset_enables[] = { {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540}, {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540}, - {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540}, + {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540}, {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, @@ -1222,7 +1222,7 @@ const struct penable chipset_enables[] = { {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ - {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, + {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, @@ -1233,8 +1233,8 @@ const struct penable chipset_enables[] = { {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x}, {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, - {0x10de, 0x07d7, NT, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, - {0x10de, 0x0aac, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, + {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, @@ -1243,12 +1243,12 @@ const struct penable chipset_enables[] = { {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge}, {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge}, {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge}, - {0x1106, 0x0691, NT, "VIA", "VT82C69x", via_no_byte_merge}, /* 691, 693a, 694t, 694x checked */ + {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge}, {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge}, /* VIA southbridges */ {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, - {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, + {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_amd8111}, {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x}, {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, @@ -1279,8 +1279,8 @@ const struct penable chipset_enables[] = { {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_pch6}, {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_pch6}, - {0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */ - {0x8086, 0x1d41, NT, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */ + {0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_pch6}, + {0x8086, 0x1d41, NT, "Intel", "X79", enable_flash_pch6}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, diff --git a/dediprog.c b/dediprog.c index f5d08ff..a730e4b 100644 --- a/dediprog.c +++ b/dediprog.c @@ -299,7 +299,7 @@ static int dediprog_spi_read(struct flashctx *flash, uint8_t *buf, return 0; } -/* Bulk write interface, will read multiple page_size byte chunks aligned to page_size bytes. +/* Bulk write interface, will write multiple page_size byte chunks aligned to page_size bytes. * @start start address * @len length * @return 0 on success, 1 on failure diff --git a/flashchips.c b/flashchips.c index ca1c57f..6f5b6f4 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1575,7 +1575,7 @@ const struct flashchip flashchips[] = { { .vendor = "Atmel", - .name = "AT25DF641", + .name = "AT25DF641(A)", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT25DF641, @@ -1961,7 +1961,7 @@ const struct flashchip flashchips[] = { .total_size = 64, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10000, /* 10mS, Enter=Exec */ .block_erasers = @@ -4421,7 +4421,7 @@ const struct flashchip flashchips[] = { .total_size = 8192, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4951,7 +4951,7 @@ const struct flashchip flashchips[] = { .model_id = ST_M25PE80, .total_size = 1024, .page_size = 256, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -6904,7 +6904,7 @@ const struct flashchip flashchips[] = { .model_id = ST_M25P40, .total_size = 512, .page_size = 256, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -8677,9 +8677,9 @@ const struct flashchip flashchips[] = { .total_size = 1024, .page_size = 64 * 1024, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { diff --git a/flashchips.h b/flashchips.h index 03efb86..8587ce9 100644 --- a/flashchips.h +++ b/flashchips.h @@ -364,7 +364,7 @@ #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ #define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ #define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ -#define MACRONIX_MX25L6405 0x2017 /* MX25L3205{,D} */ +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405{,D}, MX25L6406E, MX25L6436E */ #define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ diff --git a/flashrom.8 b/flashrom.8 index 2f23cb8..9ffd788 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -650,17 +650,15 @@ in .B "/etc/rc.securelevel" and rebooting, or rebooting into single user mode. .SH BUGS -Please report any bugs at -.sp -.B " http://www.flashrom.org/trac/flashrom/newticket" -.sp -or on the flashrom mailing list at +Please report any bugs to the flashrom mailing list at .B "<flashrom(a)flashrom.org>" .sp We recommend to subscribe first at .sp .B " http://www.flashrom.org/mailman/listinfo/flashrom" .sp +Laptops +.RS Using flashrom on laptops is dangerous and may easily make your hardware unusable unless you can desolder the flash chip and have a full flash chip backup. This is caused by the embedded controller (EC) present in many laptops, diff --git a/ichspi.c b/ichspi.c index 163ecf1..66b05a0 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1286,7 +1286,7 @@ static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf, uint16_t timeout = 100 * 60; uint8_t block_len; - if (addr < 0 || addr + len > flash->total_size * 1024) { + if (addr + len > flash->total_size * 1024) { msg_perr("Request to read from an inaccessible memory address " "(addr=0x%x, len=%d).\n", addr, len); return -1; @@ -1324,7 +1324,7 @@ static int ich_hwseq_write(struct flashctx *flash, uint8_t *buf, uint16_t timeout = 100 * 60; uint8_t block_len; - if (addr < 0 || addr + len > flash->total_size * 1024) { + if (addr + len > flash->total_size * 1024) { msg_perr("Request to write to an inaccessible memory address " "(addr=0x%x, len=%d).\n", addr, len); return -1; diff --git a/print.c b/print.c index b4900c3..2dece32 100644 --- a/print.c +++ b/print.c @@ -541,6 +541,7 @@ void print_supported(void) const struct board_info boards_known[] = { #if defined(__i386__) || defined(__x86_64__) B("A-Trend", "ATC-6220", 1, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), + B("abit", "A-S78H", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("abit", "AN-M2", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("abit", "AV8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("abit", "AX8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), @@ -560,7 +561,7 @@ const struct board_info boards_known[] = { B("Advantech", "PCM-5820", 1, "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm", NULL), B("agami", "Aruma", 1, "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…", NULL), B("Albatron", "PM266A Pro", 1, "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…", NULL), /* FIXME */ - B("AOpen", "i945GMx-VFX", 1, NULL, "This is (also?) an OEM board from FCS (used in e.g. ESPRIMO Q5010 with designation D2544-B1)."), + B("AOpen", "i945GMx-VFX", 1, NULL, "This is (also?) an OEM board from FSC (used in e.g. ESPRIMO Q5010 with designation D2544-B1)."), B("AOpen", "vKM400Am-S", 1, "http://usa.aopen.com/products_detail.aspx?Auno=824", NULL), B("Artec Group","DBE61", 1, "http://wiki.thincan.org/DBE61", NULL), B("Artec Group","DBE62", 1, "http://wiki.thincan.org/DBE62", NULL), @@ -571,6 +572,7 @@ const struct board_info boards_known[] = { B("ASRock", "A330GC", 1, "http://www.asrock.com/mb/overview.asp?Model=A330GC", NULL), B("ASRock", "A770CrossFire", 1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire", NULL), B("ASRock", "ALiveNF6G-DVI", 1, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL), + B("ASRock", "AM2NF6G-VSTA", 1, "http://www.asrock.com/mb/overview.asp?Model=AM2NF6G-VSTA", NULL), B("ASRock", "ConRoeXFire-eSATA2", 1, "http://www.asrock.com/mb/overview.asp?model=conroexfire-esata2", NULL), B("ASRock", "K7S41", 1, "http://www.asrock.com/mb/overview.asp?Model=K7S41", NULL), B("ASRock", "K7S41GX", 1, "http://www.asrock.com/mb/overview.asp?Model=K7S41GX", NULL), @@ -610,7 +612,7 @@ const struct board_info boards_known[] = { B("ASUS", "K8V-X", 1, "http://www.asus.com/Motherboards/AMD_Socket_754/K8VX/", NULL), B("ASUS", "K8V-X SE", 1, "http://www.asus.com/Motherboards/AMD_Socket_754/K8VX_SE/", NULL), B("ASUS", "M2A-MX", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2AMX/", NULL), - B("ASUS", "M2A-VM", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2AVM/", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html"), + B("ASUS", "M2A-VM (HDMI)", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2AVM/", NULL), B("ASUS", "M2N32-SLI Deluxe", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2N32SLI_DeluxeWireless_Edition/", NULL), B("ASUS", "M2N-E", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2NE/", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html"), B("ASUS", "M2N-E SLI", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2NE_SLI/", NULL), @@ -624,12 +626,13 @@ const struct board_info boards_known[] = { B("ASUS", "M3A78-EM", 1, "http://www.asus.com/Motherboards/AMD_AM2Plus/M3A78EM/", NULL), B("ASUS", "M3N78-VM", 1, "http://www.asus.com/Motherboards/AMD_AM2Plus/M3N78VM/", NULL), B("ASUS", "M4A78-EM", 1, "http://www.asus.com/Motherboards/AMD_AM2Plus/M4A78EM/", NULL), - B("ASUS", "M4A785TD-V EVO", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A785TDV_EVO/", NULL), B("ASUS", "M4A785TD-M EVO", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A785TDM_EVO/", NULL), + B("ASUS", "M4A785TD-V EVO", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A785TDV_EVO/", NULL), B("ASUS", "M4A78LT-M LE", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A78LTM_LE/", NULL), B("ASUS", "M4A79T Deluxe", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A79T_Deluxe/", NULL), B("ASUS", "M4A87TD/USB3", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A87TDUSB3/", NULL), B("ASUS", "M4A89GTD PRO", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A89GTD_PRO/", NULL), + B("ASUS", "M4N78 PRO", 1, "http://www.asus.com/Motherboards/AMD_AM2Plus/M4N78_PRO/", NULL), B("ASUS", "M5A99X EVO", 1, "http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/", NULL), B("ASUS", "MEW-AM", 0, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), B("ASUS", "MEW-VM", 0, "http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), @@ -667,6 +670,7 @@ const struct board_info boards_known[] = { B("ASUS", "P5GD2/C variants", 0, NULL, "Untested board enable."), B("ASUS", "P5K-VM", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KVM/", NULL), B("ASUS", "P5KC", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KC/", NULL), + B("ASUS", "P5KPL-CM", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KPLCM/", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LMX/", NULL), B("ASUS", "P5L-VM 1394", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LVM_1394/", NULL), B("ASUS", "P5LD2", 0, NULL, "Untested board enable."), @@ -677,8 +681,10 @@ const struct board_info boards_known[] = { B("ASUS", "P5N-D", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5ND/", NULL), B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/Motherboards/Intel_Socket_775/P5NE_SLI/", "Untested board enable."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5N32E_SLI/", NULL), + B("ASUS", "P5N7A-VM", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5N7AVM/", NULL), B("ASUS", "P5ND2-SLI Deluxe", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5ND2SLI_Deluxe/", NULL), B("ASUS", "P5PE-VM", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5PEVM/", NULL), + B("ASUS", "P5QPL-AM", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5QPLAM/", NULL), B("ASUS", "P5VD1-X", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5VD1X/", NULL), B("ASUS", "P6T SE", 1, "http://www.asus.com/Motherboards/Intel_Socket_1366/P6T_SE/", NULL), B("ASUS", "P6T Deluxe", 1, "http://www.asus.com/Motherboards/Intel_Socket_1366/P6T_Deluxe/", NULL), @@ -688,7 +694,10 @@ const struct board_info boards_known[] = { B("ASUS", "P8B-E/4L", 0, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8B WS", 0, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8H61 PRO", 0, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8H61-M LE/USB3", 0, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8H67-M PRO", 0, NULL, "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8P67 (rev. 3.1)", 0, NULL, "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8Z68-V PRO", 0, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "Z8NA-D6C", 1, "http://www.asus.com/Server_Workstation/Server_Motherboards/Z8NAD6C/", NULL), B("ASUS", "Z8PE-D12", 1, "http://www.asus.com/Server_Workstation/Server_Motherboards/Z8PED12/", NULL), B("BCOM", "WinNET100", 1, "http://www.coreboot.org/BCOM_WINNET100", "Used in the IGEL-316 thin client."), @@ -705,10 +714,12 @@ const struct board_info boards_known[] = { B("DFI", "855GME-MGF", 0, "http://www.dfi.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWindow?…", "Probably needs a board enable. http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html"), B("DFI", "Blood-Iron P35 T2RL", 1, "http://lp.lanparty.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWin…", NULL), B("Elitegroup", "GeForce6100SM-M ", 1, "http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=685&M…", NULL), + B("Elitegroup", "GF7100PVT-M3 (V1.0)", 1, "http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=853&C…", NULL), B("Elitegroup", "K7S5A", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=279&…", NULL), B("Elitegroup", "K7S6A", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=77&C…", NULL), + B("Elitegroup", "K7SEM (V1.0A)", 1, "http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=229&C…", NULL), B("Elitegroup", "K7VTA3", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…", NULL), - B("Elitegroup", "P4M800PRO-M (V1.0A)", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), + B("Elitegroup", "P4M800PRO-M (V1.0A, V2.0)", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), B("Elitegroup", "P4VXMS (V1.0A)", 1, NULL, NULL), B("Elitegroup", "P6IWP-Fe", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), B("Elitegroup", "P6VAP-A+", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…", NULL), @@ -746,6 +757,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-945PL-S3P (rev. 6.6)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2541", NULL), B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), + B("GIGABYTE", "GA-EP31-DS3L (rev. 2.1)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2964", NULL), B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), @@ -769,10 +781,13 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL), B("GIGABYTE", "GA-P67A-UD3P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3649", NULL), B("GIGABYTE", "GA-X58A-UD7 (rev. 2.0)", 1, NULL, NULL), + B("GIGABYTE", "GA-X58A-UDR3 (rev. 2.0)", 1, NULL, NULL), B("GIGABYTE", "GA-Z68MX-UD2H-B (rev. 1.3)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3854", NULL), + B("GIGABYTE", "GA-Z68XP-UD3 (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3892", NULL), B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-33…", NULL), + B("HP", "ProLiant N40L", 1, NULL, NULL), B("HP", "Puffer2-UL8E", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00300023", NULL), B("HP", "Vectra VL400", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), B("HP", "Vectra VL420 SFF", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), @@ -782,6 +797,7 @@ const struct board_info boards_known[] = { B("IBM", "x3455", 1, "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html", NULL), B("IEI", "PICOe-9452", 1, "http://www.ieiworld.com/product_groups/industrial/content.aspx?keyword=WSB&…", NULL), B("Intel", "D201GLY", 1, "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm", NULL), + B("Intel", "D425KT", 0, "http://www.intel.com/content/www/us/en/motherboards/desktop-motherboards/de…", "NM10 with SPI lock down, BIOS lock, see http://www.flashrom.org/pipermail/flashrom/2012-January/008600.html"), B("Intel", "D865GLC", 0, NULL, "ICH5 with BIOS lock enable, see http://paste.flashrom.org/view.php?id=775"), B("Intel", "DG45ID", 0, "http://www.intel.com/products/desktop/motherboards/dg45id/dg45id-overview.h…", "Probing works (Winbond W25x32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked."), B("Intel", "DH67CF", 0, NULL, "H67 with BIOS lock enable and locked ME region, see http://www.flashrom.org/pipermail/flashrom/2011-September/007789.html"), @@ -825,6 +841,7 @@ const struct board_info boards_known[] = { B("MSI", "MS-7253 (K9VGM-V)", 1, "http://www.msi.com/product/mb/K9VGM-V.html", NULL), B("MSI", "MS-7255 (P4M890M)", 1, "http://www.msi.com/product/mb/P4M890M-L-IL.html", NULL), B("MSI", "MS-7260 (K9N Neo PCB 1.0)", 0, "http://www.msi.com/product/mb/K9N-Neo--PCB-1-0-.html", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>."), + B("MSI", "MS-7309 (K9N6PGM2-V2)", 1, "http://www.msi.com/product/mb/K9N6PGM2-V2.html", NULL), B("MSI", "MS-7312 (K9MM-V)", 1, "http://www.msi.com/product/mb/K9MM-V.html", NULL), B("MSI", "MS-7345 (P35 Neo2-FIR)", 1, "http://www.msi.com/product/mb/P35-Neo2-FR---FIR.html", NULL), B("MSI", "MS-7368 (K9AG Neo2-Digital)", 1, "http://www.msi.com/product/mb/K9AG-Neo2-Digital.html", NULL), @@ -832,12 +849,14 @@ const struct board_info boards_known[] = { B("MSI", "MS-7376 (K9A2 Platinum V1)", 1, "http://www.msi.com/product/mb/K9A2-Platinum.html", NULL), B("MSI", "MS-7529 (G31M3-L(S) V2)", 1, "http://www.msi.com/product/mb/G31M3-L-V2---G31M3-LS-V2.html", NULL), B("MSI", "MS-7529 (G31TM-P21)", 1, "http://www.msi.com/product/mb/G31TM-P21.html", NULL), + B("MSI", "MS-7548 (Aspen-GL8E)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c01635688&lc=en&cc=us&d…", NULL), B("MSI", "MS-7596 (785GM-E51)", 1, "http://www.msi.com/product/mb/785GM-E51.html", NULL), B("MSI", "MS-7599 (870-C45)", 1, "http://www.msi.com/product/mb/870-C45.html", NULL), B("MSI", "MS-7613 (Iona-GL8E)", 0, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c02014355&lc=en&cc=dk&d…", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("MSI", "MS-7635 (H55M-ED55)", 0, "http://www.msi.com/product/mb/H55M-ED55.html", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("MSI", "MS-7640 (890FXA-GD70)",1, "http://www.msi.com/product/mb/890FXA-GD70.html", NULL), B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/product/mb/890GXM-G65.html", NULL), + B("MSI", "MS-7676 (H67MA-ED55(B3))", 1, "http://www.msi.com/product/mb/H67MA-ED55--B3-.html", "Seems to work fine basically, but user reported (hopefully unrelated) buggy behavior of the board after a firmware upgrade. See http://www.flashrom.org/pipermail/flashrom/2012-January/008547.html"), B("MSI", "MS-7696 (A75MA-G55)", 1, "http://www.msi.com/product/mb/A75MA-G55.html", NULL), B("MSI", "MS-7698 (E350IA-E45)", 1, "http://www.msi.com/product/mb/E350IA-E45.html", NULL), B("NEC", "PowerMate 2000", 1, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), @@ -850,6 +869,7 @@ const struct board_info boards_known[] = { B("PC Engines", "Alix.2d3", 1, "http://pcengines.ch/alix2d3.htm", NULL), B("PC Engines", "Alix.3c3", 1, "http://pcengines.ch/alix3c3.htm", NULL), B("PC Engines", "Alix.3d3", 1, "http://pcengines.ch/alix3d3.htm", NULL), + B("PC Engines", "Alix.6f2", 1, "http://pcengines.ch/alix6f2.htm", NULL), B("PC Engines", "WRAP.2E", 1, "http://pcengines.ch/wrap2e1.htm", NULL), B("Portwell", "PEB-4700VLA", 1, "http://www.portwell.com/products/detail.asp?CUSTCHAR1=PEB-4700VLA", NULL), B("RCA", "RM4100", 1, "http://www.settoplinux.org/index.php?title=RCA_RM4100", NULL), @@ -857,6 +877,7 @@ const struct board_info boards_known[] = { B("Shuttle", "AK31", 1, "http://www.motherboard.cz/mb/shuttle/AK31.htm", NULL), B("Shuttle", "AK38N", 1, "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/", NULL), B("Shuttle", "AV11V30", 1, NULL, NULL), + B("Shuttle", "AV18E2", 1, "http://www.shuttle.eu/_archive/older/de/av18.htm", NULL), B("Shuttle", "FD37", 1, "http://www.shuttle.eu/products/discontinued/barebones/sd37p2/", NULL), B("Shuttle", "FH67", 1, "http://www.shuttle.eu/products/mini-pc/sh67h3/specification/", NULL), B("Shuttle", "FN25", 1, "http://www.shuttle.eu/products/discontinued/barebones/sn25p/?0=", NULL), @@ -875,12 +896,15 @@ const struct board_info boards_known[] = { B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL), B("Supermicro", "X7SPA-HF", 1, "http://www.supermicro.com/products/motherboard/ATOM/ICH9/X7SPA.cfm?typ=H&IP…", NULL), B("Supermicro", "X8DT3", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT3.cfm", NULL), + B("Supermicro", "X8DTE-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT6-F.cfm?IPMI=Y&…", NULL), B("Supermicro", "X8DTH-6F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm", NULL), B("Supermicro", "X8DTT-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm", NULL), + B("Supermicro", "X8DTT-HIBQF", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-H.cfm", NULL), B("Supermicro", "X8DTU-6TF+", 0, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU_.cfm?TYP=SAS&…", "Probing works (Atmel AT25DF321A, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X8DTU-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU-F.cfm", NULL), B("Supermicro", "X8SIE(-F)", 0, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI…", "Requires unlocking the ME although the registers are set up correctly by the descriptor/BIOS already (tested with swseq and hwseq)."), B("Supermicro", "X8STi", 1, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm", NULL), + B("Supermicro", "X9SCA-F", 0, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCA-F.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X9SCL", 0, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCL.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("T-Online", "S-100", 1, "http://wiki.freifunk-hannover.de/T-Online_S_100", NULL), B("Tekram", "P6Pro-A5", 1, "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL), -- 1.7.1

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Re: [flashrom] [PATCH] Board enable for TriGem Anaheim-3
by Michael Karcher 12 Feb '12

12 Feb '12

Am Samstag, den 11.02.2012, 21:14 +0100 schrieb Michael Karcher: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> (ack via IRC Feb 11, 23:14 GMT) Stefan: Thanks for the ack! > + {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x7121, 0x109f, 0x3157, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise}, This is north bridge + GFX. Adjusted to north bridge + south bridge to be independent of the internal graphics being used or not. And committed in r1491 Regards, Michael Karcher

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[commit] r1491 - trunk
by repository service 12 Feb '12

12 Feb '12

Author: mkarcher Date: Sun Feb 12 01:13:14 2012 New Revision: 1491 URL: http://flashrom.org/trac/flashrom/changeset/1491 Log: Board enable for TriGem Anaheim-3 lspci: http://paste.flashrom.org/view.php?id=1069 flashrom -V: http://paste.flashrom.org/view.php?id=1072 flashrom -w: http://paste.flashrom.org/view.php?id=1073 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> (ack via IRC Feb 11, 23:14 GMT) Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Feb 9 00:28:54 2012 (r1490) +++ trunk/board_enable.c Sun Feb 12 01:13:14 2012 (r1491) @@ -1540,6 +1540,7 @@ * - ASUS P4B266: socket478 + Intel 845D + ICH2 * - ASUS P4B533-E: socket478 + 845E + ICH4 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 + * - TriGem Anaheim-3: socket370 + Intel 810 + ICH */ static int intel_ich_gpio22_raise(void) { @@ -2230,6 +2231,7 @@ {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, + {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x2410, 0, 0, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Feb 9 00:28:54 2012 (r1490) +++ trunk/print.c Sun Feb 12 01:13:14 2012 (r1491) @@ -886,6 +886,7 @@ B("Tekram", "P6Pro-A5", 1, "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL), B("Termtek", "TK-3370 (Rev:2.5B)", 1, NULL, NULL), B("Thomson", "IP1000", 1, "http://www.settoplinux.org/index.php?title=Thomson_IP1000", NULL), + B("TriGem", "Anaheim-3", 1, "http://www.e4allupgraders.info/dir1/motherboards/socket370/anaheim3.shtml", NULL), B("TriGem", "Lomita", 1, "http://www.e4allupgraders.info/dir1/motherboards/socket370/lomita.shtml", NULL), B("Tyan", "S5375-1U (Tempest i5100X)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=610", NULL), B("Tyan", "S1846 (Tsunami ATX)", 1, "http://www.tyan.com/archive/products/html/tsunamiatx.html", NULL),

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[PATCH] Board enable for TriGem Anaheim-3
by Michael Karcher 11 Feb '12

11 Feb '12

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 2 ++ print.c | 1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 06bbd70..2b682ea 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1540,6 +1540,7 @@ static int intel_ich_gpio21_raise(void) * - ASUS P4B266: socket478 + Intel 845D + ICH2 * - ASUS P4B533-E: socket478 + 845E + ICH4 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 + * - TriGem Anaheim-3: socket370 + Intel 810 + ICH */ static int intel_ich_gpio22_raise(void) { @@ -2230,6 +2231,7 @@ const struct board_match board_matches[] = { {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, + {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x7121, 0x109f, 0x3157, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, diff --git a/print.c b/print.c index f4957b1..b4900c3 100644 --- a/print.c +++ b/print.c @@ -886,6 +886,7 @@ const struct board_info boards_known[] = { B("Tekram", "P6Pro-A5", 1, "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL), B("Termtek", "TK-3370 (Rev:2.5B)", 1, NULL, NULL), B("Thomson", "IP1000", 1, "http://www.settoplinux.org/index.php?title=Thomson_IP1000", NULL), + B("TriGem", "Anaheim-3", 1, "http://www.e4allupgraders.info/dir1/motherboards/socket370/anaheim3.shtml", NULL), B("TriGem", "Lomita", 1, "http://www.e4allupgraders.info/dir1/motherboards/socket370/lomita.shtml", NULL), B("Tyan", "S5375-1U (Tempest i5100X)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=610", NULL), B("Tyan", "S1846 (Tsunami ATX)", 1, "http://www.tyan.com/archive/products/html/tsunamiatx.html", NULL), -- 1.7.7.3

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flashrom(8): HTML preview using ManPageRenderer failed
by Ivan Shmakov 10 Feb '12

10 Feb '12

The flashrom(8) revision currently in trunk fails HTML conversion: --cut: http://www.flashrom.org/trac/flashrom/browser/trunk/flashrom.8 -- Warning: HTML preview using ManPageRenderer failed (Exception: Running (/usr/bin/groff -Thtml -P -r -P -l -mandoc ) failed: 0, <standard input>:566: warning [p 1, 86.8i]: cannot adjust line .) --cut: http://www.flashrom.org/trac/flashrom/browser/trunk/flashrom.8 -- It seems that the regression is due to r1437 [1], as r1412 [2] renders without an error. [1] http://www.flashrom.org/trac/flashrom/browser/trunk/flashrom.8?rev=1437 [2] http://www.flashrom.org/trac/flashrom/browser/trunk/flashrom.8?rev=1412 -- FSF associate member #7257

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Re: [flashrom] FAILED : mcp61sm -am
by Idwer Vollering 09 Feb '12

09 Feb '12

2012/2/9 Vince S <vince06fr(a)gmail.com>: > good evening > Good news I realized what was happening and managed to flash my bios. > > The bios I was cleanliness was set to "boot block protection" > > there is no pin on the mainboard but the parameter is adjustable from the > interface of the bios, so I changed this parameter in the bios, boot from my > linux session, then I share them with the bios mine I flashed with flashrom > and that's ok I would like to see the output of "lspci -nnvvvxxx" and "superiotool -deV" (run both commands as root) before and after changing this parameter, so we can look into adding board enabling code. > > Thanks for your work > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom

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Re: [flashrom] FAILED : mcp61sm -am
by Vince S 09 Feb '12

09 Feb '12

good evening Good news I realized what was happening and managed to flash my bios. The bios I was cleanliness was set to "boot block protection" there is no pin on the mainboard but the parameter is adjustable from the interface of the bios, so I changed this parameter in the bios, boot from my linux session, then I share them with the bios mine I flashed with flashrom and that's ok Thanks for your work

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Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger 09 Feb '12

09 Feb '12

Hi Mike, On 23.02.2010 05:45, Spangler, Mike T wrote: > I can probe with a continuity tester, but would need to know specific > pin locations to try. Do you have any generic info on doing this? Yes (well, I'd have to write up something), but the solution mentioned by Michael is way easier, so I'll wait until Michael has diagnosed the GPIO settings from the flashrom run on factory BIOS. Regards, Carl-Daniel -- "I do consider assignment statements and pointer variables to be among computer science's most valuable treasures." -- Donald E. Knuth

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Re: [flashrom] FAILED : mcp61sm -am
by Stefan Tauner 09 Feb '12

09 Feb '12

On Thu, 9 Feb 2012 14:03:01 +0100 Vince S <vince06fr(a)gmail.com> wrote: > 0x07f000-0x07ffff:E hm. this last log was with the old, already erased (and partially reprogrammed) chip, right? this is even more astonishing, because the E indicates that flashrom has read that sector and found not yet erased data (i.e. bytes != 0xff), else it would just have skipped it afaics. something is really fishy here, the other guys need to look into it. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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FAILED: AXIOMTEK PICO821 REV:A2-RC
by Recovery.se 09 Feb '12

09 Feb '12

Hello I'm very pleased with flashrom! Hovever we have a problem erasing. I can work around it by running erase (flashrom -E) sevral times and then flash with (flashrom -w <rom>). When I run errase the falure posision moves forward .. "ERASE FAILED at 0x00030000!" "ERASE FAILED at 0x00040000!" "ERASE FAILED at 0x000ef000!" ... Regards Eric Eriksson Recovery.se

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Re: [flashrom] r1394: Acer Aspire E380: FAILED : mcp61sm -am
by Paul Menzel 09 Feb '12

09 Feb '12

Dear Vince, Am Donnerstag, den 09.02.2012, 14:03 +0100 schrieb Vince S: > This is curious because it is always possible to clear the bios : > > vince@Bob:~$ sudo flashrom -VE > flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci > 3.1.7, GCC 4.6.1, little endian > flashrom is free software, get the source code at http://www.flashrom.org I did not follow the thread closely, but is that version not too old? Maybe try the latest revision from the Subversion repository? […] Thanks, Paul

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Re: [flashrom] FAILED : mcp61sm -am
by Stefan Tauner 09 Feb '12

09 Feb '12

On Thu, 9 Feb 2012 08:25:51 +0100 Vince S <vince06fr(a)gmail.com> wrote: > Hi so the output of my attempt to flash is > > sudo flashrom -V -w '/home/vince/Téléchargements/BIOS_R01-C0/61AO615.BIN' > > flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci > 3.1.7, GCC 4.6.1, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 736M loops per > second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1007 us, 10000 myus > = 10003 us, 4 myus = 5 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Acer" > DMI string system-product-name: "Aspire E380" > DMI string system-version: "R01-A2" > DMI string baseboard-manufacturer: "Acer" > DMI string baseboard-product-name: "EM61SM/EM61PM " > DMI string baseboard-version: " " > DMI string chassis-type: "Desktop" > Found ITE Super I/O, ID 0x8726 on port 0x2e > Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... This chipset is not really supported yet. > Guesswork... > ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 > Flash bus type is LPC > Found SMBus device 10de:03eb at 00:01:1 > MCP SPI BAR is at 0xfec80000 > Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI > enabled. > Please send the output of "flashrom -V" to flashrom(a)flashrom.org with > your board name: flashrom -V as the subject to help us finish support for > your > chipset. Thanks. > OK. > This chipset supports the following protocols: LPC. > Super I/O ID 0x8726 is not on the list of flash capable controllers. > Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 > Found SST flash chip "SST49LF040B" (512 kB, LPC) at physical address > 0xfff80000. > […] > === > This flash part has status UNTESTED for operations: WRITE > The test status of this chip may have been updated in the latest development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above > operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, -Vr, > -Vw, -VE), and mention which mainboard or programmer you tested. > Please mention your board in the subject line. Thanks for your help! > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Trying erase function 0... > 0x000000-0x000fff:W, 0x001000-0x001fff:S, 0x002000-0x002fff:S, > 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, > 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, > 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, > 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, > 0x00f000-0x00ffff:S, 0x010000-0x010fff:W, 0x011000-0x011fff:W, > 0x012000-0x012fff:W, 0x013000-0x013fff:W, 0x014000-0x014fff:W, > 0x015000-0x015fff:W, 0x016000-0x016fff:W, 0x017000-0x017fff:W, > 0x018000-0x018fff:W, 0x019000-0x019fff:W, 0x01a000-0x01afff:W, > 0x01b000-0x01bfff:W, 0x01c000-0x01cfff:W, 0x01d000-0x01dfff:W, > 0x01e000-0x01efff:W, 0x01f000-0x01ffff:W, 0x020000-0x020fff:W, > 0x021000-0x021fff:W, 0x022000-0x022fff:W, 0x023000-0x023fff:W, > 0x024000-0x024fff:W, 0x025000-0x025fff:W, 0x026000-0x026fff:W, > 0x027000-0x027fff:W, 0x028000-0x028fff:W, 0x029000-0x029fff:W, > 0x02a000-0x02afff:W, 0x02b000-0x02bfff:W, 0x02c000-0x02cfff:W, > 0x02d000-0x02dfff:W, 0x02e000-0x02efff:W, 0x02f000-0x02ffff:W, > 0x030000-0x030fff:W, 0x031000-0x031fff:W, 0x032000-0x032fff:W, > 0x033000-0x033fff:W, 0x034000-0x034fff:W, 0x035000-0x035fff:W, > 0x036000-0x036fff:W, 0x037000-0x037fff:W, 0x038000-0x038fff:W, > 0x039000-0x039fff:W, 0x03a000-0x03afff:W, 0x03b000-0x03bfff:W, > 0x03c000-0x03cfff:W, 0x03d000-0x03dfff:W, 0x03e000-0x03efff:W, > 0x03f000-0x03ffff:W, 0x040000-0x040fff:W, 0x041000-0x041fff:W, > 0x042000-0x042fff:W, 0x043000-0x043fff:W, 0x044000-0x044fff:W, > 0x045000-0x045fff:W, 0x046000-0x046fff:W, 0x047000-0x047fff:W, > 0x048000-0x048fff:W, 0x049000-0x049fff:W, 0x04a000-0x04afff:W, > 0x04b000-0x04bfff:W, 0x04c000-0x04cfff:W, 0x04d000-0x04dfff:W, > 0x04e000-0x04efff:W, 0x04f000-0x04ffff:W, 0x050000-0x050fff:W, > 0x051000-0x051fff:W, 0x052000-0x052fff:W, 0x053000-0x053fff:W, > 0x054000-0x054fff:W, 0x055000-0x055fff:W, 0x056000-0x056fff:S, > 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, > 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, > 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, > 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, > 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, > 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, > 0x069000-0x069fff:S, 0x06a000-0x06afff:W, 0x06b000-0x06bfff:W, > 0x06c000-0x06cfff:W, 0x06d000-0x06dfff:W, 0x06e000-0x06efff:W, > 0x06f000-0x06ffff:W, 0x070000-0x070fff:W writing sector at 0x7f28ed976000 > failed! > Reading current flash chip contents... done. Looking for another erase > function. > Trying erase function 1... 0x000000-0x00ffff:S, 0x010000-0x01ffff:S, > 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, > 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:W writing > sector at 0x7f28ed976000 failed! > Looking for another erase function. > No usable erase functions left. > FAILED! > Uh oh. Erase/write failed. Checking if anything changed. > Your flash chip is in an unknown state. > Get help on IRC at irc.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! > ------------------------------------------------------------------------------- > DO NOT REBOOT OR POWEROFF! > Restoring PCI config space for 00:01:0 reg 0x6d > Restoring PCI config space for 00:01:0 reg 0x90 > Restoring PCI config space for 00:01:0 reg 0x8c > Restoring PCI config space for 00:01:0 reg 0x88 that's interesting. it always fails at the same address (0x070000). this is where the boot block protection of that chip begins. the boot block protection is enabled by setting a pin to low and can not be disabled directly by software. usually the pin is connected to a general output pin of the southbridge (or another chip) on the mainboard and can be controlled by that. adding support for this requires some reverse engineering of various difficulty. the interesting question is something different: why were we able to erase that block a month ago... can you confirm that the two chips you are using are the same model? > > what can i do?? since you have a replacement chip, you could just throw the old one away... i would really like to know what happened though. maybe my colleagues can shed some light onto this... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom@ mailing list at Gmane (news:gmane.linux.bios.flashrom)
by Ivan Shmakov 09 Feb '12

09 Feb '12

Apparently, the flashrom@ mailing list traffic isn't properly forwarded to Gmane [1]. Indeed, it seems that all the messages archived there were propagated through one or more of the other Gmane-ized lists instead. Could the forwarding please be fixed? Also, it'd make sense to import the whole mailing list archive to Gmane (check, e. g., [2].) For this, however, one needs access to the Mailman's internal archives, as the downloadable mbox'es at [3] are stripped of much of the relevant information, including, in particular, MIME headers (effectively rendering anything non-ASCII there unreadable) and MIME parts. TIA. [1] http://dir.gmane.org/gmane.linux.bios.flashrom [2] http://gmane.org/import.php [3] http://www.flashrom.org/pipermail/flashrom/ -- FSF associate member #7257

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Re: [flashrom] FAILED : mcp61sm -am
by Vince S 09 Feb '12

09 Feb '12

Hi so the output of my attempt to flash is sudo flashrom -V -w '/home/vince/Téléchargements/BIOS_R01-C0/61AO615.BIN' flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 736M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1007 us, 10000 myus = 10003 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Acer" DMI string system-product-name: "Aspire E380" DMI string system-version: "R01-A2" DMI string baseboard-manufacturer: "Acer" DMI string baseboard-product-name: "EM61SM/EM61PM " DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8726 on port 0x2e Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xfec80000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Super I/O ID 0x8726 is not on the list of flash capable controllers. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Found SST flash chip "SST49LF040B" (512 kB, LPC) at physical address 0xfff80000. Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:W, 0x001000-0x001fff:S, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:W, 0x011000-0x011fff:W, 0x012000-0x012fff:W, 0x013000-0x013fff:W, 0x014000-0x014fff:W, 0x015000-0x015fff:W, 0x016000-0x016fff:W, 0x017000-0x017fff:W, 0x018000-0x018fff:W, 0x019000-0x019fff:W, 0x01a000-0x01afff:W, 0x01b000-0x01bfff:W, 0x01c000-0x01cfff:W, 0x01d000-0x01dfff:W, 0x01e000-0x01efff:W, 0x01f000-0x01ffff:W, 0x020000-0x020fff:W, 0x021000-0x021fff:W, 0x022000-0x022fff:W, 0x023000-0x023fff:W, 0x024000-0x024fff:W, 0x025000-0x025fff:W, 0x026000-0x026fff:W, 0x027000-0x027fff:W, 0x028000-0x028fff:W, 0x029000-0x029fff:W, 0x02a000-0x02afff:W, 0x02b000-0x02bfff:W, 0x02c000-0x02cfff:W, 0x02d000-0x02dfff:W, 0x02e000-0x02efff:W, 0x02f000-0x02ffff:W, 0x030000-0x030fff:W, 0x031000-0x031fff:W, 0x032000-0x032fff:W, 0x033000-0x033fff:W, 0x034000-0x034fff:W, 0x035000-0x035fff:W, 0x036000-0x036fff:W, 0x037000-0x037fff:W, 0x038000-0x038fff:W, 0x039000-0x039fff:W, 0x03a000-0x03afff:W, 0x03b000-0x03bfff:W, 0x03c000-0x03cfff:W, 0x03d000-0x03dfff:W, 0x03e000-0x03efff:W, 0x03f000-0x03ffff:W, 0x040000-0x040fff:W, 0x041000-0x041fff:W, 0x042000-0x042fff:W, 0x043000-0x043fff:W, 0x044000-0x044fff:W, 0x045000-0x045fff:W, 0x046000-0x046fff:W, 0x047000-0x047fff:W, 0x048000-0x048fff:W, 0x049000-0x049fff:W, 0x04a000-0x04afff:W, 0x04b000-0x04bfff:W, 0x04c000-0x04cfff:W, 0x04d000-0x04dfff:W, 0x04e000-0x04efff:W, 0x04f000-0x04ffff:W, 0x050000-0x050fff:W, 0x051000-0x051fff:W, 0x052000-0x052fff:W, 0x053000-0x053fff:W, 0x054000-0x054fff:W, 0x055000-0x055fff:W, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:W, 0x06b000-0x06bfff:W, 0x06c000-0x06cfff:W, 0x06d000-0x06dfff:W, 0x06e000-0x06efff:W, 0x06f000-0x06ffff:W, 0x070000-0x070fff:W writing sector at 0x7f28ed976000 failed! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:S, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:W writing sector at 0x7f28ed976000 failed! Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88 what can i do??

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Re: [flashrom] [PATCH] dummy programmer: blacklist SPI commands
by Carl-Daniel Hailfinger 09 Feb '12

09 Feb '12

Am 08.02.2012 01:49 schrieb David Hendricks: > Acked-by: David Hendricks <dhendrix(a)google.com> Thanks, committed in r1490. Do we want to add a selftest script or "make selftest" target in the Makefile which compares known good output of a complicated write (maybe even including layout) to a reference output shipped with flashrom? That might be useful for distributors and/or as pre-checkin test of invasive changes. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1490 - trunk
by repository service 09 Feb '12

09 Feb '12

Author: hailfinger Date: Thu Feb 9 00:28:54 2012 New Revision: 1490 URL: http://flashrom.org/trac/flashrom/changeset/1490 Log: SPI command black-/ignorelisting for the flash chip emulator in the dummy programmer Usage: flashrom -p dummy:spi_blacklist=commandlist flashrom -p dummy:spi_ignorelist=commandlist If commandlist is 0302, flashrom will refuse (blacklist) or ignore (ignorelist) command 0x03 (READ) and command 0x02 (WRITE). The commandlist can be up to 512 bytes (256 commands) long. Specifying flash chip emulation is a good idea to get useful results. Very useful for testing corner cases if you don't own a locked down Intel chipset and want to simulate such a thing. Example usage: dd if=/dev/zeros bs=1024k count=4 of=dummy_simulator.rom dd if=/dev/urandom bs=1024k count=4 of=randomimage.rom flashrom -p dummy:emulate=SST25VF032B,image=dummy_simulator.rom,\ spi_blacklist=20,spi_ignorelist=52 -w randomimage.rom -V Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/dummyflasher.c trunk/flashrom.8 Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Tue Feb 7 22:29:48 2012 (r1489) +++ trunk/dummyflasher.c Thu Feb 9 00:28:54 2012 (r1490) @@ -19,6 +19,8 @@ #include <string.h> #include <stdlib.h> +#include <stdio.h> +#include <ctype.h> #include "flash.h" #include "chipdrivers.h" #include "programmer.h" @@ -55,6 +57,10 @@ static unsigned int emu_jedec_be_d8_size = 0; static unsigned int emu_jedec_ce_60_size = 0; static unsigned int emu_jedec_ce_c7_size = 0; +unsigned char spi_blacklist[256]; +unsigned char spi_ignorelist[256]; +int spi_blacklist_size = 0; +int spi_ignorelist_size = 0; #endif #endif @@ -126,6 +132,7 @@ { char *bustext = NULL; char *tmp = NULL; + int i; #if EMULATE_CHIP struct stat image_stat; #endif @@ -170,6 +177,68 @@ } } + tmp = extract_programmer_param("spi_blacklist"); + if (tmp) { + i = strlen(tmp); + if (!strncmp(tmp, "0x", 2)) { + i -= 2; + memmove(tmp, tmp + 2, i + 1); + } + if ((i > 512) || (i % 2)) { + msg_perr("Invalid SPI command blacklist length\n"); + free(tmp); + return 1; + } + spi_blacklist_size = i / 2; + for (i = 0; i < spi_blacklist_size * 2; i++) { + if (!isxdigit((unsigned char)tmp[i])) { + msg_perr("Invalid char \"%c\" in SPI command " + "blacklist\n", tmp[i]); + free(tmp); + return 1; + } + } + for (i = 0; i < spi_blacklist_size; i++) { + sscanf(tmp + i * 2, "%2hhx", &spi_blacklist[i]); + } + msg_pdbg("SPI blacklist is "); + for (i = 0; i < spi_blacklist_size; i++) + msg_pdbg("%02x ", spi_blacklist[i]); + msg_pdbg(", size %i\n", spi_blacklist_size); + } + free(tmp); + + tmp = extract_programmer_param("spi_ignorelist"); + if (tmp) { + i = strlen(tmp); + if (!strncmp(tmp, "0x", 2)) { + i -= 2; + memmove(tmp, tmp + 2, i + 1); + } + if ((i > 512) || (i % 2)) { + msg_perr("Invalid SPI command ignorelist length\n"); + free(tmp); + return 1; + } + spi_ignorelist_size = i / 2; + for (i = 0; i < spi_ignorelist_size * 2; i++) { + if (!isxdigit((unsigned char)tmp[i])) { + msg_perr("Invalid char \"%c\" in SPI command " + "ignorelist\n", tmp[i]); + free(tmp); + return 1; + } + } + for (i = 0; i < spi_ignorelist_size; i++) { + sscanf(tmp + i * 2, "%2hhx", &spi_ignorelist[i]); + } + msg_pdbg("SPI ignorelist is "); + for (i = 0; i < spi_ignorelist_size; i++) + msg_pdbg("%02x ", spi_ignorelist[i]); + msg_pdbg(", size %i\n", spi_ignorelist_size); + } + free(tmp); + #if EMULATE_CHIP tmp = extract_programmer_param("emulate"); if (!tmp) { @@ -348,7 +417,7 @@ const unsigned char *writearr, unsigned char *readarr) { - unsigned int offs; + unsigned int offs, i; static int unsigned aai_offs; static int aai_active = 0; @@ -356,7 +425,24 @@ msg_perr("No command sent to the chip!\n"); return 1; } - /* TODO: Implement command blacklists here. */ + /* spi_blacklist has precedence before spi_ignorelist. */ + for (i = 0; i < spi_blacklist_size; i++) { + if (writearr[0] == spi_blacklist[i]) { + msg_pdbg("Refusing blacklisted SPI command 0x%02x\n", + spi_blacklist[i]); + return SPI_INVALID_OPCODE; + } + } + for (i = 0; i < spi_ignorelist_size; i++) { + if (writearr[0] == spi_ignorelist[i]) { + msg_cdbg("Ignoring ignorelisted SPI command 0x%02x\n", + spi_ignorelist[i]); + /* Return success because the command does not fail, + * it is simply ignored. + */ + return 0; + } + } switch (writearr[0]) { case JEDEC_RES: if (emu_chip != EMULATE_ST_M25P10_RES) @@ -563,7 +649,7 @@ case EMULATE_SST_SST25VF032B: if (emulate_spi_chip_response(writecnt, readcnt, writearr, readarr)) { - msg_perr("Invalid command sent to flash chip!\n"); + msg_pdbg("Invalid command sent to flash chip!\n"); return 1; } break; Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Tue Feb 7 22:29:48 2012 (r1489) +++ trunk/flashrom.8 Thu Feb 9 00:28:54 2012 (r1490) @@ -421,6 +421,28 @@ Example: .sp .B " flashrom -p dummy:emulate=M25P10.RES,spi_write_256_chunksize=5" +.sp +To simulate a programmer which refuses to send certain SPI commands to the +flash chip, you can specify a blacklist of SPI commands with the +.sp +.B " flashrom -p dummy:spi_blacklist=commandlist" +.sp +syntax where commandlist is a list of two-digit hexadecimal representations of +SPI commands. If commandlist is e.g. 0302, flashrom will behave as if the SPI +controller refuses to run command 0x03 (READ) and command 0x02 (WRITE). +commandlist may be up to 512 characters (256 commands) long. +Implementation note: flashrom will detect an error during command execution. +.sp +To simulate a flash chip which ignores (doesn't support) certain SPI commands, +you can specify an ignorelist of SPI commands with the +.sp +.B " flashrom -p dummy:spi_ignorelist=commandlist" +.sp +syntax where commandlist is a list of two-digit hexadecimal representations of +SPI commands. If commandlist is e.g. 0302, the emulated flash chip will ignore +command 0x03 (READ) and command 0x02 (WRITE). commandlist may be up to 512 +characters (256 commands) long. +Implementation note: flashrom won't detect an error during command execution. .TP .BR "nic3com" , " nicrealtek" , " nicsmc1211" , " nicnatsemi" , " nicintel\ " , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\

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Re: [flashrom] FAILED : mcp61sm -am
by Stefan Tauner 09 Feb '12

09 Feb '12

On Wed, 8 Feb 2012 20:47:13 +0100 Vince S <vince06fr(a)gmail.com> wrote: > can i restore my bios from my linux session or do i have to reboot (i have > another bios with i can reboot) to flash it from a freedos live usb? *if* you are talking about the acer you reported last month and *if* i understood your question correctly, *then* you should be able to write the flash chip with flashrom in your linux session. your previous log confirmed at least that erasing works. writing will almost always work if erase works. if you read out the good contents with -r, install the bad chip, write the previously read good content with -w, the two chips should be identical. please ask further questions if something is not clear. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add support for SFDP (JESD216).
by Carl-Daniel Hailfinger 08 Feb '12

08 Feb '12

Am 31.01.2012 06:59 schrieb Stefan Tauner: > Similar to modules using the opaque programmer framework (e.g. ICH Hardware > Sequencing) this uses a template struct flashchip element in flashchips.c with > a special probe function that fills the obtained values into that struct. > > This allows yet unknown SPI chips to be supported (read, erase, write) almost > as if it was already added to flashchips.c. > > Documentation used: > http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) > W25Q32BV data sheet Revision F (2011-04-01) > EN25QH16 data sheet Revision F (2011-06-01) > > todo: > - handle programmers which have a problem with the dummy bytes needed AMD SB[678]x0 SPI has a way to specify sending one dummy byte between write and read, IIRC it is called DropOneClkOnRead or somthing like that. Quite a few other SPI masters have the one-dummy-byte functionality as well. This needs to be implemented in a generic way (I have a totally bitrotted patch for it), but it should not hold back this patch. > - move sfdp_add_uniform_eraser to spi25.c for further use like > spi_get_erasefn_from_opcode? > - is setting the generic SPI unlock method safe? > - what page_size should be set? > > Tested-by: David Hendricks <dhendrix(a)google.com> > on W25Q64CV > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > Makefile | 2 +- > chipdrivers.h | 4 + > flash.h | 2 + > flashchips.c | 23 ++++ > flashchips.h | 1 + > flashrom.c | 28 +++++- > sfdp.c | 355 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > spi.h | 5 + > spi25.c | 31 +++++ > 9 files changed, 449 insertions(+), 2 deletions(-) > create mode 100644 sfdp.c > > diff --git a/Makefile b/Makefile > index 83aa038..b890d8a 100644 > --- a/Makefile > +++ b/Makefile > @@ -252,7 +252,7 @@ endif > CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ > sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ > sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ > - a25.o at25.o opaque.o > + a25.o at25.o opaque.o sfdp.o > > LIB_OBJS = layout.o > > diff --git a/chipdrivers.h b/chipdrivers.h > index a1d0cd9..bd81098 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -41,6 +41,7 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int b > int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); > int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen); > int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); > +erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); > int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); > int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); > int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, int unsigned len); > @@ -58,6 +59,9 @@ int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, u > int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); > int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); > > +/* sfdp.c */ > +int probe_spi_sfdp(struct flashctx *flash); > + > /* opaque.c */ > int probe_opaque(struct flashctx *flash); > int read_opaque(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); > diff --git a/flash.h b/flash.h > index e51b6d4..6bcae71 100644 > --- a/flash.h > +++ b/flash.h > @@ -174,6 +174,8 @@ struct flashctx { > struct registered_programmer *pgm; > }; > > +typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); I believe that typedef to be pretty unreadable, but I see that avoiding the typedef would probably be even worse. > + > #define TEST_UNTESTED 0 > > #define TEST_OK_PROBE (1 << 0) > diff --git a/flashchips.c b/flashchips.c > index 0c8257b..b22e709 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -8872,6 +8872,29 @@ const struct flashchip flashchips[] = { > .read = read_memmapped, > .voltage = {3000, 3600}, /* Also has 12V fast program */ > }, > + > + { > + .vendor = "Unknown", > + .name = "SFDP device", > + .bustype = BUS_SPI, > + .manufacture_id = GENERIC_MANUF_ID, > + .model_id = SFDP_DEVICE_ID, > + /* We present our own "report this" text hence we do not > + * want the default "This flash part has status UNTESTED..." > + * text to be printed. */ > + .tested = TEST_OK_PREW, > + .probe = probe_spi_sfdp, > + .unlock = spi_disable_blockprotect, /* is this safe? */ Should be safe AFAICS, but that's not a hard statement, it's a gut feeling. > + .read = spi_chip_read, > + .page_size = 256, /* ? */ Argh, page_size comes to bite us again. Did I already send my "kill most uses of page_size" patch? > + /* FIXME: some vendor extensions define this */ > + .voltage = {}, > + /* Everything below will be set by the probing function. */ > + .write = NULL, > + .total_size = 0, > + .feature_bits = 0, > + .block_erasers = {}, > + }, > > { > .vendor = "Unknown", > diff --git a/flashchips.h b/flashchips.h > index 03efb86..1f2a8ca 100644 > --- a/flashchips.h > +++ b/flashchips.h > @@ -36,6 +36,7 @@ > > #define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */ > #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ > +#define SFDP_DEVICE_ID 0xfffe Side note: Should we move PROGMANUF_ID and its companion from the bottom of the file to this location to have generic match IDs in one place? > > #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ > #define ALLIANCE_AS29F002B 0x34 > diff --git a/flashrom.c b/flashrom.c > index ee68344..84fb3fc 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -986,7 +986,33 @@ int probe_flash(struct registered_programmer *pgm, int startchip, > * probe_flash() is the first one and thus no chip has been > * found before. The comment above is not really valid anymore. Can you include the following snippet in your patch? @@ -980,11 +980,10 @@ /* If this is the first chip found, accept it. * If this is not the first chip found, accept it only if it is - * a non-generic match. - * We could either make chipcount global or provide it as - * parameter, or we assume that startchip==0 means this call to - * probe_flash() is the first one and thus no chip has been - * found before. + * a non-generic match. SFDP and CFI are generic matches. + * startchip==0 means this call to probe_flash() is the first + * one for this programmer interface and thus no other chip has + * been found on this interface. */ if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) break; > */ > - if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) > + if (startchip == 0 && fill_flash->model_id == SFDP_DEVICE_ID) { > + msg_cinfo("===\n" > + "SFDP has autodetected a flash chip which is " > + "not natively supported by flashrom yet.\n"); > + if (count_usable_erasers(fill_flash) == 0) > + msg_cinfo("The standard operations read and " > + "verify should work, but to support " > + "erase, write and all other " > + "possible features"); > + else > + msg_cinfo("All standard operations (read, " > + "verify, erase and write) should " > + "work, but to support all possible " > + "features"); > + > + msg_cinfo(" we need to add them manually.\nYou " > + "can help us by mailing us the output of " > + "the following command to flashrom@flashrom." > + "org: \n'flashrom -VV [plus the " > + "-p/--programmer parameter (if needed)]" > + "'\nThanks for your help!\n" > + "===\n"); > + } > + > + if (startchip == 0 || > + ((fill_flash->model_id != GENERIC_DEVICE_ID) && > + (fill_flash->model_id != SFDP_DEVICE_ID))) > break; > > notfound: > diff --git a/sfdp.c b/sfdp.c > new file mode 100644 > index 0000000..7c00ff5 > --- /dev/null > +++ b/sfdp.c > @@ -0,0 +1,355 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (C) 2011-2012 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#include <stdint.h> > +#include <stdlib.h> > +#include "flash.h" > +#include "spi.h" > +#include "chipdrivers.h" > + > +static int spi_sfdp_wrapper(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) > +{ > + int i, ret; > + const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { > + JEDEC_SFDP, > + (address >> 16) & 0xff, > + (address >> 8) & 0xff, > + (address >> 0) & 0xff, > + 0 > + }; > + msg_cspew("spi_sfdp_wrapper: addr=0x%x, len=%d, data:\n", address, len); > + ret = spi_send_command(flash, sizeof(cmd), len, cmd, buf); > + for (i = 0; i < len; i++) > + msg_cspew(" 0x%02x", buf[i]); > + msg_cspew("\n"); > + return ret; > +} > + > +/* FIXME: eventually something similar like this but more generic should be > + * available to split up spi commands. use that then instead */ > +static int spi_sfdp(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) > +{ > + /* FIXME: this is wrong. */ > + int maxstep = 8; Yes, maxstep should be a programmer-specific setting. However, with our current infrastructure there is no way to fix this easily. > + int ret = 0; > + while (len > 0) { > + int step = min(len, maxstep); > + ret = spi_sfdp_wrapper(flash, address, buf, step); > + if (ret) Actually, there is probably a way to determine optimal size for those SFDP requests: Check if ret indicates a "command too long" error and reduce maxstep by one in that case, then retry. Such code is not exactly pretty and I'm not sure if all SPI masters have such a differentiated error code reporting. > + return ret; > + address += step; > + buf += step; > + len -= step; > + } > + return ret; > +} > + > +struct sfdp_tbl_hdr { > + uint8_t id; > + uint8_t v_minor; > + uint8_t v_major; > + uint8_t len; > + uint32_t ptp; /* 24b pointer */ > +}; > + > +static int sfdp_add_uniform_eraser(struct flashctx *f, uint8_t opcode, uint32_t bsize) struct flashctx *flash Just "f" is too short, and if you try to search for it, you'll get thousands of matches you don't want. bsize or blocksize? I prefer the latter for consistency and readability reasons. > +{ > + uint32_t total_size = f->total_size * 1024; > + int i; > + erasefunc_t *erasefn = spi_get_erasefn_from_opcode(opcode); > + if (erasefn == NULL) > + return 1; > + for (i = 0; i < NUM_ERASEFUNCTIONS; i++) { > + struct block_eraser *eraser = &f->block_erasers[i]; > + if (eraser->eraseblocks[0].size != 0 || !eraser->block_erase) > + continue; > + eraser->block_erase = erasefn; > + eraser->eraseblocks[0].size = bsize; > + eraser->eraseblocks[0].count = total_size/bsize; > + msg_cdbg2(" Block eraser %d: %d x %d B with opcode " > + "0x%02x\n", i, total_size/bsize, bsize, > + opcode); > + return 0; > + } > + msg_cinfo("%s: Not enough space to store another eraser (i=%d)." msg_cerr? > + " Please report this at flashrom(a)flashrom.org\n", > + __func__, i); > + return 1; > +} > + Rest of review follows later. > +static int sfdp_fill_flash(struct flashctx *f, uint8_t *buf, uint16_t len) > +{ > + uint32_t tmp32; > + uint8_t tmp8; > + uint32_t total_size; /* in bytes */ > + uint32_t bsize; > + uint8_t opcode_4k = 0xFF; > + int dw, j; > + > + msg_cdbg("Parsing JEDEC SFDP parameter table... "); > + if (len != 9 * 4 && len != 4 * 4) { > + msg_cerr("%s: len out of spec\n", __func__); > + return 1; > + } > + msg_cdbg2("\n"); > + > + /* 1. double word */ > + dw = 0; > + tmp32 = buf[(4 * dw) + 0]; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; > + > + tmp8 = (tmp32 >> 17) & 0x3; > + switch (tmp8) { > + case 0x0: > + msg_cdbg2(" 3-Byte only addressing.\n"); > + break; > + case 0x1: > + msg_cdbg2(" 3-Byte (and optionally 4-Byte) addressing.\n"); > + break; > + case 0x2: > + msg_cdbg(" 4-Byte only addressing not supported.\n"); > + return 1; > + default: > + msg_cdbg(" Required addressing mode (0x%x) not supported.\n", > + tmp8); > + return 1; > + } > + > + msg_cdbg2(" Writes to the status register have "); > + if (tmp32 & (1 << 3)) { > + msg_cdbg2("to be enabled with "); > + if (tmp32 & (1 << 4)) { > + f->feature_bits = FEATURE_WRSR_WREN; > + msg_cdbg2("WREN (0x06).\n"); > + } else { > + f->feature_bits = FEATURE_WRSR_EWSR; > + msg_cdbg2("EWSR (0x50).\n"); > + } > + } else > + msg_cdbg2("not to be especially enabled.\n"); > + > + msg_cdbg2(" Write granularity is "); > + if (tmp32 & (1 << 2)) { > + msg_cdbg2("at least 64 B.\n"); > + f->write = spi_chip_write_256; > + } else { > + msg_cdbg2("1 B only.\n"); > + f->write = spi_chip_write_1; > + } > + > + if ((tmp32 & 0x3) == 0x1) { > + opcode_4k = (tmp32 >> 8) & 0xFF; /* will be dealt with later */ > + } > + > + /* 2. double word */ > + dw = 1; > + tmp32 = buf[(4 * dw) + 0]; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; > + > + if (tmp32 & (1 << 31)) { > + msg_cerr("Flash chip size >= 4 Gb/512 MB not supported.\n"); > + return 1; > + } > + total_size = ((tmp32 & 0x7FFFFFFF) + 1) / 8; > + f->total_size = total_size / 1024; > + msg_cdbg2(" Flash chip size is %d kB.\n", f->total_size); > + > + /* FIXME: double words 3-7 contain unused fast read information */ > + > + if (len == 4 * 4) { > + msg_cdbg("It seems like this chip supports the preliminary " > + "Intel version of SFDP, skipping processing of double " > + "words 3-9.\n"); > + goto proc_4k; > + } > + > + dw = 8; > + for (j = 0; j < 4; j++) { > + /* 8 double words from the start + 2 words for every eraser */ > + tmp32 = buf[(4 * dw) + (2 * j)]; > + if (tmp32 == 0) { > + msg_cdbg2(" Block eraser %d is unused.\n", j); > + continue; > + } > + if (tmp32 >= 31) { > + msg_cdbg2(" Block size of eraser %d (2^%d) is too big." > + "\n", j, tmp32); > + continue; > + } > + bsize = 1 << (tmp32); /* bsize = 2 ^ field */ > + > + tmp8 = buf[(4 * dw) + (2 * j) + 1]; > + if(sfdp_add_uniform_eraser(f, tmp8, bsize)) > + continue; > + /* If there is a valid 4k value in the last double words, > + * we want to override the value from double word 1, hence force > + * skipping its processing: */ > + if (bsize == 4 * 1024) > + opcode_4k = 0xFF; > + } > + > +proc_4k: > + if (opcode_4k != 0xFF) { > + sfdp_add_uniform_eraser(f, opcode_4k, 4 * 1024); > + } > + msg_cdbg("done.\n"); > + return 0; > +} > + > +static int sfdp_fetch_pt(struct flashctx *flash, uint32_t addr, uint8_t *buf, uint16_t len) > +{ > + uint16_t i; > + if (spi_sfdp(flash, addr, buf, len)) { > + msg_cerr("Receiving SFDP parameter table failed.\n"); > + return 1; > + } > + msg_cspew(" Parameter table contents:\n"); > + for(i = 0; i < len; i++) { > + if ((i % 8) == 0) { > + msg_cspew(" 0x%03x: ", i); > + } > + msg_cspew(" 0x%02x", buf[i]); > + if ((i % 8) == 7) { > + msg_cspew("\n"); > + continue; > + } > + if ((i % 8) == 3) { > + msg_cspew(" "); > + continue; > + } > + } > + msg_cspew("\n"); > + return 0; > +} > + > +int probe_spi_sfdp(struct flashctx *flash) > +{ > + int ret = 0; > + uint8_t buf[8]; > + uint32_t tmp32; > + uint8_t nph; > + /* need to limit the table loop by comparing i to uint8_t nph hence: */ > + uint16_t i; > + struct sfdp_tbl_hdr *hdrs; > + uint8_t *hbuf; > + uint8_t *tbuf; > + > + if (spi_sfdp(flash, 0x00, buf, 4)) { > + msg_cerr("Receiving SFDP signature failed.\n"); > + return 0; > + } > + tmp32 = buf[0]; > + tmp32 |= ((unsigned int)buf[1]) << 8; > + tmp32 |= ((unsigned int)buf[2]) << 16; > + tmp32 |= ((unsigned int)buf[3]) << 24; > + > + msg_cdbg2("SFDP signature = 0x%08x (should be 0x50444653)\n", tmp32); > + if (tmp32 != 0x50444653) { > + msg_cdbg("No SFDP signature found.\n"); > + return 0; > + } > + if (spi_sfdp(flash, 0x04, buf, 3)) { > + msg_cerr("Receiving SFDP revision and number of parameter " > + "headers (NPH) failed. "); > + return 0; > + } > + msg_cdbg2("SFDP revision = %d.%d\n", buf[1], buf[0]); > + nph = buf[2]; > + msg_cdbg2("SFDP number of parameter headers (NPH) = %d (+ 1 mandatory)" > + "\n", nph); > + > + /* Fetch all parameter headers, even if we don't use them all (yet). */ > + hbuf = malloc(sizeof(struct sfdp_tbl_hdr) * (nph + 1)); > + hdrs = malloc((nph + 1) * 8); > + if (hbuf == NULL || hdrs == NULL ) { > + msg_gerr("Out of memory!\n"); > + exit(1); /* FIXME: shutdown gracefully */ > + } > + if (spi_sfdp(flash, 0x08, hbuf, (nph + 1) * 8)) { > + msg_cerr("Receiving SFDP parameter table headers failed.\n"); > + goto cleanup_hdrs; > + } > + > + i = 0; > + do { > + uint16_t len; > + hdrs[i].id = hbuf[(8 * i) + 0]; > + hdrs[i].v_minor = hbuf[(8 * i) + 1]; > + hdrs[i].v_major = hbuf[(8 * i) + 2]; > + hdrs[i].len = hbuf[(8 * i) + 3]; > + hdrs[i].ptp = hbuf[(8 * i) + 4]; > + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; > + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; > + msg_cdbg2("SFDP parameter table header %d/%d:\n", i, nph); > + msg_cdbg2(" ID 0x%02x, version %d.%d\n", hdrs[i].id, > + hdrs[i].v_major, hdrs[i].v_minor); > + len = hdrs[i].len * 4; > + tmp32 = hdrs[i].ptp; > + msg_cdbg2(" Length %d B, Parameter Table Pointer 0x%06x\n", > + len, tmp32); > + > + if (len + tmp32 > UINT16_MAX) { > + msg_cerr("SFDP Parameter Table %d supposedly " > + "overflows addressable SFDP area. This most\n" > + "probably indicates a corrupt SFDP parameter " > + "table header. Aborting SFDP probe!\n", i); > + ret = 0; > + goto cleanup_hdrs; > + } > + > + tbuf = malloc(len); > + if (tbuf == NULL) { > + msg_gerr("Out of memory!\n"); > + exit(1); /* FIXME: shutdown gracefully */ > + } > + if (sfdp_fetch_pt(flash, tmp32, tbuf, len)){ > + msg_cerr("Fetching SFDP parameter table %d failed.\n", > + i); > + free(tbuf); > + break; > + } > + if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ > + if (hdrs[i].id != 0) > + msg_cdbg("ID of the mandatory JEDEC SFDP " > + "parameter table is not 0 as demanded " > + "by JESD216 (warning only).\n"); > + > + if (len != 9 * 4 && len != 4 * 4) { > + msg_cdbg("Length of the mandatory JEDEC SFDP " > + "parameter table is %d B instead of " > + "36 B (i.e. 9 double words) as " > + "demanded by JESD216, skipping " > + "parsing.\n", len); > + } else if (sfdp_fill_flash(flash, tbuf, len) == 0) > + ret = 1; > + } > + > + free(tbuf); > + i++; > + } while(i <= nph); > + > +cleanup_hdrs: > + free(hdrs); > + free(hbuf); > + return ret; > +} Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

Re: [flashrom] FAILED : mcp61sm -am
by Joshua Roys 08 Feb '12

08 Feb '12

On 02/08/2012 02:47 PM, Vince S wrote: > can i restore my bios from my linux session or do i have to reboot (i > have another bios with i can reboot) to flash it from a freedos live usb? > > Hello, Please do NOT reboot. Can you provide the log of when flashrom failed? Also, if you made a backup, you can see if your BIOS is still intact by running `flashrom -v /path/to/backup.foo` Thanks, Josh

1 0

FAILED : mcp61sm -am
by Vince S 08 Feb '12

08 Feb '12

can i restore my bios from my linux session or do i have to reboot (i have another bios with i can reboot) to flash it from a freedos live usb?

1 0

[PATCH] dummy programmer: blacklist SPI commands
by Carl-Daniel Hailfinger 08 Feb '12

08 Feb '12

Add optional SPI command blacklisting to the flash chip emulator in the dummy programmer. Usage: flashrom -p dummy:spi_blacklist=hexstring If hexstring is 0302, flashrom will blacklist command 0x03 (READ) and command 0x02 (WRITE). The hexstring can have up to 521 bytes (256 commands) length, and must not start with 0x. TODO: Should 0x at the beginning of hexstring be tolerated? Very useful for testing corner cases if you don't own a locked down Intel chipset and want to simulate such a thing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-emulate_spi_flashchip_command_blacklist/dummyflasher.c =================================================================== --- flashrom-emulate_spi_flashchip_command_blacklist/dummyflasher.c (Revision 1224) +++ flashrom-emulate_spi_flashchip_command_blacklist/dummyflasher.c (Arbeitskopie) @@ -19,6 +19,7 @@ #include <string.h> #include <stdlib.h> +#include <stdio.h> #include <ctype.h> #include "flash.h" #include "chipdrivers.h" @@ -56,6 +57,8 @@ static int emu_jedec_be_d8_size = 0; static int emu_jedec_ce_60_size = 0; static int emu_jedec_ce_c7_size = 0; +unsigned char spi_blacklist[256]; +int spi_blacklist_size = 0; #endif #endif @@ -71,6 +74,7 @@ { char *bustext = NULL; char *tmp = NULL; + int i; #if EMULATE_CHIP struct stat image_stat; #endif @@ -116,6 +120,31 @@ } } + tmp = extract_programmer_param("spi_blacklist"); + if (tmp) { + i = strlen(tmp); + if (i % 2) { + msg_perr("Invalid SPI command blacklist\n"); + free(tmp); + return 1; + } + tolower_string(tmp); + if (strspn(tmp, "0123456789abcdef") != i) { + msg_perr("Invalid SPI command blacklist\n"); + free(tmp); + return 1; + } + spi_blacklist_size = i / 2; + for (i = 0; i < spi_blacklist_size; i++) { + sscanf(tmp, "%2hhx", &spi_blacklist[i]); + } + msg_pdbg("SPI blacklist is "); + for (i = 0; i < spi_blacklist_size; i++) + msg_pdbg("%02x ", spi_blacklist[i]); + msg_pdbg(", size %i\n", spi_blacklist_size); + } + free(tmp); + #if EMULATE_CHIP tmp = extract_programmer_param("emulate"); if (!tmp) { @@ -285,7 +314,7 @@ static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - int offs; + int offs, i; static int aai_offs; static int aai_active = 0; @@ -293,7 +322,16 @@ msg_perr("No command sent to the chip!\n"); return 1; } - /* TODO: Implement command blacklists here. */ + for (i = 0; i < spi_blacklist_size; i++) { + if (writearr[0] == spi_blacklist[i]) { + msg_perr("Refusing blacklisted SPI command 0x%02x\n", + spi_blacklist[i]); + /* FIXME: Do we want a separate return code for + * command unavailable? + */ + return 1; + } + } switch (writearr[0]) { case JEDEC_RES: if (emu_chip != EMULATE_ST_M25P10_RES) -- http://www.hailfinger.org/

3 7

[PATCH] Add RDC R6030 chipset
by Rudolf Marek 07 Feb '12

07 Feb '12

Hello, Following patch adds the support for ROMCS_EN for writes aka chipset_enable on RDC R6030 found on bifferboard. The patch for flashchip will follow in near future. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks Rudolf

2 6

[commit] r1489 - trunk
by repository service 07 Feb '12

07 Feb '12

Author: stefanct Date: Tue Feb 7 22:29:48 2012 New Revision: 1489 URL: http://flashrom.org/trac/flashrom/changeset/1489 Log: Add support for RDC R6030 chipset Tested on Bifferboard. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c trunk/print.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Feb 3 23:32:09 2012 (r1488) +++ trunk/chipset_enable.c Tue Feb 7 22:29:48 2012 (r1489) @@ -54,6 +54,32 @@ return 0; } +static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name) +{ + uint8_t tmp; + + /* enable ROMCS for writes */ + tmp = pci_read_byte(dev, 0x43); + tmp |= 0x80; + pci_write_byte(dev, 0x43, tmp); + + /* read the bootstrapping register */ + tmp = pci_read_byte(dev, 0x40) & 0x3; + switch (tmp) { + case 3: + internal_buses_supported = BUS_FWH; + break; + case 2: + internal_buses_supported = BUS_LPC; + break; + default: + internal_buses_supported = BUS_PARALLEL; + break; + } + + return 0; +} + static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -1235,6 +1261,7 @@ {0x1106, 0x8409, OK, "VIA", "VX855/VX875", enable_flash_vt823x}, {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, + {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, {0x8086, 0x1c44, OK, "Intel", "Z68", enable_flash_pch6}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Fri Feb 3 23:32:09 2012 (r1488) +++ trunk/print.c Tue Feb 7 22:29:48 2012 (r1489) @@ -692,6 +692,7 @@ B("ASUS", "Z8NA-D6C", 1, "http://www.asus.com/Server_Workstation/Server_Motherboards/Z8NAD6C/", NULL), B("ASUS", "Z8PE-D12", 1, "http://www.asus.com/Server_Workstation/Server_Motherboards/Z8PED12/", NULL), B("BCOM", "WinNET100", 1, "http://www.coreboot.org/BCOM_WINNET100", "Used in the IGEL-316 thin client."), + B("Bifferos", "Bifferboard", 1, "http://bifferos.co.uk/", NULL), B("Biostar", "N68S3+", 1, NULL, NULL), B("Biostar", "M6TBA", 0, "ftp://ftp.biostar-usa.com/manuals/M6TBA/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), B("Biostar", "M7NCD Pro", 1, "http://www.biostar.com.tw/app/en/mb/content.php?S_ID=260", NULL),

1 0

MS-7548 mainboard works
by Richard Albright 07 Feb '12

07 Feb '12

flashed a hp pavilion a6750f successfully -- *Rick Albright* Senior Quantitative Analyst Web: www.insiderscore.com <https://www.insiderscore.com/> Email: ralbright(a)insiderscore.com <mailto:ralbright@insiderscore.com>

2 1

Re: [flashrom] Hello, flashrom problem
by Stefan Tauner 07 Feb '12

07 Feb '12

On Tue, 7 Feb 2012 10:43:51 +0200 Elena Gusanu <elena.gusanu(a)gmail.com> wrote: > I tried but it doesn't work. Hello Elena, Carl-Daniel had the impression that you did just a non-writing run with flashrom (i.e. calling flashrom without any of the -w and -E parameters). It seems that you have done more permanent harm and we need to know more details to be able to help (if at all). What hardware/laptop are we talking about? Which version of flashrom did you use (which distribution? Which command line arguments did you use? Can you remember any error messages it showed when you ran it? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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