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Re: [flashrom] dediprog: Use command 0x0B only on older SF100s
by Stefan Tauner 24 Jan '16

24 Jan '16

On Sun, 2 Aug 2015 15:09:40 -0700 David Hendricks <dhendrix(a)chromium.org> wrote: > As per e-mail with Dediprog, command 0x0B (which is not listed in the > command spec) is used to set voltage level on older Dediprogs. SF100 > V6.0.0 and newer as well as all SF600 programmers do not support it. > > This patch renames dediprog_device_init() to something more > appropriate and adds comments for clarity, and only runs it > conditionally if we cannot query the devicestring during init. > > Tested with SF100 V:5.1.5 and SF600 V:7.1.4 (with subsequent patches) > Signed-off-by: David Hendricks <dhendrix(a)chromium.org> As I said on gerrit, I would really like to know what this really does. There is another function to change the SPI VCC so this is probably something else... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 1/3] Print all compile commands to the build details file as well.
by Carl-Daniel Hailfinger 24 Jan '16

24 Jan '16

On 18.01.2016 00:28, Stefan Tauner wrote: > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> I'm not totally happy about not logging the commands during actual compilation. That way, if something fails after the configure phase, we need both a paste from the shell and the debug log file. Anyway... Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel

2 1

[commit] r1919 - trunk
by repository service 24 Jan '16

24 Jan '16

Author: stefanct Date: Sun Jan 24 23:37:10 2016 New Revision: 1919 URL: http://flashrom.org/trac/flashrom/changeset/1919 Log: Makefile: print compile commands of configure steps to the build details file. This allows for even more easy debugging of build failures due to problems with libraries. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Jan 24 00:27:58 2016 (r1918) +++ trunk/Makefile Sun Jan 24 23:37:10 2016 (r1919) @@ -856,6 +856,7 @@ compiler: featuresavailable @printf "Checking for a C compiler... " | tee -a $(BUILD_DETAILS_FILE) @echo "$$COMPILER_TEST" > .test.c + @printf "\nexec: %s\n" "$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .test.c -o .test$(EXEC_SUFFIX)" >>$(BUILD_DETAILS_FILE) @{ { { { { $(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .test.c -o .test$(EXEC_SUFFIX) >&2 && \ echo "found." || { echo "not found."; \ rm -f .test.c .test$(EXEC_SUFFIX); exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 @@ -938,6 +939,7 @@ ifeq ($(CHECK_LIBPCI), yes) @printf "Checking for libpci headers... " | tee -a $(BUILD_DETAILS_FILE) @echo "$$LIBPCI_TEST" > .test.c + @printf "\nexec: %s\n" "$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o" >>$(BUILD_DETAILS_FILE) @{ { { { { $(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >&2 && \ echo "found." || { echo "not found."; echo; \ echo "Please install libpci headers."; \ @@ -945,14 +947,17 @@ rm -f .test.c .test.o; exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 @printf "Checking version of pci_get_dev... " | tee -a $(BUILD_DETAILS_FILE) @echo "$$PCI_GET_DEV_TEST" > .test.c + @printf "\nexec: %s\n" "$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o" >>$(BUILD_DETAILS_FILE) @ { $(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >&2 && \ ( echo "new version (including PCI domain parameter)."; echo "OLD_PCI_GET_DEV := no" >> .libdeps ) || \ ( echo "old version (without PCI domain parameter)."; echo "OLD_PCI_GET_DEV := yes" >> .libdeps ) } 2>>$(BUILD_DETAILS_FILE) | tee -a $(BUILD_DETAILS_FILE) @printf "Checking if libpci is present and sufficient... " | tee -a $(BUILD_DETAILS_FILE) + @printf "\nexec: %s\n" "$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(PCILIBS)" >>$(BUILD_DETAILS_FILE) @{ { { { $(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(PCILIBS) 2>>$(BUILD_DETAILS_FILE) >&2 && \ echo "yes." || { echo "no."; \ printf "Checking if libz+libpci are present and sufficient..." ; \ - { $(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(PCILIBS) -lz >&2 && \ + { printf "\nexec: %s\n" "$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(PCILIBS) -lz" >>$(BUILD_DETAILS_FILE) ; \ + $(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(PCILIBS) -lz >&2 && \ echo "yes." && echo "NEEDLIBZ := yes" > .libdeps } || { echo "no."; echo; \ echo "Please install libpci (package pciutils) and/or libz."; \ echo "See README for more information."; echo; \ @@ -962,12 +967,14 @@ ifeq ($(CHECK_LIBUSB0), yes) @printf "Checking for libusb-0.1/libusb-compat headers... " | tee -a $(BUILD_DETAILS_FILE) @echo "$$LIBUSB0_TEST" > .test.c + @printf "\nexec: %s\n" "$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o" >>$(BUILD_DETAILS_FILE) @{ { { { { $(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >&2 && \ echo "found." || { echo "not found."; echo; \ echo "Please install libusb-0.1 headers or libusb-compat headers."; \ echo "See README for more information."; echo; \ rm -f .test.c .test.o; exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 @printf "Checking if libusb-0.1 is usable... " | tee -a $(BUILD_DETAILS_FILE) + @printf "\nexec: %s\n" "$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USBLIBS)" >>$(BUILD_DETAILS_FILE) @{ { { { { $(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USBLIBS) >&2 && \ echo "yes." || { echo "no."; \ echo "Please install libusb-0.1 or libusb-compat."; \ @@ -1055,10 +1062,12 @@ ifeq ($(NEED_FTDI), yes) @printf "Checking for FTDI support... " | tee -a $(BUILD_DETAILS_FILE) @echo "$$FTDI_TEST" > .featuretest.c + @printf "\nexec: %s\n" "$(CC) $(CPPFLAGS) $(CFLAGS) $(FTDI_INCLUDES) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS)" >>$(BUILD_DETAILS_FILE) @ { $(CC) $(CPPFLAGS) $(CFLAGS) $(FTDI_INCLUDES) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS) >&2 && \ ( echo "found."; echo "FTDISUPPORT := yes" >> .features.tmp ; \ printf "Checking for FT232H support in libftdi... " ; \ echo "$$FTDI_232H_TEST" >> .featuretest.c ; \ + printf "\nexec: %s\n" "$(CC) $(CPPFLAGS) $(CFLAGS) $(FTDI_INCLUDES) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS)" >>$(BUILD_DETAILS_FILE) ; \ { $(CC) $(CPPFLAGS) $(CFLAGS) $(FTDI_INCLUDES) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS) >&2 && \ ( echo "found."; echo "FT232H := yes" >> .features.tmp ) || \ ( echo "not found."; echo "FT232H := no" >> .features.tmp ) } \ @@ -1069,6 +1078,7 @@ ifeq ($(CONFIG_LINUX_SPI), yes) @printf "Checking if Linux SPI headers are present... " | tee -a $(BUILD_DETAILS_FILE) @echo "$$LINUX_SPI_TEST" > .featuretest.c + @printf "\nexec: %s\n" "$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX)" >>$(BUILD_DETAILS_FILE) @ { $(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >&2 && \ ( echo "yes."; echo "LINUX_SPI_SUPPORT := yes" >> .features.tmp ) || \ ( echo "no."; echo "LINUX_SPI_SUPPORT := no" >> .features.tmp ) } \ @@ -1077,6 +1087,7 @@ ifeq ($(NEED_LINUX_I2C), yes) @printf "Checking if Linux I2C headers are present... " | tee -a $(BUILD_DETAILS_FILE) @echo "$$LINUX_I2C_TEST" > .featuretest.c + @printf "\nexec: %s\n" "$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX)" >>$(BUILD_DETAILS_FILE) @ { $(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >&2 && \ ( echo "yes."; echo "LINUX_I2C_SUPPORT := yes" >> .features.tmp ) || \ ( echo "no."; echo "LINUX_I2C_SUPPORT := no" >> .features.tmp ) } \ @@ -1084,6 +1095,7 @@ endif @printf "Checking for utsname support... " | tee -a $(BUILD_DETAILS_FILE) @echo "$$UTSNAME_TEST" > .featuretest.c + @printf "\nexec: %s\n" "$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX)" >>$(BUILD_DETAILS_FILE) @ { $(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >&2 && \ ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) } 2>>$(BUILD_DETAILS_FILE) | tee -a $(BUILD_DETAILS_FILE)

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FlexICE github (was: Issue with internal access to the W39V040FB)
by Stefan Tauner 24 Jan '16

24 Jan '16

On Sat, 23 Jan 2016 17:51:27 +0100 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > On Sat, 23 Jan 2016 19:32:14 +0300 > Andrey Korolyov <andrey(a)xdel.ru> wrote: > > > BTW, are there still any FWH-capable romulators in production? Looks > > like most of sockets from this era has been designed without bearing > > in mind possibility of the in-scheme reprogramming, but the only > > romulators I`ve seen on ebay are ancient devices bundled with software > > on floppies... > > You might be interested in https://www.coreboot.org/FlexyICE > I have just discovered that project a few weeks ago myself so I cannot > give much more information than that. It is probably not purchasable > anymore but open enough that one could build something new from that. > Sooner or later I am planning to give a related projected out as > Bachelor or Master thesis but that will take a while (and would > probably be SPI-related). I have freed the two repositories of the project from opencores (they require registration just to download and the registration process is manual!). Currently they reside in the flashrom realm of github: https://github.com/flashrom/artec_dongle_fpga https://github.com/flashrom/artec_dongle_ii_fpga -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Untested device success: M25PE40 - Read, Erase, Write (and apparently Probe?)
by Stefan Tauner 24 Jan '16

24 Jan '16

On Mon, 18 Jan 2016 16:18:59 -0500 David Wood <jbevren(a)gmail.com> wrote: > Hello, > > Stefanct on freenode:#flashrom requested I email this to you. > > I've successfully reprogrammed a M25PE40 device, which was listed as > untested by SVN flashrom. Setup info and related TTY log follows. > > http://pix.jbevren.net/e/LTV/leaptv-debrick > > The ROM is left in-circuit, and the LeapTV is powered up after the > Raspberry Pi boots. Power is provided by the LeapTV system board. More > relevant information is available on the page linked above, including an > image of the setup. Hello David, thanks for your report! I have marked the flash chip as fully tested and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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"Hewlett-Packard 3048h"
by Brandon Petersen 24 Jan '16

24 Jan '16

flashrom v0.9.6.1-r1563 on Linux 3.19.0-32-generic (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian Command line (3 args): flashrom --programmer internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 3188M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1004 us, 10000 myus = 9996 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Compaq 6000 Pro MT PC" DMI string system-version: " " DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "3048h" DMI string baseboard-version: "Not Specified" DMI string chassis-type: "Mini Tower" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 19. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel ICH10D" with PCI ID 8086:3a1a. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2 WARNING: Setting 0xdc from 0x2 to 0x3 on ICH10D failed. New value is 0x2. Root Complex Register Block address = 0xfed1c000 GCS = 0x465: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00001a1b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x03ff0260 FREG1: BIOS region (0x00260000-0x003fffff) is read-write. 0x5C: 0x025f000b FREG2: WARNING: Management Engine region (0x0000b000-0x0025ffff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. 0x64: 0x000a0003 FREG4: Platform Data region (0x00003000-0x0000afff) is read-write. 0x74: 0x83ff03fa PR0: WARNING: 0x003fa000-0x003fffff is read-only. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0x004200 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=0 0x94: 0x0606 (PREOP) 0x96: 0xb6f0 (OPTYPE) 0x98: 0x0220059f (OPMENU) 0x9C: 0x03020103 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00800000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=1 0xC8: 0x00002015 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=1, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) SPI Read Configuration: prefetching disabled, caching enabled, PROBLEMS, continuing anyway The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L3205" (4096 kB, SPI) at physical address 0xffc00000. Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x01, id2 0x2b, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x01, id2 0x2b, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x01, id2 0x2b, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x4b, id2 0x5d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x01, id2 0x2b, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x01, id2 0x2b, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xb1, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Macronix flash chip "MX25L3205" (4096 kB, SPI). No operations were specified. Restoring MMIO space at 0x7f75d284f8a0 Restoring PCI config space for 00:1f:0 reg 0xdc

1 0

[commit] r1918 - trunk
by repository service 24 Jan '16

24 Jan '16

Author: stefanct Date: Sun Jan 24 00:27:58 2016 New Revision: 1918 URL: http://flashrom.org/trac/flashrom/changeset/1918 Log: dediprog: support new communication protocol, cleanup and enable by default. The new protocol changes some commands, so adjust the code to support these. Use helper functions to reduce duplication in libusb calls. Testing with real hardware showed that the maximum read size via the control endpoint is about 16 bytes although specification does not mention that. Dediprog SF600 is not supported yet. Based on the following chromiumos changes: Change-Id: Ibd1e27d9e8273ba879b9b5d95675b99596255c89 Change-Id: Ifc33e7b1eed5b0cb80f83458fa24741a577fa46a Additionally, some ideas from Alex for cleaner code were incorporated as well. Tested on an SF100 V4 with both firmware generations PREWing a M25PX80 and AT45DB041D (the latter is using dediprog_spi_send_command() instead of optimized functions which make it a good test vehicle). Signed-off-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/Makefile trunk/dediprog.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat Jan 23 17:16:49 2016 (r1917) +++ trunk/Makefile Sun Jan 24 00:27:58 2016 (r1918) @@ -493,8 +493,8 @@ # Always enable Bus Pirate SPI for now. CONFIG_BUSPIRATE_SPI ?= yes -# Disable Dediprog SF100 until support is complete and tested. -CONFIG_DEDIPROG ?= no +# Always enable Dediprog SF100 for now. +CONFIG_DEDIPROG ?= yes # Always enable Marvell SATA controllers for now. CONFIG_SATAMV ?= yes Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Sat Jan 23 17:16:49 2016 (r1917) +++ trunk/dediprog.c Sun Jan 24 00:27:58 2016 (r1918) @@ -40,7 +40,7 @@ #define FIRMWARE_VERSION(x,y,z) ((x << 16) | (y << 8) | z) #define DEFAULT_TIMEOUT 3000 -#define REQTYPE_OTHER_OUT (USB_ENDPOINT_IN | USB_TYPE_VENDOR | USB_RECIP_OTHER) /* 0x43 */ +#define REQTYPE_OTHER_OUT (USB_ENDPOINT_OUT | USB_TYPE_VENDOR | USB_RECIP_OTHER) /* 0x43 */ #define REQTYPE_OTHER_IN (USB_ENDPOINT_IN | USB_TYPE_VENDOR | USB_RECIP_OTHER) /* 0xC3 */ #define REQTYPE_EP_OUT (USB_ENDPOINT_OUT | USB_TYPE_VENDOR | USB_RECIP_ENDPOINT) /* 0x42 */ #define REQTYPE_EP_IN (USB_ENDPOINT_IN | USB_TYPE_VENDOR | USB_RECIP_ENDPOINT) /* 0xC2 */ @@ -120,9 +120,9 @@ WRITE_MODE_128B_PAGE = 5, WRITE_MODE_PAGE_AT26DF041 = 6, WRITE_MODE_SILICON_BLUE_FPGA = 7, - WRITE_MODE_64B_PAGE_NUMONYX_PCM = 8, /* unit of length 512 bytes */ + WRITE_MODE_64B_PAGE_NUMONYX_PCM = 8, /* unit of 512 bytes */ WRITE_MODE_4B_ADDR_256B_PAGE_PGM = 9, - WRITE_MODE_32B_PAGE_PGM_MXIC_512K = 10, /* unit of length 512 bytes */ + WRITE_MODE_32B_PAGE_PGM_MXIC_512K = 10, /* unit of 512 bytes */ WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12 = 11, WRITE_MODE_4B_ADDR_256B_PAGE_PGM_FLAGS = 12, }; @@ -130,16 +130,26 @@ static int dediprog_firmwareversion = FIRMWARE_VERSION(0, 0, 0); -#if 0 -/* Might be useful for other pieces of code as well. */ -static void print_hex(void *buf, size_t len) +/* Returns true if firmware (and thus hardware) supports the "new" protocol */ +static bool is_new_prot(void) { - size_t i; + /* if (SF100) */ + return dediprog_firmwareversion >= FIRMWARE_VERSION(5, 5, 0); + /* else if (SF600) + return dediprog_firmwareversion >= FIRMWARE_VERSION(6, 9, 0); */ +} - for (i = 0; i < len; i++) - msg_pdbg(" %02x", ((uint8_t *)buf)[i]); +static int dediprog_read(enum dediprog_cmds cmd, unsigned int value, unsigned int idx, uint8_t *bytes, size_t size) +{ + return usb_control_msg(dediprog_handle, REQTYPE_EP_IN, cmd, value, idx, + (char *)bytes, size, DEFAULT_TIMEOUT); +} + +static int dediprog_write(enum dediprog_cmds cmd, unsigned int value, unsigned int idx, const uint8_t *bytes, size_t size) +{ + return usb_control_msg(dediprog_handle, REQTYPE_EP_OUT, cmd, value, idx, + (char *)bytes, size, DEFAULT_TIMEOUT); } -#endif /* Might be useful for other USB devices as well. static for now. */ /* device parameter allows user to specify one device of multiple installed */ @@ -166,24 +176,30 @@ if (leds < LED_NONE || leds > LED_ALL) leds = LED_ALL; - /* Older Dediprogs with 2.x.x and 3.x.x firmware only had - * two LEDs, and they were reversed. So map them around if - * we have an old device. On those devices the LEDs map as - * follows: + /* Older Dediprogs with 2.x.x and 3.x.x firmware only had two LEDs, assigned to different bits. So map + * them around if we have an old device. On those devices the LEDs map as follows: * bit 2 == 0: green light is on. - * bit 0 == 0: red light is on. + * bit 0 == 0: red light is on. + * + * Additionally, the command structure has changed with the "new" protocol. + * + * FIXME: take IO pins into account */ - int target_leds; - if (dediprog_firmwareversion < FIRMWARE_VERSION(5,0,0)) { - target_leds = ((leds & LED_ERROR) >> 2) | - ((leds & LED_PASS) << 2); + int target_leds, ret; + if (is_new_prot()) { + target_leds = (leds ^ 7) << 8; + ret = dediprog_write(CMD_SET_IO_LED, target_leds, 0, NULL, 0); } else { - target_leds = leds; + if (dediprog_firmwareversion < FIRMWARE_VERSION(5, 0, 0)) { + target_leds = ((leds & LED_ERROR) >> 2) | ((leds & LED_PASS) << 2); + } else { + target_leds = leds; + } + target_leds ^= 7; + + ret = dediprog_write(CMD_SET_IO_LED, 0x9, target_leds, NULL, 0); } - target_leds ^= 7; - int ret = usb_control_msg(dediprog_handle, REQTYPE_EP_OUT, CMD_SET_IO_LED, 0x09, target_leds, - NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { msg_perr("Command Set LED 0x%x failed (%s)!\n", leds, usb_strerror()); return 1; @@ -222,8 +238,7 @@ /* Wait some time as the original driver does. */ programmer_delay(200 * 1000); } - ret = usb_control_msg(dediprog_handle, REQTYPE_EP_OUT, CMD_SET_VCC, voltage_selector, 0, - NULL, 0x0, DEFAULT_TIMEOUT); + ret = dediprog_write(CMD_SET_VCC, voltage_selector, 0, NULL, 0); if (ret != 0x0) { msg_perr("Command Set SPI Voltage 0x%x failed!\n", voltage_selector); @@ -263,8 +278,7 @@ const struct dediprog_spispeeds *spispeed = &spispeeds[spispeed_idx]; msg_pdbg("SPI speed is %sHz\n", spispeed->name); - int ret = usb_control_msg(dediprog_handle, REQTYPE_EP_OUT, CMD_SET_SPI_CLK, spispeed->speed, 0xff, - NULL, 0x0, DEFAULT_TIMEOUT); + int ret = dediprog_write(CMD_SET_SPI_CLK, spispeed->speed, 0, NULL, 0); if (ret != 0x0) { msg_perr("Command Set SPI Speed 0x%x failed!\n", spispeed->speed); return 1; @@ -272,52 +286,66 @@ return 0; } +static void fill_rw_cmd_payload(uint8_t *data_packet, unsigned int count, uint8_t dedi_spi_cmd, unsigned int *value, unsigned int *idx, unsigned int start) { + /* First 5 bytes are common in both generations. */ + data_packet[0] = count & 0xff; + data_packet[1] = (count >> 8) & 0xff; + data_packet[2] = 0; /* RFU */ + data_packet[3] = dedi_spi_cmd; /* Read/Write Mode (currently READ_MODE_STD, WRITE_MODE_PAGE_PGM or WRITE_MODE_2B_AAI) */ + data_packet[4] = 0; /* "Opcode". Specs imply necessity only for READ_MODE_4B_ADDR_FAST and WRITE_MODE_4B_ADDR_256B_PAGE_PGM */ + + if (is_new_prot()) { + *value = *idx = 0; + data_packet[5] = 0; /* RFU */ + data_packet[6] = (start >> 0) & 0xff; + data_packet[7] = (start >> 8) & 0xff; + data_packet[8] = (start >> 16) & 0xff; + data_packet[9] = (start >> 24) & 0xff; + } else { + *value = start % 0x10000; + *idx = start / 0x10000; + } +} + /* Bulk read interface, will read multiple 512 byte chunks aligned to 512 bytes. * @start start address * @len length * @return 0 on success, 1 on failure */ -static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, - unsigned int start, unsigned int len) +static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int ret; - unsigned int i; /* chunksize must be 512, other sizes will NOT work at all. */ - const unsigned int chunksize = 0x200; + const unsigned int chunksize = 512; const unsigned int count = len / chunksize; - const char count_and_chunk[] = {count & 0xff, - (count >> 8) & 0xff, - chunksize & 0xff, - (chunksize >> 8) & 0xff}; if ((start % chunksize) || (len % chunksize)) { - msg_perr("%s: Unaligned start=%i, len=%i! Please report a bug " - "at flashrom(a)flashrom.org\n", __func__, start, len); + msg_perr("%s: Unaligned start=%i, len=%i! Please report a bug at flashrom(a)flashrom.org\n", + __func__, start, len); return 1; } - /* No idea if the hardware can handle empty reads, so chicken out. */ - if (!len) + if (len == 0) return 0; - /* Command Read SPI Bulk. No idea which read command is used on the - * SPI side. - */ - ret = usb_control_msg(dediprog_handle, REQTYPE_EP_OUT, CMD_READ, start % 0x10000, - start / 0x10000, (char *)count_and_chunk, - sizeof(count_and_chunk), DEFAULT_TIMEOUT); - if (ret != sizeof(count_and_chunk)) { - msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, - usb_strerror()); + + /* Command packet size of protocols: new 10 B, old 5 B. */ + uint8_t data_packet[is_new_prot() ? 10 : 5]; + unsigned int value, idx; + fill_rw_cmd_payload(data_packet, count, READ_MODE_STD, &value, &idx, start); + + int ret = dediprog_write(CMD_READ, value, idx, data_packet, sizeof(data_packet)); + if (ret != sizeof(data_packet)) { + msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, usb_strerror()); return 1; } + unsigned int i; for (i = 0; i < count; i++) { ret = usb_bulk_read(dediprog_handle, 0x80 | dediprog_endpoint, (char *)buf + i * chunksize, chunksize, DEFAULT_TIMEOUT); if (ret != chunksize) { - msg_perr("SPI bulk read %i failed, expected %i, got %i " - "%s!\n", i, chunksize, ret, usb_strerror()); + msg_perr("SPI bulk read %i failed, expected %i, got %i %s!\n", + i, chunksize, ret, usb_strerror()); return 1; } } @@ -325,8 +353,7 @@ return 0; } -static int dediprog_spi_read(struct flashctx *flash, uint8_t *buf, - unsigned int start, unsigned int len) +static int dediprog_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { int ret; /* chunksize must be 512, other sizes will NOT work at all. */ @@ -346,13 +373,12 @@ /* Round down. */ bulklen = (len - residue) / chunksize * chunksize; - ret = dediprog_spi_bulk_read(flash, buf + residue, start + residue, - bulklen); + ret = dediprog_spi_bulk_read(flash, buf + residue, start + residue, bulklen); if (ret) goto err; len -= residue + bulklen; - if (len) { + if (len != 0) { msg_pdbg("Slow read for partial block from 0x%x, length 0x%x\n", start, len); ret = spi_read_chunked(flash, buf + residue + bulklen, @@ -378,15 +404,11 @@ static int dediprog_spi_bulk_write(struct flashctx *flash, const uint8_t *buf, unsigned int chunksize, unsigned int start, unsigned int len, uint8_t dedi_spi_cmd) { - int ret; - unsigned int i; /* USB transfer size must be 512, other sizes will NOT work at all. * chunksize is the real data size per USB bulk transfer. The remaining * space in a USB bulk transfer must be filled with 0xff padding. */ const unsigned int count = len / chunksize; - const char count_and_cmd[] = {count & 0xff, (count >> 8) & 0xff, 0x00, dedi_spi_cmd}; - char usbbuf[512]; /* * We should change this check to @@ -406,28 +428,28 @@ } /* No idea if the hardware can handle empty writes, so chicken out. */ - if (!len) + if (len == 0) return 0; - /* Command Write SPI Bulk. No idea which write command is used on the - * SPI side. - */ - ret = usb_control_msg(dediprog_handle, REQTYPE_EP_OUT, CMD_WRITE, start % 0x10000, start / 0x10000, - (char *)count_and_cmd, sizeof(count_and_cmd), DEFAULT_TIMEOUT); - if (ret != sizeof(count_and_cmd)) { + + /* Command packet size of protocols: new 10 B, old 5 B. */ + uint8_t data_packet[is_new_prot() ? 10 : 5]; + unsigned int value, idx; + fill_rw_cmd_payload(data_packet, count, dedi_spi_cmd, &value, &idx, start); + int ret = dediprog_write(CMD_WRITE, value, idx, data_packet, sizeof(data_packet)); + if (ret != sizeof(data_packet)) { msg_perr("Command Write SPI Bulk failed, %i %s!\n", ret, usb_strerror()); return 1; } + unsigned int i; for (i = 0; i < count; i++) { - memset(usbbuf, 0xff, sizeof(usbbuf)); + char usbbuf[512]; memcpy(usbbuf, buf + i * chunksize, chunksize); - ret = usb_bulk_write(dediprog_handle, dediprog_endpoint, - usbbuf, 512, - DEFAULT_TIMEOUT); + memset(usbbuf + chunksize, 0xff, sizeof(usbbuf) - chunksize); // fill up with 0xFF + ret = usb_bulk_write(dediprog_handle, dediprog_endpoint, usbbuf, 512, DEFAULT_TIMEOUT); if (ret != 512) { - msg_perr("SPI bulk write failed, expected %i, got %i " - "%s!\n", 512, ret, usb_strerror()); + msg_perr("SPI bulk write failed, expected %i, got %i %s!\n", 512, ret, usb_strerror()); return 1; } } @@ -506,30 +528,45 @@ int ret; msg_pspew("%s, writecnt=%i, readcnt=%i\n", __func__, writecnt, readcnt); - if (writecnt > UINT16_MAX) { + if (writecnt > flash->mst->spi.max_data_write) { msg_perr("Invalid writecnt=%i, aborting.\n", writecnt); return 1; } - if (readcnt > UINT16_MAX) { + if (readcnt > flash->mst->spi.max_data_read) { msg_perr("Invalid readcnt=%i, aborting.\n", readcnt); return 1; } - ret = usb_control_msg(dediprog_handle, REQTYPE_EP_OUT, CMD_TRANSCEIVE, 0, readcnt ? 0x1 : 0x0, - (char *)writearr, writecnt, DEFAULT_TIMEOUT); + unsigned int idx, value; + /* New protocol has options and timeout combined as value while the old one used the value field for + * timeout and the index field for options. */ + if (is_new_prot()) { + idx = 0; + value = readcnt ? 0x1 : 0x0; // Indicate if we require a read + } else { + idx = readcnt ? 0x1 : 0x0; // Indicate if we require a read + value = 0; + } + ret = dediprog_write(CMD_TRANSCEIVE, value, idx, writearr, writecnt); if (ret != writecnt) { msg_perr("Send SPI failed, expected %i, got %i %s!\n", writecnt, ret, usb_strerror()); return 1; } - if (readcnt == 0) + if (readcnt == 0) // If we don't require a response, we are done here return 0; - ret = usb_control_msg(dediprog_handle, REQTYPE_EP_IN, CMD_TRANSCEIVE, 0, 0, - (char *)readarr, readcnt, DEFAULT_TIMEOUT); + const uint8_t read_timeout = 10 + readcnt/512; + if (is_new_prot()) { + idx = 0; + value = min(read_timeout, 0xFF) | (0 << 8) ; // Timeout in lower byte, option in upper byte + } else { + idx = (0 & 0xFF); // Lower byte is option (0x01 = require SR, 0x02 keep CS low) + value = min(read_timeout, 0xFF); // Possibly two bytes but we play safe here + } + ret = dediprog_read(CMD_TRANSCEIVE, value, idx, readarr, readcnt); if (ret != readcnt) { - msg_perr("Receive SPI failed, expected %i, got %i %s!\n", - readcnt, ret, usb_strerror()); + msg_perr("Receive SPI failed, expected %i, got %i %s!\n", readcnt, ret, usb_strerror()); return 1; } return 0; @@ -541,20 +578,8 @@ int fw[3]; char buf[0x11]; -#if 0 - /* Command Prepare Receive Device String. */ - ret = usb_control_msg(dediprog_handle, REQTYPE_OTHER_IN, 0x7, 0x0, 0xef03, - buf, 0x1, DEFAULT_TIMEOUT); - /* The char casting is needed to stop gcc complaining about an always true comparison. */ - if ((ret != 0x1) || (buf[0] != (char)0xff)) { - msg_perr("Unexpected response to Command Prepare Receive Device" - " String!\n"); - return 1; - } -#endif /* Command Receive Device String. */ - ret = usb_control_msg(dediprog_handle, REQTYPE_EP_IN, CMD_READ_PROG_INFO, 0, 0, - buf, 0x10, DEFAULT_TIMEOUT); + ret = dediprog_read(CMD_READ_PROG_INFO, 0, 0, (uint8_t *)buf, 0x10); if (ret != 0x10) { msg_perr("Incomplete/failed Command Receive Device String!\n"); return 1; @@ -566,16 +591,16 @@ return 1; } if (sscanf(buf, "SF100 V:%d.%d.%d ", &fw[0], &fw[1], &fw[2]) != 3) { - msg_perr("Unexpected firmware version string!\n"); + msg_perr("Unexpected firmware version string '%s'\n", buf); return 1; } - /* Only these versions were tested. */ - if (fw[0] < 2 || fw[0] > 5) { - msg_perr("Unexpected firmware version %d.%d.%d!\n", fw[0], - fw[1], fw[2]); + /* Only these major versions were tested. */ + if (fw[0] < 2 || fw[0] > 6) { + msg_perr("Unexpected firmware version %d.%d.%d!\n", fw[0], fw[1], fw[2]); return 1; } dediprog_firmwareversion = FIRMWARE_VERSION(fw[0], fw[1], fw[2]); + return 0; } @@ -700,8 +725,8 @@ static const struct spi_master spi_master_dediprog = { .type = SPI_CONTROLLER_DEDIPROG, - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, + .max_data_read = 16, /* 18 seems to work fine as well, but 19 times out sometimes with FW 5.15. */ + .max_data_write = 16, .command = dediprog_spi_send_command, .multicommand = default_spi_send_multicommand, .read = dediprog_spi_read, @@ -711,8 +736,6 @@ static int dediprog_shutdown(void *data) { - msg_pspew("%s\n", __func__); - dediprog_firmwareversion = FIRMWARE_VERSION(0, 0, 0); /* URB 28. Command Set SPI Voltage to 0. */ @@ -730,7 +753,6 @@ return 0; } -/* URB numbers refer to the first log ever captured. */ int dediprog_init(void) { struct usb_device *dev; @@ -741,8 +763,6 @@ long target = 1; int i, ret; - msg_pspew("%s\n", __func__); - spispeed = extract_programmer_param("spispeed"); if (spispeed) { for (i = 0; spispeeds[i].name; ++i) { @@ -861,7 +881,7 @@ /* Set all possible LEDs as soon as possible to indicate activity. * Because knowing the firmware version is required to set the LEDs correctly we need to this after - * dediprog_setup() has queried the device and set dediprog_firmwareversion. */ + * dediprog_check_devicestring() has queried the device and set dediprog_firmwareversion. */ dediprog_set_leds(LED_ALL); /* Select target/socket, frequency and VCC. */ @@ -872,9 +892,8 @@ return 1; } - register_spi_master(&spi_master_dediprog); - - dediprog_set_leds(LED_NONE); + if (register_spi_master(&spi_master_dediprog) || dediprog_set_leds(LED_NONE)) + return 1; return 0; }

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Re: [flashrom] flashrom Digest, Vol 80, Issue 8
by Márton Miklós 23 Jan '16

23 Jan '16

Hello, I wanted to contact with you earlier about the buspirate write failure, just I have forgotten it I have also had problems with different external programmers and a the solution was adding a 100nF capacitor right next to the SPI flash. That sorted out the intermittent failures. HTH Regards, Miklos Marton 2016-01-05 12:54 keltezéssel, flashrom-request(a)flashrom.org írta: > Send flashrom mailing list submissions to > flashrom(a)flashrom.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://www.flashrom.org/mailman/listinfo/flashrom > or, via email, send a message with subject or body 'help' to > flashrom-request(a)flashrom.org > > You can reach the person managing the list at > flashrom-owner(a)flashrom.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of flashrom digest..." > > > Today's Topics: > > 1. READ ERASE WRITE tested for W25X64 on buspirate_spi, ICH9M-E > (Johannes Krampf) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Tue, 5 Jan 2016 12:43:31 +0100 > From: Johannes Krampf <johannes.krampf(a)googlemail.com> > To: flashrom(a)flashrom.org > Subject: [flashrom] READ ERASE WRITE tested for W25X64 on > buspirate_spi, ICH9M-E > Message-ID: <568BAC63.30008(a)googlemail.com> > Content-Type: text/plain; charset="utf-8"; Format="flowed" > > Hello, > > I have successfully tested the Winbond W25X64 flash chip (8192 kB, SPI) > for Probe, Read, Erase and Write operations using the buspirate_spi and > Intel ICH9M-E (Thinkpad T400) programmers. > > Testing was done with flashrom v0.9.8-r1901 on ICH9M-E and v0.9.8-r1888 > (Parabola/Arch default) on buspirate_spi. > > I slightly modified board_enable.c in flashrom to add the T400 to the > whitelist when flashing on r1901 (taken from libreboot patch): > > + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, > "^ThinkPad T400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T400", > 0, OK, p2_whitelist_laptop}, > > My buspirate is the sparkfun version and I used the 30cm long cable > which connects directly to 0.1" headers and the recommended 6.2 FW > version. Flashing worked at default (8M) speed with multiple reads > always producing the same checksum.[1] Reading the ROM took around 13min. > > Logs are attached. > > Please don't hesitate to ask for more information if required. > > - Johannes > > [1] This was not the case when flashing a Lenovo X200 with a Macronix > MX25L6405D chip, where reading was *never* reliable, even though > flashing worked. This was at spispeed=30K, with ~8cm cables and both > external and internal power. The chip would not be detected at higher > speeds. No such issues at all with the W25X64. >

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Re: [flashrom] [PATCH] Modify strnlen() check for old OSes to check its presence directly
by Stefan Tauner 23 Jan '16

23 Jan '16

On Mon, 4 Jan 2016 13:14:03 +0300 Andrey Korolyov <andrey(a)xdel.ru> wrote: > > > > thanks for the patch. Did you notice any breakage in the wild? I > > hesitate to include your change because that could actually break some > > configurations: in case HAVE_STRNLEN is not defined but strnlen is > > provided nonetheless linking would fail. Actually I'd be surprised if it > > would not make problems with other libc implementations. > > NetBSD before 6.0 is definitely the one which breaks here, as well as > other late adopters of srtnlen(), like FreeBSD before 8.0. Please feel > free to NAK the patch if you think that the support of ancient libcs > is not something to worry about (and old BSDs are definitely not LTS > distros with ten-year support span). Thanks for the explanation. I have merged the respective change now in r1917 because I could not find any problems with it on any of our buildbot tests. Hopefully no one else will either :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Issue with internal access to the W39V040FB
by Stefan Tauner 23 Jan '16

23 Jan '16

On Sat, 23 Jan 2016 19:32:14 +0300 Andrey Korolyov <andrey(a)xdel.ru> wrote: > BTW, are there still any FWH-capable romulators in production? Looks > like most of sockets from this era has been designed without bearing > in mind possibility of the in-scheme reprogramming, but the only > romulators I`ve seen on ebay are ancient devices bundled with software > on floppies... You might be interested in https://www.coreboot.org/FlexyICE I have just discovered that project a few weeks ago myself so I cannot give much more information than that. It is probably not purchasable anymore but open enough that one could build something new from that. Sooner or later I am planning to give a related projected out as Bachelor or Master thesis but that will take a while (and would probably be SPI-related). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Issue with internal access to the W39V040FB
by Andrey Korolyov 23 Jan '16

23 Jan '16

On Fri, Jan 15, 2016 at 8:42 PM, Andrey Korolyov <andrey(a)xdel.ru> wrote: > On Fri, Jan 15, 2016 at 8:11 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> Hi Andrey, >> >> On 15.01.2016 15:33, Andrey Korolyov wrote: >>> On Sun, Jan 3, 2016 at 9:44 PM, Andrey Korolyov <andrey(a)xdel.ru> wrote: >>>>> >> Hi Andrey, >>>>> >> >>>>> >> please post complete logs of a working and non-working probe as well as >>>>> >> the exact flashrom version you are using. The output of lspci -nnv >>>>> >> might become handy as well. >>>>> >> >>>> > >>>> > >>>> > Thanks Stefan, >>>> > >>>> > even giving out a fact that I am very lucky to hit very twisted issues >>>> > at all, this time it looks like chip eventually stopped to respond via >>>> > an appropriate interface (slight voltage change? bit-flip during a >>>> > board initialization? lack of a probe delay? ), so I think that the >>>> > initial report could be incorrect, as the flash is not responding >>>> > anymore even where is was supposed to. Nevertheless, the appropriate >>>> > log and lspci output are attached, please take a look on them if they >>>> > could be helpful. >>> Got an another sample of the same board, because original was died >>> from overheating during EEPROM resoldering procedure. Internal WRITE >>> effectively bricked a board over cold reboot but I finally obtained >>> logs with some possible usefulness. Should I check same random >>> behavior as I reported previously after reflashing the chip >>> externally? Unfortunate to me, the board layout strictly requires chip >>> desoldering before I would be able to program it with anything, >>> in-place attempts are failing even with external power source, but >>> when de-soldered, chip flashes just perfectly via Minipro. >>> >>> flashrom v0.9.7-r1711 on NetBSD 7.0 (i386) >>> flashrom is free software, get the source code at http://www.flashrom.org >>> >>> flashrom was built with libpci 3.3.0, GCC 4.8.4, little endian >>> Command line (7 args): flashrom -p internal:laptop=this_is_not_a_laptop -c W39V040FB -r bios.bin -V >>> Calibrating delay loop... OS timer resolution is 5 usecs, 166M loops per second, 10 myus = 14 us, 100 myus = 105 us, 1000 myus = 1004 us, 10000 myus = 10042 us, 20 myus = 24 us, OK. >>> Initializing internal programmer >>> [...] >>> Found chipset "AMD CS5536" with PCI ID 1022:2080. Enabling flash write... No MSR support for your OS yet. >>> FAILED! >>> Warning: unexpected second chipset match: "AMD CS5536" >>> ignoring, please report lspci and board URL to flashrom(a)flashrom.org >>> with 'CHIPSET: your board name' in the subject line. >> >> I suspect this may be part of the issue. Another suspicion is that older >> NetBSD may automatically enable the MSRs we need, and later NetBSD >> versions don't. >> >> Regards, >> Carl-Daniel > > Okay, once I flash coreboot rom (GX3 is very simular to the existing > implementations in the tree and its support almost entirely > copy-pasted from db800), I`ll be able to boot Linux and check > hypothesis about MSRs. Another interesting part, as I wrote before, is > a heisenberg-style disappearance of the SuperIO register availability. To follow this up: Linux exposes same mixed behavior as NetBSD earlier, e.g. erase+write sometimes could be completed successfully, sometimes erase procedure just messes PROM contents as mentioned before. Software environment and operating voltage are absolutely stable between those tries so this is almost surely a timing issue in the prom chip itself or mis-engineering in its electrical neighborhood which results in a protocol violation. This is just for information, I do not own any hardware which `ll be able to prove or disprove this hypothesis by measuring data on a parallel interface directly, BTW, are there still any FWH-capable romulators in production? Looks like most of sockets from this era has been designed without bearing in mind possibility of the in-scheme reprogramming, but the only romulators I`ve seen on ebay are ancient devices bundled with software on floppies...

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[commit] r1917 - trunk
by repository service 23 Jan '16

23 Jan '16

Author: stefanct Date: Sat Jan 23 17:16:49 2016 New Revision: 1917 URL: http://flashrom.org/trac/flashrom/changeset/1917 Log: Add a bunch of new/tested stuff and various small changes 24. Tested mainboards: OK: - ASRock G31M-GS Reported by Александр Трубицын - ASRock G41M-VS3 Reported by Александр Трубицын - ASRock N68C-S UCC Reported by Alexey Belyaev - ASRock AMCP7AION-HT (ION 330HT(-BD)) Reported by Stefan Tauner - ASUS P5K SE Reported by Александр Трубицын - ASUS P5KPL-VM Reported by Marin Vlah - ASUS RAMPAGE III GENE Reported by stevessss on IRC - GIGABYTE GA-945GM-S2 Reported by Александр Трубицын - GIGABYTE GA-945GCM-S2 (rev. 3.0) Reported by Александр Трубицын - GIGABYTE GA-965P-S3 Reported by Александр Трубицын - GIGABYTE GA-EG43M-S2H Reported by Александр Трубицын - GIGABYTE GA-EP31-DS3L (rev. 1.0) Reported by Александр Трубицын - GIGABYTE GA-G33M-S2 Reported by Александр Трубицын - GIGABYTE GA-G33M-S2L Reported by Александр Трубицын - GIGABYTE GA-H55M-S2 Reported by Александр Трубицын - GIGABYTE GA-J1900N-D3V Reported by Marcos Truchado and Guillermo von Hünefeld - GIGABYTE GA-K8NS Reported by nicolae788 - GIGABYTE GA-M56S-S3 Reported by Estevo Paz Freire - GIGABYTE GA-P31-DS3L Reported by Александр Трубицын - GIGABYTE GA-P31-S3G Reported by Александр Трубицын - MSI MS-7336 Reported by Benjamin Bellec - MSI X79A-GD45 (8D) (MS-7760)" Reported by mortehu on IRC - Supermicro A1SAi-2550F Reported by Bernard Grymonpon - Supermicro X7DWT Reported by Steven Stremciuc Laptop: - ASUS U38N Reported by Ultra on IRC - Dell Latitude D630 Reported by Márton Miklós - Fujitsu Amilo Xi 3650 Reported by Elmar Stellnberger - Lenovo T400 (whitelisting only) Chipsets: - Mark 8086:1f38 (Intel Avoton/Rangeley) as tested Reported by Jeremy Porter and Bernard Grymonpon - Add Intel Sunrise Point IDs but no support yet. Flash chips: - Atmel AT45DB321D to PREW (+PREW) Reported by The Raven - Eon EN25QH32 to PREW (+PREW) Reported by Josua Mayer - Eon EN25QH64 to PREW (+EW) Reported by David s. Alessio - GigaDevice GD25LQ64(B) to PREW (+PREW) Reported by Greg Tippit - Intel 28F001BN/BX-T to PREW (+EW) Reported by Lu Xie - Micron M25P10-A to PREW (+W) Reported by the Raven - Micron M25PE40 Reported by David Wood - Micron N25Q128..3E to PREW (+PREW) Reported by Miklós Márton - Macronix MX25L3273E to PREW (+PREW) Reported by Roklobsta on IRC - Macronix MX23L6454 to PR (+PR) Reported by Steven Honeyman - Macronix MX25U6435E/F to PREW (+PREW) Reported by Marcos Truchado and Guillermo von Hünefeld - PMC Pm25LQ032C to PREW (+EW) Reported by Dirk Knop - Spansion S25FL016A to PREW (+EW) Reported by Márton Miklós - Spansion S25FL128S......0 to PREW (+PREW) Reported by Jim Houston - Spansion S25FL204K to PR (+PR) Reported by Thomas Debrunner - SST SST49LF016C to PREW (+EW) Reported by Steven Stremciuc - SST SST39VF040 to PREW (+PREW) Reported by Xavier Bourgeois - SST SST49LF040B to PREW (+EW) Reported by Rikard Åhlund - ST M25P10-A to PREW (+W) Reported by Martijn Schiedon - Winbond W39V040FA to PREW (+EW) Reported by Евгений Черкашин - Winbond W39V080FA to PREW (+EW) Reported by protagonist0 on IRC - Winbond W25Q80.W to PREW (+PREW) Reported by Miklós Márton - Winbond W25X64 to PREW (+REW) Reported by Johannes Krampf and Manuel Dejonghe - Fix ID of AMIC A25LQ64 Reported by Roman Titov - Fix page size of Spansion S25FL129P......1 Copy and paste error from the 128S uniform 256kB variant, probably. - Add Micron/Numonyx phase-change memory IDs Miscellaneous: - Detect Android target OS. No changes are required to build flashrom (excluding programmers with NEED_PCI) on Android. - Update rayerspi (spipgm) URL - Fix max_data_write handling of at45db. - Minor refinement of the README - Mark board enable for the GA-K8NS variants as tested. Tested by "nicolae788" on a board with socket 754. - Mark "Multi-system" chassis as non-laptop case. - Remove W836xx log requests. We got enough (and no one is looking at them for the time being anyway). - serprog: improve invalid reply error message, contributed by Urja Rannikko. - Remove default include paths for MinGW. - Disable implicit rules in the Makefile because we don't need them and they just make the build (imperceptibly) slower. - Enable our own strnlen() implementation not only on DJGPP but also if HAVE_STRNLEN is not defined. This is needed to get older BSDs (e.g. NetBSD 6.0, FreeBSD < 8.0) to work. - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/Makefile trunk/README trunk/at45db.c trunk/board_enable.c trunk/chipset_enable.c trunk/dmi.c trunk/dummyflasher.c trunk/flash.h trunk/flashchips.c trunk/flashchips.h trunk/flashrom.8.tmpl trunk/flashrom.c trunk/helpers.c trunk/hwaccess.h trunk/jedec.c trunk/linux_spi.c trunk/os.h trunk/print.c trunk/programmer.h trunk/serprog.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/Makefile Sat Jan 23 17:16:49 2016 (r1917) @@ -186,11 +186,8 @@ # MinGW doesn't have the ffs() function, but we can use gcc's __builtin_ffs(). FLASHROM_CFLAGS += -Dffs=__builtin_ffs # Some functions provided by Microsoft do not work as described in C99 specifications. This macro fixes that -# for MinGW. See http://sourceforge.net/apps/trac/mingw-w64/wiki/printf%20and%20scanf%20fami… */ +# for MinGW. See http://sourceforge.net/p/mingw-w64/wiki2/printf%20and%20scanf%20family/ */ FLASHROM_CFLAGS += -D__USE_MINGW_ANSI_STDIO=1 -# libusb-win32/libftdi stuff is usually installed in /usr/local. -CPPFLAGS += -I/usr/local/include -LDFLAGS += -L/usr/local/lib # For now we disable all PCI-based programmers on Windows/MinGW (no libpci). ifeq ($(CONFIG_INTERNAL), yes) UNSUPPORTED_FEATURES += CONFIG_INTERNAL=yes @@ -1126,4 +1123,7 @@ .PHONY: all install clean distclean compiler hwlibs features export tarball djgpp-dos featuresavailable libpayload +# Disable implicit suffixes and built-in rules (for performance and profit) +.SUFFIXES: + -include $(OBJS:.o=.d) Modified: trunk/README ============================================================================== --- trunk/README Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/README Sat Jan 23 17:16:49 2016 (r1917) @@ -8,12 +8,13 @@ cards (NICs), SATA controller cards, and other external devices which can program flash chips. -It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and TSOP40 -chips, which use various protocols such as LPC, FWH, parallel flash, or SPI. +It supports a wide range of flash chips (most commonly found in SOIC8, DIP8, +SOIC16, WSON8, PLCC32, DIP32, TSOP32, and TSOP40 packages), which use various +protocols such as LPC, FWH, parallel flash, or SPI. -Do not use flashrom on laptops! The embedded controller (EC) present in many -laptops interacts badly with any flash attempts and can brick your laptop -permanently. +Do not use flashrom on laptops (yet)! The embedded controller (EC) present in +many laptops might interact badly with any attempts to communicate with the +flash chip and may brick your laptop. Please make a backup of your flash chip before writing to it. Modified: trunk/at45db.c ============================================================================== --- trunk/at45db.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/at45db.c Sat Jan 23 17:16:49 2016 (r1917) @@ -99,6 +99,10 @@ static uint8_t at45db_prettyprint_protection_register(struct flashctx *flash, uint8_t opcode, const char *regname) { const uint8_t cmd[] = { opcode, 0, 0, 0 }; + const size_t sec_count = at45db_get_sector_count(flash); + if (sec_count < 2) + return 0; + /* The first two sectors share the first result byte. */ uint8_t buf[at45db_get_sector_count(flash) - 1]; @@ -332,7 +336,7 @@ /* Wait for completion. */ ret = at45db_wait_ready(flash, stepsize, retries); if (ret != 0) - msg_cerr("%s: chip did not became ready again after sending the erase command!\n", __func__); + msg_cerr("%s: chip did not become ready again after sending the erase command!\n", __func__); return ret; } @@ -463,7 +467,7 @@ } /* Create a suitable buffer to store opcode, address and data chunks for buffer1. */ - const unsigned int max_data_write = flash->mst->spi.max_data_write; + const int max_data_write = flash->mst->spi.max_data_write - 4; const unsigned int max_chunk = (max_data_write > 0 && max_data_write <= page_size) ? max_data_write : page_size; uint8_t buf[4 + max_chunk]; @@ -504,7 +508,7 @@ /* Wait for completion (typically a few ms). */ ret = at45db_wait_ready(flash, 250, 200); // 50 ms if (ret != 0) { - msg_cerr("%s: chip did not became ready again!\n", __func__); + msg_cerr("%s: chip did not become ready again!\n", __func__); return ret; } Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/board_enable.c Sat Jan 23 17:16:49 2016 (r1917) @@ -333,12 +333,9 @@ continue; } } - msg_pinfo("Active config mode, unknown reg 0x20 ID: %02x.\n", model); - msg_pinfo("Please send the output of \"flashrom -V -p internal\" to \n" - "flashrom(a)flashrom.org with W836xx: your board name: flashrom -V\n" - "as the subject to help us finish support for your Super I/O. Thanks.\n"); + msg_pdbg("Active config mode, unknown reg 0x20 ID: %02x.\n", model); continue; - } + } /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */ w836xx_ext_enter(s.port); s.model = sio_read(s.port, 0x20); @@ -1156,6 +1153,7 @@ /* * Suited for: * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8 + * - Probably other versions of the GA-K8NS */ static int nvidia_mcp_gpio0a_raise(void) { @@ -2387,8 +2385,10 @@ {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^CUSL2-C", NULL, NULL, P3, "ASUS", "CUSL2-C", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^TUSL2-C", NULL, NULL, P3, "ASUS", "TUSL2-C", 0, NT, intel_ich_gpio21_raise}, + {0x1022, 0x780E, 0x1043, 0x1437, 0x1022, 0x780B, 0x1043, 0x1437, "^U38N$", NULL, NULL, P2, "ASUS", "U38N", 0, OK, p2_whitelist_laptop}, {0x1106, 0x3059, 0x1106, 0x4161, 0x1106, 0x3065, 0x1106, 0x0102, NULL, NULL, NULL, P3, "Bcom/Clientron", "WinNET P680", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3116, 0x1106, 0x3116, "^KM266-8235$", "biostar", "m7viq", P3, "Biostar", "M7VIQ", 0, NT, w83697xx_memw_enable_2e}, + {0x8086, 0x283e, 0x1028, 0x01f9, 0x8086, 0x2a01, 0, 0, "^Latitude D630", NULL, NULL, P2, "Dell", "Latitude D630", 0, OK, p2_whitelist_laptop}, {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3189, 0x1106, 0x3189, 0x1106, 0x3177, 0x1106, 0x3177, "^AD77", "dfi", "ad77", P3, "DFI", "AD77", 0, NT, w836xx_memw_enable_2e}, @@ -2401,6 +2401,7 @@ {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise}, {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise}, + {0x8086, 0x2A40, 0x1734, 0x1148, 0x8086, 0x2930, 0x1734, 0x1148, "^XY680", NULL, NULL, P2, "Fujitsu", "Amilo Xi 3650", 0, OK, p2_whitelist_laptop}, {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise}, {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise}, @@ -2410,7 +2411,7 @@ {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, - {0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise}, + {0x10DE, 0x00E4, 0x1458, 0x0C11, 0x10DE, 0x00E0, 0x1458, 0x0C11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS", 0, OK, nvidia_mcp_gpio0a_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, @@ -2426,10 +2427,11 @@ {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T400", 0, OK, p2_whitelist_laptop}, {0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad X200$", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X200", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad X200", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X200", 0, OK, p2_whitelist_laptop}, {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X201", 0, OK, p2_whitelist_laptop}, {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X230", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27A0, 0x17AA, 0x2017, 0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X60(s)", 0, OK, p2_whitelist_laptop}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/chipset_enable.c Sat Jan 23 17:16:49 2016 (r1917) @@ -1632,7 +1632,7 @@ {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7}, {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7}, {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7}, - {0x8086, 0x1f38, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x1f38, DEP, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, @@ -1781,6 +1781,10 @@ {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9}, {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9}, {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9}, + {0x8086, 0x9d41, BAD, "Intel", "Sunrise Point (Skylake LP Sample)", NULL}, + {0x8086, 0x9d43, BAD, "Intel", "Sunrise Point (Skylake-U Base)", NULL}, + {0x8086, 0x9d48, BAD, "Intel", "Sunrise Point (Skylake-U Premium)", NULL}, + {0x8086, 0x9d46, BAD, "Intel", "Sunrise Point (Skylake-Y Premium)", NULL}, #endif {0}, }; @@ -1816,6 +1820,10 @@ chipset_enables[i].device_id); msg_pinfo(".\n"); + if (chipset_enables[i].status == BAD) { + msg_perr("ERROR: This chipset is not supported yet.\n"); + return ERROR_FATAL; + } if (chipset_enables[i].status == NT) { msg_pinfo("This chipset is marked as untested. If " "you are using an up-to-date version\nof " @@ -1826,8 +1834,7 @@ "(-V) log.\nThank you!\n"); } msg_pinfo("Enabling flash write... "); - ret = chipset_enables[i].doit(dev, - chipset_enables[i].device_name); + ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); if (ret == NOT_DONE_YET) { ret = -2; msg_pinfo("OK - searching further chips.\n"); Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/dmi.c Sat Jan 23 17:16:49 2016 (r1917) @@ -90,6 +90,7 @@ {0x11, 0, "Main Server Chassis"}, {0x17, 0, "Rack Mount Chassis"}, {0x18, 0, "Sealed-case PC"}, /* used by Supermicro (X8SIE) */ + {0x19, 0, "Multi-system"}, /* used by Supermicro (X7DWT) */ }; #if CONFIG_INTERNAL_DMI == 1 Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/dummyflasher.c Sat Jan 23 17:16:49 2016 (r1917) @@ -376,8 +376,8 @@ /* We will silently (in default verbosity) ignore the file if it does not exist (yet) or the size does * not match the emulated chip. */ if (!stat(emu_persistent_image, &image_stat)) { - msg_pdbg("Found persistent image %s, size %li ", - emu_persistent_image, (long)image_stat.st_size); + msg_pdbg("Found persistent image %s, %jd B ", + emu_persistent_image, (intmax_t)image_stat.st_size); if (image_stat.st_size == emu_chip_size) { msg_pdbg("matches.\n"); msg_pdbg("Reading %s\n", emu_persistent_image); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/flash.h Sat Jan 23 17:16:49 2016 (r1917) @@ -260,7 +260,7 @@ #ifdef __MINGW32__ char* strtok_r(char *str, const char *delim, char **nextp); #endif -#if defined(__DJGPP__) +#if defined(__DJGPP__) || !defined(HAVE_STRNLEN) size_t strnlen(const char *str, size_t n); #endif Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/flashchips.c Sat Jan 23 17:16:49 2016 (r1917) @@ -1246,7 +1246,7 @@ .name = "A25LQ64", .bustype = BUS_SPI, .manufacture_id = AMIC_ID_NOPREFIX, - .model_id = AMIC_A25LQ032, + .model_id = AMIC_A25LQ64, .total_size = 8192, .page_size = 256, /* supports SFDP */ @@ -2658,7 +2658,7 @@ .block_erase = spi_erase_at45db_block, }, /* Although the datasheets describes sectors (which can be write protected) * there seems to be no erase functions for them. - { + { .eraseblocks = { {8 * 528, 1}, {120 * 528, 1}, @@ -2688,7 +2688,7 @@ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_at45db, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4657,7 +4657,7 @@ /* OTP: 512B total; enter 0x3A */ /* QPI enable 0x38, disable 0xFF */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4695,7 +4695,7 @@ /* OTP: 512B total; enter 0x3A */ /* QPI enable 0x38, disable 0xFF */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -5630,7 +5630,7 @@ .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -6438,7 +6438,7 @@ .model_id = INTEL_28F001T, .total_size = 128, .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = @@ -6821,7 +6821,7 @@ .model_id = MACRONIX_MX23L6454, .total_size = 8192, .page_size = 256, - .tested = {.probe = NT, .read = NT, .erase = NA, .write = NA}, + .tested = {.probe = OK, .read = OK, .erase = NA, .write = NA}, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .write = NULL, /* MX23L6454 is a mask ROM, so it is read-only */ @@ -7337,7 +7337,7 @@ .page_size = 256, /* OTP: 64B total; enter 0xB1, exit 0xC1 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7725,7 +7725,7 @@ /* OTP: 512B total; enter 0xB1, exit 0xC1 */ /* QPI enable 0x35, disable 0xF5 (0xFF et al. work too) */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -8354,7 +8354,7 @@ .total_size = 128, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -8737,7 +8737,7 @@ .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -9031,7 +9031,7 @@ }, .printlock = spi_prettyprint_status_register_default_welwip, .unlock = NULL, /* #WP pin write-protects lower 64kB. */ - .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .write = spi_chip_write_256, /* Page write supported (similar to PP but allows 0->1 changes) */ .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, }, @@ -9274,7 +9274,7 @@ /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -10069,7 +10069,7 @@ .page_size = 256, /* OTP: 64B total; read 0x4B, write 0xB1 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -10658,10 +10658,10 @@ { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_d7, - }, { + }, { .eraseblocks = { {64 * 1024, 8} }, .block_erase = spi_block_erase_d8, - }, { + }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, } @@ -10726,10 +10726,10 @@ { .eraseblocks = { {256, 1024} }, .block_erase = spi_block_erase_db, - }, { + }, { .eraseblocks = { {64 * 1024, 4} }, .block_erase = spi_block_erase_d8, - }, { + }, { .eraseblocks = { {256 * 1024, 1} }, .block_erase = spi_block_erase_c7, } @@ -10756,10 +10756,10 @@ { .eraseblocks = { {256, 2 * 1024} }, .block_erase = spi_block_erase_db, - }, { + }, { .eraseblocks = { {64 * 1024, 8} }, .block_erase = spi_block_erase_d8, - }, { + }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, } @@ -10787,10 +10787,10 @@ { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_d7, - }, { + }, { .eraseblocks = { {64 * 1024, 8} }, .block_erase = spi_block_erase_d8, - }, { + }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, } @@ -10818,13 +10818,13 @@ { .eraseblocks = { {4 * 1024, 256} }, .block_erase = spi_block_erase_20, - }, { + }, { .eraseblocks = { {4 * 1024, 256} }, .block_erase = spi_block_erase_d7, - }, { + }, { .eraseblocks = { {64 * 1024, 16} }, .block_erase = spi_block_erase_d8, - }, { + }, { .eraseblocks = { {1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } @@ -10852,10 +10852,10 @@ { .eraseblocks = { {8 * 1024, 128} }, .block_erase = spi_block_erase_d7, - }, { + }, { .eraseblocks = { {64 * 1024, 16} }, .block_erase = spi_block_erase_d8, - }, { + }, { .eraseblocks = { {1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } @@ -10997,7 +10997,7 @@ .total_size = 2048, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -11084,7 +11084,7 @@ .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -11398,7 +11398,7 @@ /* supports 4B addressing */ /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -11517,7 +11517,7 @@ .manufacture_id = SPANSION_ID, .model_id = SPANSION_S25FL128, .total_size = 16384, - .page_size = 512, + .page_size = 256, /* OTP: 506B total, 16B reserved; read 0x4B; write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, @@ -12655,7 +12655,7 @@ .total_size = 512, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers = @@ -12911,7 +12911,7 @@ .total_size = 2048, .page_size = 4 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (sst49lfxxxc.c) */ .block_erasers = @@ -13035,7 +13035,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_EITHER_RESET | FEATURE_REGISTERMAP, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150ns */ .block_erasers = @@ -14261,7 +14261,7 @@ .page_size = 256, /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -14623,7 +14623,7 @@ .total_size = 8192, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -15182,7 +15182,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .block_erasers = @@ -15419,7 +15419,7 @@ .total_size = 1024, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .block_erasers = Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/flashchips.h Sat Jan 23 17:16:49 2016 (r1917) @@ -847,6 +847,9 @@ #define ST_N25Q512__3E 0xBA20 /* N25Q512, 3.0V, (uniform sectors expected) */ #define ST_N25Q512__1E 0xBB20 /* N25Q512, 1.8V, (uniform sectors expected) */ #define ST_N25Q00A__3E 0xBA21 /* N25Q00A, 3.0V, (uniform sectors expected) */ +#define ST_NP5Q032 0xDA16 /* Phase-change memory (PCM), 3V */ +#define ST_NP5Q064 0xDA17 /* Phase-change memory (PCM), 3V */ +#define ST_NP5Q128 0xDA18 /* Phase-change memory (PCM), 3V */ #define SYNCMOS_MVC_ID 0x40 /* SyncMOS (SM) and Mosel Vitelic Corporation (MVC) */ #define MVC_V29C51000T 0x00 Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/flashrom.8.tmpl Sat Jan 23 17:16:49 2016 (r1917) @@ -552,13 +552,13 @@ is one of the following chips (please specify only the chip name, not the vendor): .sp -.RB "* ST " M25P10.RES " SPI flash chip (RES, page write)" +.RB "* ST " M25P10.RES " SPI flash chip (128 kB, RES, page write)" .sp -.RB "* SST " SST25VF040.REMS " SPI flash chip (REMS, byte write)" +.RB "* SST " SST25VF040.REMS " SPI flash chip (512 kB, REMS, byte write)" .sp -.RB "* SST " SST25VF032B " SPI flash chip (RDID, AAI write)" +.RB "* SST " SST25VF032B " SPI flash chip (4096 kB, RDID, AAI write)" .sp -.RB "* Macronix " MX25L6436 " SPI flash chip (RDID, SFDP)" +.RB "* Macronix " MX25L6436 " SPI flash chip (8192 kB, RDID, SFDP)" .sp Example: .B "flashrom -p dummy:emulate=SST25VF040.REMS" @@ -899,6 +899,7 @@ STK200/300, " wiggler " for the Macraigor Wiggler, or " xilinx " for the Xilinx Parallel Cable III (DLC 5)." .sp More information about the RayeR hardware is available at +.nh .URLB "http://rayer.g6.cz/elektro/spipgm.htm" "RayeR's website" . The Altera ByteBlasterMV datasheet can be obtained from .URLB "http://www.altera.co.jp/literature/ds/dsbytemv.pdf" Altera . @@ -953,10 +954,6 @@ parameter as explained in the .B nic3com et al.\& section above. -.sp -More information about the hardware is available at -.nh -.BR http://wiki.opengraphics.org . .SS .BR "linux_spi " programmer .IP @@ -1148,7 +1145,7 @@ .SH LICENSE .B flashrom is covered by the GNU General Public License (GPL), version 2. Some files are -additionally available under the GPL (version 2, or any later version). +additionally available under any later version of the GPL. .SH COPYRIGHT .br Please see the individual files. @@ -1219,6 +1216,8 @@ .br Steven James .br +Urja Rannikko +.br Uwe Hermann .br Wang Qingpei Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/flashrom.c Sat Jan 23 17:16:49 2016 (r1917) @@ -1672,7 +1672,7 @@ if (p < PROGRAMMER_INVALID - 1) msg_ginfo("%s", delim); } - msg_ginfo("\n"); + msg_ginfo("\n"); } void list_programmers_linebreak(int startcol, int cols, int paren) Modified: trunk/helpers.c ============================================================================== --- trunk/helpers.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/helpers.c Sat Jan 23 17:16:49 2016 (r1917) @@ -92,7 +92,7 @@ #endif /* There is no strnlen in DJGPP */ -#if defined(__DJGPP__) +#if defined(__DJGPP__) || !defined(HAVE_STRNLEN) size_t strnlen(const char *str, size_t n) { size_t i; Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/hwaccess.h Sat Jan 23 17:16:49 2016 (r1917) @@ -45,7 +45,7 @@ /* The next big hunk tries to guess endianess from various preprocessor macros */ -/* First some error checking in case some weird header has defines both. +/* First some error checking in case some weird header has defined both. * NB: OpenBSD always defines _BIG_ENDIAN and _LITTLE_ENDIAN. */ #if defined (__LITTLE_ENDIAN__) && defined (__BIG_ENDIAN__) #error Conflicting endianness #define Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/jedec.c Sat Jan 23 17:16:49 2016 (r1917) @@ -184,13 +184,11 @@ else if (chip->probe_timing == TIMING_ZERO) { /* No delay. */ probe_timing_enter = probe_timing_exit = 0; } else if (chip->probe_timing == TIMING_FIXME) { /* == _IGNORED */ - msg_cdbg("Chip lacks correct probe timing information, " - "using default 10mS/40uS. "); + msg_cdbg("Chip lacks correct probe timing information, using default 10ms/40us. "); probe_timing_enter = 10000; probe_timing_exit = 40; } else { - msg_cerr("Chip has negative value in probe_timing, failing " - "without chip access\n"); + msg_cerr("Chip has negative value in probe_timing, failing without chip access\n"); return 0; } Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/linux_spi.c Sat Jan 23 17:16:49 2016 (r1917) @@ -35,6 +35,12 @@ #include "programmer.h" #include "spi.h" +/* Devices known to work with this module (FIXME: export as struct dev_entry): + * Beagle Bone Black + * Raspberry Pi + * HummingBoard + */ + static int fd = -1; static int linux_spi_shutdown(void *data); Modified: trunk/os.h ============================================================================== --- trunk/os.h Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/os.h Sat Jan 23 17:16:49 2016 (r1917) @@ -58,6 +58,11 @@ #define __FLASHROM_OS__ "libpayload" // Linux #elif defined(__linux__) -#define __FLASHROM_OS__ "Linux" + // There are various flags in use on Android apparently. __ANDROID__ seems to be the most trustworthy. + #if defined(__ANDROID__) + #define __FLASHROM_OS__ "Android" + #else + #define __FLASHROM_OS__ "Linux" + #endif #endif __FLASHROM_OS__ Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/print.c Sat Jan 23 17:16:49 2016 (r1917) @@ -542,7 +542,7 @@ B("abit", "VA6", OK, NULL, NULL), B("abit", "VT6X4", OK, NULL, NULL), B("Acer", "V75-M", OK, NULL, "This is an OEM board used by IBM in e.g. Aptiva 2170-G"), - B("Acer", "EM61SM/EM61PM", OK, NULL, "Used in Acer Aspire T180."), + B("Acer", "EM61SM/EM61PM", OK, NULL, "Used in Acer Aspire T180 and E380. Seems to be an OEM variant of abit's NF-M2S."), B("Acorp", "6A815EPD", OK, "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…", NULL), B("Acorp", "6M810C", OK, NULL, NULL), B("ADLINK", "Express-HR", OK, "http://www.adlinktech.com/PD/web/PD_detail.php?pid=1012", NULL), @@ -568,10 +568,13 @@ B("ASRock", "A780FullHD", OK, "http://www.asrock.com/mb/overview.asp?Model=A780FullHD", "While flashrom is working correctly, there might be problems with the firmware images themselves. Please see https://flashrom.org/pipermail/flashrom/2012-July/009600.html for details."), B("ASRock", "ALiveNF6G-DVI", OK, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL), B("ASRock", "AM2NF6G-VSTA", OK, "http://www.asrock.com/mb/overview.asp?Model=AM2NF6G-VSTA", NULL), + B("ASRock", "AMCP7AION-HT", OK, "http://www.asrock.com/nettop/NVIDIA/ION%20330HT/", "Used in ION 330HT(-BD) barebones."), B("ASRock", "ConRoeXFire-eSATA2", OK, "http://www.asrock.com/mb/overview.asp?model=conroexfire-esata2", NULL), - B("ASRock", "E350M1/USB3", OK, "http://www.asrock.com/mb/overview.asp?model=e350m1/usb3", NULL), + B("ASRock", "E350M1/USB3", OK, "http://www.asrock.com/mb/overview.asp?model=e350m1/usb3", "Vendor firmware writes to flash at shutdown. This probably corrupts the flash in case you write coreboot while running the vendor firmware. Simply updating the vendor firmware should be fine."), B("ASRock", "Fatal1ty Z77 Performance", BAD, "http://www.asrock.com/mb/overview.asp?Model=Fatal1ty%20Z77%20Performance", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASRock", "G31M-GS", OK, "http://www.asrock.com/mb/overview.asp?Model=G31M-GS", NULL), B("ASRock", "G31M-S rev 2.0", OK, "http://www.asrock.com/mb/overview.asp?model=G31M-S", NULL), + B("ASRock", "G41M-VS3", OK, "http://www.asrock.com/mb/overview.asp?Model=G41M-VS3", NULL), B("ASRock", "H61M-ITX", BAD, "http://www.asrock.com/mb/overview.asp?Model=H61M-ITX", "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASRock", "H67M", BAD, "http://www.asrock.com/mb/overview.asp?Model=H67M", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASRock", "IMB-180-H", OK, "http://www.asrock.com/ipc/overview.asp?Model=IMB-A180-H", NULL), @@ -581,6 +584,7 @@ B("ASRock", "K8S8X", OK, "http://www.asrock.com/mb/overview.asp?Model=K8S8X", NULL), B("ASRock", "M3A790GXH/128M", OK, "http://www.asrock.com/mb/overview.asp?Model=M3A790GXH/128M", NULL), B("ASRock", "N61P-S", OK, "http://www.asrock.com/mb/overview.asp?Model=N61P-S", NULL), + B("ASRock", "N68C-S UCC", OK, "http://www.asrock.com/mb/overview.asp?Model=N68C-S%20UCC", NULL), B("ASRock", "P4i65GV", OK, "http://www.asrock.com/mb/overview.asp?Model=P4i65GV", NULL), B("ASRock", "Z68 Extreme4", BAD, "http://www.asrock.com/mb/overview.asp?Model=Z68%20Extreme4", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "A7N8X Deluxe", OK, "http://www.asus.com/Motherboards/AMD_Socket_A/A7N8X_Deluxe/", NULL), @@ -609,6 +613,7 @@ B("ASUS", "C60M1-I", OK, "http://www.asus.com/Motherboards/C60M1I/", "The MAC address of the onboard network card is stored in flash."), B("ASUS", "Crosshair II Formula", OK, "http://www.asus.com/Motherboards/AMD_AM2Plus/Crosshair_II_Formula/", NULL), B("ASUS", "Crosshair IV Extreme", OK, "http://www.asus.com/Motherboards/AMD_AM3/Crosshair_IV_Extreme/", NULL), + B("ASUS", "CUSL2-C", OK, NULL, "The image provided by ASUS is only 256 kB big and has to be written to the upper 256 kB of the 512 kB chip."), B("ASUS", "DSAN-DX", NT, "http://www.asus.com/Server_Workstation/Server_Motherboards/DSANDX/", NULL), B("ASUS", "E35M1-I DELUXE", OK, "http://www.asus.com/Motherboards/AMD_CPU_on_Board/E35M1I_DELUXE/", NULL), B("ASUS", "F1A75-V PRO", OK, "http://www.asus.com/Motherboard/F1A75V_PRO/", NULL), @@ -694,11 +699,13 @@ B("ASUS", "P5GDC Deluxe", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5GDC_Deluxe/", NULL), B("ASUS", "P5GDC-V Deluxe", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5GDCV_Deluxe/", NULL), B("ASUS", "P5GD2/C variants", NT, NULL, "Untested board enable."), + B("ASUS", "P5K SE", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5K_SE/", NULL), B("ASUS", "P5K-V", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KV/", NULL), B("ASUS", "P5K-VM", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KVM/", NULL), B("ASUS", "P5KC", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KC/", NULL), B("ASUS", "P5KPL-AM IN/GB", OK, "http://support.asus.com/download.aspx?SLanguage=en&m=P5KPL-AM+IN%2fGB&os=29", NULL), B("ASUS", "P5KPL-CM", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KPLCM/", NULL), + B("ASUS", "P5KPL-VM", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KPLVM/", "Found in V3-P5G31."), B("ASUS", "P5L-MX", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LMX/", NULL), B("ASUS", "P5L-VM 1394", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LVM_1394/", NULL), B("ASUS", "P5LD2", OK, NULL, NULL), @@ -740,9 +747,9 @@ B("ASUS", "P8Z68-V LE", BAD, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8Z68-V PRO", BAD, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8Z68-V PRO/GEN3", OK, "http://www.asus.com/Motherboards/Intel_Socket_1155/P8Z68V_PROGEN3/", "Warning: MAC address of LOM is stored at 0x1000 - 0x1005 of the image."), + B("ASUS", "RAMPAGE III GENE", OK, "http://www.asus.com/Motherboards/RAMPAGE_III_GENE/", "The MAC address of the onboard network card is stored in flash."), B("ASUS", "SABERTOOTH 990FX", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/SABERTOOTH_990FX/", NULL), B("ASUS", "SABERTOOTH 990FX R2.0", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/SABERTOOTH_990FX_R20/", NULL), - B("ASUS", "CUSL2-C", OK, NULL, "The image provided by ASUS is only 256 kB big and has to be written to the upper 256 kB of the 512 kB chip."), B("ASUS", "TUSL2-C", NT, "http://support.asus.com/download.aspx?SLanguage=en&p=1&s=4&m=TUSL2-C&os=&ha…", "Untested board enable."), B("ASUS", "Z8NA-D6C", OK, "http://www.asus.com/Server_Workstation/Server_Motherboards/Z8NAD6C/", NULL), B("ASUS", "Z8PE-D12", OK, "http://www.asus.com/Server_Workstation/Server_Motherboards/Z8PED12/", NULL), @@ -827,27 +834,36 @@ B("GIGABYTE", "GA-8S648", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1674", NULL), B("GIGABYTE", "GA-8SIMLFS 2.0", OK, NULL, "This is an OEM board used by Fujitsu."), B("GIGABYTE", "GA-8SIMLH", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1399", NULL), + B("GIGABYTE", "GA-945GCM-S2 (rev. 3.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2466", NULL), + B("GIGABYTE", "GA-945GM-S2", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2331", NULL), B("GIGABYTE", "GA-945PL-S3P (rev. 6.6)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2541", NULL), B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), + B("GIGABYTE", "GA-965P-S3 (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2321", NULL), B("GIGABYTE", "GA-970A-D3P (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4642", NULL), B("GIGABYTE", "GA-970A-UD3P (rev. 2.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=5194", "Primary flash chip is a Macronix MX25L3206E."), B("GIGABYTE", "GA-990FXA-UD3 (rev. 4.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4672", NULL), B("GIGABYTE", "GA-A75M-UD2H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3928", NULL), B("GIGABYTE", "GA-B85M-D3H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4567", NULL), - B("GIGABYTE", "GA-EP31-DS3L (rev. 2.1)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2964", NULL), + B("GIGABYTE", "GA-EG43M-S2H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2878", NULL), + B("GIGABYTE", "GA-EP31-DS3L (rev. 1.0, 2.1)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2964", NULL), B("GIGABYTE", "GA-EP35-DS3L", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), + B("GIGABYTE", "GA-G33M-S2", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2557", NULL), + B("GIGABYTE", "GA-G33M-S2L", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2692", NULL), B("GIGABYTE", "GA-G41MT-S2PT", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3960", NULL), + B("GIGABYTE", "GA-H55M-S2", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3509", "8 MB (ME) + 1 MB (BIOS) flash chips - hardware sequencing required."), B("GIGABYTE", "GA-H61M-D2-B3", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3773", NULL), B("GIGABYTE", "GA-H61M-D2H-USB3", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4004", NULL), B("GIGABYTE", "GA-H77-D3H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4141", "Does only work with -p internal:ich_spi_mode=hwseq due to an evil twin of MX25L6405 and ICH SPI lockdown."), B("GIGABYTE", "GA-H77-DS3H (rev. 1.1)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4318", NULL), B("GIGABYTE", "GA-H77M-D3H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4388", NULL), + B("GIGABYTE", "GA-J1900N-D3V", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4918", NULL), B("GIGABYTE", "GA-K8N51GMF-9", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-K8N51GMF", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N-SLI", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), - B("GIGABYTE", "GA-K8NS Pro-939", NT, "http://www.gigabyte.com/products/product-page.aspx?pid=1875", "Untested board enable."), + B("GIGABYTE", "GA-K8NS", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1784", NULL), + B("GIGABYTE", "GA-M56S-S3", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2607", NULL), B("GIGABYTE", "GA-M57SLI-S4", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL), B("GIGABYTE", "GA-M720-US3", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3006", NULL), @@ -863,6 +879,8 @@ B("GIGABYTE", "GA-MA790FX-DQ6", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), B("GIGABYTE", "GA-MA790GP-DS4H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), B("GIGABYTE", "GA-MA790XT-UD4P (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3010", NULL), + B("GIGABYTE", "GA-P31-DS3L", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2615", NULL), + B("GIGABYTE", "GA-P31-S3G", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2676", NULL), B("GIGABYTE", "GA-P55-USB3 (rev. 2.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3440", NULL), B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL), B("GIGABYTE", "GA-P55A-UD7" , OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3324", NULL), @@ -889,7 +907,7 @@ B("HP", "Vectra VL420 SFF", OK, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), B("HP", "xw4400 (0A68h)", BAD, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c007…", "ICH7 with SPI lock down, BIOS lock, flash block detection (SST25VF080B); see http://paste.flashrom.org/view.php?id=686"), B("HP", "xw6400", BAD, NULL, "No chip found, see https://flashrom.org/pipermail/flashrom/2012-March/009006.html"), - B("HP", "xw9300", BAD, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", "Missing board enable, see https://flashrom.org/pipermail/flashrom/2012-February/008862.html"), + B("HP", "xw9300", BAD, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", "Missing board enable, see https://flashrom.org/pipermail/flashrom/2012-March/008885.html"), B("HP", "xw9400", OK, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", "Boot block is write protected unless the solder points next to F2 are shorted."), B("HP", "Z400 Workstation (0AE4h)", BAD, NULL, "ICH10R with BIOS lock enable and a protected range PRBAD, see https://flashrom.org/pipermail/flashrom/2012-June/009350.html"), B("IBASE", "MB899", OK, "http://www.ibase-i.com.tw/2009/mb899.html", NULL), @@ -958,6 +976,7 @@ B("MSI", "MS-7309 (K9N6SGM-V)", BAD, "http://www.msi.com/product/mb/K9N6SGM-V---K9N6PGM-FI---K9N6PGM-F.html", "Uses Fintek F71882F/F71883F/F71887 SPI-to-LPC translation."), B("MSI", "MS-7309 (K9N6PGM2-V2)", OK, "http://www.msi.com/product/mb/K9N6PGM2-V2.html", NULL), B("MSI", "MS-7312 (K9MM-V)", OK, "http://www.msi.com/product/mb/K9MM-V.html", NULL), + B("MSI", "MS-7336", OK, NULL, "Some non-essential DMI data (e.g. serial numbers) is overwritten when using flashrom. This is an OEM board used by HP (e.g. dx2300 Microtower)."), B("MSI", "MS-7345 (P35 Neo2-FIR)", OK, "http://www.msi.com/product/mb/P35-Neo2-FR---FIR.html", NULL), B("MSI", "MS-7357 (G33M)", OK, "http://www.msi.com/product/mb/G33M.html", NULL), B("MSI", "MS-7368 (K9AG Neo2-Digital)", OK, "http://www.msi.com/product/mb/K9AG-Neo2-Digital.html", NULL), @@ -984,6 +1003,7 @@ B("MSI", "MS-7698 (E350IA-E45)", OK, "http://www.msi.com/product/mb/E350IA-E45.html", NULL), B("MSI", "MS-7740 (H61MA-E35(B3))", OK, "http://www.msi.com/product/mb/H61MA-E35--B3-.html", NULL), B("MSI", "MS-7756 (H77MA-G43)", OK, "http://www.msi.com/product/mb/H77MA-G43.html", NULL), + B("MSI", "MS-7760 (X79A-GD45 (8D))", OK, "http://www.msi.com/product/mb/X79A-GD45-8D.html", NULL), B("MSI", "MS-7808 (B75MA-E33)", OK, "http://www.msi.com/product/mb/B75MA-E33.html", NULL), B("MSI", "MS-7816 (H87-G43)", OK, "http://www.msi.com/product/mb/H87-G43.html", NULL), B("MSI", "MS-7817 (H81M-E33)", OK, "http://www.msi.com/product/mb/H81ME33.html", NULL), @@ -1028,11 +1048,13 @@ B("Sun", "Fire x4540", BAD, "http://www.sun.com/servers/x64/x4540/", "No public report found. May work now."), B("Sun", "Fire x4600", BAD, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), B("Sun", "Ultra 40 M2", OK, "http://download.oracle.com/docs/cd/E19127-01/ultra40.ws/820-0123-13/intro.h…", NULL), + B("Supermicro", "A1SAi-2550F", OK, "http://www.supermicro.com/products/motherboard/Atom/X10/A1SAi-2550F.cfm", NULL), B("Supermicro", "H8QC8", OK, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), B("Supermicro", "H8QME-2", OK, "http://www.supermicro.com/Aplus/motherboard/Opteron8000/MCP55/H8QME-2.cfm", NULL), B("Supermicro", "X10SLM-F", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C220/X10SLM-F.cfm", "Probing works (Winbond W25Q128, 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked; SMM protection enabled."), B("Supermicro", "X5DP8-G2", OK, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), B("Supermicro", "X7DBT-INF", OK, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL), + B("Supermicro", "X7DWT", OK, "http://www.supermicro.com/products/motherboard/Xeon1333/5400/X7DWT.cfm", "Used in Dell C6100 servers."), B("Supermicro", "X7SPA-H(F)", OK, "http://www.supermicro.com/products/motherboard/ATOM/ICH9/X7SPA.cfm?typ=H", NULL), B("Supermicro", "X7SPE-HF-D525", OK, "http://www.supermicro.com/products/motherboard/ATOM/ICH9/X7SPE-HF-D525.cfm", NULL), B("Supermicro", "X8DT3", OK, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT3.cfm", NULL), @@ -1129,19 +1151,22 @@ B("Acer", "Aspire One", BAD, NULL, "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html"), B("ASUS", "A8Jm", OK, NULL, NULL), B("ASUS", "Eee PC 701 4G", BAD, "http://www.asus.com/Eee/Eee_PC/Eee_PC_4G/", "It seems the chip (25X40) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)."), - B("ASUS", "M6Ne", NT, "http://www.asus.com/Notebooks/Versatile_Performance/M6NNe/", "Untested board enable."), + B("ASUS", "M6Ne", NT, NULL, "Untested board enable."), + B("ASUS", "U38N", OK, NULL, NULL), B("Clevo", "P150HM", BAD, "http://www.clevo.com.tw/en/products/prodinfo_2.asp?productid=307", "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("Dell", "Latitude D630", OK, NULL, NULL), B("Dell", "Inspiron 1420", OK, NULL, NULL), B("Dell", "Latitude CPi A366XT", BAD, "http://www.coreboot.org/Dell_Latitude_CPi_A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop."), B("Dell", "Vostro 3700", BAD, NULL, "Locked ME, see https://flashrom.org/pipermail/flashrom/2012-May/009197.html."), B("Dell", "Latitude E6520", BAD, NULL, "Locked ME, see https://flashrom.org/pipermail/flashrom/2012-June/009420.html."), B("Elitegroup", "A928", OK, NULL, "Bootsector is locked and needs to be skipped with a layout file (writeable address range is 00000000:0003bfff)."), + B("Fujitsu", "Amilo Xi 3650", OK, NULL, NULL), B("HP/Compaq", "EliteBook 8560p", BAD, NULL, "SPI lock down, SMM protection, PR in BIOS region, read-only descriptor, locked ME region."), B("HP/Compaq", "nx9005", BAD, "http://h18000.www1.hp.com/products/quickspecs/11602_na/11602_na.HTML", "Shuts down when probing for a chip. https://flashrom.org/pipermail/flashrom/2010-May/003321.html"), B("HP/Compaq", "nx9010", BAD, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)."), B("IBM/Lenovo", "ThinkPad T40p", BAD, "http://www.thinkwiki.org/wiki/Category:T40p", NULL), - B("IBM/Lenovo", "ThinkPad T420", BAD, "http://www.thinkwiki.org/wiki/Category:T420", "Probing works (Macronix MX25L6405, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), B("IBM/Lenovo", "ThinkPad T410s", BAD, "http://www.thinkwiki.org/wiki/Category:T410s", "Probing works (Winbond W25X64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), + B("IBM/Lenovo", "ThinkPad T420", BAD, "http://www.thinkwiki.org/wiki/Category:T420", "Probing works (Macronix MX25L6405, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), B("IBM/Lenovo", "ThinkPad X1", BAD, "http://www.thinkwiki.org/wiki/Category:X1", "Probing works (ST M25PX64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), B("IBM/Lenovo", "ThinkPad T530", DEP, "http://www.thinkwiki.org/wiki/Category:T530", "Works fine but only with coreboot (due to locked regions and additional PR restrictions)."), B("IBM/Lenovo", "ThinkPad 240", BAD, "http://www.stanford.edu/~bresnan//tp240.html", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later."), Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/programmer.h Sat Jan 23 17:16:49 2016 (r1917) @@ -592,8 +592,8 @@ #define MAX_DATA_WRITE_UNLIMITED 256 struct spi_master { enum spi_controller type; - unsigned int max_data_read; - unsigned int max_data_write; + unsigned int max_data_read; // (Ideally,) maximum data read size in one go (excluding opcode+address). + unsigned int max_data_write; // (Ideally,) maximum data write size in one go (excluding opcode+address). int (*command)(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct flashctx *flash, struct spi_command *cmds); Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Sun Jan 17 00:45:25 2016 (r1916) +++ trunk/serprog.c Sat Jan 23 17:16:49 2016 (r1917) @@ -232,7 +232,7 @@ if (c == S_NAK) return 1; if (c != S_ACK) { - msg_perr("Error: invalid response 0x%02X from device\n", c); + msg_perr("Error: invalid response 0x%02X from device (to command 0x%02X)\n", c, command); return 1; } if (retlen) {

1 0

Getting started with flashrom and GSoC
by Hatim Kanchwala 23 Jan '16

23 Jan '16

Hello! I am Hatim Kanchwala from India. I am a sophomore pursuing Bachelor's in Electrical Engineering at the Indian Institute of Technology Patna. I came across flashrom through coreboot's GSoC page. I am aspiring to apply for GSoC 2016. I have looked through flashrom's GSoC page and the Easy Projects page. I have checked out the code and built it as well. Currently I am looking around the repo and will start working on a project listed on the Easy Projects page. Am I moving in the correct direction for getting started? Is there something more I can do? Any suggestion/advice is welcome. I have taken an introductory course in the C language at my University and a basic Digital Circuits course. I am experienced with Linux and version control tools. I am new to open-source development. Academically, I am interested in Embedded Systems and Computer Architecture, in which I hope to pursue higher studies. I consider contributing to flashrom (and perhaps coreboot) as an opportunity to learn more about these fields. You can find me on IRC (Freenode and OFTC) under the nick hatim. I am already a member of the #flashrom channel. Thank you for your time and help. Hatim -- http://hatimak.me

1 0

REPORT: MACRONIX MX 25L800(5PC-15G) AND WINBOND 25Q64F(VAIQ)
by Marin Vlah 23 Jan '16

23 Jan '16

Hello everyone, just wanted to report successful read from 8mbit (1mb) MACRONIX MX 25L800(5PC-15G) chip and write to 64mbit (8mb) WINBOND 25Q64F(VAIQ) chip. I've used some old ASUS motherboard dating from May 2009 (could check exact model if needed) asbase for flashing. Booted it into prepared FreeDOS usb stick with flashrom, made backup of MACRONIX chip, hot swapped it with WINBOND chip and flashed it with new image. Everything worked like a charm and thanks so much to all people which created this great tool! Additionaly, if this will be of any help to somebody, new image / WINBOND chip was for AsRock Extreme 4+ FM2A88M motherboard, downloaded at http://www.asrock.com/mb/AMD/FM2A88M%20Extreme4+/?cat=Download&os=BIOS.Vers… was 2.80 for "Instant Flash" and encapsulation in BIOS image file found inside ZIP archive (size 8mb+4kb) was trimmed to exactly 8mb using another great tool: https://github.com/LongSoft/UEFITool. Greetings,Marin.

2 3

Re: [flashrom] Problem flashing on APU2b4
by Stefan Tauner 23 Jan '16

23 Jan '16

On Fri, 22 Jan 2016 22:58:25 +0100 Richard Hartmann <richih.mailinglist(a)gmail.com> wrote: > neutronium [3] ~/apu2b4_rom # flashrom -w apu151109.rom -p internal > flashrom v0.9.7-r1852 on Linux 4.3.0-1-amd64 (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Error accessing high tables, 0x100000 bytes at 0x00000000dffae000 > /dev/mem mmap failed: Resource temporarily unavailable > Failed getting access to coreboot high tables. > Found chipset "AMD FCH". Enabling flash write... FCH device found but > SMBus revision 0x42 does not match known values. > Please report this to flashrom(a)flashrom.org and include this log and > the output of lspci -nnvx, thanks!. > Could not determine chipset generation.PROBLEMS, continuing anyway > No EEPROM/flash device found. > Note: flashrom can never write if the flash chip isn't found automatically. > A simple flashrom update should solve this too I think. The respective revision of the chipset is detected correctly since r1879. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Re: [flashrom] Problem flashing on APU2b4
by Michael Steinmann 22 Jan '16

22 Jan '16

please see http://pcengines.ch/howto.htm#TinyCoreLinux and use http://pcengines.ch/file/apu2-tinycore6.4-usb-installer.exe Best regards, Michael Steinmann 2016-01-22 22:58 GMT+01:00 Richard Hartmann <richih.mailinglist(a)gmail.com>: > neutronium [3] ~/apu2b4_rom # flashrom -w apu151109.rom -p internal > flashrom v0.9.7-r1852 on Linux 4.3.0-1-amd64 (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Error accessing high tables, 0x100000 bytes at 0x00000000dffae000 > /dev/mem mmap failed: Resource temporarily unavailable > Failed getting access to coreboot high tables. > Found chipset "AMD FCH". Enabling flash write... FCH device found but > SMBus revision 0x42 does not match known values. > Please report this to flashrom(a)flashrom.org and include this log and > the output of lspci -nnvx, thanks!. > Could not determine chipset generation.PROBLEMS, continuing anyway > No EEPROM/flash device found. > Note: flashrom can never write if the flash chip isn't found automatically. > neutronium [3] ~/apu2b4_rom # lspci -nnvx > 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device > [1022:1566] > Subsystem: Advanced Micro Devices, Inc. [AMD] Device [1022:1566] > Flags: bus master, fast devsel, latency 0 > 00: 22 10 66 15 04 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 66 15 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device > [1022:156b] > Flags: fast devsel > 00: 22 10 6b 15 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:02.2 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family > 16h Processor Functions 5:1 [1022:1439] (prog-if 00 [Normal decode]) > Flags: bus master, fast devsel, latency 0, IRQ 24 > Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 > I/O behind bridge: 00001000-00001fff > Memory behind bridge: fe600000-fe6fffff > Capabilities: [50] Power Management version 3 > Capabilities: [58] Express Root Port (Slot+), MSI 00 > Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ > Capabilities: [b0] Subsystem: Advanced Micro Devices, Inc. [AMD] > Family 16h Processor Functions 5:1 [1022:1234] > Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ > Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> > Kernel driver in use: pcieport > Kernel modules: shpchp > 00: 22 10 39 14 07 04 10 00 00 00 04 06 10 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 01 01 00 11 11 00 00 > 20: 60 fe 60 fe f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 02 03 00 > > 00:02.3 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family > 16h Processor Functions 5:1 [1022:1439] (prog-if 00 [Normal decode]) > Flags: bus master, fast devsel, latency 0, IRQ 25 > Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 > I/O behind bridge: 00002000-00002fff > Memory behind bridge: fe700000-fe7fffff > Capabilities: [50] Power Management version 3 > Capabilities: [58] Express Root Port (Slot+), MSI 00 > Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ > Capabilities: [b0] Subsystem: Advanced Micro Devices, Inc. [AMD] > Family 16h Processor Functions 5:1 [1022:1234] > Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ > Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> > Kernel driver in use: pcieport > Kernel modules: shpchp > 00: 22 10 39 14 07 04 10 00 00 00 04 06 10 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 02 02 00 21 21 00 00 > 20: 70 fe 70 fe f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 03 03 00 > > 00:02.4 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family > 16h Processor Functions 5:1 [1022:1439] (prog-if 00 [Normal decode]) > Flags: bus master, fast devsel, latency 0, IRQ 26 > Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 > I/O behind bridge: 00003000-00003fff > Memory behind bridge: fe800000-fe8fffff > Capabilities: [50] Power Management version 3 > Capabilities: [58] Express Root Port (Slot+), MSI 00 > Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ > Capabilities: [b0] Subsystem: Advanced Micro Devices, Inc. [AMD] > Family 16h Processor Functions 5:1 [1022:1234] > Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ > Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> > Kernel driver in use: pcieport > Kernel modules: shpchp > 00: 22 10 39 14 07 04 10 00 00 00 04 06 10 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 03 03 00 31 31 00 00 > 20: 80 fe 80 fe f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 04 03 00 > > 00:08.0 Encryption controller [1080]: Advanced Micro Devices, Inc. > [AMD] Device [1022:1537] > Subsystem: Advanced Micro Devices, Inc. [AMD] Device [1022:1537] > Flags: bus master, fast devsel, latency 0 > Memory at feb00000 (64-bit, prefetchable) [size=128K] > Memory at fe900000 (32-bit, non-prefetchable) [size=1M] > Memory at feb24000 (32-bit, non-prefetchable) [size=4K] > Memory at fea00000 (32-bit, non-prefetchable) [size=1M] > Memory at feb20000 (32-bit, non-prefetchable) [size=8K] > Capabilities: [50] MSI-X: Enable+ Count=2 Masked- > Capabilities: [5c] HyperTransport: MSI Mapping Enable+ Fixed+ > Capabilities: [60] Power Management version 3 > Kernel driver in use: AMD Cryptographic Coprocessor > Kernel modules: ccp > 00: 22 10 37 15 06 04 10 00 00 00 80 10 00 00 00 00 > 10: 0c 00 b0 fe 00 00 00 00 00 00 90 fe 00 40 b2 fe > 20: 00 00 a0 fe 00 00 b2 fe 00 00 00 00 22 10 37 15 > 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 > > 00:10.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH > USB XHCI Controller [1022:7814] (rev 11) (prog-if 30 [XHCI]) > Subsystem: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller > [1022:1410] > Flags: bus master, fast devsel, latency 0 > Memory at feb22000 (64-bit, non-prefetchable) [size=8K] > Capabilities: [50] Power Management version 3 > Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+ > Capabilities: [90] MSI-X: Enable+ Count=8 Masked- > Capabilities: [a0] Express Root Complex Integrated Endpoint, MSI 00 > Capabilities: [100] Latency Tolerance Reporting > Kernel driver in use: xhci_hcd > Kernel modules: xhci_pci > 00: 22 10 14 78 06 04 10 00 11 30 03 0c 10 00 00 00 > 10: 04 20 b2 fe 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 10 14 > 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00 > > 00:11.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH > SATA Controller [IDE mode] [1022:7800] (rev 40) (prog-if 01 [AHCI > 1.0]) > Subsystem: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [IDE > mode] [1022:7800] > Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 19 > I/O ports at 4010 [size=8] > I/O ports at 4020 [size=4] > I/O ports at 4018 [size=8] > I/O ports at 4024 [size=4] > I/O ports at 4000 [size=16] > Memory at feb25000 (32-bit, non-prefetchable) [size=1K] > Capabilities: [60] Power Management version 3 > Capabilities: [70] SATA HBA v1.0 > Kernel driver in use: ahci > Kernel modules: ahci > 00: 22 10 00 78 07 00 30 02 40 01 06 01 10 40 00 00 > 10: 11 40 00 00 21 40 00 00 19 40 00 00 25 40 00 00 > 20: 01 40 00 00 00 50 b2 fe 00 00 00 00 22 10 00 78 > 30: 00 00 00 00 60 00 00 00 00 00 00 00 00 01 00 00 > > 00:13.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH > USB EHCI Controller [1022:7808] (rev 39) (prog-if 20 [EHCI]) > Subsystem: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller > [1022:7808] > Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 18 > Memory at feb25400 (32-bit, non-prefetchable) [size=256] > Capabilities: [c0] Power Management version 2 > Capabilities: [e4] Debug port: BAR=1 offset=00e0 > Kernel driver in use: ehci-pci > Kernel modules: ehci_pci > 00: 22 10 08 78 16 00 b0 02 39 20 03 0c 10 40 00 00 > 10: 00 54 b2 fe 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 08 78 > 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 01 00 00 > > 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus > Controller [1022:780b] (rev 42) > Subsystem: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller > [1022:780b] > Flags: 66MHz, medium devsel > Kernel driver in use: piix4_smbus > Kernel modules: i2c_piix4 > 00: 22 10 0b 78 03 04 20 02 42 00 05 0c 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 0b 78 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC > Bridge [1022:780e] (rev 11) > Subsystem: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:780e] > Flags: bus master, 66MHz, medium devsel, latency 0 > 00: 22 10 0e 78 0f 00 20 02 11 00 01 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 0e 78 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:14.7 SD Host controller [0805]: Advanced Micro Devices, Inc. [AMD] > FCH SD Flash Controller [1022:7813] (rev 01) (prog-if 01) > Subsystem: Advanced Micro Devices, Inc. [AMD] FCH SD Flash Controller > [1022:7806] > Flags: bus master, 66MHz, medium devsel, latency 71, IRQ 16 > Memory at feb25500 (64-bit, non-prefetchable) [size=256] > Kernel driver in use: sdhci-pci > Kernel modules: sdhci_pci > 00: 22 10 13 78 06 00 20 02 01 01 05 08 10 47 80 00 > 10: 04 55 b2 fe 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 06 78 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 > > 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device > [1022:1580] > Flags: fast devsel > 00: 22 10 80 15 00 00 10 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device > [1022:1581] > Flags: fast devsel > 00: 22 10 81 15 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device > [1022:1582] > Flags: fast devsel > Kernel driver in use: amd64_edac > Kernel modules: amd64_edac_mod > 00: 22 10 82 15 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device > [1022:1583] > Flags: fast devsel > Capabilities: [f0] Secure device <?> > Kernel driver in use: k10temp > Kernel modules: k10temp > 00: 22 10 83 15 00 00 10 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 > > 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device > [1022:1584] > Flags: fast devsel > Kernel driver in use: fam15h_power > Kernel modules: fam15h_power > 00: 22 10 84 15 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device > [1022:1585] > Flags: fast devsel > 00: 22 10 85 15 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 01:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit > Network Connection [8086:157b] (rev 03) > Subsystem: Intel Corporation I210 Gigabit Network Connection [8086:0000] > Flags: bus master, fast devsel, latency 0 > Memory at fe600000 (32-bit, non-prefetchable) [size=128K] > I/O ports at 1000 [size=32] > Memory at fe620000 (32-bit, non-prefetchable) [size=16K] > Capabilities: [40] Power Management version 3 > Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ > Capabilities: [70] MSI-X: Enable+ Count=5 Masked- > Capabilities: [a0] Express Endpoint, MSI 00 > Capabilities: [100] Advanced Error Reporting > Capabilities: [140] Device Serial Number 00-0d-b9-ff-ff-40-82-b4 > Capabilities: [1a0] Transaction Processing Hints > Kernel driver in use: igb > Kernel modules: igb > 00: 86 80 7b 15 07 04 10 00 03 00 00 02 10 00 00 00 > 10: 00 00 60 fe 00 00 00 00 01 10 00 00 00 00 62 fe > 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 > > 02:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit > Network Connection [8086:157b] (rev 03) > Subsystem: Intel Corporation I210 Gigabit Network Connection [8086:0000] > Flags: bus master, fast devsel, latency 0 > Memory at fe700000 (32-bit, non-prefetchable) [size=128K] > I/O ports at 2000 [size=32] > Memory at fe720000 (32-bit, non-prefetchable) [size=16K] > Capabilities: [40] Power Management version 3 > Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ > Capabilities: [70] MSI-X: Enable+ Count=5 Masked- > Capabilities: [a0] Express Endpoint, MSI 00 > Capabilities: [100] Advanced Error Reporting > Capabilities: [140] Device Serial Number 00-0d-b9-ff-ff-40-82-b5 > Capabilities: [1a0] Transaction Processing Hints > Kernel driver in use: igb > Kernel modules: igb > 00: 86 80 7b 15 07 04 10 00 03 00 00 02 10 00 00 00 > 10: 00 00 70 fe 00 00 00 00 01 20 00 00 00 00 72 fe > 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 > > 03:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit > Network Connection [8086:157b] (rev 03) > Subsystem: Intel Corporation I210 Gigabit Network Connection [8086:0000] > Flags: bus master, fast devsel, latency 0 > Memory at fe800000 (32-bit, non-prefetchable) [size=128K] > I/O ports at 3000 [size=32] > Memory at fe820000 (32-bit, non-prefetchable) [size=16K] > Capabilities: [40] Power Management version 3 > Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ > Capabilities: [70] MSI-X: Enable+ Count=5 Masked- > Capabilities: [a0] Express Endpoint, MSI 00 > Capabilities: [100] Advanced Error Reporting > Capabilities: [140] Device Serial Number 00-0d-b9-ff-ff-40-82-b6 > Capabilities: [1a0] Transaction Processing Hints > Kernel driver in use: igb > Kernel modules: igb > 00: 86 80 7b 15 07 04 10 00 03 00 00 02 10 00 00 00 > 10: 00 00 80 fe 00 00 00 00 01 30 00 00 00 00 82 fe > 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 > > neutronium [3] ~/apu2b4_rom # > > > -- > Richard >

1 0

Problem flashing on APU2b4
by Richard Hartmann 22 Jan '16

22 Jan '16

neutronium [3] ~/apu2b4_rom # flashrom -w apu151109.rom -p internal flashrom v0.9.7-r1852 on Linux 4.3.0-1-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Error accessing high tables, 0x100000 bytes at 0x00000000dffae000 /dev/mem mmap failed: Resource temporarily unavailable Failed getting access to coreboot high tables. Found chipset "AMD FCH". Enabling flash write... FCH device found but SMBus revision 0x42 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. Could not determine chipset generation.PROBLEMS, continuing anyway No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. neutronium [3] ~/apu2b4_rom # lspci -nnvx 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1566] Subsystem: Advanced Micro Devices, Inc. [AMD] Device [1022:1566] Flags: bus master, fast devsel, latency 0 00: 22 10 66 15 04 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 66 15 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:156b] Flags: fast devsel 00: 22 10 6b 15 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.2 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1 [1022:1439] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 24 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00001000-00001fff Memory behind bridge: fe600000-fe6fffff Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot+), MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [b0] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1 [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Kernel driver in use: pcieport Kernel modules: shpchp 00: 22 10 39 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 11 11 00 00 20: 60 fe 60 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 02 03 00 00:02.3 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1 [1022:1439] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 25 Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: fe700000-fe7fffff Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot+), MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [b0] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1 [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Kernel driver in use: pcieport Kernel modules: shpchp 00: 22 10 39 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 21 21 00 00 20: 70 fe 70 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 03 03 00 00:02.4 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1 [1022:1439] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 26 Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 00003000-00003fff Memory behind bridge: fe800000-fe8fffff Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot+), MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [b0] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1 [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Kernel driver in use: pcieport Kernel modules: shpchp 00: 22 10 39 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 31 31 00 00 20: 80 fe 80 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 04 03 00 00:08.0 Encryption controller [1080]: Advanced Micro Devices, Inc. [AMD] Device [1022:1537] Subsystem: Advanced Micro Devices, Inc. [AMD] Device [1022:1537] Flags: bus master, fast devsel, latency 0 Memory at feb00000 (64-bit, prefetchable) [size=128K] Memory at fe900000 (32-bit, non-prefetchable) [size=1M] Memory at feb24000 (32-bit, non-prefetchable) [size=4K] Memory at fea00000 (32-bit, non-prefetchable) [size=1M] Memory at feb20000 (32-bit, non-prefetchable) [size=8K] Capabilities: [50] MSI-X: Enable+ Count=2 Masked- Capabilities: [5c] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [60] Power Management version 3 Kernel driver in use: AMD Cryptographic Coprocessor Kernel modules: ccp 00: 22 10 37 15 06 04 10 00 00 00 80 10 00 00 00 00 10: 0c 00 b0 fe 00 00 00 00 00 00 90 fe 00 40 b2 fe 20: 00 00 a0 fe 00 00 b2 fe 00 00 00 00 22 10 37 15 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 00:10.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller [1022:7814] (rev 11) (prog-if 30 [XHCI]) Subsystem: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller [1022:1410] Flags: bus master, fast devsel, latency 0 Memory at feb22000 (64-bit, non-prefetchable) [size=8K] Capabilities: [50] Power Management version 3 Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+ Capabilities: [90] MSI-X: Enable+ Count=8 Masked- Capabilities: [a0] Express Root Complex Integrated Endpoint, MSI 00 Capabilities: [100] Latency Tolerance Reporting Kernel driver in use: xhci_hcd Kernel modules: xhci_pci 00: 22 10 14 78 06 04 10 00 11 30 03 0c 10 00 00 00 10: 04 20 b2 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 10 14 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00 00:11.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [IDE mode] [1022:7800] (rev 40) (prog-if 01 [AHCI 1.0]) Subsystem: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [IDE mode] [1022:7800] Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 19 I/O ports at 4010 [size=8] I/O ports at 4020 [size=4] I/O ports at 4018 [size=8] I/O ports at 4024 [size=4] I/O ports at 4000 [size=16] Memory at feb25000 (32-bit, non-prefetchable) [size=1K] Capabilities: [60] Power Management version 3 Capabilities: [70] SATA HBA v1.0 Kernel driver in use: ahci Kernel modules: ahci 00: 22 10 00 78 07 00 30 02 40 01 06 01 10 40 00 00 10: 11 40 00 00 21 40 00 00 19 40 00 00 25 40 00 00 20: 01 40 00 00 00 50 b2 fe 00 00 00 00 22 10 00 78 30: 00 00 00 00 60 00 00 00 00 00 00 00 00 01 00 00 00:13.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller [1022:7808] (rev 39) (prog-if 20 [EHCI]) Subsystem: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller [1022:7808] Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 18 Memory at feb25400 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci-pci Kernel modules: ehci_pci 00: 22 10 08 78 16 00 b0 02 39 20 03 0c 10 40 00 00 10: 00 54 b2 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 08 78 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 01 00 00 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:780b] (rev 42) Subsystem: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:780b] Flags: 66MHz, medium devsel Kernel driver in use: piix4_smbus Kernel modules: i2c_piix4 00: 22 10 0b 78 03 04 20 02 42 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 0b 78 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:780e] (rev 11) Subsystem: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:780e] Flags: bus master, 66MHz, medium devsel, latency 0 00: 22 10 0e 78 0f 00 20 02 11 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 0e 78 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.7 SD Host controller [0805]: Advanced Micro Devices, Inc. [AMD] FCH SD Flash Controller [1022:7813] (rev 01) (prog-if 01) Subsystem: Advanced Micro Devices, Inc. [AMD] FCH SD Flash Controller [1022:7806] Flags: bus master, 66MHz, medium devsel, latency 71, IRQ 16 Memory at feb25500 (64-bit, non-prefetchable) [size=256] Kernel driver in use: sdhci-pci Kernel modules: sdhci_pci 00: 22 10 13 78 06 00 20 02 01 01 05 08 10 47 80 00 10: 04 55 b2 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 06 78 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1580] Flags: fast devsel 00: 22 10 80 15 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1581] Flags: fast devsel 00: 22 10 81 15 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1582] Flags: fast devsel Kernel driver in use: amd64_edac Kernel modules: amd64_edac_mod 00: 22 10 82 15 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1583] Flags: fast devsel Capabilities: [f0] Secure device <?> Kernel driver in use: k10temp Kernel modules: k10temp 00: 22 10 83 15 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1584] Flags: fast devsel Kernel driver in use: fam15h_power Kernel modules: fam15h_power 00: 22 10 84 15 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1585] Flags: fast devsel 00: 22 10 85 15 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:157b] (rev 03) Subsystem: Intel Corporation I210 Gigabit Network Connection [8086:0000] Flags: bus master, fast devsel, latency 0 Memory at fe600000 (32-bit, non-prefetchable) [size=128K] I/O ports at 1000 [size=32] Memory at fe620000 (32-bit, non-prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ Capabilities: [70] MSI-X: Enable+ Count=5 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number 00-0d-b9-ff-ff-40-82-b4 Capabilities: [1a0] Transaction Processing Hints Kernel driver in use: igb Kernel modules: igb 00: 86 80 7b 15 07 04 10 00 03 00 00 02 10 00 00 00 10: 00 00 60 fe 00 00 00 00 01 10 00 00 00 00 62 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 02:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:157b] (rev 03) Subsystem: Intel Corporation I210 Gigabit Network Connection [8086:0000] Flags: bus master, fast devsel, latency 0 Memory at fe700000 (32-bit, non-prefetchable) [size=128K] I/O ports at 2000 [size=32] Memory at fe720000 (32-bit, non-prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ Capabilities: [70] MSI-X: Enable+ Count=5 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number 00-0d-b9-ff-ff-40-82-b5 Capabilities: [1a0] Transaction Processing Hints Kernel driver in use: igb Kernel modules: igb 00: 86 80 7b 15 07 04 10 00 03 00 00 02 10 00 00 00 10: 00 00 70 fe 00 00 00 00 01 20 00 00 00 00 72 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 03:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:157b] (rev 03) Subsystem: Intel Corporation I210 Gigabit Network Connection [8086:0000] Flags: bus master, fast devsel, latency 0 Memory at fe800000 (32-bit, non-prefetchable) [size=128K] I/O ports at 3000 [size=32] Memory at fe820000 (32-bit, non-prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ Capabilities: [70] MSI-X: Enable+ Count=5 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number 00-0d-b9-ff-ff-40-82-b6 Capabilities: [1a0] Transaction Processing Hints Kernel driver in use: igb Kernel modules: igb 00: 86 80 7b 15 07 04 10 00 03 00 00 02 10 00 00 00 10: 00 00 80 fe 00 00 00 00 01 30 00 00 00 00 82 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 neutronium [3] ~/apu2b4_rom # -- Richard

1 0

[PATCH] Add infrastructure to support libusb-1.0.
by Stefan Tauner 19 Jan '16

19 Jan '16

Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Makefile | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++- flashrom.8.tmpl | 2 +- 2 files changed, 51 insertions(+), 2 deletions(-) I have added some quirks for the BSDs and refined the test case: I previously forgot to include stddef.h to import NULL. On FreeBSD and DragonFlyBSD there is a tool available called pkgconf that is similar to pkg-config but it must be installed explicitly and the default shell does not support export etc... I don't think it is worth it at the moment. diff --git a/Makefile b/Makefile index b4c6d86..5f4a1b6 100644 --- a/Makefile +++ b/Makefile @@ -783,6 +783,23 @@ FEATURE_CFLAGS += -D'NEED_USB=1' USBLIBS := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --libs libusb || printf "%s" "-lusb") endif +ifeq ($(NEED_LIBUSB1), yes) +CHECK_LIBUSB1 = yes +FEATURE_CFLAGS += -D'NEED_LIBUSB1=1' +# FreeBSD and DragonflyBSD use a reimplementation of libusb-1.0 that is simply called libusb +ifeq ($(TARGET_OS),$(filter $(TARGET_OS),FreeBSD DragonFlyBSD)) +USB1LIBS += -lusb +else +ifeq ($(TARGET_OS),NetBSD) +CPPFLAGS += -I/usr/pkg/include/libusb-1.0 +USB1LIBS += -lusb-1.0 +else +USB1LIBS += $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)"; pkg-config --libs libusb-1.0 || printf "%s" "-lusb-1.0") +CPPFLAGS += $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)"; pkg-config --cflags-only-I libusb-1.0 || printf "%s" "-I/usr/include/libusb-1.0") +endif +endif +endif + ifeq ($(CONFIG_PRINT_WIKI), yes) FEATURE_CFLAGS += -D'CONFIG_PRINT_WIKI=1' CLI_OBJS += print_wiki.o @@ -802,7 +819,7 @@ ifeq ($(ARCH), x86) endif $(PROGRAM)$(EXEC_SUFFIX): $(OBJS) - $(CC) $(LDFLAGS) -o $(PROGRAM)$(EXEC_SUFFIX) $(OBJS) $(LIBS) $(PCILIBS) $(FEATURE_LIBS) $(USBLIBS) + $(CC) $(LDFLAGS) -o $(PROGRAM)$(EXEC_SUFFIX) $(OBJS) $(LIBS) $(PCILIBS) $(FEATURE_LIBS) $(USBLIBS) $(USB1LIBS) libflashrom.a: $(LIBFLASHROM_OBJS) $(AR) rcs $@ $^ @@ -923,6 +940,20 @@ int main(int argc, char **argv) endef export LIBUSB0_TEST + +define LIBUSB1_TEST +#include <stddef.h> +#include <libusb.h> +int main(int argc, char **argv) +{ + (void)argc; + (void)argv; + libusb_init(NULL); + return 0; +} +endef +export LIBUSB1_TEST + hwlibs: compiler @printf "" > .libdeps ifeq ($(CHECK_LIBPCI), yes) @@ -971,6 +1002,24 @@ ifeq ($(CHECK_LIBUSB0), yes) rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 @rm -f .test.c .test.o .test$(EXEC_SUFFIX) endif +ifeq ($(CHECK_LIBUSB1), yes) + @printf "Checking for libusb-1.0 headers... " | tee -a $(BUILD_DETAILS_FILE) + @echo "$$LIBUSB1_TEST" > .test.c + @printf "\nexec: %s\n" "$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o" >>$(BUILD_DETAILS_FILE) + @{ { { { { $(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >&2 && \ + echo "found." || { echo "not found."; echo; \ + echo "Please install libusb-1.0 headers."; \ + echo "See README for more information."; echo; \ + rm -f .test.c .test.o; exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 + @printf "Checking if libusb-1.0 is usable... " | tee -a $(BUILD_DETAILS_FILE) + @printf "\nexec: %s\n" "$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USB1LIBS)" >>$(BUILD_DETAILS_FILE) + @{ { { { { $(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USB1LIBS) >&2 && \ + echo "yes." || { echo "no."; \ + echo "Please install libusb-1.0."; \ + echo "See README for more information."; echo; \ + rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 + @rm -f .test.c .test.o .test$(EXEC_SUFFIX) +endif .features: features diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 517c00e..a7eb9ca 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -1070,7 +1070,7 @@ needs TCP access to the network or userspace access to a serial port. needs userspace access to a serial port. .sp .BR dediprog ", " ft2232_spi ", " usbblaster_spi " and " pickit2_spi -need access to the USB device via libusb. +need access to the respective USB device via libusb API version 0.1. .sp .B dummy needs no access permissions at all. -- Kind regards, Stefan Tauner

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Untested device success: M25PE40 - Read, Erase, Write (and apparently Probe?)
by David Wood 18 Jan '16

18 Jan '16

Hello, Stefanct on freenode:#flashrom requested I email this to you. I've successfully reprogrammed a M25PE40 device, which was listed as untested by SVN flashrom. Setup info and related TTY log follows. http://pix.jbevren.net/e/LTV/leaptv-debrick The ROM is left in-circuit, and the LeapTV is powered up after the Raspberry Pi boots. Power is provided by the LeapTV system board. More relevant information is available on the page linked above, including an image of the setup. root@raspberrypi:~# flashrom -p linux_spi:dev=/dev/spidev0.0 -r 2016010801.bin flashrom v0.9.8-r1916 on Linux 4.1.15+ (armv6l) flashrom is free software, get the source code at https://flashrom.org Calibrating delay loop... OK. Found Micron/Numonyx/ST flash chip "M25PE40" (512 kB, SPI) on linux_spi. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Reading flash... done. root@raspberrypi:~# ls (removed unrelated tty history) root@raspberrypi:~# flashrom -p linux_spi:dev=/dev/spidev0.0 -E flashrom v0.9.8-r1916 on Linux 4.1.15+ (armv6l) flashrom is free software, get the source code at https://flashrom.org Calibrating delay loop... OK. Found Micron/Numonyx/ST flash chip "M25PE40" (512 kB, SPI) on linux_spi. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Erasing and writing flash chip... Erase/write done. root@raspberrypi:~# flashrom -p linux_spi:dev=/dev/spidev0.0 -w rewrite.bin flashrom v0.9.8-r1916 on Linux 4.1.15+ (armv6l) flashrom is free software, get the source code at https://flashrom.org Calibrating delay loop... OK. Found Micron/Numonyx/ST flash chip "M25PE40" (512 kB, SPI) on linux_spi. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. root@raspberrypi:~#

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[PATCH 3/3] Add support for WCH CH341A as an SPI programmer.
by Stefan Tauner 18 Jan '16

18 Jan '16

Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Makefile | 23 ++- ch341a_spi.c | 531 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ flashrom.8.tmpl | 12 +- flashrom.c | 12 ++ programmer.h | 13 ++ 5 files changed, 588 insertions(+), 3 deletions(-) create mode 100644 ch341a_spi.c diff --git a/Makefile b/Makefile index 6862200..676bb66 100644 --- a/Makefile +++ b/Makefile @@ -157,7 +157,7 @@ UNSUPPORTED_FEATURES += CONFIG_PONY_SPI=yes else override CONFIG_PONY_SPI = no endif -# Dediprog, USB-Blaster, PICkit2 and FT2232 are not supported under DOS (missing USB support). +# Dediprog, USB-Blaster, PICkit2, CH341A and FT2232 are not supported under DOS (missing USB support). ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -178,6 +178,11 @@ UNSUPPORTED_FEATURES += CONFIG_PICKIT2_SPI=yes else override CONFIG_PICKIT2_SPI = no endif +ifeq ($(CONFIG_CH341A_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_CH341A_SPI=yes +else +override CONFIG_CH341A_SPI = no +endif endif # FIXME: Should we check for Cygwin/MSVC as well? @@ -301,7 +306,7 @@ UNSUPPORTED_FEATURES += CONFIG_PONY_SPI=yes else override CONFIG_PONY_SPI = no endif -# Dediprog, USB-Blaster, PICkit2 and FT2232 are not supported with libpayload (missing libusb support) +# Dediprog, USB-Blaster, PICkit2, CH341A and FT2232 are not supported with libpayload (missing libusb support) ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -322,6 +327,11 @@ UNSUPPORTED_FEATURES += CONFIG_PICKIT2_SPI=yes else override CONFIG_PICKIT2_SPI = no endif +ifeq ($(CONFIG_CH341A_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_CH341A_SPI=yes +else +override CONFIG_CH341A_SPI = no +endif endif ifneq ($(TARGET_OS), Linux) @@ -500,6 +510,9 @@ CONFIG_LINUX_SPI ?= yes # Always enable ITE IT8212F PATA controllers for now. CONFIG_IT8212 ?= yes +# Winchiphead CH341A +CONFIG_CH341A_SPI ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -740,6 +753,12 @@ NEED_LINUX_I2C := yes PROGRAMMER_OBJS += mstarddc_spi.o endif +ifeq ($(CONFIG_CH341A_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_CH341A_SPI=1' +PROGRAMMER_OBJS += ch341a_spi.o +NEED_LIBUSB1 := yes +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif diff --git a/ch341a_spi.c b/ch341a_spi.c new file mode 100644 index 0000000..36282ed --- /dev/null +++ b/ch341a_spi.c @@ -0,0 +1,531 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 asbokid <ballymunboy(a)gmail.com> + * Copyright (C) 2014 Pluto Yang <yangyj.ee(a)gmail.com> + * Copyright (C) 2015-2016 Stefan Tauner + * Copyright (C) 2015 Urja Rannikko <urjaman(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <libusb.h> +#include "flash.h" +#include "programmer.h" + +/* LIBUSB_CALL ensures the right calling conventions on libusb callbacks. + * However, the macro is not defined everywhere. m( + */ +#ifndef LIBUSB_CALL +#define LIBUSB_CALL +#endif + +#define USB_TIMEOUT 1000 /* 1000 ms is plenty and we have no backup strategy anyway. */ +#define WRITE_EP 0x02 +#define READ_EP 0x82 + +#define CH341_PACKET_LENGTH 0x20 +#define CH341_MAX_PACKETS 256 +#define CH341_MAX_PACKET_LEN (CH341_PACKET_LENGTH * CH341_MAX_PACKETS) + +#define CH341A_CMD_SET_OUTPUT 0xA1 +#define CH341A_CMD_IO_ADDR 0xA2 +#define CH341A_CMD_PRINT_OUT 0xA3 +#define CH341A_CMD_SPI_STREAM 0xA8 +#define CH341A_CMD_SIO_STREAM 0xA9 +#define CH341A_CMD_I2C_STREAM 0xAA +#define CH341A_CMD_UIO_STREAM 0xAB + +#define CH341A_CMD_I2C_STM_START 0x74 +#define CH341A_CMD_I2C_STM_STOP 0x75 +#define CH341A_CMD_I2C_STM_OUT 0x80 +#define CH341A_CMD_I2C_STM_IN 0xC0 +#define CH341A_CMD_I2C_STM_MAX ( min( 0x3F, CH341_PACKET_LENGTH ) ) +#define CH341A_CMD_I2C_STM_SET 0x60 // bit 2: SPI with two data pairs D5,D4=out, D7,D6=in +#define CH341A_CMD_I2C_STM_US 0x40 +#define CH341A_CMD_I2C_STM_MS 0x50 +#define CH341A_CMD_I2C_STM_DLY 0x0F +#define CH341A_CMD_I2C_STM_END 0x00 + +#define CH341A_CMD_UIO_STM_IN 0x00 +#define CH341A_CMD_UIO_STM_DIR 0x40 +#define CH341A_CMD_UIO_STM_OUT 0x80 +#define CH341A_CMD_UIO_STM_US 0xC0 +#define CH341A_CMD_UIO_STM_END 0x20 + +#define CH341A_STM_I2C_20K 0x00 +#define CH341A_STM_I2C_100K 0x01 +#define CH341A_STM_I2C_400K 0x02 +#define CH341A_STM_I2C_750K 0x03 +#define CH341A_STM_SPI_DBL 0x04 + + +/* Number of parallel IN transfers. 32 seems to produce the most stable throughput on Windows. */ +#define USB_IN_TRANSFERS 32 + +/* We need to use many queued IN transfers for any resemblance of performance (especially on Windows) + * because USB spec says that transfers end on non-full packets and the device sends the 31 reply + * data bytes to each 32-byte packet with command + 31 bytes of data... */ +static struct libusb_transfer *transfer_out = NULL; +static struct libusb_transfer *transfer_ins[USB_IN_TRANSFERS] = {0}; + +/* Accumulate delays to be plucked between CS deassertion and CS assertions. */ +static unsigned int stored_delay_us = 0; + +static struct libusb_device_handle *handle = NULL; + +const struct dev_entry devs_ch341a_spi[] = { + {0x1A86, 0x5512, OK, "Winchiphead (WCH)", "CH341A"}, + + {0}, +}; + +enum trans_state {TRANS_ACTIVE = -2, TRANS_ERR = -1, TRANS_IDLE = 0}; + +static void print_hex(const void *buf, size_t len) +{ + size_t i; + for (i = 0; i < len; i++) { + msg_pspew(" %02x", ((uint8_t *)buf)[i]); + if (i % CH341_PACKET_LENGTH == CH341_PACKET_LENGTH - 1) + msg_pspew("\n"); + } +} + +static void cb_common(const char *func, struct libusb_transfer *transfer) +{ + int *transfer_cnt = (int*)transfer->user_data; + + if (transfer->status == LIBUSB_TRANSFER_CANCELLED) { + /* Silently ACK and exit. */ + *transfer_cnt = TRANS_IDLE; + return; + } + + if (transfer->status != LIBUSB_TRANSFER_COMPLETED) { + msg_perr("\n%s: error: %s\n", func, libusb_error_name(transfer->status)); + *transfer_cnt = TRANS_ERR; + } else { + *transfer_cnt = transfer->actual_length; + } +} + +/* callback for bulk out async transfer */ +static void LIBUSB_CALL cb_out(struct libusb_transfer *transfer) +{ + cb_common(__func__, transfer); +} + +/* callback for bulk in async transfer */ +static void LIBUSB_CALL cb_in(struct libusb_transfer *transfer) +{ + cb_common(__func__, transfer); +} + +static int32_t usb_transfer(const char *func, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) +{ + if (handle == NULL) + return -1; + + int state_out = TRANS_IDLE; + transfer_out->buffer = (uint8_t*)writearr; + transfer_out->length = writecnt; + transfer_out->user_data = &state_out; + + /* Schedule write first */ + if (writecnt > 0) { + state_out = TRANS_ACTIVE; + int ret = libusb_submit_transfer(transfer_out); + if (ret) { + msg_perr("%s: failed to submit OUT transfer: %s\n", func, libusb_error_name(ret)); + state_out = TRANS_ERR; + goto err; + } + } + + /* Handle all asynchronous packets as long as we have stuff to write or read. The write(s) simply need + * to complete but we need to scheduling reads as long as we are not done. */ + unsigned int free_idx = 0; /* The IN transfer we expect to be free next. */ + unsigned int in_idx = 0; /* The IN transfer we expect to be completed next. */ + unsigned int in_done = 0; + unsigned int in_active = 0; + unsigned int out_done = 0; + int state_in[USB_IN_TRANSFERS] = {0}; + do { + /* Schedule new reads as long as there are free transfers and unscheduled bytes to read. */ + while ((in_done + in_active) < readcnt && state_in[free_idx] == TRANS_IDLE) { + unsigned int cur_todo = min(CH341_PACKET_LENGTH - 1, readcnt - in_done - in_active); + transfer_ins[free_idx]->length = cur_todo; + transfer_ins[free_idx]->buffer = readarr; + transfer_ins[free_idx]->user_data = &state_in[free_idx]; + int ret = libusb_submit_transfer(transfer_ins[free_idx]); + if (ret) { + state_in[free_idx] = TRANS_ERR; + msg_perr("%s: failed to submit IN transfer: %s\n", + func, libusb_error_name(ret)); + goto err; + } + readarr += cur_todo; + in_active += cur_todo; + state_in[free_idx] = TRANS_ACTIVE; + free_idx = (free_idx + 1) % USB_IN_TRANSFERS; /* Increment (and wrap around). */ + } + + /* Actually get some work done. */ + libusb_handle_events_timeout(NULL, &(struct timeval){1, 0}); + + /* Check for the write */ + if (out_done < writecnt) { + if (state_out == TRANS_ERR) { + goto err; + } else if (state_out > 0) { + out_done += state_out; + state_out = TRANS_IDLE; + } + } + /* Check for completed transfers. */ + while (state_in[in_idx] != TRANS_IDLE && state_in[in_idx] != TRANS_ACTIVE) { + if (state_in[in_idx] == TRANS_ERR) { + goto err; + } + /* If a transfer is done, record the number of bytes read and reuse it later. */ + in_done += state_in[in_idx]; + in_active -= state_in[in_idx]; + state_in[in_idx] = TRANS_IDLE; + in_idx = (in_idx + 1) % USB_IN_TRANSFERS; /* Increment (and wrap around). */ + } + } while ((out_done < writecnt) || (in_done < readcnt)); + + if (out_done > 0) { + msg_pspew("Wrote %d bytes:\n", out_done); + print_hex(writearr, out_done); + msg_pspew("\n\n"); + } + if (in_done > 0) { + msg_pspew("Read %d bytes:\n", in_done); + print_hex(readarr, in_done); + msg_pspew("\n\n"); + } + return 0; +err: + /* Clean up on errors. */ + msg_perr("%s: Failed to %s %d bytes\n", func, (state_out == TRANS_ERR) ? "write" : "read", + (state_out == TRANS_ERR) ? writecnt : readcnt); + /* First, we must cancel any ongoing requests and wait for them to be canceled. */ + if ((writecnt > 0) && (state_out == TRANS_ACTIVE)) { + if (libusb_cancel_transfer(transfer_out) != 0) + state_out = TRANS_ERR; + } + if (readcnt > 0) { + unsigned int i; + for (i = 0; i < USB_IN_TRANSFERS; i++) { + if (state_in[i] == TRANS_ACTIVE) + if (libusb_cancel_transfer(transfer_ins[i]) != 0) + state_in[i] = TRANS_ERR; + } + } + + /* Wait for cancellations to complete. */ + while (1) { + bool finished = true; + if ((writecnt > 0) && (state_out == TRANS_ACTIVE)) + finished = false; + if (readcnt > 0) { + unsigned int i; + for (i = 0; i < USB_IN_TRANSFERS; i++) { + if (state_in[i] == TRANS_ACTIVE) + finished = false; + } + } + if (finished) + break; + libusb_handle_events_timeout(NULL, &(struct timeval){1, 0}); + } + return -1; +} + +/* Set the I2C bus speed (speed(b1b0): 0 = 20kHz; 1 = 100kHz, 2 = 400kHz, 3 = 750kHz). + * Set the SPI bus data width (speed(b2): 0 = Single, 1 = Double). */ +static int32_t config_stream(uint32_t speed) +{ + if (handle == NULL) + return -1; + + uint8_t buf[] = { + CH341A_CMD_I2C_STREAM, + CH341A_CMD_I2C_STM_SET | (speed & 0x7), + CH341A_CMD_I2C_STM_END + }; + + int32_t ret = usb_transfer(__func__, sizeof(buf), 0, buf, NULL); + if (ret < 0) { + msg_perr("Could not configure stream interface.\n"); + } + return ret; +} + +/* ch341 requires LSB first, swap the bit order before send and after receive */ +static uint8_t swap_byte(uint8_t x) +{ + x = ((x >> 1) & 0x55) | ((x << 1) & 0xaa); + x = ((x >> 2) & 0x33) | ((x << 2) & 0xcc); + x = ((x >> 4) & 0x0f) | ((x << 4) & 0xf0); + return x; +} + +/* The assumed map between UIO command bits, pins on CH341A chip and pins on SPI chip: + * UIO CH341A SPI CH341A SPI name + * 0 D0/15 CS/1 (CS0) + * 1 D1/16 unused (CS1) + * 2 D2/17 unused (CS2) + * 3 D3/18 SCK/6 (DCK) + * 4 D4/19 unused (DOUT2) + * 5 D5/20 SI/5 (DOUT) + * - The UIO stream commands seem to only have 6 bits of output, and D6/D7 are the SPI inputs, + * mapped as follows: + * D6/21 unused (DIN2) + * D7/22 SO/2 (DIN) + */ +static int32_t enable_pins(bool enable) +{ + uint8_t buf[] = { + CH341A_CMD_UIO_STREAM, + CH341A_CMD_UIO_STM_OUT | 0x37, // CS high (all of them), SCK=0, DOUT*=1 + CH341A_CMD_UIO_STM_DIR | (enable ? 0x3F : 0x00), // Interface output enable / disable + CH341A_CMD_UIO_STM_END, + }; + + int32_t ret = usb_transfer(__func__, sizeof(buf), 0, buf, NULL); + if (ret < 0) { + msg_perr("Could not %sable output pins.\n", enable ? "en" : "dis"); + } + return ret; +} + +/* De-assert and assert CS in one operation. */ +static void pluck_cs(uint8_t *ptr) +{ + /* This was measured to give a minumum deassertion time of 2.25 us, + * >20x more than needed for most SPI chips (100ns). */ + int delay_cnt = 2; + if (stored_delay_us) { + delay_cnt = (stored_delay_us * 4) / 3; + stored_delay_us = 0; + } + *ptr++ = CH341A_CMD_UIO_STREAM; + *ptr++ = CH341A_CMD_UIO_STM_OUT | 0x37; /* deasserted */ + int i; + for (i = 0; i < delay_cnt; i++) + *ptr++ = CH341A_CMD_UIO_STM_OUT | 0x37; /* "delay" */ + *ptr++ = CH341A_CMD_UIO_STM_OUT | 0x36; /* asserted */ + *ptr++ = CH341A_CMD_UIO_STM_END; +} + +void ch341a_spi_delay(unsigned int usecs) +{ + /* There is space for 28 bytes instructions of 750 ns each in the CS packet (32 - 4 for the actual CS + * instructions), thus max 21 us, but we avoid getting too near to this boundary and use + * internal_delay() for durations over 20 us. */ + if ((usecs + stored_delay_us) > 20) { + unsigned int inc = 20 - stored_delay_us; + internal_delay(usecs - inc); + usecs = inc; + } + stored_delay_us += usecs; +} + +static int ch341a_spi_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) +{ + if (handle == NULL) + return -1; + + /* How many packets ... */ + const size_t packets = (writecnt + readcnt + CH341_PACKET_LENGTH - 2) / (CH341_PACKET_LENGTH - 1); + + uint8_t wbuf[packets+1][CH341_PACKET_LENGTH]; + uint8_t rbuf[writecnt + readcnt]; + memset(wbuf[0], 0, CH341_PACKET_LENGTH); // dont want to write stack random to device... + + uint8_t *ptr = wbuf[0]; + /* CS usage is optimized by doing both transitions in one packet. + * Final transition to deselected state is in the pin disable. */ + pluck_cs(ptr); + unsigned int write_left = writecnt; + unsigned int read_left = readcnt; + unsigned int p; + for (p = 0; p < packets; p++) { + unsigned int write_now = min(CH341_PACKET_LENGTH - 1, write_left); + unsigned int read_now = min ((CH341_PACKET_LENGTH - 1) - write_now, read_left); + ptr = wbuf[p+1]; + *ptr++ = CH341A_CMD_SPI_STREAM; + unsigned int i; + for (i = 0; i < write_now; ++i) + *ptr++ = swap_byte(*writearr++); + if (read_now) { + memset(ptr, 0xFF, read_now); + read_left -= read_now; + } + write_left -= write_now; + } + + int32_t ret = usb_transfer(__func__, CH341_PACKET_LENGTH + packets + writecnt + readcnt, + writecnt + readcnt, wbuf[0], rbuf); + if (ret < 0) + return -1; + + unsigned int i; + for (i = 0; i < readcnt; i++) { + /* FIXME: does working on words instead of bytes improve speed? */ + *readarr++ = swap_byte(rbuf[writecnt + i]); + } + + return 0; +} + +static const struct spi_master spi_master_ch341a_spi = { + .type = SPI_CONTROLLER_CH341A_SPI, + /* TODO: flashrom's current maximum is 256 B. Device was tested on Linux to accept atleast 16 kB. */ + .max_data_read = 16 * 1024, + .max_data_write = 16 * 1024, + .command = ch341a_spi_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +static int ch341a_spi_shutdown(void *data) +{ + if (handle == NULL) + return -1; + + enable_pins(false); + libusb_free_transfer(transfer_out); + transfer_out = NULL; + int i; + for (i = 0; i < USB_IN_TRANSFERS; i++) { + libusb_free_transfer(transfer_ins[i]); + transfer_ins[i] = NULL; + } + libusb_release_interface(handle, 0); + libusb_close(handle); + libusb_exit(NULL); + handle = NULL; + return 0; +} + +int ch341a_spi_init(void) +{ + if (handle != NULL) { + msg_cerr("%s: handle already set! Please report a bug at flashrom(a)flashrom.org\n", __func__); + return -1; + } + + int32_t ret = libusb_init(NULL); + if (ret < 0) { + msg_perr("Couldnt initialize libusb!\n"); + return -1; + } + + libusb_set_debug(NULL, 3); // Enable information, warning and error messages (only). + + uint16_t vid = devs_ch341a_spi[0].vendor_id; + uint16_t pid = devs_ch341a_spi[0].device_id; + handle = libusb_open_device_with_vid_pid(NULL, vid, pid); + if (handle == NULL) { + msg_perr("Couldn't open device %04x:%04x.\n", vid, pid); + return -1; + } + +/* libusb_detach_kernel_driver() and friends basically only work on Linux. We simply try to detach on Linux + * without a lot of passion here. If that works fine else we will fail on claiming the interface anyway. */ +#if IS_LINUX + ret = libusb_detach_kernel_driver(handle, 0); + if (ret == LIBUSB_ERROR_NOT_SUPPORTED) { + msg_pwarn("Detaching kernel drivers is not supported. Further accesses may fail.\n"); + } else if (ret != 0 && ret != LIBUSB_ERROR_NOT_FOUND) { + msg_pwarn("Failed to detach kernel driver: '%s'. Further accesses will probably fail.\n", + libusb_error_name(ret)); + } +#endif + + ret = libusb_claim_interface(handle, 0); + if (ret != 0) { + msg_perr("Failed to claim interface 0: '%s'\n", libusb_error_name(ret)); + goto close_handle; + } + + struct libusb_device *dev; + if (!(dev = libusb_get_device(handle))) { + msg_perr("Failed to get device from device handle.\n"); + goto close_handle; + } + + struct libusb_device_descriptor desc; + ret = libusb_get_device_descriptor(dev, &desc); + if (ret < 0) { + msg_perr("Failed to get device descriptor: '%s'\n", libusb_error_name(ret)); + goto release_interface; + } + + msg_pdbg("Device revision is %d.%01d.%01d\n", + (desc.bcdDevice >> 8) & 0x00FF, + (desc.bcdDevice >> 4) & 0x000F, + (desc.bcdDevice >> 0) & 0x000F); + + /* Allocate and pre-fill transfer structures. */ + transfer_out = libusb_alloc_transfer(0); + if (!transfer_out) { + msg_perr("Failed to alloc libusb OUT transfer\n"); + goto release_interface; + } + int i; + for (i = 0; i < USB_IN_TRANSFERS; i++) { + transfer_ins[i] = libusb_alloc_transfer(0); + if (transfer_ins[i] == NULL) { + msg_perr("Failed to alloc libusb IN transfer %d\n", i); + goto dealloc_transfers; + } + } + /* We use these helpers but dont fill the actual buffer yet. */ + libusb_fill_bulk_transfer(transfer_out, handle, WRITE_EP, NULL, 0, cb_out, NULL, USB_TIMEOUT); + for (i = 0; i < USB_IN_TRANSFERS; i++) + libusb_fill_bulk_transfer(transfer_ins[i], handle, READ_EP, NULL, 0, cb_in, NULL, USB_TIMEOUT); + + if ((config_stream(CH341A_STM_I2C_100K) < 0) || (enable_pins(true) < 0)) + goto dealloc_transfers; + + register_shutdown(ch341a_spi_shutdown, NULL); + register_spi_master(&spi_master_ch341a_spi); + + return 0; + +dealloc_transfers: + for (i = 0; i < USB_IN_TRANSFERS; i++) { + if (transfer_ins[i] == NULL) + break; + libusb_free_transfer(transfer_ins[i]); + transfer_ins[i] = NULL; + } + libusb_free_transfer(transfer_out); + transfer_out = NULL; +release_interface: + libusb_release_interface(handle, 0); +close_handle: + libusb_close(handle); + handle = NULL; + return -1; +} diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 7c8c70c..0dd8322 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -269,6 +269,8 @@ bitbanging adapter) .sp .BR "* pickit2_spi" " (for SPI flash ROMs accessible via Microchip PICkit2)" .sp +.BR "* ch341a_spi" " (for SPI flash ROMs attached to WCH CH341A)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER-SPECIFIC INFORMATION @@ -1013,6 +1015,10 @@ an operation), without the parameter, once the flash read/write operation you intended to perform has completed successfully. .sp Please also note that the mstarddc_spi driver only works on Linux. +.SS +.BR "ch341a_spi " programmer +The WCH CH341A programmer does not support any parameters currently. SPI frequency is fixed at 2 MHz, and CS0 is +used as per the device. .SH EXAMPLES To back up and update your BIOS, run .sp @@ -1072,6 +1078,9 @@ needs userspace access to a serial port. .BR dediprog ", " ft2232_spi ", " usbblaster_spi " and " pickit2_spi need access to the respective USB device via libusb-0.1. .sp +.BR ch341a_spi +needs access to the respective USB device via libusb-1.0. +.sp .B dummy needs no access permissions at all. .sp @@ -1079,7 +1088,8 @@ needs no access permissions at all. .BR gfxnvidia ", " drkaiser ", " satasii ", " satamv ", " atahpt" and " atavia have to be run as superuser/root, and need additional raw access permission. .sp -.BR serprog ", " buspirate_spi ", " dediprog ", " usbblaster_spi ", " ft2232_spi " and " pickit2_spi +.BR serprog ", " buspirate_spi ", " dediprog ", " usbblaster_spi ", " ft2232_spi ", " pickit2_spi " and " \ +ch341a_spi can be run as normal user on most operating systems if appropriate device permissions are set. .sp diff --git a/flashrom.c b/flashrom.c index 3853e19..0ff088f 100644 --- a/flashrom.c +++ b/flashrom.c @@ -380,6 +380,18 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_CH341A_SPI == 1 + { + .name = "ch341a_spi", + .type = USB, + .devs.dev = devs_ch341a_spi, + .init = ch341a_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = ch341a_spi_delay, + }, +#endif + {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; diff --git a/programmer.h b/programmer.h index 97f0ffa..b9f8708 100644 --- a/programmer.h +++ b/programmer.h @@ -105,6 +105,9 @@ enum programmer { #if CONFIG_PICKIT2_SPI == 1 PROGRAMMER_PICKIT2_SPI, #endif +#if CONFIG_CH341A_SPI == 1 + PROGRAMMER_CH341A_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -516,6 +519,13 @@ int linux_spi_init(void); int dediprog_init(void); #endif +/* ch341a_spi.c */ +#if CONFIG_CH341A_SPI == 1 +int ch341a_spi_init(void); +void ch341a_spi_delay(unsigned int usecs); +extern const struct dev_entry devs_ch341a_spi[]; +#endif + /* flashrom.c */ struct decode_sizes { uint32_t parallel; @@ -575,6 +585,9 @@ enum spi_controller { #if CONFIG_PICKIT2_SPI == 1 SPI_CONTROLLER_PICKIT2, #endif +#if CONFIG_CH341A_SPI == 1 + SPI_CONTROLLER_CH341A_SPI, +#endif }; #define MAX_DATA_UNSPECIFIED 0 -- Kind regards, Stefan Tauner

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[PATCH 2/3] Add infrastructure to support libusb-1.0.
by Stefan Tauner 18 Jan '16

18 Jan '16

Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Makefile | 40 +++++++++++++++++++++++++++++++++++++++- flashrom.8.tmpl | 2 +- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index b4c6d86..6862200 100644 --- a/Makefile +++ b/Makefile @@ -783,6 +783,13 @@ FEATURE_CFLAGS += -D'NEED_USB=1' USBLIBS := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --libs libusb || printf "%s" "-lusb") endif +ifeq ($(NEED_LIBUSB1), yes) +CHECK_LIBUSB1 = yes +FEATURE_CFLAGS += -D'NEED_LIBUSB1=1' +USB1LIBS += $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)"; pkg-config --libs libusb-1.0 || printf "%s" "-lusb-1.0") +CPPFLAGS += $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)"; pkg-config --cflags-only-I libusb-1.0 || printf "%s" "-I/usr/include/libusb-1.0") +endif + ifeq ($(CONFIG_PRINT_WIKI), yes) FEATURE_CFLAGS += -D'CONFIG_PRINT_WIKI=1' CLI_OBJS += print_wiki.o @@ -802,7 +809,7 @@ ifeq ($(ARCH), x86) endif $(PROGRAM)$(EXEC_SUFFIX): $(OBJS) - $(CC) $(LDFLAGS) -o $(PROGRAM)$(EXEC_SUFFIX) $(OBJS) $(LIBS) $(PCILIBS) $(FEATURE_LIBS) $(USBLIBS) + $(CC) $(LDFLAGS) -o $(PROGRAM)$(EXEC_SUFFIX) $(OBJS) $(LIBS) $(PCILIBS) $(FEATURE_LIBS) $(USBLIBS) $(USB1LIBS) libflashrom.a: $(LIBFLASHROM_OBJS) $(AR) rcs $@ $^ @@ -923,6 +930,19 @@ int main(int argc, char **argv) endef export LIBUSB0_TEST + +define LIBUSB1_TEST +#include <libusb.h> +int main(int argc, char **argv) +{ + (void)argc; + (void)argv; + libusb_init(NULL); + return 0; +} +endef +export LIBUSB1_TEST + hwlibs: compiler @printf "" > .libdeps ifeq ($(CHECK_LIBPCI), yes) @@ -971,6 +991,24 @@ ifeq ($(CHECK_LIBUSB0), yes) rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 @rm -f .test.c .test.o .test$(EXEC_SUFFIX) endif +ifeq ($(CHECK_LIBUSB1), yes) + @printf "Checking for libusb-1.0 headers... " | tee -a $(BUILD_DETAILS_FILE) + @echo "$$LIBUSB1_TEST" > .test.c + @printf "\nexec: %s\n" "$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o" >>$(BUILD_DETAILS_FILE) + @{ { { { { $(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >&2 && \ + echo "found." || { echo "not found."; echo; \ + echo "Please install libusb-1.0 headers."; \ + echo "See README for more information."; echo; \ + rm -f .test.c .test.o; exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 + @printf "Checking if libusb-1.0 is usable... " | tee -a $(BUILD_DETAILS_FILE) + @printf "\nexec: %s\n" "$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USB1LIBS)" >>$(BUILD_DETAILS_FILE) + @{ { { { { $(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USB1LIBS) >&2 && \ + echo "yes." || { echo "no."; \ + echo "Please install libusb-1.0."; \ + echo "See README for more information."; echo; \ + rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 + @rm -f .test.c .test.o .test$(EXEC_SUFFIX) +endif .features: features diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 517c00e..7c8c70c 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -1070,7 +1070,7 @@ needs TCP access to the network or userspace access to a serial port. needs userspace access to a serial port. .sp .BR dediprog ", " ft2232_spi ", " usbblaster_spi " and " pickit2_spi -need access to the USB device via libusb. +need access to the respective USB device via libusb-0.1. .sp .B dummy needs no access permissions at all. -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH] Add infrastructure to support libusb-1.0.
by Carl-Daniel Hailfinger 18 Jan '16

18 Jan '16

On 07.01.2016 19:50, Stefan Tauner wrote: > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Thanks! Comments below. > diff --git a/Makefile b/Makefile > index 6ddca58..500f71f 100644 > --- a/Makefile > +++ b/Makefile > @@ -966,6 +986,24 @@ ifeq ($(CHECK_LIBUSB0), yes) > rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 > @rm -f .test.c .test.o .test$(EXEC_SUFFIX) > endif > +ifeq ($(CHECK_LIBUSB1), yes) > + @printf "Checking for libusb-1.0 headers... " > + @echo "$$LIBUSB1_TEST" > .test.c > + @printf "\nexec: %s\n" "$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o" >>$(BUILD_DETAILS_FILE) > + @$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null && \ > + echo "found." || ( echo "not found."; echo; \ > + echo "Please install libusb-1.0 headers."; \ > + echo "See README for more information."; echo; \ > + rm -f .test.c .test.o; exit 1) > + @printf "Checking if libusb-1.0 is usable... " > + @printf "\nexec: %s\n" "$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USB1LIBS)" >>$(BUILD_DETAILS_FILE) > + @$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USB1LIBS) >/dev/null && \ > + echo "yes." || ( echo "no."; \ > + echo "Please install libusb-1.0."; \ > + echo "See README for more information."; echo; \ > + rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1) > + @rm -f .test.c .test.o .test$(EXEC_SUFFIX) > +endif The libusb1 test doesn't use the same fd redirect and tee operations which are present in the libusb0 test. Is that intentional? Regards, Carl-Daniel

2 2

Re: [flashrom] Can't identify SPI chip with buspirate_spi programmer
by David Hendricks 17 Jan '16

17 Jan '16

Hi Donald, Were you able to get it working? With the battery disconnected as you describe flashing with the Bus Pirate should work fine. I suspect there must be a bad connection elsewhere. You might be able to get further assistance on #flashrom on irc.freenode.net . On Thu, Jan 14, 2016 at 11:52 PM, Donald Dade <donald.dade(a)gmail.com> wrote: > Hi again, > > Something else which just occurred to me: > > I used flashrom on the Chromebook itself to program this very same > chip in the first place, without the -p option, which I assume > defaults to the internal programmer. It worked perfectly. Now that I > bricked it somehow, I tried to restore the BIOS image using flashrom > and the bus pirate as the programmer. This is the failure whose log I > sent you previously. > > Any idea why the internal programmer works, but the bus pirate > programmer can't recognize the chip? > > Thanks, > > Donald > > > On Thu, Jan 14, 2016 at 10:47 PM, Donald Dade <donald.dade(a)gmail.com> > wrote: > > Hi, > > > > I bricked my Chromebook and am trying to recover it. > > > > I'm using: > > > > Ubuntu 15.10 > > Bus Pirate v3.6 with firmware v6.2 > > flashrom 0.9.8 r1914 > > > > to try to read a: > > > > Windbond 25Q64FV on a Toshiba Chromebook 2 2015 (battery disconnected) > > > > by doing: > > > > sudo ./flashrom-0.9.8-r1914 -p buspirate_spi:dev=/dev/ttyUSB0 -r > > spi.bin -VVV -o log.txt > > > > but no operations are supported because the chip is not recognized. > > Can you provide any advice on how to move forward? > > > > Thank you, > > > > Donald > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

1 0

[PATCH] Add atapromise programmer
by Joseph Lehner 17 Jan '16

17 Jan '16

This patch adds a new programmer that supports (admittedly ancient) Promise ATA controllers. I've successfully tested this on an Ultra100 controller I had lying around. Mine uses a 128 kB MX29F001T flash chip, but I was not able to write anything past the first page (32 kB), which is not that much of a problem, since the option ROM files for these controllers are only 16 kB). It uses a (dirty?) hack to limit the chip size to 16 kB (so you can flash unmodified images) and provides an "allow32k=y" option, allowing you to flash larger images. Signed-off-by: Joseph C. Lehner <joseph.c.lehner(a)gmail.com>

3 11

[commit] r1916 - trunk
by repository service 17 Jan '16

17 Jan '16

Author: hailfinger Date: Sun Jan 17 00:45:25 2016 New Revision: 1916 URL: http://flashrom.org/trac/flashrom/changeset/1916 Log: Add atapromise programmer Supported controllers are Promise PDC20262 (FastTrak66/Ultra66), PDC20265 (FastTrak100 Lite/Ultra100), PDC20267 (FastTrak100/Ultra100). At least the Ultra100 only has address lines A0-A14 wired up, limiting addressable chip size to 32 kB. The flash chips mounted on those controllers usually is 128 kB, i.e. parts of the flash chip are inaccessible. As a workaround, the driver implicitly truncates the size of all flash chips to 32 kB. Works well for the factory installed flash. Do NOT use as a generic programmer for chips >32 kB. Signed-off-by: Joseph C. Lehner <joseph.c.lehner(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Urja Rannikko <urjaman(a)gmail.com> Added: trunk/atapromise.c Modified: trunk/Makefile trunk/flashrom.8.tmpl trunk/flashrom.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat Jan 16 19:50:27 2016 (r1915) +++ trunk/Makefile Sun Jan 17 00:45:25 2016 (r1916) @@ -227,6 +227,11 @@ else override CONFIG_ATAVIA = no endif +ifeq ($(CONFIG_ATAPROMISE), yes) +UNSUPPORTED_FEATURES += CONFIG_ATAPROMISE=yes +else +override CONFIG_ATAPROMISE = no +endif ifeq ($(CONFIG_IT8212), yes) UNSUPPORTED_FEATURES += CONFIG_IT8212=yes else @@ -449,6 +454,9 @@ # VIA VT6421A LPC memory support CONFIG_ATAVIA ?= yes +# Promise ATA controller support. +CONFIG_ATAPROMISE ?= no + # Always enable FT2232 SPI dongles for now. CONFIG_FT2232_SPI ?= yes @@ -626,6 +634,12 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_ATAPROMISE), yes) +FEATURE_CFLAGS += -D'CONFIG_ATAPROMISE=1' +PROGRAMMER_OBJS += atapromise.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_IT8212), yes) FEATURE_CFLAGS += -D'CONFIG_IT8212=1' PROGRAMMER_OBJS += it8212.o Added: trunk/atapromise.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/atapromise.c Sun Jan 17 00:45:25 2016 (r1916) @@ -0,0 +1,177 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2015 Joseph C. Lehner <joseph.c.lehner(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include <string.h> +#include <stdlib.h> +#include "flash.h" +#include "programmer.h" +#include "hwaccess.h" + +#define MAX_ROM_DECODE (32 * 1024) +#define ADDR_MASK (MAX_ROM_DECODE - 1) + +/* + * In the absence of any public docs on the PDC2026x family, this programmer was created through a mix of + * reverse-engineering and trial and error. + * + * The only device tested is an Ultra100 controller, but the logic for programming the other 2026x controllers + * is the same, so it should, in theory, work for those as well. + * + * While the tested Ultra100 controller used a 128 kB MX29F001T chip, A16 and A15 showed continuity to ground, + * thus limiting the the programmer on this card to 32 kB. Without other controllers to test this programmer on, + * this is currently a hard limit. Note that ROM files for these controllers are 16 kB only. + * + * Since flashrom does not support accessing flash chips larger than the size limit of the programmer (the + * tested Ultra100 uses a 128 kB MX29F001T chip), the chip size is hackishly adjusted in atapromise_limit_chip. + */ + +static uint32_t io_base_addr = 0; +static uint32_t rom_base_addr = 0; + +static uint8_t *atapromise_bar = NULL; +static size_t rom_size = 0; + +const struct dev_entry ata_promise[] = { + {0x105a, 0x4d38, NT, "Promise", "PDC20262 (FastTrak66/Ultra66)"}, + {0x105a, 0x0d30, NT, "Promise", "PDC20265 (FastTrak100 Lite/Ultra100)"}, + {0x105a, 0x4d30, OK, "Promise", "PDC20267 (FastTrak100/Ultra100)"}, + {0}, +}; + +static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); +static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr); + +static const struct par_master par_master_atapromise = { + .chip_readb = atapromise_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atapromise_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len) +{ + /* In case fallback_map ever returns something other than NULL. */ + return NULL; +} + +static void atapromise_limit_chip(struct flashchip *chip) +{ + static uint32_t last_model_id = 0; + unsigned int i, size; + + if (chip->model_id == last_model_id) + return; + + size = chip->total_size * 1024; + if (size > rom_size) { + /* Undefine all block_erasers that don't operate on the whole chip, + * and adjust the eraseblock size of the one that does. + */ + for (i = 0; i < NUM_ERASEFUNCTIONS; ++i) { + if (chip->block_erasers[i].eraseblocks[0].size != size) { + chip->block_erasers[i].eraseblocks[0].count = 0; + chip->block_erasers[i].block_erase = NULL; + } else { + chip->block_erasers[i].eraseblocks[0].size = rom_size; + break; + } + } + + if (i != NUM_ERASEFUNCTIONS) { + chip->total_size = rom_size / 1024; + if (chip->page_size > rom_size) + chip->page_size = rom_size; + } else { + msg_pdbg("Failed to adjust size of chip \"%s\" (%d kB).\n", chip->name, + chip->total_size); + } + } + + last_model_id = chip->model_id; +} + +int atapromise_init(void) +{ + struct pci_dev *dev = NULL; + + if (rget_io_perms()) + return 1; + + dev = pcidev_init(ata_promise, PCI_BASE_ADDRESS_4); + if (!dev) + return 1; + + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4) & 0xfffe; + if (!io_base_addr) { + return 1; + } + + /* Not exactly sure what this does, because flashing seems to work + * well without it. However, PTIFLASH does it, so we do it too. + */ + OUTB(1, io_base_addr + 0x10); + + rom_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5); + if (!rom_base_addr) { + msg_pdbg("Failed to read BAR5\n"); + return 1; + } + + rom_size = dev->rom_size > MAX_ROM_DECODE ? MAX_ROM_DECODE : dev->rom_size; + atapromise_bar = (uint8_t*)rphysmap("Promise", rom_base_addr, rom_size); + if (atapromise_bar == ERROR_PTR) { + return 1; + } + + max_rom_decode.parallel = rom_size; + register_par_master(&par_master_atapromise, BUS_PARALLEL); + + msg_pwarn("Do not use this device as a generic programmer. It will leave anything outside\n" + "the first %zu kB of the flash chip in an undefined state. It works fine for the\n" + "purpose of updating the firmware of this device (padding may neccessary).\n", + rom_size / 1024); + + return 0; +} + +static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + uint32_t data; + + atapromise_limit_chip(flash->chip); + data = (rom_base_addr + (addr & ADDR_MASK)) << 8 | val; + OUTL(data, io_base_addr + 0x14); +} + +static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + atapromise_limit_chip(flash->chip); + return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK)); +} + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sat Jan 16 19:50:27 2016 (r1915) +++ trunk/flashrom.8.tmpl Sun Jan 17 00:45:25 2016 (r1916) @@ -233,6 +233,8 @@ .sp .BR "* atavia" " (for flash ROMs on VIA VT6421A SATA controllers)" .sp +.BR "* atapromise" " (for flash ROMs on Promise PDC2026x ATA/RAID controllers)" +.sp .BR "* it8212" " (for flash ROMs on ITE IT8212F ATA/RAID controller)" .sp .BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H/FT232H family \ @@ -636,7 +638,7 @@ .SS .BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ -, " satamv" , " atahpt", " atavia " and " it8212 " programmers +, " satamv" , " atahpt", " atavia ", " atapromise " and " it8212 " programmers .IP These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported @@ -669,6 +671,13 @@ For more information please see .URLB https://flashrom.org/VT6421A "its wiki page" . .SS +.BR "atapromise " programmer +.IP +This programmer is currently limited to 32 kB, regardless of the actual size of the flash chip. This stems +from the fact that, on the tested device (a Promise Ultra100), not all of the chip's address lines were +actually connected. You may use this programmer to flash firmware updates, since these are only 16 kB in +size (padding to 32 kB is required). +.SS .BR "nicintel_eeprom " programmer .IP This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs @@ -1059,8 +1068,8 @@ .BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi need PCI configuration space read access and raw memory access. .sp -.B satamv -needs PCI configuration space read access, raw I/O port access and raw memory +.BR satamv " and " atapromise +need PCI configuration space read access, raw I/O port access and raw memory access. .sp .B serprog @@ -1076,7 +1085,7 @@ needs no access permissions at all. .sp .BR internal ", " nic3com ", " nicrealtek ", " nicnatsemi ", " -.BR gfxnvidia ", " drkaiser ", " satasii ", " satamv ", " atahpt" and " atavia +.BR gfxnvidia ", " drkaiser ", " satasii ", " satamv ", " atahpt ", " atavia " and " atapromise have to be run as superuser/root, and need additional raw access permission. .sp .BR serprog ", " buspirate_spi ", " dediprog ", " usbblaster_spi ", " ft2232_spi " and " pickit2_spi Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Jan 16 19:50:27 2016 (r1915) +++ trunk/flashrom.c Sun Jan 17 00:45:25 2016 (r1916) @@ -182,6 +182,18 @@ }, #endif +#if CONFIG_ATAPROMISE == 1 + { + .name = "atapromise", + .type = PCI, + .devs.dev = ata_promise, + .init = atapromise_init, + .map_flash_region = atapromise_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_IT8212 == 1 { .name = "it8212", Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Jan 16 19:50:27 2016 (r1915) +++ trunk/programmer.h Sun Jan 17 00:45:25 2016 (r1916) @@ -57,6 +57,9 @@ #if CONFIG_ATAVIA == 1 PROGRAMMER_ATAVIA, #endif +#if CONFIG_ATAPROMISE == 1 + PROGRAMMER_ATAPROMISE, +#endif #if CONFIG_IT8212 == 1 PROGRAMMER_IT8212, #endif @@ -460,6 +463,13 @@ extern const struct dev_entry ata_via[]; #endif +/* atapromise.c */ +#if CONFIG_ATAPROMISE == 1 +int atapromise_init(void); +void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len); +extern const struct dev_entry ata_promise[]; +#endif + /* it8212.c */ #if CONFIG_IT8212 == 1 int it8212_init(void);

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