- flashrom - mail.coreboot.org

Flashrom with Sil 3132
by Bernhardt, Pepper 22 May '10

22 May '10

I tried using your product to update the BIOS on a Silicon Image SATA controller but it gave me an error. Any help would be appreciated. Thanks, Pepper Here is the output: [root@oort Desktop]# flashrom -p satasii flashrom v0.9.1-r710 Found "Silicon Image SiI 3132 SATA Raid II Ctrl" (1095:3132, BDF 02:00.0). Found "Silicon Image SiI 3132 SATA Raid II Ctrl" (1095:3132, BDF 03:00.0). Found "Silicon Image SiI 3132 SATA Raid II Ctrl" (1095:3132, BDF 04:00.0). Found "Silicon Image SiI 3124 PCI-X SATA Ctrl" (1095:3124, BDF 06:02.0). === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom(a)flashrom.org if it works for you. Thank you for your help! === Error: Multiple supported PCI devices found. Use 'flashrom -p xxxx=bb:dd.f' to explicitly select the card with the given BDF (PCI bus, device, function). [root@oort Desktop]# flashrom -wV -p satasii:02:00.0 SiI3132_r7702.bin flashrom v0.9.1-r710 Found "Silicon Image SiI 3132 SATA Raid II Ctrl" (1095:3132, BDF 02:00.0). Mapping SATA SIL registers at 0xe0984000, unaligned size 0x100. Calibrating delay loop... 945M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0x55, id2 0xaa Probing for AMD Am29F002(N)BB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for AMD Am29F002(N)BT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0x55, id2 0xaa Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x55, id2 0xaa Probing for AMD Am29F080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x55, id2 0xaa Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0x55, id2 0xaa Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Atmel AT49F002(N), 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Atmel AT49F002(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xbf, id2 0xd7 Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xbf, id2 0xd7 Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0x55, id2 0xaa Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Eon EN25B05, 64 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for EON EN29F002(A)(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Fujitsu MBM29F004BC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Fujitsu MBM29F004TC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x55, id2 0x64 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x55, id2 0x64 Probing for Intel 28F001BX-B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Intel 28F001BX-T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Intel 82802AB, 512 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: probe_29f002: id1 0xbf, id2 0xd7 Probing for Macronix MX29F001T, 128 KB: probe_29f002: id1 0xbf, id2 0xd7 Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0xbf, id2 0xd7 Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0xbf, id2 0xd7 Probing for Macronix MX29LV040, 512 KB: probe_29f002: id1 0xbf, id2 0xd7 Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for PMC Pm29F0002T, 256 KB: probe_29f040b: id1 0x55, id2 0xaa Probing for PMC Pm29F0002B, 256 KB: probe_29f040b: id1 0x55, id2 0xaa Probing for PMC Pm39LV010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type Parallel and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type Parallel and chip bus type LPC,FWH are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x55, id2 0xaa Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST29EE020A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xbf, id2 0xd7 Found chip "SST SST39VF040" (512 KB, Parallel) at physical address 0xfff80000. Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for ST M29F002T/NT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x55, id2 0xaa Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x55, id2 0x64 Probing for ST M29W010B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for ST M29W040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for ST M50FLW040A, 512 KB: skipped. Host bus type Parallel and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type Parallel and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type Parallel and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type Parallel and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for SyncMOS S29C51001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for SyncMOS S29C51002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for SyncMOS S29C51004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for TI TMS29F002RB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for TI TMS29F002RT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Winbond W25x10, 128 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xbf, id2 0xd7 Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0xd7 Probing for Winbond W49V002A, 256 KB: skipped. Host bus type Parallel and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type Parallel and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Parallel and chip bus type SPI are incompatible. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help! === Error: Image size doesn't match

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[PATCH] Various programmer fixes
by Carl-Daniel Hailfinger 22 May '10

22 May '10

Initialize the internal delay function before running programmer init. The programmer init may need a good host delay function. Fix Tyan S2915 by commenting out MCP55 LPC PCI ID 10de:0361 and add debug output to avoid similar nightmares in the future. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-0.9.2-programmer_fixes/chipset_enable.c =================================================================== --- flashrom-0.9.2-programmer_fixes/chipset_enable.c (Revision 998) +++ flashrom-0.9.2-programmer_fixes/chipset_enable.c (Arbeitskopie) @@ -1354,7 +1354,15 @@ {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/ - {0x10de, 0x0361, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + /* 10de:0361 is present in Tyan S2915 systems, but not connected to + * the flash chip. Instead, 10de:0364 is connected to the flash chip. + * Until we have PCI device class matching or some fallback mechanism, + * this is needed to get flashrom working on Tyan S2915 and maybe other + * dual-MCP55 boards. + */ +#if 0 + {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ +#endif {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ @@ -1439,6 +1447,9 @@ msg_pinfo("Found chipset \"%s %s\", enabling flash write... ", chipset_enables[i].vendor_name, chipset_enables[i].device_name); + msg_pdbg("chipset PCI ID is %04x:%04x, ", + chipset_enables[i].vendor_id, + chipset_enables[i].device_id); ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); Index: flashrom-0.9.2-programmer_fixes/cli_classic.c =================================================================== --- flashrom-0.9.2-programmer_fixes/cli_classic.c (Revision 998) +++ flashrom-0.9.2-programmer_fixes/cli_classic.c (Arbeitskopie) @@ -378,6 +378,9 @@ flash = NULL; } + /* FIXME: Delay calibration should happen in programmer code. */ + myusec_calibrate_delay(); + msg_pdbg("Initializing %s programmer\n", programmer_table[programmer].name); if (programmer_init()) { @@ -386,8 +389,6 @@ } /* FIXME: Delay calibration should happen in programmer code. */ - myusec_calibrate_delay(); - for (i = 0; i < ARRAY_SIZE(flashes); i++) { flashes[i] = probe_flash(i ? flashes[i - 1] + 1 : flashchips, 0); -- http://www.hailfinger.org/

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[commit] r1008 - trunk
by repository service 22 May '10

22 May '10

Author: hailfinger Date: Sat May 22 09:31:50 2010 New Revision: 1008 URL: http://flashrom.org/trac/coreboot/changeset/1008 Log: Add debug output of the exact matched chipset PCI ID to keep track of tested PCI IDs for chipsets with one name and multiple IDs. This will help avoid problems similar to the Tyan S2915 OEM undetected flash in the future. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sat May 22 09:27:16 2010 (r1007) +++ trunk/chipset_enable.c Sat May 22 09:31:50 2010 (r1008) @@ -1447,6 +1447,9 @@ msg_pinfo("Found chipset \"%s %s\", enabling flash write... ", chipset_enables[i].vendor_name, chipset_enables[i].device_name); + msg_pdbg("chipset PCI ID is %04x:%04x, ", + chipset_enables[i].vendor_id, + chipset_enables[i].device_id); ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name);

1 0

[commit] r1007 - trunk
by repository service 22 May '10

22 May '10

Author: hailfinger Date: Sat May 22 09:27:16 2010 New Revision: 1007 URL: http://flashrom.org/trac/coreboot/changeset/1007 Log: Fix Tyan S2915 OEM board by commenting out MCP55 LPC bridge PCI ID 10de:0361 which is the secondary LPC bridge. The same effect could be achieved by refusing to run enable_flash_mcp55 if the device class is not ISA bridge [0601]. Thanks to Alessandro Polverini, Joel Robertson, Nicolas Aveline, Phil LoCascio and Nils-Helge Garli Hegvik for testing flashrom on hardware and Michael Karcher for analyzing the factory BIOS for clues. In the end, no board enable was needed and it was a pure chipset issue. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sat May 22 09:10:46 2010 (r1006) +++ trunk/chipset_enable.c Sat May 22 09:27:16 2010 (r1007) @@ -1354,7 +1354,15 @@ {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/ - {0x10de, 0x0361, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to + * the flash chip. Instead, 10de:0364 is connected to the flash chip. + * Until we have PCI device class matching or some fallback mechanism, + * this is needed to get flashrom working on Tyan S2915 and maybe other + * dual-MCP55 boards. + */ +#if 0 + {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ +#endif {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */

1 0

[commit] r1006 - trunk
by repository service 22 May '10

22 May '10

Author: hailfinger Date: Sat May 22 09:10:46 2010 New Revision: 1006 URL: http://flashrom.org/trac/coreboot/changeset/1006 Log: Initialize the internal delay function before running programmer init. The programmer init may need a good host delay function. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/cli_classic.c Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Sat May 22 01:09:42 2010 (r1005) +++ trunk/cli_classic.c Sat May 22 09:10:46 2010 (r1006) @@ -378,6 +378,9 @@ flash = NULL; } + /* FIXME: Delay calibration should happen in programmer code. */ + myusec_calibrate_delay(); + msg_pdbg("Initializing %s programmer\n", programmer_table[programmer].name); if (programmer_init()) { @@ -386,8 +389,6 @@ } /* FIXME: Delay calibration should happen in programmer code. */ - myusec_calibrate_delay(); - for (i = 0; i < ARRAY_SIZE(flashes); i++) { flashes[i] = probe_flash(i ? flashes[i - 1] + 1 : flashchips, 0);

1 0

[commit] r1005 - trunk
by repository service 22 May '10

22 May '10

Author: hailfinger Date: Sat May 22 01:09:42 2010 New Revision: 1005 URL: http://flashrom.org/trac/coreboot/changeset/1005 Log: Every SPI programmer driver had its own completely different chip write implementation, and all of them were insufficiently commented. Create spi_write_chunked as a copy of spi_read_chunked and convert all SPI programmers to use it. No functional changes except: - Bus Pirate uses 12 Byte writes instead of 8 Byte writes - SB600 uses 5 Byte writes instead of 1 Byte writes Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/bitbang_spi.c trunk/buspirate_spi.c trunk/chipdrivers.h trunk/ft2232_spi.c trunk/ichspi.c trunk/sb600spi.c trunk/spi25.c Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Sat May 22 01:00:56 2010 (r1004) +++ trunk/bitbang_spi.c Sat May 22 01:09:42 2010 (r1005) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -142,24 +142,7 @@ int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; msg_pdbg("total_size is %d\n", total_size); - for (i = 0; i < total_size; i += 256) { - int l, r; - if (i + 256 <= total_size) - l = 256; - else - l = total_size - i; - - if ((r = spi_nbyte_program(i, &buf[i], l))) { - msg_perr("%s: write fail %d\n", __func__, r); - return 1; - } - - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - /* loop */; - } - - return 0; + return spi_write_chunked(flash, buf, 0, total_size, 256); } Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Sat May 22 01:00:56 2010 (r1004) +++ trunk/buspirate_spi.c Sat May 22 01:09:42 2010 (r1005) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -319,7 +319,6 @@ int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; spi_disable_blockprotect(); /* Erase first. */ @@ -330,25 +329,5 @@ } msg_pinfo("done.\n"); - /* FIXME: We could do 12 byte writes, but then we'd have to make sure - * not to cross a 256 byte page boundary. This problem only applies to - * writes, reads can cross page boundaries just fine. - */ - for (i = 0; i < total_size; i += 8) { - int l, r; - if (i + 8 <= total_size) - l = 8; - else - l = total_size - i; - - if ((r = spi_nbyte_program(i, &buf[i], l))) { - msg_perr("%s: write fail %d\n", __func__, r); - return 1; - } - - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - /* loop */; - } - - return 0; + return spi_write_chunked(flash, buf, 0, total_size, 12); } Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sat May 22 01:00:56 2010 (r1004) +++ trunk/chipdrivers.h Sat May 22 01:09:42 2010 (r1005) @@ -51,6 +51,7 @@ int spi_nbyte_program(int addr, uint8_t *bytes, int len); int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); /* 82802ab.c */ Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Sat May 22 01:00:56 2010 (r1004) +++ trunk/ft2232_spi.c Sat May 22 01:09:42 2010 (r1005) @@ -2,7 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009 Paul Fox <pgf(a)laptop.org> - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -288,7 +288,6 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; spi_disable_blockprotect(); /* Erase first. */ @@ -299,23 +298,7 @@ } msg_pinfo("done.\n"); msg_pdbg("total_size is %d\n", total_size); - for (i = 0; i < total_size; i += 256) { - int l, r; - if (i + 256 <= total_size) - l = 256; - else - l = total_size - i; - - if ((r = spi_nbyte_program(i, &buf[i], l))) { - msg_perr("%s: write fail %d\n", __func__, r); - return 1; - } - - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - /* loop */; - } - - return 0; + return spi_write_chunked(flash, buf, 0, total_size, 256); } #endif Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat May 22 01:00:56 2010 (r1004) +++ trunk/ichspi.c Sat May 22 01:09:42 2010 (r1005) @@ -5,7 +5,7 @@ * Copyright (C) 2008 Claus Gindhart <claus.gindhart(a)kontron.com> * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -149,8 +149,6 @@ static int program_opcodes(OPCODES * op); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); -static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, - int offset, int maxdata); /* for pairing opcodes with their required preop */ struct preop_opcode_pair { @@ -636,28 +634,6 @@ return -1; } -static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, - int offset, int maxdata) -{ - int page_size = flash->page_size; - uint32_t remaining = page_size; - int towrite; - - msg_pspew("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", - offset, page_size, bytes); - - for (; remaining > 0; remaining -= towrite) { - towrite = min(remaining, maxdata); - if (spi_nbyte_program(offset + (page_size - remaining), - &bytes[page_size - remaining], towrite)) { - msg_perr("Error writing"); - return 1; - } - } - - return 0; -} - int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; @@ -670,12 +646,14 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) { - int i, j, rc = 0; + int i, ret = 0; int total_size = flash->total_size * 1024; - int page_size = flash->page_size; int erase_size = 64 * 1024; int maxdata = 64; + if (spi_controller == SPI_CONTROLLER_VIA) + maxdata = 16; + spi_disable_blockprotect(); /* Erase first */ msg_pinfo("Erasing flash before programming... "); @@ -687,19 +665,15 @@ msg_pinfo("Programming page: \n"); for (i = 0; i < total_size / erase_size; i++) { - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - for (j = 0; j < erase_size / page_size; j++) { - ich_spi_write_page(flash, - (void *)(buf + (i * erase_size) + (j * page_size)), - (i * erase_size) + (j * page_size), maxdata); - } + ret = spi_write_chunked(flash, buf + (i * erase_size), + i * erase_size, erase_size, maxdata); + if (ret) + break; } msg_pinfo("\n"); - return rc; + return ret; } int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Sat May 22 01:00:56 2010 (r1004) +++ trunk/sb600spi.c Sat May 22 01:09:42 2010 (r1005) @@ -4,6 +4,7 @@ * Copyright (C) 2008 Wang Qingpei <Qingpei.Wang(a)amd.com> * Copyright (C) 2008 Joe Bao <Zheng.Bao(a)amd.com> * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -49,7 +50,6 @@ /* FIXME: SB600 can write 5 bytes per transaction. */ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) { - int i; int total_size = flash->total_size * 1024; int result = 0; @@ -63,19 +63,7 @@ msg_pinfo("done.\n"); msg_pinfo("Programming flash"); - for (i = 0; i < total_size; i++, buf++) { - result = spi_nbyte_program(i, buf, 1); - if (result) { - msg_perr("Write error!\n"); - return result; - } - - /* wait program complete. */ - if (i % 0x8000 == 0) - msg_pspew("."); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - ; - } + result = spi_write_chunked(flash, buf, 0, total_size, 5); msg_pinfo(" done.\n"); return result; } Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sat May 22 01:00:56 2010 (r1004) +++ trunk/spi25.c Sat May 22 01:09:42 2010 (r1005) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger + * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger * Copyright (C) 2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify @@ -874,7 +874,7 @@ } /* - * Read a complete flash chip. + * Read a part of the flash chip. * Each page is read separately in chunks with a maximum size of chunksize. */ int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) @@ -907,6 +907,52 @@ } if (rc) break; + } + + return rc; +} + +/* + * Write a part of the flash chip. + * Each page is written separately in chunks with a maximum size of chunksize. + */ +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) +{ + int rc = 0; + int i, j, starthere, lenhere; + /* FIXME: page_size is the wrong variable. We need max_writechunk_size + * in struct flashchip to do this properly. All chips using + * spi_chip_write_256 have page_size set to max_writechunk_size, so + * we're OK for now. + */ + int page_size = flash->page_size; + int towrite; + + /* Warning: This loop has a very unusual condition and body. + * The loop needs to go through each page with at least one affected + * byte. The lowest page number is (start / page_size) since that + * division rounds down. The highest page number we want is the page + * where the last byte of the range lives. That last byte has the + * address (start + len - 1), thus the highest page number is + * (start + len - 1) / page_size. Since we want to include that last + * page as well, the loop condition uses <=. + */ + for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { + /* Byte position of the first byte in the range in this page. */ + /* starthere is an offset to the base address of the chip. */ + starthere = max(start, i * page_size); + /* Length of bytes in the range in this page. */ + lenhere = min(start + len, (i + 1) * page_size) - starthere; + for (j = 0; j < lenhere; j += chunksize) { + towrite = min(chunksize, lenhere - j); + rc = spi_nbyte_program(starthere + j, buf + starthere - start + j, towrite); + if (rc) + break; + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(10); + } + if (rc) + break; } return rc;

1 0

[PATCH] Support old libpci <2.2.4
by Carl-Daniel Hailfinger 22 May '10

22 May '10

libpci < 2.2.4 can not store class info in struct pci_dev. Read class info manually and store it in a separate variable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-libpci_old_workaround/board_enable.c =================================================================== --- flashrom-libpci_old_workaround/board_enable.c (Revision 997) +++ flashrom-libpci_old_workaround/board_enable.c (Arbeitskopie) @@ -789,9 +789,11 @@ /* First, look for a known LPC bridge */ for (dev = pacc->devices; dev; dev = dev->next) { - pci_fill_info(dev, PCI_FILL_CLASS); + uint16_t device_class; + /* libpci before version 2.2.4 does not store class info. */ + device_class = pci_read_word(dev, PCI_CLASS_DEVICE); if ((dev->vendor_id == 0x8086) && - (dev->device_class == 0x0601)) { /* ISA Bridge */ + (device_class == 0x0601)) { /* ISA Bridge */ /* Is this device in our list? */ for (i = 0; intel_ich_gpio_table[i].id; i++) if (dev->device_id == intel_ich_gpio_table[i].id) -- http://www.hailfinger.org/

4 5

Patch to fix wrmsr for some toolchains
by Mart Raudsepp 22 May '10

22 May '10

Hello, My co-worker sent me a patch many months ago to forward upstream as appropriate, but apparently I had forgotten to do so and now hit the bug with my compiler version as well while testing something from SVN. So attached is that patch now, so that flash chip detection would work again on my Geode/CS5536 system. PS: I'm not subscribed to flashrom list right now, so please CC me on any replies Regards, Mart Raudsepp

4 5

[commit] r1004 - trunk
by repository service 22 May '10

22 May '10

Author: hailfinger Date: Sat May 22 01:00:56 2010 New Revision: 1004 URL: http://flashrom.org/trac/coreboot/changeset/1004 Log: libpci < 2.2.4 can not store class info in struct pci_dev. Read class info manually and store it in a separate variable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat May 22 00:28:19 2010 (r1003) +++ trunk/board_enable.c Sat May 22 01:00:56 2010 (r1004) @@ -789,9 +789,11 @@ /* First, look for a known LPC bridge */ for (dev = pacc->devices; dev; dev = dev->next) { - pci_fill_info(dev, PCI_FILL_CLASS); + uint16_t device_class; + /* libpci before version 2.2.4 does not store class info. */ + device_class = pci_read_word(dev, PCI_CLASS_DEVICE); if ((dev->vendor_id == 0x8086) && - (dev->device_class == 0x0601)) { /* ISA Bridge */ + (device_class == 0x0601)) { /* ISA Bridge */ /* Is this device in our list? */ for (i = 0; intel_ich_gpio_table[i].id; i++) if (dev->device_id == intel_ich_gpio_table[i].id)

1 0

[PATCH] support for NIC RTL8139 onboard flashing
by Jörg Fischer 22 May '10

22 May '10

Hi, here is the patch for RTL1839 based NICs. Still got some problems: * Those Nics can have a wide varity of PCI (Vendor) IDs. * Code is instable, "erase" fails but "read" reads only FFs. It is disabled by default in the Makefile. Regards, Jörg Fischer Signed-off-by: Joerg Fischer <turboj(a)gmx.de> Index: flash.h =================================================================== --- flash.h (Revision 999) +++ flash.h (Arbeitskopie) @@ -46,6 +46,10 @@ #if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM, #endif +#if NICREALTEK_SUPPORT == 1 + PROGRAMMER_NICREALTEK, + PROGRAMMER_NICREALTEK2, +#endif #if GFXNVIDIA_SUPPORT == 1 PROGRAMMER_GFXNVIDIA, #endif @@ -330,7 +334,7 @@ /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); -#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) || (ATAHPT_SUPPORT == 1) +#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) || (ATAHPT_SUPPORT == 1) || (NICREALTEK_SUPPORT == 1) void print_supported_pcidevs(struct pcidev_status *devs); #endif void print_supported_wiki(void); @@ -462,6 +466,18 @@ extern struct pcidev_status drkaiser_pcidev[]; #endif +/* nicrealtek.c */ +#if NICREALTEK_SUPPORT == 1 +int nicrealtek_init(void); +int nicsmc1211_init(void); +int nicrealtek_shutdown(void); +void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); +uint8_t nicrealtek_chip_readb(const chipaddr addr); +extern struct pcidev_status nics_realtek[]; +extern struct pcidev_status nics_realteksmc1211[]; +#endif + + /* satasii.c */ #if SATASII_SUPPORT == 1 int satasii_init(void); Index: flashrom.c =================================================================== --- flashrom.c (Revision 999) +++ flashrom.c (Arbeitskopie) @@ -47,13 +47,17 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if NIC3COM_SUPPORT+GFXNVIDIA_SUPPORT+DRKAISER_SUPPORT+SATASII_SUPPORT+ATAHPT_SUPPORT+FT2232_SPI_SUPPORT+SERPROG_SUPPORT+BUSPIRATE_SPI_SUPPORT+DEDIPROG_SUPPORT > 1 +#if NIC3COM_SUPPORT+GFXNVIDIA_SUPPORT+DRKAISER_SUPPORT+SATASII_SUPPORT+ATAHPT_SUPPORT+FT2232_SPI_SUPPORT+SERPROG_SUPPORT+BUSPIRATE_SPI_SUPPORT+DEDIPROG_SUPPORT+NICREALTEK_SUPPORT > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all external programmers except one. #endif enum programmer programmer = #if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM #endif +#if NICREALTEK_SUPPORT == 1 + PROGRAMMER_NICREALTEK + PROGRAMMER_NICREALTEK2 +#endif #if GFXNVIDIA_SUPPORT == 1 PROGRAMMER_GFXNVIDIA #endif @@ -159,6 +163,42 @@ }, #endif +#if NICREALTEK_SUPPORT == 1 + { + .name = "nicrealtek", + .init = nicrealtek_init, + .shutdown = nicrealtek_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, + { + .name = "nicsmc1211", + .init = nicsmc1211_init, + .shutdown = nicrealtek_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + + #if GFXNVIDIA_SUPPORT == 1 { .name = "gfxnvidia", Index: Makefile =================================================================== --- Makefile (Revision 999) +++ Makefile (Arbeitskopie) @@ -110,6 +110,9 @@ # Always enable Dr. Kaiser for now. CONFIG_DRKAISER ?= yes +# Disable Realtek NICs for now, not working correctly. +CONFIG_NICREALTEK ?= no + # Always enable Bus Pirate SPI for now. CONFIG_BUSPIRATESPI ?= yes @@ -181,6 +184,14 @@ NEED_PCI := yes endif + +ifeq ($(CONFIG_NICREALTEK), yes) +FEATURE_CFLAGS += -D'NICREALTEK_SUPPORT=1' +PROGRAMMER_OBJS += nicrealtek.o +NEED_PCI := yes +endif + + ifeq ($(CONFIG_BUSPIRATESPI), yes) FEATURE_CFLAGS += -D'BUSPIRATE_SPI_SUPPORT=1' PROGRAMMER_OBJS += buspirate_spi.o Index: nicrealtek.c =================================================================== --- nicrealtek.c (Revision 0) +++ nicrealtek.c (Revision 0) @@ -0,0 +1,84 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 TURBO J <turboj(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include <sys/types.h> +#include "flash.h" + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_VENDOR_ID_SMC1211 0x1113 + +#define BIOS_ROM_ADDR 0xD4 +#define BIOS_ROM_DATA 0xD7 + +struct pcidev_status nics_realtek[] = { + {0x10ec, 0x8139, OK, "Realtek","rtl8139b/c PCI 10/100 Mbps"}, + {}, +}; + +struct pcidev_status nics_realteksmc1211[] = { + {0x1113, 0x1211, OK, "SMC", "SMC 1211TX rtl8139 clone 10/100 Mbps"}, + {} +}; + + +int nicrealtek_init(void) +{ + get_io_perms(); + io_base_addr = pcidev_init(PCI_VENDOR_ID_REALTEK, PCI_BASE_ADDRESS_0, + nics_realtek, programmer_param); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + + +int nicsmc1211_init(void) +{ + get_io_perms(); + io_base_addr = pcidev_init(PCI_VENDOR_ID_SMC1211, PCI_BASE_ADDRESS_0, + nics_realteksmc1211, programmer_param); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + +int nicrealtek_shutdown(void) +{ + free(programmer_param); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +void nicrealtek_chip_writeb(uint8_t val, chipaddr addr) +{ + OUTL(((uint32_t)addr &0x01FFFF)|0x0A0000| (val << 24), io_base_addr + BIOS_ROM_ADDR); + OUTL(((uint32_t)addr &0x01FFFF)|0x1E0000| (val << 24), io_base_addr + BIOS_ROM_ADDR); +} + +uint8_t nicrealtek_chip_readb(const chipaddr addr) +{ + OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000, io_base_addr + BIOS_ROM_ADDR); + return INB(io_base_addr + BIOS_ROM_DATA); +}

3 5

[commit] r1003 - trunk
by repository service 22 May '10

22 May '10

Author: hailfinger Date: Sat May 22 00:28:19 2010 New Revision: 1003 URL: http://flashrom.org/trac/coreboot/changeset/1003 Log: Add missing nicrealtek.c which was missing from revision 1002 which was Support for Realtek RTL8139 network card flashing. Signed-off-by: Joerg Fischer <turboj(a)gmx.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/nicrealtek.c Added: trunk/nicrealtek.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/nicrealtek.c Sat May 22 00:28:19 2010 (r1003) @@ -0,0 +1,89 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Joerg Fischer <turboj(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include <sys/types.h> +#include "flash.h" + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_VENDOR_ID_SMC1211 0x1113 + +#define BIOS_ROM_ADDR 0xD4 +#define BIOS_ROM_DATA 0xD7 + +struct pcidev_status nics_realtek[] = { + {0x10ec, 0x8139, OK, "Realtek","rtl8139b/c PCI 10/100 Mbps"}, + {}, +}; + +struct pcidev_status nics_realteksmc1211[] = { + {0x1113, 0x1211, OK, "SMC", "SMC 1211TX rtl8139 clone 10/100 Mbps"}, + {} +}; + + +int nicrealtek_init(void) +{ + get_io_perms(); + io_base_addr = pcidev_init(PCI_VENDOR_ID_REALTEK, PCI_BASE_ADDRESS_0, + nics_realtek, programmer_param); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + + +int nicsmc1211_init(void) +{ + get_io_perms(); + io_base_addr = pcidev_init(PCI_VENDOR_ID_SMC1211, PCI_BASE_ADDRESS_0, + nics_realteksmc1211, programmer_param); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + +int nicrealtek_shutdown(void) +{ + free(programmer_param); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +void nicrealtek_chip_writeb(uint8_t val, chipaddr addr) +{ + OUTL(((uint32_t)addr &0x01FFFF)|0x0A0000| (val << 24), io_base_addr + BIOS_ROM_ADDR); + OUTL(((uint32_t)addr &0x01FFFF)|0x1E0000| (val << 24), io_base_addr + BIOS_ROM_ADDR); +} + +uint8_t nicrealtek_chip_readb(const chipaddr addr) + +{ + uint8_t val=INB(io_base_addr + BIOS_ROM_DATA); + OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24), io_base_addr + BIOS_ROM_ADDR); + val=INB(io_base_addr + BIOS_ROM_DATA); + OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), io_base_addr + BIOS_ROM_ADDR); + return val ; + +}

1 0

[commit] r1002 - trunk
by repository service 21 May '10

21 May '10

Author: hailfinger Date: Fri May 21 23:54:07 2010 New Revision: 1002 URL: http://flashrom.org/trac/coreboot/changeset/1002 Log: Support for Realtek RTL8139 network card flashing. Signed-off-by: Joerg Fischer <turboj(a)gmx.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile trunk/flash.h trunk/flashrom.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed May 19 18:55:43 2010 (r1001) +++ trunk/Makefile Fri May 21 23:54:07 2010 (r1002) @@ -110,6 +110,9 @@ # Always enable Dr. Kaiser for now. CONFIG_DRKAISER ?= yes +# Always enable Realtek NICs for now. +CONFIG_NICREALTEK ?= yes + # Always enable Bus Pirate SPI for now. CONFIG_BUSPIRATESPI ?= yes @@ -181,6 +184,12 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_NICREALTEK), yes) +FEATURE_CFLAGS += -D'NICREALTEK_SUPPORT=1' +PROGRAMMER_OBJS += nicrealtek.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_BUSPIRATESPI), yes) FEATURE_CFLAGS += -D'BUSPIRATE_SPI_SUPPORT=1' PROGRAMMER_OBJS += buspirate_spi.o Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Wed May 19 18:55:43 2010 (r1001) +++ trunk/flash.h Fri May 21 23:54:07 2010 (r1002) @@ -46,6 +46,10 @@ #if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM, #endif +#if NICREALTEK_SUPPORT == 1 + PROGRAMMER_NICREALTEK, + PROGRAMMER_NICREALTEK2, +#endif #if GFXNVIDIA_SUPPORT == 1 PROGRAMMER_GFXNVIDIA, #endif @@ -330,7 +334,7 @@ /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); -#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) || (ATAHPT_SUPPORT == 1) +#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) || (ATAHPT_SUPPORT == 1) || (NICREALTEK_SUPPORT == 1) void print_supported_pcidevs(struct pcidev_status *devs); #endif void print_supported_wiki(void); @@ -462,6 +466,18 @@ extern struct pcidev_status drkaiser_pcidev[]; #endif +/* nicrealtek.c */ +#if NICREALTEK_SUPPORT == 1 +int nicrealtek_init(void); +int nicsmc1211_init(void); +int nicrealtek_shutdown(void); +void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); +uint8_t nicrealtek_chip_readb(const chipaddr addr); +extern struct pcidev_status nics_realtek[]; +extern struct pcidev_status nics_realteksmc1211[]; +#endif + + /* satasii.c */ #if SATASII_SUPPORT == 1 int satasii_init(void); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed May 19 18:55:43 2010 (r1001) +++ trunk/flashrom.c Fri May 21 23:54:07 2010 (r1002) @@ -47,13 +47,17 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if NIC3COM_SUPPORT+GFXNVIDIA_SUPPORT+DRKAISER_SUPPORT+SATASII_SUPPORT+ATAHPT_SUPPORT+FT2232_SPI_SUPPORT+SERPROG_SUPPORT+BUSPIRATE_SPI_SUPPORT+DEDIPROG_SUPPORT > 1 +#if NIC3COM_SUPPORT+GFXNVIDIA_SUPPORT+DRKAISER_SUPPORT+SATASII_SUPPORT+ATAHPT_SUPPORT+FT2232_SPI_SUPPORT+SERPROG_SUPPORT+BUSPIRATE_SPI_SUPPORT+DEDIPROG_SUPPORT+NICREALTEK_SUPPORT > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all external programmers except one. #endif enum programmer programmer = #if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM #endif +#if NICREALTEK_SUPPORT == 1 + PROGRAMMER_NICREALTEK + PROGRAMMER_NICREALTEK2 +#endif #if GFXNVIDIA_SUPPORT == 1 PROGRAMMER_GFXNVIDIA #endif @@ -159,6 +163,42 @@ }, #endif +#if NICREALTEK_SUPPORT == 1 + { + .name = "nicrealtek", + .init = nicrealtek_init, + .shutdown = nicrealtek_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, + { + .name = "nicsmc1211", + .init = nicsmc1211_init, + .shutdown = nicrealtek_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + + #if GFXNVIDIA_SUPPORT == 1 { .name = "gfxnvidia",

1 0

Re: [flashrom] flashrom Digest, Vol 12, Issue 35
by Julio Barrios 20 May '10

20 May '10

Hello Guenter, Thank you for taking the time to look for info about my MB. It is very similar to the one in the picture that you asked me to look at. I guess I have found the chip that you need to know about. It was covered by a heatsink and that's why I didn't see it. I hope this is the one. If it is not I will ask a friend to take a good picture of my MB. Please let me know. The chip that I uncovered says: Intel *NH82801IR* L7395128 SLA9N On the board I can also read: Foxconn DG33M03 SE0709 Rev A00 Hope that this helps. Thank you! Julio On 20 May 2010 18:12, <flashrom-request(a)flashrom.org> wrote: > Send flashrom mailing list submissions to > flashrom(a)flashrom.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://www.flashrom.org/mailman/listinfo/flashrom > or, via email, send a message with subject or body 'help' to > flashrom-request(a)flashrom.org > > You can reach the person managing the list at > flashrom-owner(a)flashrom.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of flashrom digest..." > > > Today's Topics: > > 1. Re: disaster (Carl-Daniel Hailfinger) > 2. Re: disaster (Julio Barrios) > 3. Re: disaster (Carl-Daniel Hailfinger) > 4. Re: disaster (Julio Barrios) > 5. Re: disaster (Guenter) > 6. TYAN s3992 (Alessandro Gervaso) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Thu, 20 May 2010 12:50:39 +0200 > From: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > To: Julio Barrios <jvbn.barrios(a)yahoo.co.uk>, flashrom > <flashrom(a)flashrom.org> > Subject: Re: [flashrom] disaster > Message-ID: <4BF513FF.60006(a)gmx.net> > Content-Type: text/plain; charset=ISO-8859-1 > > Hi Julio, > > it seems flashrom(a)flashrom.org was left out of the conversation by > accident. I've added it back, please use the "reply all" button in the > future. > > On 20.05.2010 12:12, Julio Barrios wrote: > > Hi Carl-Daniel, Joseph and Michael, > > > > Many thanks for your replies. I very much appreciate it. I'm not sure if > a > > flash chip is the same as the BIOS chip (I'm a complete newbie here and > am > > just learning a bit, and destroying computers along the way it seems > LOL!). > > Anyway, my BIOS is a Phoenix D686 and my PC is a Dell Inspiron 530. > > > > "Phoenix D686" is probably written on a sticker. Can you peel off the > sticker and tell us what's written on the BIOS flash chip? > > > > By the look of things, I guess that I will need to buy a new motherboard. > If > > that is the case, then I will need to buy one that is compatible with > linux > > because I'm not prepared to give up Ubuntu and go back to Windows. > > > > If you need any more information so that you can help me, please let me > > know. > > > > Some people/companies in the UK offer services to reflash mainboards. > That might be what you want, but I'm not sure if the shipping cost is > worth it. > Besides that, some vendors might offer top hat flash solutions for your > board, but I'm not 100% sure about this. > > > > Again, guys, thanks a lot. > > > > Julio > > > > Good luck! > > Regards, > Carl-Daniel > > > > On 20 May 2010 09:45, Carl-Daniel Hailfinger < > > c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > > > > >> Hi Julio, > >> > >> please note that the method in the link can destroy your mainboard if > >> your flash chip uses a different interface (very likely). See below for > >> details. > >> > >> On 20.05.2010 09:37, Carl-Daniel Hailfinger wrote: > >> > >>> On 20.05.2010 00:44, Joseph Smith wrote: > >>> > >>> > >>>> On 05/19/2010 06:38 PM, Michael Karcher wrote: > >>>> > >>>> > >>>>> IIRC, we recently had a link showing two stacked flash chips (but I > >>>>> think they were parallel, not LPC/FWH) with some control signals only > >>>>> connected to the top one - the idea was to mount a working flash chip > >>>>> > >> on > >> > >>>>> top of the one with damaged/wrong contents without removing the lower > >>>>> one from the system. Anyone knows what I'm talking about and still > has > >>>>> the link? > >>>>> > >>>>> > >>>> http://www.coreboot.org/pipermail/linuxbios/2007-April/020384.html > >>>> > >>>> > >>> The back-to-back socket solution (sometimes also marketed as top hat > >>> flash) would be the one which does not require soldering on the board > >>> and thus has a lower risk. > >>> > >>> > >> The best way to figure this out is to find out which flash chip you have > >> and tell us. Then we can try to find out which pins need to be bent and > >> disconnected. > >> > >> Regards, > >> Carl-Daniel > >> > >> -- > >> http://www.hailfinger.org/ > >> > >> > >> > > > > > > > -- > http://www.hailfinger.org/ > > > > > ------------------------------ > > Message: 2 > Date: Thu, 20 May 2010 12:15:15 +0100 > From: Julio Barrios <jvbn.barrios(a)yahoo.co.uk> > To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Cc: flashrom <flashrom(a)flashrom.org> > Subject: Re: [flashrom] disaster > Message-ID: > <AANLkTilTQN-bhH1p9ZNKpaKoM1lPNpMhkpFINbRb6RaK(a)mail.gmail.com> > Content-Type: text/plain; charset="iso-8859-1" > > Hi Carl-Daniel, > > Sorry about not sending my message in the correct way. > > I have now peeled off the sticker. This is what is on the flash chip: > > iTE > IT8718F-S > 2M24MA L > > I hope this means something to you. > > Best regarsd, > > Julio > > On 20 May 2010 11:50, Carl-Daniel Hailfinger < > c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > > Hi Julio, > > > > it seems flashrom(a)flashrom.org was left out of the conversation by > > accident. I've added it back, please use the "reply all" button in the > > future. > > > > On 20.05.2010 12:12, Julio Barrios wrote: > > > Hi Carl-Daniel, Joseph and Michael, > > > > > > Many thanks for your replies. I very much appreciate it. I'm not sure > if > > a > > > flash chip is the same as the BIOS chip (I'm a complete newbie here and > > am > > > just learning a bit, and destroying computers along the way it seems > > LOL!). > > > Anyway, my BIOS is a Phoenix D686 and my PC is a Dell Inspiron 530. > > > > > > > "Phoenix D686" is probably written on a sticker. Can you peel off the > > sticker and tell us what's written on the BIOS flash chip? > > > > > > > By the look of things, I guess that I will need to buy a new > motherboard. > > If > > > that is the case, then I will need to buy one that is compatible with > > linux > > > because I'm not prepared to give up Ubuntu and go back to Windows. > > > > > > If you need any more information so that you can help me, please let me > > > know. > > > > > > > Some people/companies in the UK offer services to reflash mainboards. > > That might be what you want, but I'm not sure if the shipping cost is > > worth it. > > Besides that, some vendors might offer top hat flash solutions for your > > board, but I'm not 100% sure about this. > > > > > > > Again, guys, thanks a lot. > > > > > > Julio > > > > > > > Good luck! > > > > Regards, > > Carl-Daniel > > > > > > > On 20 May 2010 09:45, Carl-Daniel Hailfinger < > > > c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > > > > > > > >> Hi Julio, > > >> > > >> please note that the method in the link can destroy your mainboard if > > >> your flash chip uses a different interface (very likely). See below > for > > >> details. > > >> > > >> On 20.05.2010 09:37, Carl-Daniel Hailfinger wrote: > > >> > > >>> On 20.05.2010 00:44, Joseph Smith wrote: > > >>> > > >>> > > >>>> On 05/19/2010 06:38 PM, Michael Karcher wrote: > > >>>> > > >>>> > > >>>>> IIRC, we recently had a link showing two stacked flash chips (but I > > >>>>> think they were parallel, not LPC/FWH) with some control signals > only > > >>>>> connected to the top one - the idea was to mount a working flash > chip > > >>>>> > > >> on > > >> > > >>>>> top of the one with damaged/wrong contents without removing the > lower > > >>>>> one from the system. Anyone knows what I'm talking about and still > > has > > >>>>> the link? > > >>>>> > > >>>>> > > >>>> http://www.coreboot.org/pipermail/linuxbios/2007-April/020384.html > > >>>> > > >>>> > > >>> The back-to-back socket solution (sometimes also marketed as top hat > > >>> flash) would be the one which does not require soldering on the board > > >>> and thus has a lower risk. > > >>> > > >>> > > >> The best way to figure this out is to find out which flash chip you > have > > >> and tell us. Then we can try to find out which pins need to be bent > and > > >> disconnected. > > >> > > >> Regards, > > >> Carl-Daniel > > >> > > >> -- > > >> http://www.hailfinger.org/ > > >> > > >> > > >> > > > > > > > > > > > > -- > > http://www.hailfinger.org/ > > > > >

2 1

Re: [flashrom] disaster
by Carl-Daniel Hailfinger 20 May '10

20 May '10

Hi Julio, it seems flashrom(a)flashrom.org was left out of the conversation by accident. I've added it back, please use the "reply all" button in the future. On 20.05.2010 12:12, Julio Barrios wrote: > Hi Carl-Daniel, Joseph and Michael, > > Many thanks for your replies. I very much appreciate it. I'm not sure if a > flash chip is the same as the BIOS chip (I'm a complete newbie here and am > just learning a bit, and destroying computers along the way it seems LOL!). > Anyway, my BIOS is a Phoenix D686 and my PC is a Dell Inspiron 530. > "Phoenix D686" is probably written on a sticker. Can you peel off the sticker and tell us what's written on the BIOS flash chip? > By the look of things, I guess that I will need to buy a new motherboard. If > that is the case, then I will need to buy one that is compatible with linux > because I'm not prepared to give up Ubuntu and go back to Windows. > > If you need any more information so that you can help me, please let me > know. > Some people/companies in the UK offer services to reflash mainboards. That might be what you want, but I'm not sure if the shipping cost is worth it. Besides that, some vendors might offer top hat flash solutions for your board, but I'm not 100% sure about this. > Again, guys, thanks a lot. > > Julio > Good luck! Regards, Carl-Daniel > On 20 May 2010 09:45, Carl-Daniel Hailfinger < > c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > >> Hi Julio, >> >> please note that the method in the link can destroy your mainboard if >> your flash chip uses a different interface (very likely). See below for >> details. >> >> On 20.05.2010 09:37, Carl-Daniel Hailfinger wrote: >> >>> On 20.05.2010 00:44, Joseph Smith wrote: >>> >>> >>>> On 05/19/2010 06:38 PM, Michael Karcher wrote: >>>> >>>> >>>>> IIRC, we recently had a link showing two stacked flash chips (but I >>>>> think they were parallel, not LPC/FWH) with some control signals only >>>>> connected to the top one - the idea was to mount a working flash chip >>>>> >> on >> >>>>> top of the one with damaged/wrong contents without removing the lower >>>>> one from the system. Anyone knows what I'm talking about and still has >>>>> the link? >>>>> >>>>> >>>> http://www.coreboot.org/pipermail/linuxbios/2007-April/020384.html >>>> >>>> >>> The back-to-back socket solution (sometimes also marketed as top hat >>> flash) would be the one which does not require soldering on the board >>> and thus has a lower risk. >>> >>> >> The best way to figure this out is to find out which flash chip you have >> and tell us. Then we can try to find out which pins need to be bent and >> disconnected. >> >> Regards, >> Carl-Daniel >> >> -- >> http://www.hailfinger.org/ >> >> >> > > -- http://www.hailfinger.org/

3 4

disaster
by Julio Barrios 20 May '10

20 May '10

Hello there, I guess I have just ruined my computer. I was trying flashrom under Ubuntu 10.04. All seemed to have gone well. I turned off my PC, but...well, you surely know the rest of the story. I cannot find any way of getting it to start. Any ideas that may help me will be very much appreciated. By the way, my PC is a Dell Inspiron 530. I look forward to your reply. Julio

4 4

[PATCH] flashrom 0.9.2
by Carl-Daniel Hailfinger 20 May '10

20 May '10

Finally! (And yes, I know that the release announement still needs to be written, and we have some pending bugfixes. I just want to get this out now to resume normal development, and AFAICS it has no regressions.) Increase flashrom release number to 0.9.2. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-0.9.2/Makefile =================================================================== --- flashrom-0.9.2/Makefile (Revision 998) +++ flashrom-0.9.2/Makefile (Arbeitskopie) @@ -73,7 +73,7 @@ # will not require subversion. The downloadable snapshots are already exported. SVNVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) -RELEASE := 0.9.1 +RELEASE := 0.9.2 VERSION := $(RELEASE)-r$(SVNVERSION) RELEASENAME ?= $(VERSION) -- http://www.hailfinger.org/

5 6

[commit] r1000 - trunk
by repository service 19 May '10

19 May '10

Author: hailfinger Date: Wed May 19 18:46:52 2010 New Revision: 1000 URL: http://flashrom.org/trac/coreboot/changeset/1000 Log: Increase flashrom release number to 0.9.2. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue May 18 01:19:22 2010 (r999) +++ trunk/Makefile Wed May 19 18:46:52 2010 (r1000) @@ -73,7 +73,7 @@ # will not require subversion. The downloadable snapshots are already exported. SVNVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) -RELEASE := 0.9.1 +RELEASE := 0.9.2 VERSION := $(RELEASE)-r$(SVNVERSION) RELEASENAME ?= $(VERSION)

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MSI K9N Neo-F v2 (MCP SPI)
by Kjell Braden 19 May '10

19 May '10

Hi, I own a MSI K9N Neo-F v2 (NVidia MCP65, Winbond W83627DHG) board. Find attached the outputs of "flashrom -V", "lspci -nnvvvxxx" and "superiotool -deV". A bios update archive can be found here at the vendors website [1], as well as a (low-res) photo [2]. HTH -Kjell [1] http://download1.msi.com/files/downloads/bos_exe/7369v29.zip [2] http://msi.com/uploads/prod_6ee5713ac0f0e194a49ec7183c185f7e.jpg

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flashrom -V on Zotac 9300 ITX WIFI
by Joakim Gissberg 19 May '10

19 May '10

Attatched.

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This flash part has status UNTESTED for operations: ERASE
by Németh Csaba 19 May '10

19 May '10

csaba@lucid_lynx:~/Letöltések$ sudo flashrom -EV > flashrom_EV.txt spi_block_erase_20 failed during command execution at address 0x0 csaba@lucid_lynx:~/Letöltések$ TESTED :)

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[PROPOSAL] support for NIC RTL8139 onboard flashing
by Guenter 18 May '10

18 May '10

Hi all, a lot of Realtek RTL8139 NICs have a DIL-32 bootrom socket, and it is possible from DOS to flash PXE bootcode directly onboard provided you use ATMEL AT29C512 or AT29C010A flashs; here's the download of the Realtek flash program (see DOS section): http://www.realtek.com.tw/downloads/downloadsView.aspx?Langid=1&PNid=6&PFid… unfortunately Realtek's flash utility only supports ATMEL flashs, and even more worse is the trap that you can only flash the chip if it is detected by the BIOS - if you just insert an empty chip then it didnt work for me; the chip needs at least the 55AA code at the beginning so that its memory is mapped into adapter space by the MB BIOS. Do you think that it is possible to add support for flashing these cards (omst likely the RTL8169 GB NICs work same) to flashrom? Günter.

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[commit] r999 - trunk
by repository service 18 May '10

18 May '10

Author: mkarcher Date: Tue May 18 01:19:22 2010 New Revision: 999 URL: http://flashrom.org/trac/coreboot/changeset/999 Log: msr_t memory layout may depend on compiler; with optimizations this may lead to writing incorrect data to MSR. Create a temporary buffer with correct layout to avoid this problem. Signed-off-by: Anti Sullin <anti.sullin(a)artecdesign.ee> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/physmap.c Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Sat May 15 17:04:37 2010 (r998) +++ trunk/physmap.c Tue May 18 01:19:22 2010 (r999) @@ -282,13 +282,17 @@ int wrmsr(int addr, msr_t msr) { + uint32_t buf[2]; + buf[0] = msr.lo; + buf[1] = msr.hi; + if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { perror("Could not lseek() to MSR"); close(fd_msr); exit(1); } - if (write(fd_msr, &msr, 8) != 8 && errno != EIO) { + if (write(fd_msr, buf, 8) != 8 && errno != EIO) { perror("Could not write() MSR"); close(fd_msr); exit(1);

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flashrom command line syntax change
by Carl-Daniel Hailfinger 15 May '10

15 May '10

Hi, [please followup to flashrom(a)flashrom.org] since I didn't get any answers except "hmm..." on IRC, I hope that list feedback will be more verbose. In the past, flashrom served one purpose (developers writing LinuxBIOS images or parts thereof to onboard flash), but nowadays it can handle external programmers, graphics/network/storage cards and other hardware as well. Given that the flashrom user base is growing rapidly especially among less technically inclined people, we changed the flashrom command line interface in various ways to eliminate nasty surprises. The flashrom 0.9.2 release is impending (only one small bugfix and one big frontend/documentation patch left), and this is why I'd like comments about the following change: -r and -w and -v currently take a filename argument, but that filename can be anywhere on the command line. Examples: flashrom -p dummy backup.rom -r flashrom -rp dummy backup.rom flashrom -rV backup.rom flashrom -p dummy -r backup.rom This flashrom behaviour is confusing and contradicts the man page which says that -r/-w/-v are followed by a filename. Besides that, all other options with arguments want their arguments directly after the option. I posted a patch which will make the accepted command line syntax conform to the man page, but I'd like to hear about any problems this change may cause. The patch is at http://patchwork.coreboot.org/patch/1298/ (click on "patch" to download it in raw form) and applies cleanly against latest flashrom from svn. Tests of current svn flashrom with the patch applied are really appreciated, and feedback about the interface change will be taken seriously. Regards, Carl-Daniel -- http://www.hailfinger.org/

3 3

[PATCH] Unlocking for W39V040FA
by Michael Karcher 15 May '10

15 May '10

Now added the missing "REGISTERMAP" feature. --- flashchips.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/flashchips.c b/flashchips.c index 10c0989..d51c2bf 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6080,35 +6080,37 @@ struct flashchip flashchips[] = { { .vendor = "Winbond", .name = "W39V040FA", .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = WINBOND_ID, .model_id = W_39V040FA, .total_size = 512, .page_size = 64 * 1024, - .feature_bits = FEATURE_EITHER_RESET, + .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = 10, .block_erasers = { { .eraseblocks = { {4 * 1024, 128} }, .block_erase = erase_block_jedec, }, { .eraseblocks = { {64 * 1024, 8} }, .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = erase_chip_block_jedec, } }, + .printlock = printlock_sst_fwhub, + .unlock = unlock_sst_fwhub, .write = write_jedec_1, .read = read_memmapped, }, { .vendor = "Winbond", .name = "W39V080A", .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = WINBOND_ID, -- 1.7.1

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[PATCH] Unlocking for W39V040FA
by Michael Karcher 15 May '10

15 May '10

Should fix the current issue, probably obsoleted by the pending FWH unification. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- flashchips.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/flashchips.c b/flashchips.c index 10c0989..bc96a4a 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6097,18 +6097,20 @@ struct flashchip flashchips[] = { .block_erase = erase_block_jedec, }, { .eraseblocks = { {64 * 1024, 8} }, .block_erase = erase_sector_jedec, }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = erase_chip_block_jedec, } }, + .printlock = printlock_sst_fwhub, + .unlock = unlock_sst_fwhub, .write = write_jedec_1, .read = read_memmapped, }, { .vendor = "Winbond", .name = "W39V080A", .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = WINBOND_ID, -- 1.7.1

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