- flashrom - mail.coreboot.org

Double success story
by Maarten 14 Jul '10

14 Jul '10

Hi all! I'm here to tell you an success story with flashrom. It is about how flashrom solving problems created by using official tools. My first problem emerged when I tied to flash my EPIA-SP to it's latest bios release (I had some problems with PAL output). Well, VIA has a WinXP and a DOS tool available. I don't have any XP install so I decided to stick to FreeDOS. Took me two hours or so but after that I was all set. Having a hard drive with FreeDOS, viaflash and my image file, I began. I told viaflash to write the image file to flash. It said "Writing NOW!!!". There was no progress bar or anything, so I don't know when it crashed. But it did and it locked the computer completely, as I found out 10 minutes later. Power cable out, power cable in, no boot. Bricked. Nice. In an epic quest to find a suitable machine for hotswapping (I want a chip programmer this christmas, seriously) I found my neighbors PC. Same flash, same southbridge. Perfect! After some preparations for hotswapping I booted my GRML Linux disk, told flashrom to write my image, verified it once more and I were done. If I only used flashrom the first time... It would have saved me two days of messing around with all kinds of hardware and inferior pieces of software. Lesson learned. And now I knew how the job was done I also decided to update my laptop's bios. Stupid fuck I am I decided to erase the chip prior to backing it up and/or checking whether the update file did fit into my flash at all. It turned out to be bigger than 1024k and I panicked somewhat. Luckily a bunch of helpful people on IRC helped me to get a working image out of a >1024k Phoenix flash file (it has a footer) and after some commands I had updated my laptop too. Lesson learned here: Don't throw away your old landing gear in mid-flight if you are not sure whether your updated landing gear actually fits in the airplane. tnx for the great tools! grtz, Maarten "merethan"

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[PATCH] Convert SPI chips to partial write
by Carl-Daniel Hailfinger 14 Jul '10

14 Jul '10

Convert SPI chips to partial write, but wrap the write functions in a compat layer to allow converting the rest of flashrom later. I actually have patches for most of the remaining conversion, but I wanted to get this out and reviewed first. Compile tested, but that's it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-partial_write_spi_intermediate/flash.h =================================================================== --- flashrom-partial_write_spi_intermediate/flash.h (Revision 1072) +++ flashrom-partial_write_spi_intermediate/flash.h (Arbeitskopie) @@ -528,7 +528,7 @@ int ft2232_spi_init(void); int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); +int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* bitbang_spi.c */ extern int bitbang_spi_half_period; @@ -536,7 +536,7 @@ int bitbang_spi_init(void); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf); +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* buspirate_spi.c */ struct buspirate_spispeeds { @@ -547,7 +547,7 @@ int buspirate_spi_shutdown(void); int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf); +int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* dediprog.c */ int dediprog_init(void); @@ -667,7 +667,7 @@ /* Optimized functions for this programmer */ int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); - int (*write_256)(struct flashchip *flash, uint8_t *buf); + int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); }; extern enum spi_controller spi_controller; @@ -688,7 +688,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); +int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ @@ -701,13 +701,13 @@ int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf); +int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); +int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); extern uint8_t *sb600_spibar; /* wbsio_spi.c */ @@ -715,7 +715,7 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf); +int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf, int start, int len); /* serprog.c */ int serprog_init(void); Index: flashrom-partial_write_spi_intermediate/spi25.c =================================================================== --- flashrom-partial_write_spi_intermediate/spi25.c (Revision 1072) +++ flashrom-partial_write_spi_intermediate/spi25.c (Arbeitskopie) @@ -874,6 +874,7 @@ /* * Read a part of the flash chip. + * FIXME: Use the chunk code from Michael Karcher instead. * Each page is read separately in chunks with a maximum size of chunksize. */ int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) @@ -913,6 +914,7 @@ /* * Write a part of the flash chip. + * FIXME: Use the chunk code from Michael Karcher instead. * Each page is written separately in chunks with a maximum size of chunksize. */ int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) @@ -963,20 +965,13 @@ * and for chips where memory mapped programming is impossible * (e.g. due to size constraints in IT87* for over 512 kB) */ -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) +/* real chunksize is 1, logical chunksize is 1 */ +int spi_chip_write_1_new(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = 1024 * flash->total_size; int i, result = 0; spi_disable_blockprotect(); - /* Erase first */ - msg_cinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_cerr("ERASE FAILED!\n"); - return -1; - } - msg_cinfo("done.\n"); - for (i = 0; i < total_size; i++) { + for (i = start; i < start + len; i++) { result = spi_byte_program(i, buf[i]); if (result) return 1; @@ -987,11 +982,23 @@ return 0; } -int spi_aai_write(struct flashchip *flash, uint8_t *buf) +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) { - uint32_t addr = 0; - uint32_t len = flash->total_size * 1024; - uint32_t pos = addr; + spi_disable_blockprotect(); + /* Erase first */ + msg_cinfo("Erasing flash before programming... "); + if (erase_flash(flash)) { + msg_cerr("ERASE FAILED!\n"); + return -1; + } + msg_cinfo("done.\n"); + + return spi_chip_write_1_new(flash, buf, 0, flash->total_size * 1024); +} + +int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + uint32_t pos = start; int result; unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { JEDEC_AAI_WORD_PROGRAM, @@ -1006,9 +1013,9 @@ .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_AAI_WORD_PROGRAM, - (pos >> 16) & 0xff, - (pos >> 8) & 0xff, - (pos & 0xff), + (start >> 16) & 0xff, + (start >> 8) & 0xff, + (start & 0xff), buf[0], buf[1] }, @@ -1026,9 +1033,9 @@ #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: - msg_cerr("%s: impossible with this SPI controller," + msg_perr("%s: impossible with this SPI controller," " degrading to byte program\n", __func__); - return spi_chip_write_1(flash, buf); + return spi_chip_write_1_new(flash, buf, start, len); #endif #endif default: @@ -1036,7 +1043,7 @@ } /* The data sheet requires a start address with the low bit cleared. */ - if (addr % 2) { + if (start % 2) { msg_cerr("%s: start address not even! Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return SPI_GENERIC_ERROR; @@ -1048,10 +1055,6 @@ return SPI_GENERIC_ERROR; } - if (erase_flash(flash)) { - msg_cerr("ERASE FAILED!\n"); - return -1; - } result = spi_send_multicommand(cmds); if (result) { @@ -1065,7 +1068,7 @@ /* We already wrote 2 bytes in the multicommand step. */ pos += 2; - while (pos < addr + len) { + while (pos < start + len) { cmd[1] = buf[pos++]; cmd[2] = buf[pos++]; spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); Index: flashrom-partial_write_spi_intermediate/it87spi.c =================================================================== --- flashrom-partial_write_spi_intermediate/it87spi.c (Revision 1072) +++ flashrom-partial_write_spi_intermediate/it87spi.c (Arbeitskopie) @@ -328,30 +328,29 @@ return 0; } -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf) +int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = 1024 * flash->total_size; - int i; - /* * IT8716F only allows maximum of 512 kb SPI chip size for memory * mapped access. */ - if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) { - spi_chip_write_1(flash, buf); +#ifdef TODO +#warning This function needs to be converted to partial write + if ((programmer == PROGRAMMER_IT87SPI) || (flash->total_size * 1024 > 512 * 1024)) { +#endif + spi_chip_write_1_new(flash, buf, start, len); +#ifdef TODO +#warning This function needs to be converted to partial write } else { + int i; spi_disable_blockprotect(); - /* Erase first */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; - } - msg_pinfo("done.\n"); - for (i = 0; i < total_size / 256; i++) { + + /* FIXME: Handle chips which have max writechunk size >1 and <256. */ + for (i = 0; i < flash->total_size * 1024 / 256; i++) { it8716f_spi_page_program(flash, i, buf); } } +#endif return 0; } Index: flashrom-partial_write_spi_intermediate/buspirate_spi.c =================================================================== --- flashrom-partial_write_spi_intermediate/buspirate_spi.c (Revision 1072) +++ flashrom-partial_write_spi_intermediate/buspirate_spi.c (Arbeitskopie) @@ -309,18 +309,8 @@ return spi_read_chunked(flash, buf, start, len, 12); } -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf) +int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = 1024 * flash->total_size; - spi_disable_blockprotect(); - /* Erase first. */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; - } - msg_pinfo("done.\n"); - - return spi_write_chunked(flash, buf, 0, total_size, 12); + return spi_write_chunked(flash, buf, start, len, 12); } Index: flashrom-partial_write_spi_intermediate/bitbang_spi.c =================================================================== --- flashrom-partial_write_spi_intermediate/bitbang_spi.c (Revision 1072) +++ flashrom-partial_write_spi_intermediate/bitbang_spi.c (Arbeitskopie) @@ -139,10 +139,8 @@ return spi_read_chunked(flash, buf, start, len, 64 * 1024); } -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf) +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = 1024 * flash->total_size; - - msg_pdbg("total_size is %d\n", total_size); - return spi_write_chunked(flash, buf, 0, total_size, 256); + spi_disable_blockprotect(); + return spi_write_chunked(flash, buf, start, len, 256); } Index: flashrom-partial_write_spi_intermediate/flashchips.c =================================================================== --- flashrom-partial_write_spi_intermediate/flashchips.c (Revision 1072) +++ flashrom-partial_write_spi_intermediate/flashchips.c (Arbeitskopie) @@ -1392,7 +1392,7 @@ .block_erase = spi_block_erase_c7, } }, - .write = spi_aai_write, + .write = spi_chip_write_1, .read = read_memmapped, }, Index: flashrom-partial_write_spi_intermediate/spi.c =================================================================== --- flashrom-partial_write_spi_intermediate/spi.c (Revision 1072) +++ flashrom-partial_write_spi_intermediate/spi.c (Arbeitskopie) @@ -66,7 +66,7 @@ .command = sb600_spi_send_command, .multicommand = default_spi_send_multicommand, .read = sb600_spi_read, - .write_256 = sb600_spi_write_1, + .write_256 = sb600_spi_write_256, }, { /* SPI_CONTROLLER_VIA */ @@ -117,7 +117,7 @@ .command = dediprog_spi_send_command, .multicommand = default_spi_send_multicommand, .read = dediprog_spi_read, - .write_256 = spi_chip_write_1, + .write_256 = spi_chip_write_1_new, }, #endif @@ -197,7 +197,8 @@ * Program chip using page (256 bytes) programming. * Some SPI masters can't do this, they use single byte programming instead. */ -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) +/* real chunksize is up to 256, logical chunksize is 256 */ +int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].write_256) { msg_perr("%s called, but SPI page write is unsupported on this " @@ -206,9 +207,30 @@ return 1; } - return spi_programmer[spi_controller].write_256(flash, buf); + return spi_programmer[spi_controller].write_256(flash, buf, start, len); } +/* Wrapper function until the generic code is converted to partial writes. */ +int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) +{ + int ret; + + spi_disable_blockprotect(); + msg_pinfo("Erasing flash before programming... "); + if (erase_flash(flash)) { + msg_perr("ERASE FAILED!\n"); + return -1; + } + msg_pinfo("done.\n"); + msg_pinfo("Programming flash... "); + ret = spi_chip_write_256_new(flash, buf, 0, flash->total_size * 1024); + if (!ret) + msg_pinfo("done.\n"); + else + msg_pinfo("\n"); + return ret; +} + /* * Get the lowest allowed address for read accesses. This often happens to * be the lowest allowed address for all commands which take an address. Index: flashrom-partial_write_spi_intermediate/ft2232_spi.c =================================================================== --- flashrom-partial_write_spi_intermediate/ft2232_spi.c (Revision 1072) +++ flashrom-partial_write_spi_intermediate/ft2232_spi.c (Arbeitskopie) @@ -288,20 +288,10 @@ return spi_read_chunked(flash, buf, start, len, 64 * 1024); } -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf) +int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = 1024 * flash->total_size; - spi_disable_blockprotect(); - /* Erase first. */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; - } - msg_pinfo("done.\n"); - msg_pdbg("total_size is %d\n", total_size); - return spi_write_chunked(flash, buf, 0, total_size, 256); + return spi_write_chunked(flash, buf, start, len, 256); } #endif Index: flashrom-partial_write_spi_intermediate/wbsio_spi.c =================================================================== --- flashrom-partial_write_spi_intermediate/wbsio_spi.c (Revision 1072) +++ flashrom-partial_write_spi_intermediate/wbsio_spi.c (Arbeitskopie) @@ -189,16 +189,14 @@ return read_memmapped(flash, buf, start, len); } -int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf) +int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf, int start, int len) { - int size = flash->total_size * 1024; - - if (size > 1024 * 1024) { + if (flash->total_size * 1024 > 1024 * 1024) { msg_perr("%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); return 1; } - return spi_chip_write_1(flash, buf); + return spi_chip_write_1_new(flash, buf, start, len); } #endif Index: flashrom-partial_write_spi_intermediate/sb600spi.c =================================================================== --- flashrom-partial_write_spi_intermediate/sb600spi.c (Revision 1072) +++ flashrom-partial_write_spi_intermediate/sb600spi.c (Arbeitskopie) @@ -48,25 +48,10 @@ return spi_read_chunked(flash, buf, start, len, 8); } -/* FIXME: SB600 can write 5 bytes per transaction. */ -int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) +int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = flash->total_size * 1024; - int result = 0; - spi_disable_blockprotect(); - /* Erase first */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; - } - msg_pinfo("done.\n"); - - msg_pinfo("Programming flash"); - result = spi_write_chunked(flash, buf, 0, total_size, 5); - msg_pinfo(" done.\n"); - return result; + return spi_write_chunked(flash, buf, start, len, 5); } static void reset_internal_fifo_pointer(void) Index: flashrom-partial_write_spi_intermediate/ichspi.c =================================================================== --- flashrom-partial_write_spi_intermediate/ichspi.c (Revision 1072) +++ flashrom-partial_write_spi_intermediate/ichspi.c (Arbeitskopie) @@ -683,36 +683,15 @@ return spi_read_chunked(flash, buf, start, len, maxdata); } -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) +int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) { - int i, ret = 0; - int total_size = flash->total_size * 1024; - int erase_size = 64 * 1024; int maxdata = 64; if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; spi_disable_blockprotect(); - /* Erase first */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; - } - msg_pinfo("done.\n"); - - msg_pinfo("Programming page: \n"); - for (i = 0; i < total_size / erase_size; i++) { - ret = spi_write_chunked(flash, buf + (i * erase_size), - i * erase_size, erase_size, maxdata); - if (ret) - break; - } - - msg_pinfo("\n"); - - return ret; + return spi_write_chunked(flash, buf, start, len, maxdata); } int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, Index: flashrom-partial_write_spi_intermediate/chipdrivers.h =================================================================== --- flashrom-partial_write_spi_intermediate/chipdrivers.h (Revision 1072) +++ flashrom-partial_write_spi_intermediate/chipdrivers.h (Arbeitskopie) @@ -43,6 +43,8 @@ int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int spi_chip_write_256(struct flashchip *flash, uint8_t *buf); +int spi_chip_write_1_new(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len); int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); int spi_disable_blockprotect(void); @@ -51,7 +53,7 @@ int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf); +int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); /* 82802ab.c */ uint8_t wait_82802ab(chipaddr bios); -- http://www.hailfinger.org/

3 12

[commit] r1080 - trunk
by repository service 14 Jul '10

14 Jul '10

Author: hailfinger Date: Wed Jul 14 18:19:05 2010 New Revision: 1080 URL: http://flashrom.org/trac/coreboot/changeset/1080 Log: Convert SPI chips to partial write, but wrap the write functions in a compat layer to allow converting the rest of flashrom later. I actually have patches for most of the remaining conversion, but I wanted to get this out and reviewed first. Tested on Intel NM10 by David Hendricks. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/bitbang_spi.c trunk/buspirate_spi.c trunk/chipdrivers.h trunk/dummyflasher.c trunk/flash.h trunk/flashchips.c trunk/ft2232_spi.c trunk/ichspi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.c trunk/spi25.c trunk/wbsio_spi.c Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/bitbang_spi.c Wed Jul 14 18:19:05 2010 (r1080) @@ -139,10 +139,8 @@ return spi_read_chunked(flash, buf, start, len, 64 * 1024); } -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf) +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = 1024 * flash->total_size; - - msg_pdbg("total_size is %d\n", total_size); - return spi_write_chunked(flash, buf, 0, total_size, 256); + spi_disable_blockprotect(); + return spi_write_chunked(flash, buf, start, len, 256); } Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/buspirate_spi.c Wed Jul 14 18:19:05 2010 (r1080) @@ -309,18 +309,8 @@ return spi_read_chunked(flash, buf, start, len, 12); } -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf) +int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = 1024 * flash->total_size; - spi_disable_blockprotect(); - /* Erase first. */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; - } - msg_pinfo("done.\n"); - - return spi_write_chunked(flash, buf, 0, total_size, 12); + return spi_write_chunked(flash, buf, start, len, 12); } Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/chipdrivers.h Wed Jul 14 18:19:05 2010 (r1080) @@ -43,6 +43,8 @@ int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int spi_chip_write_256(struct flashchip *flash, uint8_t *buf); +int spi_chip_write_1_new(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len); int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); int spi_disable_blockprotect(void); @@ -51,7 +53,7 @@ int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf); +int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); /* 82802ab.c */ uint8_t wait_82802ab(chipaddr bios); Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/dummyflasher.c Wed Jul 14 18:19:05 2010 (r1080) @@ -167,3 +167,12 @@ return spi_read_chunked(flash, buf, start, len, 64 * 1024); } +/* Is is impossible to trigger this code path because dummyflasher probing will + * never be successful, and the current frontend refuses to write in that case. + * Other frontends may allow writing even for non-detected chips, though. + */ +int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + spi_disable_blockprotect(); + return spi_write_chunked(flash, buf, start, len, 256); +} Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/flash.h Wed Jul 14 18:19:05 2010 (r1080) @@ -456,6 +456,7 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ @@ -529,7 +530,7 @@ int ft2232_spi_init(void); int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); +int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* bitbang_spi.c */ extern int bitbang_spi_half_period; @@ -537,7 +538,7 @@ int bitbang_spi_init(void); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf); +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* buspirate_spi.c */ struct buspirate_spispeeds { @@ -548,7 +549,7 @@ int buspirate_spi_shutdown(void); int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf); +int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* dediprog.c */ int dediprog_init(void); @@ -668,7 +669,7 @@ /* Optimized functions for this programmer */ int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); - int (*write_256)(struct flashchip *flash, uint8_t *buf); + int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); }; extern enum spi_controller spi_controller; @@ -689,7 +690,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); +int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ @@ -701,13 +702,13 @@ int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf); +int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); +int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); extern uint8_t *sb600_spibar; /* wbsio_spi.c */ @@ -715,7 +716,7 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf); +int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf, int start, int len); /* serprog.c */ int serprog_init(void); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/flashchips.c Wed Jul 14 18:19:05 2010 (r1080) @@ -1423,7 +1423,7 @@ .block_erase = spi_block_erase_c7, } }, - .write = spi_aai_write, + .write = spi_chip_write_1, .read = spi_chip_read, }, Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/ft2232_spi.c Wed Jul 14 18:19:05 2010 (r1080) @@ -288,20 +288,10 @@ return spi_read_chunked(flash, buf, start, len, 64 * 1024); } -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf) +int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = 1024 * flash->total_size; - spi_disable_blockprotect(); - /* Erase first. */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; - } - msg_pinfo("done.\n"); - msg_pdbg("total_size is %d\n", total_size); - return spi_write_chunked(flash, buf, 0, total_size, 256); + return spi_write_chunked(flash, buf, start, len, 256); } #endif Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/ichspi.c Wed Jul 14 18:19:05 2010 (r1080) @@ -683,36 +683,15 @@ return spi_read_chunked(flash, buf, start, len, maxdata); } -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) +int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) { - int i, ret = 0; - int total_size = flash->total_size * 1024; - int erase_size = 64 * 1024; int maxdata = 64; if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; spi_disable_blockprotect(); - /* Erase first */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; - } - msg_pinfo("done.\n"); - - msg_pinfo("Programming page: \n"); - for (i = 0; i < total_size / erase_size; i++) { - ret = spi_write_chunked(flash, buf + (i * erase_size), - i * erase_size, erase_size, maxdata); - if (ret) - break; - } - - msg_pinfo("\n"); - - return ret; + return spi_write_chunked(flash, buf, start, len, maxdata); } int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/it87spi.c Wed Jul 14 18:19:05 2010 (r1080) @@ -292,7 +292,7 @@ } /* Page size is usually 256 bytes */ -static int it8716f_spi_page_program(struct flashchip *flash, int block, uint8_t *buf) +static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int start) { int i; int result; @@ -305,7 +305,7 @@ OUTB(0x06, it8716f_flashport + 1); OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { - chip_writeb(buf[256 * block + i], bios + 256 * block + i); + chip_writeb(buf[i], bios + start + i); } OUTB(0, it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. @@ -334,29 +334,39 @@ return 0; } -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf) +int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = 1024 * flash->total_size; - int i; - /* * IT8716F only allows maximum of 512 kb SPI chip size for memory * mapped access. */ - if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) { - spi_chip_write_1(flash, buf); + if ((programmer == PROGRAMMER_IT87SPI) || (flash->total_size * 1024 > 512 * 1024)) { + spi_chip_write_1_new(flash, buf, start, len); } else { + int lenhere; spi_disable_blockprotect(); - /* Erase first */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; + + if (start % 256) { + /* start to the end of the page or start + len, + * whichever is smaller. Page length is hardcoded to + * 256 bytes (IT87 SPI hardware limitation). + */ + lenhere = min(len, (start | 0xff) - start + 1); + spi_chip_write_1_new(flash, buf, start, lenhere); + start += lenhere; + len -= lenhere; + buf += lenhere; } - msg_pinfo("done.\n"); - for (i = 0; i < total_size / 256; i++) { - it8716f_spi_page_program(flash, i, buf); + + /* FIXME: Handle chips which have max writechunk size >1 and <256. */ + while (len >= 256) { + it8716f_spi_page_program(flash, buf, start); + start += 256; + len -= 256; + buf += 256; } + if (len) + spi_chip_write_1_new(flash, buf, start, len); } return 0; Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/sb600spi.c Wed Jul 14 18:19:05 2010 (r1080) @@ -48,25 +48,10 @@ return spi_read_chunked(flash, buf, start, len, 8); } -/* FIXME: SB600 can write 5 bytes per transaction. */ -int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) +int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = flash->total_size * 1024; - int result = 0; - spi_disable_blockprotect(); - /* Erase first */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; - } - msg_pinfo("done.\n"); - - msg_pinfo("Programming flash"); - result = spi_write_chunked(flash, buf, 0, total_size, 5); - msg_pinfo(" done.\n"); - return result; + return spi_write_chunked(flash, buf, start, len, 5); } static void reset_internal_fifo_pointer(void) Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/spi.c Wed Jul 14 18:19:05 2010 (r1080) @@ -66,7 +66,7 @@ .command = sb600_spi_send_command, .multicommand = default_spi_send_multicommand, .read = sb600_spi_read, - .write_256 = sb600_spi_write_1, + .write_256 = sb600_spi_write_256, }, { /* SPI_CONTROLLER_VIA */ @@ -99,7 +99,7 @@ .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, .read = dummy_spi_read, - .write_256 = NULL, + .write_256 = dummy_spi_write_256, }, #endif @@ -117,7 +117,7 @@ .command = dediprog_spi_send_command, .multicommand = default_spi_send_multicommand, .read = dediprog_spi_read, - .write_256 = spi_chip_write_1, + .write_256 = spi_chip_write_1_new, }, #endif @@ -196,8 +196,11 @@ /* * Program chip using page (256 bytes) programming. * Some SPI masters can't do this, they use single byte programming instead. + * The redirect to single byte programming is achieved by setting + * .write_256 = spi_chip_write_1 */ -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) +/* real chunksize is up to 256, logical chunksize is 256 */ +int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].write_256) { msg_perr("%s called, but SPI page write is unsupported on this " @@ -206,7 +209,28 @@ return 1; } - return spi_programmer[spi_controller].write_256(flash, buf); + return spi_programmer[spi_controller].write_256(flash, buf, start, len); +} + +/* Wrapper function until the generic code is converted to partial writes. */ +int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) +{ + int ret; + + spi_disable_blockprotect(); + msg_pinfo("Erasing flash before programming... "); + if (erase_flash(flash)) { + msg_perr("ERASE FAILED!\n"); + return -1; + } + msg_pinfo("done.\n"); + msg_pinfo("Programming flash... "); + ret = spi_chip_write_256_new(flash, buf, 0, flash->total_size * 1024); + if (!ret) + msg_pinfo("done.\n"); + else + msg_pinfo("\n"); + return ret; } /* Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/spi25.c Wed Jul 14 18:19:05 2010 (r1080) @@ -874,6 +874,7 @@ /* * Read a part of the flash chip. + * FIXME: Use the chunk code from Michael Karcher instead. * Each page is read separately in chunks with a maximum size of chunksize. */ int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) @@ -913,6 +914,7 @@ /* * Write a part of the flash chip. + * FIXME: Use the chunk code from Michael Karcher instead. * Each page is written separately in chunks with a maximum size of chunksize. */ int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) @@ -963,20 +965,13 @@ * and for chips where memory mapped programming is impossible * (e.g. due to size constraints in IT87* for over 512 kB) */ -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) +/* real chunksize is 1, logical chunksize is 1 */ +int spi_chip_write_1_new(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = 1024 * flash->total_size; int i, result = 0; spi_disable_blockprotect(); - /* Erase first */ - msg_cinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_cerr("ERASE FAILED!\n"); - return -1; - } - msg_cinfo("done.\n"); - for (i = 0; i < total_size; i++) { + for (i = start; i < start + len; i++) { result = spi_byte_program(i, buf[i]); if (result) return 1; @@ -987,11 +982,23 @@ return 0; } -int spi_aai_write(struct flashchip *flash, uint8_t *buf) +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) +{ + spi_disable_blockprotect(); + /* Erase first */ + msg_cinfo("Erasing flash before programming... "); + if (erase_flash(flash)) { + msg_cerr("ERASE FAILED!\n"); + return -1; + } + msg_cinfo("done.\n"); + + return spi_chip_write_1_new(flash, buf, 0, flash->total_size * 1024); +} + +int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) { - uint32_t addr = 0; - uint32_t len = flash->total_size * 1024; - uint32_t pos = addr; + uint32_t pos = start; int result; unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { JEDEC_AAI_WORD_PROGRAM, @@ -1006,9 +1013,9 @@ .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_AAI_WORD_PROGRAM, - (pos >> 16) & 0xff, - (pos >> 8) & 0xff, - (pos & 0xff), + (start >> 16) & 0xff, + (start >> 8) & 0xff, + (start & 0xff), buf[0], buf[1] }, @@ -1026,17 +1033,21 @@ #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: - msg_cerr("%s: impossible with this SPI controller," + msg_perr("%s: impossible with this SPI controller," " degrading to byte program\n", __func__); - return spi_chip_write_1(flash, buf); + return spi_chip_write_1_new(flash, buf, start, len); #endif #endif default: break; } + /* The even start address and even length requirements can be either + * honored outside this function, or we can call spi_byte_program + * for the first and/or last byte and use AAI for the rest. + */ /* The data sheet requires a start address with the low bit cleared. */ - if (addr % 2) { + if (start % 2) { msg_cerr("%s: start address not even! Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return SPI_GENERIC_ERROR; @@ -1048,15 +1059,14 @@ return SPI_GENERIC_ERROR; } - if (erase_flash(flash)) { - msg_cerr("ERASE FAILED!\n"); - return -1; - } result = spi_send_multicommand(cmds); if (result) { msg_cerr("%s failed during start command execution\n", __func__); + /* FIXME: Should we send WRDI here as well to make sure the chip + * is not in AAI mode? + */ return result; } while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) @@ -1065,7 +1075,7 @@ /* We already wrote 2 bytes in the multicommand step. */ pos += 2; - while (pos < addr + len) { + while (pos < start + len) { cmd[1] = buf[pos++]; cmd[2] = buf[pos++]; spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Wed Jul 14 01:56:13 2010 (r1079) +++ trunk/wbsio_spi.c Wed Jul 14 18:19:05 2010 (r1080) @@ -189,16 +189,14 @@ return read_memmapped(flash, buf, start, len); } -int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf) +int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf, int start, int len) { - int size = flash->total_size * 1024; - - if (size > 1024 * 1024) { + if (flash->total_size * 1024 > 1024 * 1024) { msg_perr("%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); return 1; } - return spi_chip_write_1(flash, buf); + return spi_chip_write_1_new(flash, buf, start, len); } #endif

1 0

[RFC] Address space alignment of flash
by Carl-Daniel Hailfinger 14 Jul '10

14 Jul '10

Hi, with the pending support of multiple architectures for internal flashing, we have to decide how to do flash mapping properly. Right now we have a number of ad-hoc hacks, and some of them work only by accident. Code snippets follow. probe_flash() { ... base = flashbase ? flashbase : (0xffffffff - size + 1); ... } map_flash_registers() { ... flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); ... } flashbase is only set for the AMD Elan SC520, and it is completely ignored for register mapping. Fortunately the SC520 supports no chips which would need register mapping. Some systems have bottom-aligned flash (fixed base address, variable end address). The ICT Loongson 2F processor and the AMD Elan SC520 are examples of that. Other systems have top-aligned flash (variable base address, fixed end address). Pretty much every x86 out there follows that model. It gets worse. Some flash chips have no register space (easy to handle), some have their register space 8 MB below content space (SST49LF040), some have their register space 4 MB below content space, and AFAIK some chips have their register space above content space. And sometimes people may want to specify an alternative location for a secondary flash chip (e.g. stacked/dual BIOS chips for LPC/FWH). Throw in cases where flash addresses are memory mapped at the address seen by the flash chip (most x86), memory mapped at an address different from the one seen by the flash chip (gfxnvidia, drkaiser), or accessed indirectly (nic3com etc.). I propose to have two global variables (or two local variables with global set/get functions): flashbase and flashtop. Exactly one of the variables has to be set by the programmer init function, and the one being nonzero is used. For flash chips without separate register space, no additional complexity is required. For flash chips with register space, FEATURE_REGISTERMAP would be replaced by FEATURE_REGISTER_4M_BELOW (a blanket change would probably be correct for 95% of all chips) and complemented with FEATURE_REGISTER_8M_BELOW and FEATURE_REGISTER_xM_ABOVE. flashrom would refuse to handle chips with "below" register space on bottom-aligned systems and refuse chips with "above" register space on top-aligned systems (well, it could do something sensible, but I have no idea what that would be). gfxnvidia and drkaiser would use flashbase (unless flashtop makes more sense there, but both programmers seem to support only non-register flash anyway), and programmers with indirect access can use either flashbase or flashtop depending on whether flash registers are above or below flash contents. This proposal breaks down once we want to support both register locations in the same flashrom run (in that case we have to specify both flashbase and flashtop), and it breaks down for systems where flash is bottom-aligned at address zero (flashbase would be valid but zero). We could add two additional variables flashbase_valid and flashtop_valid, and pick the one we want based on FEATURE_REGISTER_*. That should work everywhere. Comments? Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

SynMOS / Mosel Vitelic Chips
by Mattias Mattsson 14 Jul '10

14 Jul '10

Hi, I've done some research regarding SyncMOS and Mosel Vitelic (MVC) chips. There are essentially 15 different chips (or maybe 17, see below). They have the same model number and aslo, as far I can see identical other properties (id, size, bootblock position, etc). But it's probably a good idea if someone else cross checks the datasheets. According to the date stamps in the datasheets: Early chips seems to have the SyncMOS brand (before October 2000). The "Mosel Vitelic" brand is used between October 2000 and May 2002. From May 2002 and onwards "SyncMOS" is used again. (The above should probably be taken as an approximation only. Eg, I have a MVC-chip dated "9936".) The early SyncMOS chips use "F" as prefix, MVC use "V" and the later SyncMOS chips uses "S". The fourth group of characters designates Vcc and the suffix charcter (T/B) indicates top/bottom boot block. Here's a table with the chips I've found. Not all chips have all brands. +--------------------------+------------------------------+ | CHIP NAME | DEVICE ID | +--------------------------+------------------------------+ | V 29 C 51 000 T | 0x00 [1] | | V 29 C 51 000 B | 0xA0 [1] | | V 29 LC 51 000 | 0x20 [2] | | | | | {F,S,V} 29 C 51 001 T | 0x01 [3,4,5] | | {F,S,V} 29 C 51 001 B | 0xA1 [3,4,5] | | V 29 LC 51 001 | 0x60 [6] | | | | | {F,S,V} 29 C 51 002 T | 0x02 [7,8,9] | | {F,S,V} 29 C 51 002 B | 0xA2 [7,8,9] | | V 29 LC 51 002 | 0x82 [10] | | | | | {F,S,V} 29 C 51 004 T | 0x03 [14,15,16] | | {F,S,V} 29 C 51 004 B | 0xA3 [14,15,16] | | | | | {S,V} 29 C 31 004 T | 0x63 [11,13] 0x03 [12] | | {S,V} 29 C 31 004 B | 0x73 [11] 0xA3 [12] | | | | | V 29 C 51 400 T | 0x13 [17] | | V 29 C 51 400 B | 0xB3 [17] | +--------------------------+------------------------------+ Note that this table only contains chips for which I've found datasheets. I've also seen references to 0x83 (V29C31400T), 0xC3 (V29C31004B), (eg. in UNIFLASH's source code) but have not been able to find any datasheets for them. Also I think the Device ID:s in [12] are wrong. Cheers, -mattias 1. V29C51000T/V29C51000B Rev. 0.5 October 2000 http://www.ezoflash.com/datasheets/flash/Mosel_Vitelic/V29C51000.pdf 2. V29LC51000 Rev. 0.4 October 2000 http://www.ezoflash.com/datasheets/flash/Mosel_Vitelic/V29LC51000.pdf 3. F29C51001T/F29C51001B V1.0 May 1999 http://www.ezoflash.com/datasheets/flash/SyncMos/F29C51001.pdf 4. V29C51001T/V29C51001B Rev. 0.8 October 2000 http://www.ezoflash.com/datasheets/flash/Mosel_Vitelic/V29C51001.pdf 5. S29C51001T/S29C51001B V1.0 February 2003 http://www.ezoflash.com/datasheets/flash/SyncMos/S29C51001.pdf 6. V29LC51001 Rev. 0.5 October 2000 http://www.ezoflash.com/datasheets/flash/Mosel_Vitelic/V29LC51001.pdf 7. F29C51002T/F29C51002B V1.0 February 1998 http://www.ezoflash.com/datasheets/flash/SyncMos/F29C51002.pdf 8. V29C51002T/V29C51002B Rev. 2.1 October 2000 http://www.ezoflash.com/datasheets/flash/Mosel_Vitelic/V29C51002.pdf 9. S29C51002T/S29C51002B V1.0 May 2002 http://www.ezoflash.com/datasheets/flash/SyncMos/S29C51002.pdf 10. V29LC51002 Rev. 0.5 October 2000 http://www.ezoflash.com/datasheets/flash/Mosel_Vitelic/V29LC51002.pdf 11. V29C31004T/V29C31004B Rev. 0.3 October 2000 http://www.ezoflash.com/datasheets/flash/Mosel_Vitelic/V29C31004.pdf 12. S29C31004T/S29C31004B V0.1 September 2002 http://www.ezoflash.com/datasheets/flash/SyncMos/S29C31004.pdf 13. S29C31004T V1.0 MARCH 2005 http://www.dataman.com/Datasheets/SyncMOS/S29C31004T(20050311).pdf 14. F29C51004T/F29C51004B V1.0 November 1998 http://www.ezoflash.com/datasheets/flash/SyncMos/F29C51004.pdf 15. V29C51004T/V29C51004B Rev. 1.5 October 2000 http://www.ezoflash.com/datasheets/flash/Mosel_Vitelic/V29C51004.pdf 16. S29C51004T/S29C51004B V1.0 May 2002 http://www.ezoflash.com/datasheets/flash/SyncMos/S29C51004.pdf 17. V29C51400T/V29C51400B Rev. 1.5 October 2000 http://www.ezoflash.com/datasheets/flash/Mosel_Vitelic/V29C51400.pdf

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[PATCH] Refactor/fix read-to-file
by Carl-Daniel Hailfinger 14 Jul '10

14 Jul '10

Print an error message on read errors and abort instead of proceeding anyway. Improve error checking in file write, chip read and chip verify. Refactor the read routines a bit to split reading from file writing. Parts of this patch were already present in [PATCH] Avoid scary warning if nothing changed Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-read_error_checking/flash.h =================================================================== --- flashrom-read_error_checking/flash.h (Revision 1063) +++ flashrom-read_error_checking/flash.h (Arbeitskopie) @@ -578,7 +578,7 @@ int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); struct flashchip *probe_flash(struct flashchip *first_flash, int force); -int read_flash(struct flashchip *flash, char *filename); +int read_flash_to_file(struct flashchip *flash, char *filename); void check_chip_supported(struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); int min(int a, int b); Index: flashrom-read_error_checking/cli_classic.c =================================================================== --- flashrom-read_error_checking/cli_classic.c (Revision 1063) +++ flashrom-read_error_checking/cli_classic.c (Arbeitskopie) @@ -418,7 +418,7 @@ exit(1); } printf("Please note that forced reads most likely contain garbage.\n"); - return read_flash(flashes[0], filename); + return read_flash_to_file(flashes[0], filename); } // FIXME: flash writes stay enabled! programmer_shutdown(); Index: flashrom-read_error_checking/flashrom.c =================================================================== --- flashrom-read_error_checking/flashrom.c (Revision 1063) +++ flashrom-read_error_checking/flashrom.c (Arbeitskopie) @@ -673,7 +673,12 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; - flash->read(flash, readbuf, starthere, lenhere); + ret = flash->read(flash, readbuf, starthere, lenhere); + if (ret) { + msg_gerr("Verification impossible because read failed " + "at 0x%x (len 0x%x)\n", starthere, lenhere); + break; + } for (j = 0; j < lenhere; j++) { if (cmpbuf[starthere - start + j] != readbuf[j]) { /* Only print the first failure. */ @@ -1024,38 +1029,60 @@ return ret; } -int read_flash(struct flashchip *flash, char *filename) +int write_buf_to_file(unsigned char *buf, unsigned long size, char *filename) { unsigned long numbytes; FILE *image; - unsigned long size = flash->total_size * 1024; - unsigned char *buf = calloc(size, sizeof(char)); if (!filename) { - msg_gerr("Error: No filename specified.\n"); + msg_gerr("No filename specified.\n"); return 1; } if ((image = fopen(filename, "wb")) == NULL) { perror(filename); - exit(1); + return 1; } - msg_cinfo("Reading flash... "); - if (!flash->read) { - msg_cinfo("FAILED!\n"); - msg_cerr("ERROR: flashrom has no read function for this flash chip.\n"); - return 1; - } else - flash->read(flash, buf, 0, size); numbytes = fwrite(buf, 1, size, image); fclose(image); - free(buf); - msg_cinfo("%s.\n", numbytes == size ? "done" : "FAILED"); - if (numbytes != size) + if (numbytes != size) { + msg_gerr("File %s could not be written completely.\n", + filename); return 1; + } return 0; } +int read_flash_to_file(struct flashchip *flash, char *filename) +{ + unsigned long size = flash->total_size * 1024; + unsigned char *buf = calloc(size, sizeof(char)); + int ret = 0; + + msg_cinfo("Reading flash... "); + if (!buf) { + msg_gerr("Memory allocation failed!\n"); + msg_cinfo("FAILED.\n"); + return 1; + } + if (!flash->read) { + msg_cerr("No read function available for this flash chip.\n"); + ret = 1; + goto out_free; + } + if (flash->read(flash, buf, 0, size)) { + msg_cerr("Read operation failed!\n"); + ret = 1; + goto out_free; + } + + ret = write_buf_to_file(buf, flash->total_size * 1024, filename); +out_free: + free(buf); + msg_cinfo("%s.\n", ret ? "done" : "FAILED"); + return ret; +} + /* This function shares a lot of its structure with erase_flash(). * Even if an error is found, the function will keep going and check the rest. */ @@ -1383,7 +1410,7 @@ if (flash->unlock) flash->unlock(flash); - if (read_flash(flash, filename)) { + if (read_flash_to_file(flash, filename)) { programmer_shutdown(); return 1; } -- http://www.hailfinger.org/

2 3

[commit] r1079 - trunk
by repository service 14 Jul '10

14 Jul '10

Author: hailfinger Date: Wed Jul 14 01:56:13 2010 New Revision: 1079 URL: http://flashrom.org/trac/coreboot/changeset/1079 Log: Print an error message on read errors and abort instead of proceeding anyway. Improve error checking in file write, chip read and chip verify. Refactor the read routines a bit to split reading from file writing. Log for a failed read: [...] Found chip "Winbond W25x16" (2048 KB, SPI) at physical address 0xffe00000. Reading flash... Invalid OPCODE 0x03 Read operation failed! FAILED. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-By: Stephen Kou <stephen(a)hyarros.com> Modified: trunk/cli_classic.c trunk/flash.h trunk/flashrom.c Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Tue Jul 13 02:42:00 2010 (r1078) +++ trunk/cli_classic.c Wed Jul 14 01:56:13 2010 (r1079) @@ -417,7 +417,7 @@ exit(1); } printf("Please note that forced reads most likely contain garbage.\n"); - return read_flash(flashes[0], filename); + return read_flash_to_file(flashes[0], filename); } // FIXME: flash writes stay enabled! programmer_shutdown(); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Tue Jul 13 02:42:00 2010 (r1078) +++ trunk/flash.h Wed Jul 14 01:56:13 2010 (r1079) @@ -579,7 +579,7 @@ int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); struct flashchip *probe_flash(struct flashchip *first_flash, int force); -int read_flash(struct flashchip *flash, char *filename); +int read_flash_to_file(struct flashchip *flash, char *filename); void check_chip_supported(struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); int min(int a, int b); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Tue Jul 13 02:42:00 2010 (r1078) +++ trunk/flashrom.c Wed Jul 14 01:56:13 2010 (r1079) @@ -713,7 +713,12 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; - flash->read(flash, readbuf, starthere, lenhere); + ret = flash->read(flash, readbuf, starthere, lenhere); + if (ret) { + msg_gerr("Verification impossible because read failed " + "at 0x%x (len 0x%x)\n", starthere, lenhere); + break; + } for (j = 0; j < lenhere; j++) { if (cmpbuf[starthere - start + j] != readbuf[j]) { /* Only print the first failure. */ @@ -1064,38 +1069,60 @@ return ret; } -int read_flash(struct flashchip *flash, char *filename) +int write_buf_to_file(unsigned char *buf, unsigned long size, char *filename) { unsigned long numbytes; FILE *image; - unsigned long size = flash->total_size * 1024; - unsigned char *buf = calloc(size, sizeof(char)); if (!filename) { - msg_gerr("Error: No filename specified.\n"); + msg_gerr("No filename specified.\n"); return 1; } if ((image = fopen(filename, "wb")) == NULL) { perror(filename); - exit(1); - } - msg_cinfo("Reading flash... "); - if (!flash->read) { - msg_cinfo("FAILED!\n"); - msg_cerr("ERROR: flashrom has no read function for this flash chip.\n"); return 1; - } else - flash->read(flash, buf, 0, size); + } numbytes = fwrite(buf, 1, size, image); fclose(image); - free(buf); - msg_cinfo("%s.\n", numbytes == size ? "done" : "FAILED"); - if (numbytes != size) + if (numbytes != size) { + msg_gerr("File %s could not be written completely.\n", + filename); return 1; + } return 0; } +int read_flash_to_file(struct flashchip *flash, char *filename) +{ + unsigned long size = flash->total_size * 1024; + unsigned char *buf = calloc(size, sizeof(char)); + int ret = 0; + + msg_cinfo("Reading flash... "); + if (!buf) { + msg_gerr("Memory allocation failed!\n"); + msg_cinfo("FAILED.\n"); + return 1; + } + if (!flash->read) { + msg_cerr("No read function available for this flash chip.\n"); + ret = 1; + goto out_free; + } + if (flash->read(flash, buf, 0, size)) { + msg_cerr("Read operation failed!\n"); + ret = 1; + goto out_free; + } + + ret = write_buf_to_file(buf, flash->total_size * 1024, filename); +out_free: + free(buf); + msg_cinfo("%s.\n", ret ? "FAILED" : "done"); + return ret; +} + /* This function shares a lot of its structure with erase_flash(). * Even if an error is found, the function will keep going and check the rest. */ @@ -1444,7 +1471,7 @@ if (flash->unlock) flash->unlock(flash); - if (read_flash(flash, filename)) { + if (read_flash_to_file(flash, filename)) { programmer_shutdown(); return 1; }

1 0

Re: [flashrom] [PATCH] Simplify chunking logic
by Carl-Daniel Hailfinger 13 Jul '10

13 Jul '10

On 11.07.2010 18:42, Michael Karcher wrote: > Read function tested for chunk size 62 and with start offset 3, works > as expected. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > --- > spi25.c | 80 +++++++++++++++++++++++++------------------------------------- > 1 files changed, 32 insertions(+), 48 deletions(-) > > diff --git a/spi25.c b/spi25.c > index 51be397..260dd1c 100644 > --- a/spi25.c > +++ b/spi25.c > @@ -879,35 +879,27 @@ int spi_nbyte_read(int address, uint8_t *bytes, int len) > int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) > { > int rc = 0; > - int i, j, starthere, lenhere; > + int ofs, startofs, endofs; /* offsets relative to page begin */ > int page_size = flash->page_size; > - int toread; > - > - /* Warning: This loop has a very unusual condition and body. > - * The loop needs to go through each page with at least one affected > - * byte. The lowest page number is (start / page_size) since that > - * division rounds down. The highest page number we want is the page > - * where the last byte of the range lives. That last byte has the > - * address (start + len - 1), thus the highest page number is > - * (start + len - 1) / page_size. Since we want to include that last > - * page as well, the loop condition uses <=. > - */ > - for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { > - /* Byte position of the first byte in the range in this page. */ > - /* starthere is an offset to the base address of the chip. */ > - starthere = max(start, i * page_size); > - /* Length of bytes in the range in this page. */ > - lenhere = min(start + len, (i + 1) * page_size) - starthere; > - for (j = 0; j < lenhere; j += chunksize) { > - toread = min(chunksize, lenhere - j); > - rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread); > + int pageaddr, toread; > + > /* startofs is an offset to current page address. */ > + startofs = start % page_size; > + /* iterate over all affected pages */ > + for (pageaddr = start - startofs; pageaddr < start + len; > + pageaddr += page_size) { > Please use tabs here, at least for the first 8-space blocks. > + endofs = min(page_size, start + len - pageaddr); > endofs is a misnomer. The correct name would be one_after_endofs, but that name is ugly. What about /* Number of bytes to write in this page. */ lenhere = min(page_size, start + len - pageaddr) - startofs; and using (startofs + lenhere) in place of endofs everywhere? > + /* iterate over all chunks in the current page */ > + for (ofs = startofs; ofs < endofs; ofs += chunksize) { > + toread = min(chunksize, endofs - ofs); > + rc = spi_nbyte_read(pageaddr + ofs, buf, toread); > + buf += toread; > if (rc) > - break; > + goto leave_page_loop; > return rc; > } > - if (rc) > - break; > + startofs = 0; /* all further pages processed from start */ > } > > +leave_page_loop: > Not needed if you return rc immediately in the error case. > return rc; > } > Here is my variant of your code. Feel free to ignore it completely, I just wanted to send it for reference. int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) { int rc = 0; int j, lenhere; int page_size = flash->page_size; int pageaddr, toread, startofs; /* This loop needs to go through each page with at least one affected * byte. */ startofs = start % page_size; for (pageaddr = start - startofs; pageaddr < start + len; pageaddr += page_size) { /* startofs is an offset to current page address. */ /* Number of bytes to write in this page. */ lenhere = min(page_size, start + len - pageaddr) - startofs; for (j = startofs; j < startofs + lenhere; j += chunksize) { toread = min(chunksize, startofs + lenhere - j); rc = spi_nbyte_read(pageaddr + j, buf, toread); if (rc) return rc; buf += toread; } startofs = 0; } return rc; } Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

gigabyte dual bios programming
by Qing Pei Wang 13 Jul '10

13 Jul '10

hi Vadim, i am trying to flashing the gigabyte dual bios at this moment, have you ever tried to boot coreboot from the main bios? i flashed the main bios, but the board always did the checksum failed, the restore the bios to the legacy bios. Have you ever tried that? if flash the backup chip, how to make it boot first? -- Wang Qing Pei Phone: 86+13426369984

1 0

[PATCH] Split out erase region walking
by Carl-Daniel Hailfinger 13 Jul '10

13 Jul '10

Split erase region walking out of erase_flash. That allows us to use erase region walking for a combined erase/write action, and is a prerequisite for partial flashing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-walk_eraseregions/flashrom.c =================================================================== --- flashrom-walk_eraseregions/flashrom.c (Revision 1072) +++ flashrom-walk_eraseregions/flashrom.c (Arbeitskopie) @@ -1164,14 +1164,36 @@ return ret; } -int erase_flash(struct flashchip *flash) +static int walk_eraseregions(struct flashchip *flash, int erasefunction, int (*do_something) (struct flashchip *flash, unsigned int addr, unsigned int len)) { - int i, j, k, ret = 0, found = 0; + int i, j; + unsigned int done = 0; unsigned int start, len; + struct block_eraser eraser = flash->block_erasers[erasefunction]; + for (i = 0; i < NUM_ERASEREGIONS; i++) { + /* count==0 for all automatically initialized array + * members so the loop below won't be executed for them. + */ + for (j = 0; j < eraser.eraseblocks[i].count; j++) { + start = done + eraser.eraseblocks[i].size * j; + len = eraser.eraseblocks[i].size; + msg_cdbg("0x%06x-0x%06x, ", start, + start + len - 1); + if (do_something(flash, start, len)) + return 1; + } + done += eraser.eraseblocks[i].count * + eraser.eraseblocks[i].size; + } + return 0; +} +int erase_flash(struct flashchip *flash) +{ + int k, ret = 0, found = 0; + msg_cinfo("Erasing flash chip... "); for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { - unsigned int done = 0; struct block_eraser eraser = flash->block_erasers[k]; msg_cdbg("Looking at blockwise erase function %i... ", k); @@ -1194,24 +1216,7 @@ } found = 1; msg_cdbg("trying... "); - for (i = 0; i < NUM_ERASEREGIONS; i++) { - /* count==0 for all automatically initialized array - * members so the loop below won't be executed for them. - */ - for (j = 0; j < eraser.eraseblocks[i].count; j++) { - start = done + eraser.eraseblocks[i].size * j; - len = eraser.eraseblocks[i].size; - msg_cdbg("0x%06x-0x%06x, ", start, - start + len - 1); - ret = eraser.block_erase(flash, start, len); - if (ret) - break; - } - if (ret) - break; - done += eraser.eraseblocks[i].count * - eraser.eraseblocks[i].size; - } + ret = walk_eraseregions(flash, k, eraser.block_erase); msg_cdbg("\n"); /* If everything is OK, don't try another erase function. */ if (!ret) -- http://www.hailfinger.org/

2 4

[commit] r1078 - trunk
by repository service 13 Jul '10

13 Jul '10

Author: hailfinger Date: Tue Jul 13 02:42:00 2010 New Revision: 1078 URL: http://flashrom.org/trac/coreboot/changeset/1078 Log: Wrap a line which was 156 columns wide. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/flashrom.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Tue Jul 13 02:37:19 2010 (r1077) +++ trunk/flashrom.c Tue Jul 13 02:42:00 2010 (r1078) @@ -1164,7 +1164,10 @@ return ret; } -static int walk_eraseregions(struct flashchip *flash, int erasefunction, int (*do_something) (struct flashchip *flash, unsigned int addr, unsigned int len)) +static int walk_eraseregions(struct flashchip *flash, int erasefunction, + int (*do_something) (struct flashchip *flash, + unsigned int addr, + unsigned int len)) { int i, j; unsigned int start = 0;

1 0

[commit] r1077 - trunk
by repository service 13 Jul '10

13 Jul '10

Author: hailfinger Date: Tue Jul 13 02:37:19 2010 New Revision: 1077 URL: http://flashrom.org/trac/coreboot/changeset/1077 Log: Split erase region walking out of erase_flash. That allows us to use erase region walking for a combined erase/write action, and is a prerequisite for partial flashing, Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/flashrom.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Tue Jul 13 02:04:52 2010 (r1076) +++ trunk/flashrom.c Tue Jul 13 02:37:19 2010 (r1077) @@ -1164,14 +1164,34 @@ return ret; } +static int walk_eraseregions(struct flashchip *flash, int erasefunction, int (*do_something) (struct flashchip *flash, unsigned int addr, unsigned int len)) +{ + int i, j; + unsigned int start = 0; + unsigned int len; + struct block_eraser eraser = flash->block_erasers[erasefunction]; + for (i = 0; i < NUM_ERASEREGIONS; i++) { + /* count==0 for all automatically initialized array + * members so the loop below won't be executed for them. + */ + len = eraser.eraseblocks[i].size; + for (j = 0; j < eraser.eraseblocks[i].count; j++) { + msg_cdbg("0x%06x-0x%06x, ", start, + start + len - 1); + if (do_something(flash, start, len)) + return 1; + start += len; + } + } + return 0; +} + int erase_flash(struct flashchip *flash) { - int i, j, k, ret = 0, found = 0; - unsigned int start, len; + int k, ret = 0, found = 0; msg_cinfo("Erasing flash chip... "); for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { - unsigned int done = 0; struct block_eraser eraser = flash->block_erasers[k]; msg_cdbg("Looking at blockwise erase function %i... ", k); @@ -1194,24 +1214,7 @@ } found = 1; msg_cdbg("trying... "); - for (i = 0; i < NUM_ERASEREGIONS; i++) { - /* count==0 for all automatically initialized array - * members so the loop below won't be executed for them. - */ - for (j = 0; j < eraser.eraseblocks[i].count; j++) { - start = done + eraser.eraseblocks[i].size * j; - len = eraser.eraseblocks[i].size; - msg_cdbg("0x%06x-0x%06x, ", start, - start + len - 1); - ret = eraser.block_erase(flash, start, len); - if (ret) - break; - } - if (ret) - break; - done += eraser.eraseblocks[i].count * - eraser.eraseblocks[i].size; - } + ret = walk_eraseregions(flash, k, eraser.block_erase); msg_cdbg("\n"); /* If everything is OK, don't try another erase function. */ if (!ret)

1 0

Calpella Dump
by stephen＠hyarros.com 13 Jul '10

13 Jul '10

flashrom v0.9.2-r1075 on Linux 2.6.32-23-generic (x86_64), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1598M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10001 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Intel Corporation" DMI string system-product-name: "Calpella platform" DMI string system-version: "To be filled by O.E.M." DMI string baseboard-manufacturer: "To be filled by O.E.M." DMI string baseboard-product-name: "To be filled by O.E.M." DMI string baseboard-version: "To be filled by O.E.M." DMI string chassis-type: "Laptop" Found chipset "Intel 3400 Mobile", enabling flash write... chipset PCI ID is 8086:3b01, 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 Root Complex Register Block address = 0xfed1c000 GCS = 0xc61: BIOS Interface Lock-Down: enabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) FLOCKDN 1, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-write 0x58: 0x07ff0600 (FREG1: BIOS) 0x00600000-0x007fffff is read-write 0x5C: 0x05ff0003 (FREG2: Management Engine) 0x00003000-0x005fffff is read-write 0x60: 0x00020001 (FREG3: Gigabit Ethernet) 0x00001000-0x00002fff is read-write 0x64: 0x00000fff (FREG4: Platform Data) 0x00fff000-0x00000fff is read-write 0x74: 0x80120003 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0xfc400000 (SSFS, SSFC) 0x94: 0x0606 (PREOP) 0x96: 0x7f48 (OPTYPE) 0x98: 0x0405039f (OPMENU) 0x9C: 0x0102d820 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00000000 (FDOC) WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done SPI Read Configuration: prefetching enabled, caching enabled, OK. This chipset supports the following protocols: FWH,SPI. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Chip status register is 10 Found chip "Atmel AT25DF321" (4096 KB, SPI) at physical address 0xffc00000. Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xb6, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x53, id2 0xe8, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xb6, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for SST SST25VF040.REMS, 512 KB: Invalid OPCODE 0x90 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for SST SST25LF040A.RES, 512 KB: Invalid OPCODE 0xab Probing for SST SST25VF040B.REMS, 512 KB: Invalid OPCODE 0x90 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0x53, id2 0xe8, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xb6, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xb6, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xb6, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xb6, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x53, id2 0xe8, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xb6, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0x53, id2 0xe8, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xb6, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for EON unknown EON SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Probing for Generic unknown SPI chip (REMS), 0 KB: Invalid OPCODE 0x90 === This flash part has status UNTESTED for operations: ERASE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified.

1 0

[PATCH] Fix out-of-bounds ICH FREG permission printing
by Carl-Daniel Hailfinger 13 Jul '10

13 Jul '10

Fix out-of-bounds ICH FREG permission printing. A bit was masked, but not shifted, and that led to worst-case accesses of index 24 in an array with 4 members. I've improved readability in the variable declaration block as well. Thanks to Stephen Kou for reporting the bug. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich_freg_nosegfault/chipset_enable.c =================================================================== --- flashrom-ich_freg_nosegfault/chipset_enable.c (Revision 1075) +++ flashrom-ich_freg_nosegfault/chipset_enable.c (Arbeitskopie) @@ -452,10 +452,11 @@ "Flash Descriptor", "BIOS", "Management Engine", "Gigabit Ethernet", "Platform Data" }; - int rwperms = ((ICH_BRWA(frap) & (1 << i)) << 1) | - ((ICH_BRRA(frap) & (1 << i)) << 0); + uint32_t base, limit; + int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | + (((ICH_BRRA(frap) >> i) & 1) << 0); int offset = 0x54 + i * 4; - uint32_t freg = mmio_readl(ich_spibar + offset), base, limit; + uint32_t freg = mmio_readl(ich_spibar + offset); msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", offset, freg, i, region_names[i]); -- http://www.hailfinger.org/

2 2

[commit] r1076 - trunk
by repository service 13 Jul '10

13 Jul '10

Author: hailfinger Date: Tue Jul 13 02:04:52 2010 New Revision: 1076 URL: http://flashrom.org/trac/coreboot/changeset/1076 Log: Fix out-of-bounds ICH FREG permission printing. A bit was masked, but not shifted, and that led to worst-case accesses of index 24 in an array with 4 members. I've improved readability in the variable declaration block as well. Thanks to Stephen Kou for reporting the bug. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stephen Kou <stephen(a)hyarros.com> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Jul 11 23:33:31 2010 (r1075) +++ trunk/chipset_enable.c Tue Jul 13 02:04:52 2010 (r1076) @@ -452,10 +452,11 @@ "Flash Descriptor", "BIOS", "Management Engine", "Gigabit Ethernet", "Platform Data" }; - int rwperms = ((ICH_BRWA(frap) & (1 << i)) << 1) | - ((ICH_BRRA(frap) & (1 << i)) << 0); + uint32_t base, limit; + int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | + (((ICH_BRRA(frap) >> i) & 1) << 0); int offset = 0x54 + i * 4; - uint32_t freg = mmio_readl(ich_spibar + offset), base, limit; + uint32_t freg = mmio_readl(ich_spibar + offset); msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", offset, freg, i, region_names[i]);

1 0

new chip: AMIC A25L80P
by Daniel Lenski 12 Jul '10

12 Jul '10

Hi all, I've tested flashrom with a new chip, the AMIC A25L80P. This is a 1 MB SPI chip that seems to be straightforwardly related to the AMIC A25L40PU, which has half the capacity but is otherwise identical. (Found datasheet at http://www.datasheetarchive.com/pdf/getfile.php?dir=Datasheet-078&file=DSAE…<http://www.datasheetarchive.com/pdf/getfile.php?dir=Datasheet-078&file=DSAE…>). I am attaching a patch, as well as the output of flashrom -VE, -Vr, and -Vw run on this chip with the patch in place. I'm programming it via the AMD SB7x0 interface. Everything works fine... at least, I used it to upgrade my BIOS and I've been able to reboot ;-) I also attempted to test the block-by-block erase/write capabilities, which seemed to work as well... but I'm less familiar with how to use these properly. Thanks for this great software, and I hope this patch is helpful, Dan

5 13

Pm49FL004T_erase failed on i865 !
by Alex Loktionoff 12 Jul '10

12 Jul '10

Good day, I have flashing problem. The Pm49FL004T flash recognized automatically. I can read it no problem. But I can't re-flash it. Please help me... root@AXP:/home/love# flashrom -E -V >dump_erase_Pm49FL004T_on_i865.txt ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0x403 ERASE FAILED! ERASE FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x49 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org

2 3

Asus PTGD-LA (HP Puffer2-UL8E)
by Mattias Mattsson 12 Jul '10

12 Jul '10

Hi, I'm trying flashrom (r1074) on a HP Pavillion t3170.dk. This machine uses a ASUS PTGD-LA mainboard which HP/Compaq calls by "Puffer2-UL8E".[1] Probe, read and verify works fine. But write fails. Logs attached. Since this is an AMI BIOS maybe a board enable is needed? 1. http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00300023 -mattias

2 2

[commit] r1075 - trunk
by repository service 11 Jul '10

11 Jul '10

Author: mkarcher Date: Sun Jul 11 23:33:31 2010 New Revision: 1075 URL: http://flashrom.org/trac/coreboot/changeset/1075 Log: Add support for the AMIC A25L80P. This is a 1 MB SPI chip that seems to be straightforwardly related to the AMIC A25L40PU, which has half the capacity but is otherwise identical. Datasheet is at http://www.amictechnology.com/pdf/A25L80P.pdf flashrom -VE, -Vr, and -Vw has been tested using the AMD SB7x0 interface. Everything works fine... at least, I used it to upgrade my BIOS and I've been able to reboot. Signed-off-by: Daniel Lenski <dlenski(a)gmail.com> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sat Jul 10 21:34:15 2010 (r1074) +++ trunk/flashchips.c Sun Jul 11 23:33:31 2010 (r1075) @@ -1221,6 +1221,37 @@ { .vendor = "AMIC", + .name = "A25L80P", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L80P, + .total_size = 1024, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {4 * 1024, 2}, + {8 * 1024, 1}, + {16 * 1024, 1}, + {32 * 1024, 1}, + {64 * 1024, 15}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", .name = "A29002B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMIC_ID_NOPREFIX, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sat Jul 10 21:34:15 2010 (r1074) +++ trunk/flashchips.h Sun Jul 11 23:33:31 2010 (r1075) @@ -76,6 +76,7 @@ #define AMIC_ID 0x7F37 /* AMIC */ #define AMIC_ID_NOPREFIX 0x37 /* AMIC */ #define AMIC_A25L40P 0x2013 +#define AMIC_A25L80P 0x2014 #define AMIC_A29002B 0x0d #define AMIC_A29002T 0x8C /* Same as A290021T */ #define AMIC_A29040B 0x86

1 0

RFC/RFD: GPIO multiplexing/direction policy
by Michael Karcher 11 Jul '10

11 Jul '10

Hello flashrom developers, currently flashrom programs GPIO pins it needs for a board enable generally for output and chooses the GPIO function if that pin is multiplexed (as long as selecting output and multiplexing is implemented for that type of GPIO). Another policy would be to *require* that the GPIO pin is *already* set to output and GPIO and abort otherwise. I consider the second approach much safer than the first one, but I suspect there are boards where flashrom finds the pins in the wrong state and reprogramming them is really needed. Still I think that disallowing GPIOs that are not already set to output would be a good idea (and have gpio=force as programmer option) to protect against accidental board matches disabling core functionality. The concrete background of this post is the Asus P2B-N board. It has write enable on GPO18 (lower to enable write). Currently intel_piix4_gpo_set rejects this GPO pin, because it is a "dual function pin which is most likely in use already". In fact, it is multiplexed with PCI_STP#, an output signal to stop the PCI bus clock. It would be fatal on a board that really stops the PCI clock on lowering the pin to set this pin to GPO and lower it. Just lowering it without touching the multiplex bit would be safe, because it won't do anything if the PCI_STP# functionality of that pin is in use - but this would be inconsistent with what flashrom is doing now. Any other oppinions on this topic? Regards, Michael Karcher

2 1

[PATCH][RFC] Progress bar
by Carl-Daniel Hailfinger 11 Jul '10

11 Jul '10

I wanted to get some discussion about a progress bar going. I'm not really happy with the current patch, and it will screw up in various places if its design is not improved, but hey... it works. Sort of. The biggest problem is deciding which operations should print a progress bar. Write? Sure. Erase? Sure. But how do you handle a one-sector erase in the middle of some write operation? You can't print two progress bars at the same time. Read? Makes sense as well. But how do you handle the reads used for verification of erase/write? The two-bars problem strikes again. We could add a bar_type parameter to each progressbar call, and make sure nested calls don't cause confusion. That would solve the issues above. Another problem: How often do we call the progress bar update? Once per byte? Per sector? Per arbitrary unit? Will the division and multiplication performed on every progress bar update affect performance, especially on architectures where such operations are sloooooooooow? This patch also starts progress bars at all the wrong places. Still, it should give you an impression of what's needed. Test with flashrom -p dummy -c MX25L1005 -f -r foo.rom -V flashrom -p dummy -c Am29LV081B -f -r foo.rom -V or any read or erase action on real hardware. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-progressbar/flash.h =================================================================== --- flashrom-progressbar/flash.h (Revision 1072) +++ flashrom-progressbar/flash.h (Arbeitskopie) @@ -588,6 +588,10 @@ int check_erased_range(struct flashchip *flash, int start, int len); int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, char *message); int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); +void progressbar_start(struct flashchip *flash); +void progressbar_update(struct flashchip *flash, int bytepos); +void progressbar_done(struct flashchip *flash); +void progressbar_abort(struct flashchip *flash); char *strcat_realloc(char *dest, const char *src); void print_version(void); void print_banner(void); Index: flashrom-progressbar/spi25.c =================================================================== --- flashrom-progressbar/spi25.c (Revision 1072) +++ flashrom-progressbar/spi25.c (Arbeitskopie) @@ -892,6 +892,7 @@ * (start + len - 1) / page_size. Since we want to include that last * page as well, the loop condition uses <=. */ + progressbar_start(flash); for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { /* Byte position of the first byte in the range in this page. */ /* starthere is an offset to the base address of the chip. */ @@ -900,6 +901,7 @@ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { toread = min(chunksize, lenhere - j); + progressbar_update(flash, starthere + j); rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread); if (rc) break; @@ -908,6 +910,10 @@ break; } + if (!rc) + progressbar_done(flash); + else + progressbar_abort(flash); return rc; } Index: flashrom-progressbar/flashrom.c =================================================================== --- flashrom-progressbar/flashrom.c (Revision 1072) +++ flashrom-progressbar/flashrom.c (Arbeitskopie) @@ -544,8 +544,12 @@ int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len) { + progressbar_start(flash); + /* chip_readn does not take a struct flashchip argument, and this means + * we can't print progress. + */ chip_readn(buf, flash->virtual_memory + start, len); - + progressbar_done(flash); return 0; } @@ -1193,7 +1197,7 @@ continue; } found = 1; - msg_cdbg("trying... "); + progressbar_start(flash); for (i = 0; i < NUM_ERASEREGIONS; i++) { /* count==0 for all automatically initialized array * members so the loop below won't be executed for them. @@ -1201,8 +1205,7 @@ for (j = 0; j < eraser.eraseblocks[i].count; j++) { start = done + eraser.eraseblocks[i].size * j; len = eraser.eraseblocks[i].size; - msg_cdbg("0x%06x-0x%06x, ", start, - start + len - 1); + progressbar_update(flash, start); ret = eraser.block_erase(flash, start, len); if (ret) break; @@ -1212,10 +1215,12 @@ done += eraser.eraseblocks[i].count * eraser.eraseblocks[i].size; } - msg_cdbg("\n"); /* If everything is OK, don't try another erase function. */ - if (!ret) + if (!ret) { + progressbar_done(flash); break; + } else + progressbar_abort(flash); } if (!found) { msg_cerr("ERROR: flashrom has no erase function for this flash chip.\n"); @@ -1230,6 +1235,43 @@ return ret; } +static int progressbar_pos = 0; + +void progressbar_start(struct flashchip *flash) +{ + msg_cdbg("|"); + progressbar_pos = 0; +} + +/** + * Print a progress bar with 64 dots. This allows fitting the progress bar in + * an 80 column screen next to some other output. + */ +void progressbar_update(struct flashchip *flash, int bytepos) +{ + int newpos; + /* This will be simpler once total_size is in bytes. + * bytepos + 1 to get the full progress bar on the highest address + * which is flash->total_size * 1024 - 1. + */ + newpos = (bytepos + 1) * 64 / (flash->total_size * 1024); + for (; progressbar_pos < newpos; progressbar_pos++) + msg_cdbg("."); +} + +void progressbar_done(struct flashchip *flash) +{ + progressbar_update(flash, flash->total_size * 1024 - 1); + msg_cdbg("|"); +} + +void progressbar_abort(struct flashchip *flash) +{ + for (; progressbar_pos < 64; progressbar_pos++) + msg_cdbg("!"); + msg_cdbg("|"); +} + void emergency_help_message(void) { msg_gerr("Your flash chip is in an unknown state.\n" -- http://www.hailfinger.org/

2 1

[PATCH] Partial writes for SPI
by Carl-Daniel Hailfinger 11 Jul '10

11 Jul '10

Every SPI programmer driver had its own completely different chip write implementation, and all of them were insufficiently commented. Create spi_write_chunked as a copy of spi_read_chunked and convert all SPI programmers to use it. No functional changes except: - Bus Pirate uses 12 Byte writes instead of 8 Byte writes - SB600 uses 5 Byte writes instead of 1 Byte writes Should work. Not for 0.9.1, but since I had that thing on my disk anyway, I figured I'd post it to the list in case someone wants to experiment with partial writes. Tests appreciated. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-partial_write_spi/spi25.c =================================================================== --- flashrom-partial_write_spi/spi25.c (Revision 982) +++ flashrom-partial_write_spi/spi25.c (Arbeitskopie) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger + * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger * Copyright (C) 2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify @@ -874,7 +874,7 @@ } /* - * Read a complete flash chip. + * Read a part of the flash chip. * Each page is read separately in chunks with a maximum size of chunksize. */ int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) @@ -913,6 +913,52 @@ } /* + * Write a part of the flash chip. + * Each page is written separately in chunks with a maximum size of chunksize. + */ +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) +{ + int rc = 0; + int i, j, starthere, lenhere; + /* FIXME: page_size is the wrong variable. We need max_writechunk_size + * in struct flashchip to do this properly. All chips using + * spi_chip_write_256 have page_size set to max_writechunk_size, so + * we're OK for now. + */ + int page_size = flash->page_size; + int towrite; + + /* Warning: This loop has a very unusual condition and body. + * The loop needs to go through each page with at least one affected + * byte. The lowest page number is (start / page_size) since that + * division rounds down. The highest page number we want is the page + * where the last byte of the range lives. That last byte has the + * address (start + len - 1), thus the highest page number is + * (start + len - 1) / page_size. Since we want to include that last + * page as well, the loop condition uses <=. + */ + for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { + /* Byte position of the first byte in the range in this page. */ + /* starthere is an offset to the base address of the chip. */ + starthere = max(start, i * page_size); + /* Length of bytes in the range in this page. */ + lenhere = min(start + len, (i + 1) * page_size) - starthere; + for (j = 0; j < lenhere; j += chunksize) { + towrite = min(chunksize, lenhere - j); + rc = spi_nbyte_program(starthere + j, buf + starthere - start + j, towrite); + if (rc) + break; + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(10); + } + if (rc) + break; + } + + return rc; +} + +/* * Program chip using byte programming. (SLOW!) * This is for chips which can only handle one byte writes * and for chips where memory mapped programming is impossible Index: flashrom-partial_write_spi/buspirate_spi.c =================================================================== --- flashrom-partial_write_spi/buspirate_spi.c (Revision 982) +++ flashrom-partial_write_spi/buspirate_spi.c (Arbeitskopie) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -319,7 +319,6 @@ int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; spi_disable_blockprotect(); /* Erase first. */ @@ -330,25 +329,5 @@ } msg_pinfo("done.\n"); - /* FIXME: We could do 12 byte writes, but then we'd have to make sure - * not to cross a 256 byte page boundary. This problem only applies to - * writes, reads can cross page boundaries just fine. - */ - for (i = 0; i < total_size; i += 8) { - int l, r; - if (i + 8 <= total_size) - l = 8; - else - l = total_size - i; - - if ((r = spi_nbyte_program(i, &buf[i], l))) { - msg_perr("%s: write fail %d\n", __func__, r); - return 1; - } - - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - /* loop */; - } - - return 0; + return spi_write_chunked(flash, buf, 0, total_size, 12); } Index: flashrom-partial_write_spi/bitbang_spi.c =================================================================== --- flashrom-partial_write_spi/bitbang_spi.c (Revision 982) +++ flashrom-partial_write_spi/bitbang_spi.c (Arbeitskopie) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -142,24 +142,7 @@ int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; msg_pdbg("total_size is %d\n", total_size); - for (i = 0; i < total_size; i += 256) { - int l, r; - if (i + 256 <= total_size) - l = 256; - else - l = total_size - i; - - if ((r = spi_nbyte_program(i, &buf[i], l))) { - msg_perr("%s: write fail %d\n", __func__, r); - return 1; - } - - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - /* loop */; - } - - return 0; + return spi_write_chunked(flash, buf, 0, total_size, 256); } Index: flashrom-partial_write_spi/ft2232_spi.c =================================================================== --- flashrom-partial_write_spi/ft2232_spi.c (Revision 982) +++ flashrom-partial_write_spi/ft2232_spi.c (Arbeitskopie) @@ -2,7 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009 Paul Fox <pgf(a)laptop.org> - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -288,7 +288,6 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; spi_disable_blockprotect(); /* Erase first. */ @@ -299,23 +298,7 @@ } msg_pinfo("done.\n"); msg_pdbg("total_size is %d\n", total_size); - for (i = 0; i < total_size; i += 256) { - int l, r; - if (i + 256 <= total_size) - l = 256; - else - l = total_size - i; - - if ((r = spi_nbyte_program(i, &buf[i], l))) { - msg_perr("%s: write fail %d\n", __func__, r); - return 1; - } - - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - /* loop */; - } - - return 0; + return spi_write_chunked(flash, buf, 0, total_size, 256); } #endif Index: flashrom-partial_write_spi/sb600spi.c =================================================================== --- flashrom-partial_write_spi/sb600spi.c (Revision 982) +++ flashrom-partial_write_spi/sb600spi.c (Arbeitskopie) @@ -4,6 +4,7 @@ * Copyright (C) 2008 Wang Qingpei <Qingpei.Wang(a)amd.com> * Copyright (C) 2008 Joe Bao <Zheng.Bao(a)amd.com> * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -49,7 +50,6 @@ /* FIXME: SB600 can write 5 bytes per transaction. */ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) { - int i; int total_size = flash->total_size * 1024; int result = 0; @@ -63,19 +63,7 @@ msg_pinfo("done.\n"); msg_pinfo("Programming flash"); - for (i = 0; i < total_size; i++, buf++) { - result = spi_nbyte_program(i, buf, 1); - if (result) { - msg_perr("Write error!\n"); - return result; - } - - /* wait program complete. */ - if (i % 0x8000 == 0) - msg_pspew("."); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - ; - } + result = spi_write_chunked(flash, buf, 0, total_size, 5); msg_pinfo(" done.\n"); return result; } Index: flashrom-partial_write_spi/ichspi.c =================================================================== --- flashrom-partial_write_spi/ichspi.c (Revision 982) +++ flashrom-partial_write_spi/ichspi.c (Arbeitskopie) @@ -5,7 +5,7 @@ * Copyright (C) 2008 Claus Gindhart <claus.gindhart(a)kontron.com> * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -160,8 +160,6 @@ static int program_opcodes(OPCODES * op); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); -static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, - int offset, int maxdata); /* for pairing opcodes with their required preop */ struct preop_opcode_pair { @@ -645,28 +643,6 @@ return -1; } -static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, - int offset, int maxdata) -{ - int page_size = flash->page_size; - uint32_t remaining = page_size; - int towrite; - - msg_comm_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", - offset, page_size, bytes); - - for (; remaining > 0; remaining -= towrite) { - towrite = min(remaining, maxdata); - if (spi_nbyte_program(offset + (page_size - remaining), - &bytes[page_size - remaining], towrite)) { - printf_debug("Error writing"); - return 1; - } - } - - return 0; -} - int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; @@ -679,12 +655,14 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) { - int i, j, rc = 0; + int i, ret = 0; int total_size = flash->total_size * 1024; - int page_size = flash->page_size; int erase_size = 64 * 1024; int maxdata = 64; + if (spi_controller == SPI_CONTROLLER_VIA) + maxdata = 16; + spi_disable_blockprotect(); /* Erase first */ printf("Erasing flash before programming... "); @@ -696,19 +674,15 @@ printf("Programming page: \n"); for (i = 0; i < total_size / erase_size; i++) { - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - for (j = 0; j < erase_size / page_size; j++) { - ich_spi_write_page(flash, - (void *)(buf + (i * erase_size) + (j * page_size)), - (i * erase_size) + (j * page_size), maxdata); - } + ret = spi_write_chunked(flash, buf + (i * erase_size), + i * erase_size, erase_size, maxdata); + if (ret) + break; } printf("\n"); - return rc; + return ret; } int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, Index: flashrom-partial_write_spi/chipdrivers.h =================================================================== --- flashrom-partial_write_spi/chipdrivers.h (Revision 982) +++ flashrom-partial_write_spi/chipdrivers.h (Arbeitskopie) @@ -51,6 +51,7 @@ int spi_nbyte_program(int addr, uint8_t *bytes, int len); int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); /* 82802ab.c */ -- http://www.hailfinger.org/

3 8

[commit] r1074 - trunk
by repository service 10 Jul '10

10 Jul '10

Author: mkarcher Date: Sat Jul 10 21:34:15 2010 New Revision: 1074 URL: http://flashrom.org/trac/coreboot/changeset/1074 Log: Fix read function for EMST F25L008A SPI chips never should use read_memmapped. The SPI master code might decide that read_memmapped is fine for this chip, though, in a lower layer. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sat Jul 10 18:56:32 2010 (r1073) +++ trunk/flashchips.c Sat Jul 10 21:34:15 2010 (r1074) @@ -1393,7 +1393,7 @@ } }, .write = spi_aai_write, - .read = read_memmapped, + .read = spi_chip_read, }, {

1 0

Support for HP Compaq 6820s laptop
by Jean Dupont 10 Jul '10

10 Jul '10

Hello, I just tried flashrom with my laptop: model: HP Compaq 6820s s/n: CNU74829VJ p/n: GR713ET#ABF service tag: C6820sST7250F7x16GIBN20Ca FR no idea how to find the revision number, but here some numbers lying around: HPK-HSTNN-I40C(B) here a link to some bios versions: http://h20000.www2.hp.com/bizsupport/TechSupport/SoftwareDescription.jsp?la… my current experience when flashing a new rom file is that flashrom tries to erase before writing, cannot erase the block beginning at F0000 because it's write-protected and exits. carldani on irc just helped me to recover. I suppose that there is some region, say F0000-FFEFF which is write-protected. it would be great if we could specify to flashrom to skip it and flash 00000-EFFFF and FFF00-FFFFF only. There is only zeros when you read the write-protected region anyway. Thank you very much. This is a great project :) Julius. P.S.: here some debug info: output of flashrom -V: root@ubuntu:~/Dokumente/vrac# flashrom -V flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Compaq 6820s" DMI string system-version: "F.0B" DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "30D7" DMI string baseboard-version: "KBC Version 83.13" DMI string chassis-type: "Notebook" Laptop detected via DMI ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. ======================================================================== Found chipset "Intel ICH8M", enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 Root Complex Register Block address = 0xfed90000 GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed90000 + 0x3020 0x04: 0xe008 (HSFS) FLOCKDN 1, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 0x50: 0x0000ffff (FRAP) BMWAG 0, BMRAG 0, BRWA 255, BRRA 255 0x54: 0x00000000 (FREG0) 0x58: 0x00ff0003 (FREG1) 0x5C: 0x00000fff (FREG2) 0x60: 0x00020001 (FREG3) 0x64: 0x00000000 (FREG4) 0x74: 0x80ff00f0 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x00420004 (SSFS, SSFC) 0x94: 0x5006 (PREOP) 0x96: 0x7f48 (OPTYPE) 0x98: 0x0405039f (OPMENU) 0x9C: 0x0102d820 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00000000 (FDOC) WARNING: SPI Configuration Lockdown activated. Generating OPCODES... done SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH,SPI. Calibrating delay loop... 609M loops per second, 100 myus = 196 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT29C512, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: RDID returned 0xc2 0x20 0x14 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 KB: RDID returned 0xc2 0x20 0x14 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A29002B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25D16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN29F010, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x02, id2 0x37 Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x02, id2 0x37, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Spansion S25FL008A, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF016B, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 KB: Invalid OPCODE 0x90 Probing for SST SST25VF040B, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040B.REMS, 512 KB: Invalid OPCODE 0x90 Probing for SST SST25VF080B, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST28SF040A, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x02, id2 0x37, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x02, id2 0x37 Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 KB: RDID returned 0xc2 0x20 0x14. Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 KB: RDID returned 0xc2 0x20 0x14. Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 KB: RDID returned 0xc2 0x20 0x14. Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M29F002B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x02, id2 0x37 Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x02, id2 0x37 Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x02, id2 0x37 Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x64, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W29C011, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x02, id2 0x37, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x02, id2 0x37, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for Sanyo unknown Sanyo SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for Generic unknown SPI chip (RDID), 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Not unmapping zero size at (nil) Probing for Generic unknown SPI chip (REMS), 0 KB: Not mapping flash chip, zero size at 0x00000000. Invalid OPCODE 0x90 Not unmapping zero size at (nil) === This flash part has status UNTESTED for operations: ERASE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. output of lspci -nnvvvxxx: root@ubuntu:~/Dokumente/vrac# lspci -nnvvvxxx 00:00.0 Host bridge [0600]: Intel Corporation Mobile PM965/GM965/GL960 Memory Controller Hub [8086:2a00] (rev 0c) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information <?> Kernel modules: intel-agp 00: 86 80 00 2a 06 00 90 20 0c 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 90 d9 fe 00 00 00 00 01 40 d9 fe 00 00 00 00 50: 00 00 02 00 13 03 00 00 00 00 00 00 00 00 00 00 60: 05 00 00 f8 00 00 00 00 01 80 d9 fe 00 00 00 00 70: 00 00 00 00 00 00 00 00 01 10 00 00 00 00 00 00 80: 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 11 11 00 00 13 11 00 ff 03 00 00 00 1a b8 00 a0: 10 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 03 01 00 00 e0: 09 00 0a 91 a2 7c 00 30 04 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 90 0f 04 00 10 00 00 00 00:01.0 PCI bridge [0604]: Intel Corporation Mobile PM965/GM965/GL960 PCI Express Root Port [8086:2a01] (rev 0c) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00004000-00004fff Memory behind bridge: dc400000-dc4fffff Prefetchable memory behind bridge: 00000000d0000000-00000000d7ffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [88] Subsystem: Hewlett-Packard Company Device [103c:30d7] Capabilities: [80] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [90] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Address: fee0300c Data: 4159 Capabilities: [a0] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Capabilities: [140] Root Complex Link <?> Kernel driver in use: pcieport Kernel modules: shpchp 00: 86 80 01 2a 07 04 10 00 0c 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 40 40 00 20 20: 40 dc 40 dc 01 d0 f1 d7 00 00 00 00 00 00 00 00 30: 00 00 00 00 88 00 00 00 00 00 00 00 0a 01 1c 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 90 03 c8 00 00 00 00 0d 80 00 00 3c 10 d7 30 90: 05 a0 01 00 0c 30 e0 fe 59 41 00 00 00 00 00 00 a0: 10 00 41 00 00 80 00 00 00 00 01 00 01 2d 01 02 b0: 43 00 01 11 c0 25 0c 00 c0 01 48 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 20 00 01 84 0c 00 00 a0 90 0f 04 00 31 00 00 00 00:19.0 Ethernet controller [0200]: Intel Corporation 82562GT 10/100 Network Connection [8086:10c4] (rev 03) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 28 Region 0: Memory at dc500000 (32-bit, non-prefetchable) [size=128K] Region 1: Memory at dc520000 (32-bit, non-prefetchable) [size=4K] Region 2: I/O ports at 5000 [size=32] Capabilities: [c8] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [d0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable+ Address: 00000000fee0200c Data: 41c1 Kernel driver in use: e1000e Kernel modules: e1000e 00: 86 80 c4 10 07 04 10 00 03 00 00 02 00 00 00 00 10: 00 00 50 dc 00 00 52 dc 01 50 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 c8 00 00 00 00 00 00 00 05 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 01 d0 22 c8 00 20 00 04 d0: 05 00 81 00 0c 20 e0 fe 00 00 00 00 c1 41 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1a.0 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 [8086:2834] (rev 03) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at 5020 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 34 28 05 00 80 02 03 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 21 50 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1a.1 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 [8086:2835] (rev 03) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 17 Region 4: I/O ports at 5040 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 35 28 05 00 80 02 03 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 41 50 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1a.7 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 [8086:283a] (rev 03) (prog-if 20) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 0: Memory at dc521000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Kernel driver in use: ehci_hcd 00: 86 80 3a 28 06 00 90 02 03 20 03 0c 00 00 00 00 10: 00 10 52 dc 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 c2 c9 00 00 00 00 0a 00 a0 20 00 00 00 00 60: 20 20 e1 01 00 00 00 00 01 00 00 00 00 00 08 c0 70: 00 00 c7 03 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 88 85 40 00 86 0f 05 00 0a 17 02 20 00:1b.0 Audio device [0403]: Intel Corporation 82801H (ICH8 Family) HD Audio Controller [8086:284b] (rev 03) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at dc524000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [60] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v1) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 <64ns, L1 <1us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100] Virtual Channel <?> Capabilities: [130] Root Complex Link <?> Kernel driver in use: HDA Intel Kernel modules: snd-hda-intel 00: 86 80 4b 28 06 00 10 00 03 00 03 04 10 00 00 00 10: 04 40 52 dc 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 00 00 40: 01 00 00 03 00 00 00 00 00 00 00 00 00 80 00 00 50: 01 60 42 c8 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 70 80 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 91 00 c0 0f 00 00 00 08 10 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1c.0 PCI bridge [0604]: Intel Corporation 82801H (ICH8 Family) PCI Express Port 1 [8086:283f] (rev 03) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=08, subordinate=08, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Address: fee0300c Data: 4161 Capabilities: [90] Subsystem: Hewlett-Packard Company Device [103c:30d7] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Virtual Channel <?> Capabilities: [180] Root Complex Link <?> Kernel driver in use: pcieport Kernel modules: shpchp 00: 86 80 3f 28 07 04 10 00 03 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 08 08 00 f0 00 00 20 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 04 00 40: 10 80 41 00 c0 8f 00 00 00 00 10 00 11 4c 11 01 50: 00 00 01 10 60 05 10 00 00 00 40 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 0c 30 e0 fe 61 41 00 00 00 00 00 00 90: 0d a0 00 00 3c 10 d7 30 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 e0: 00 0f c7 00 06 07 08 00 31 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1c.1 PCI bridge [0604]: Intel Corporation 82801H (ICH8 Family) PCI Express Port 2 [8086:2841] (rev 03) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=10, subordinate=10, sec-latency=0 I/O behind bridge: 00006000-00006fff Memory behind bridge: dc000000-dc0fffff Prefetchable memory behind bridge: 0000000080000000-00000000801fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+ Slot # 2, PowerLimit 0.160000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Address: fee0300c Data: 4169 Capabilities: [90] Subsystem: Hewlett-Packard Company Device [103c:30d7] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Virtual Channel <?> Capabilities: [180] Root Complex Link <?> Kernel driver in use: pcieport Kernel modules: shpchp 00: 86 80 41 28 07 04 10 00 03 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 10 10 00 60 60 00 00 20: 00 dc 00 dc 01 80 11 80 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 02 04 00 40: 10 80 41 01 c0 8f 00 00 00 00 10 00 11 2c 11 02 50: 40 00 11 30 60 08 11 00 00 00 40 01 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 0c 30 e0 fe 69 41 00 00 00 00 00 00 90: 0d a0 00 00 3c 10 d7 30 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 88 00 00 00 00 e0: 00 0f c7 84 06 07 08 00 31 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1c.4 PCI bridge [0604]: Intel Corporation 82801H (ICH8 Family) PCI Express Port 5 [8086:2847] (rev 03) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=28, subordinate=28, sec-latency=0 I/O behind bridge: 00002000-00003fff Memory behind bridge: d8000000-dbffffff Prefetchable memory behind bridge: 0000000080200000-00000000803fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+ Slot # 5, PowerLimit 0.160000; Interlock- NoCompl- SltCtl: Enable: AttnBtn+ PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Address: fee0300c Data: 4171 Capabilities: [90] Subsystem: Hewlett-Packard Company Device [103c:30d7] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Virtual Channel <?> Capabilities: [180] Root Complex Link <?> Kernel driver in use: pcieport Kernel modules: shpchp 00: 86 80 47 28 07 04 10 00 03 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 28 28 00 20 30 00 00 20: 00 d8 f0 db 21 80 31 80 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 04 00 40: 10 80 41 01 c0 8f 00 00 00 00 10 00 11 4c 11 05 50: 00 00 01 10 60 08 29 00 09 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 0c 30 e0 fe 71 41 00 00 00 00 00 00 90: 0d a0 00 00 3c 10 d7 30 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 c8 00 00 00 00 e0: 00 0f c7 00 06 07 08 00 31 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1d.0 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 [8086:2830] (rev 03) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 20 Region 4: I/O ports at 5060 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 30 28 05 00 80 02 03 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 61 50 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1d.1 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 [8086:2831] (rev 03) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 21 Region 4: I/O ports at 5080 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 31 28 05 00 80 02 03 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 50 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1d.2 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 [8086:2832] (rev 03) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at 50a0 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 32 28 05 00 80 02 03 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: a1 50 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1d.7 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 [8086:2836] (rev 03) (prog-if 20) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 20 Region 0: Memory at dc528000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Kernel driver in use: ehci_hcd 00: 86 80 36 28 06 00 90 02 03 20 03 0c 00 00 00 00 10: 00 80 52 dc 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 c2 c9 00 00 00 00 0a 00 a0 20 00 00 00 00 60: 20 20 9f 01 00 00 00 00 01 00 00 00 00 00 08 c0 70: 00 00 df 3f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 88 85 40 00 86 0f 05 00 0a 17 02 20 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 Mobile PCI Bridge [8086:2448] (rev f3) (prog-if 01) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=02, subordinate=02, sec-latency=32 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Subsystem: Hewlett-Packard Company Device [103c:30d7] 00: 86 80 48 24 07 01 10 00 f3 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 20 f0 00 80 22 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 06 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 50: 0d 00 00 00 3c 10 d7 30 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1f.0 ISA bridge [0601]: Intel Corporation 82801HEM (ICH8M) LPC Interface Controller [8086:2815] (rev 03) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information <?> Kernel modules: iTCO_wdt 00: 86 80 15 28 07 00 10 02 03 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 10 00 00 80 00 00 00 01 11 00 00 10 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 80 80 80 80 92 00 00 00 80 80 80 80 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 00 3c 01 05 7c 00 00 00 00 00 00 00 00 00 90: e9 02 04 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 24 0e 00 00 e1 00 03 00 01 1c 0b 00 00 03 00 00 b0: 00 00 f0 00 00 00 00 00 04 a0 62 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 33 22 11 00 67 45 00 00 00 c0 00 00 01 00 00 00 e0: 09 00 0c 10 20 02 4c c3 60 00 00 00 00 00 00 00 f0: 01 00 d9 fe 0c 69 22 00 86 0f 05 00 00 00 00 00 00:1f.1 IDE interface [0101]: Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) IDE Controller [8086:2850] (rev 03) (prog-if 8a [Master SecP PriP]) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: I/O ports at 01f0 [size=8] Region 1: I/O ports at 03f4 [size=1] Region 2: I/O ports at 0170 [size=8] Region 3: I/O ports at 0374 [size=1] Region 4: I/O ports at 50c0 [size=16] Kernel driver in use: ata_piix 00: 86 80 50 28 05 00 80 02 03 8a 01 01 00 00 00 00 10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 20: c1 50 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 03 e3 00 40 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 00:1f.2 SATA controller [0106]: Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) SATA AHCI Controller [8086:2829] (rev 03) (prog-if 01) Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 30 Region 0: I/O ports at 13f0 [size=8] Region 1: I/O ports at 15f4 [size=4] Region 2: I/O ports at 1370 [size=8] Region 3: I/O ports at 1574 [size=4] Region 4: I/O ports at 5100 [size=32] Region 5: Memory at dc529000 (32-bit, non-prefetchable) [size=2K] Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/2 Enable+ Address: fee0100c Data: 41a9 Capabilities: [70] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a8] SATA HBA <?> Kernel driver in use: ahci Kernel modules: ahci 00: 86 80 29 28 07 04 b0 02 03 01 06 01 00 00 00 00 10: f1 13 00 00 f5 15 00 00 71 13 00 00 75 15 00 00 20: 01 51 00 00 00 90 52 dc 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 02 00 00 40: 07 a3 00 80 00 00 00 00 01 00 01 00 00 00 00 00 50: 00 00 00 00 11 10 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 80: 05 70 05 00 0c 10 e0 fe a9 41 00 00 00 00 00 00 90: 40 00 03 01 80 01 00 7e 00 00 00 00 0c 00 00 00 a0: 00 00 00 00 00 00 00 00 12 00 10 00 48 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 05 00 00 00 00 00 01:00.0 VGA compatible controller [0300]: ATI Technologies Inc RV516 [Mobility Radeon X1350] [1002:7196] Subsystem: Hewlett-Packard Company Device [103c:30d7] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 29 Region 0: Memory at d0000000 (32-bit, prefetchable) [size=128M] Region 1: I/O ports at 4000 [size=256] Region 2: Memory at dc400000 (32-bit, non-prefetchable) [size=64K] [virtual] Expansion ROM at dc420000 [disabled] [size=128K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v1) Legacy Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [80] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable+ Address: 00000000fee0200c Data: 41a1 Kernel driver in use: radeon Kernel modules: radeon 00: 02 10 96 71 07 04 10 00 00 00 00 03 10 00 00 00 10: 08 00 00 d0 01 40 00 00 00 00 40 dc 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 d7 30 50: 01 58 02 06 00 00 00 00 10 80 11 00 a0 0f 2c 01 60: 10 08 00 00 01 0d 00 00 43 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 00 81 00 0c 20 e0 fe 00 00 00 00 a1 41 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10:00.0 Network controller [0280]: Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection [8086:4222] (rev 02) Subsystem: Hewlett-Packard Company Device [103c:135c] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 31 Region 0: Memory at dc000000 (32-bit, non-prefetchable) [size=4K] Capabilities: [c8] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [d0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable+ Address: 00000000fee0300c Data: 41b1 Capabilities: [e0] Express (v1) Legacy Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 unlimited ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <128ns, L1 <64us ClockPM+ Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [100] Advanced Error Reporting <?> Capabilities: [140] Device Serial Number 5a-e1-58-ff-ff-bf-1c-00 Kernel driver in use: iwl3945 Kernel modules: iwl3945 00: 86 80 22 42 06 04 10 00 02 00 80 02 10 00 00 00 10: 00 00 00 dc 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 5c 13 30: 00 00 00 00 c8 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 01 d0 22 c8 00 00 00 0d d0: 05 e0 81 00 0c 30 e0 fe 00 00 00 00 b1 41 00 00 e0: 10 00 11 00 c0 0e 00 00 10 08 10 00 11 1c 07 00 f0: 40 01 11 10 00 00 00 00 00 00 00 00 00 00 00 00 output of superiotool -deV: root@ubuntu:~/Dokumente/vrac# superiotool -deV superiotool r3844 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x8400, id=0x0036 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x3600, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x3600, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x3600, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x3600, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0x36, rev=0x00 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff No Super I/O found

3 4

[PATCH] Add IT8705 autodetection
by Carl-Daniel Hailfinger 10 Jul '10

10 Jul '10

I'd love to get in-depth reviews for this because it adds some sort of generic (well, ITE) Super I/O enable stage. Autodetect the ITE IT8705 Super I/O and enable flash writes if it performs LPC->Parallel translation. Remove board enables which triggered the IT8705 write enable manually. Change the IT87 SPI special case to cover IT87 LPC->SPI and LPC->Parallel translation. We need all affected board owners to test this. Probe is sufficient. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-it8705_autodetect/flash.h =================================================================== --- flashrom-it8705_autodetect/flash.h (revision 1033) +++ flashrom-it8705_autodetect/flash.h (working copy) @@ -353,6 +353,7 @@ /* board_enable.c */ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); +int it8705f_write_enable(uint8_t port); uint8_t sio_read(uint16_t port, uint8_t reg); void sio_write(uint16_t port, uint8_t reg, uint8_t data); void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); @@ -685,12 +686,11 @@ int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ -extern uint16_t it8716f_flashport; void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); struct superio probe_superio_ite(void); +int init_superio_ite(void); int it87spi_init(void); -int it87xx_probe_spi_flash(const char *name); int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); Index: flashrom-it8705_autodetect/it87spi.c =================================================================== --- flashrom-it8705_autodetect/it87spi.c (revision 1033) +++ flashrom-it8705_autodetect/it87spi.c (working copy) @@ -96,16 +96,12 @@ return ret; } -static uint16_t find_ite_spi_flash_port(uint16_t port, uint16_t id) +static uint16_t it87spi_probe(uint16_t port) { uint8_t tmp = 0; char *portpos = NULL; uint16_t flashport = 0; - switch (id) { - case 0x8716: - case 0x8718: - case 0x8720: enter_conf_mode_ite(port); /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; @@ -115,7 +111,8 @@ if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) { msg_pdbg("No IT87* serial flash segment enabled.\n"); exit_conf_mode_ite(port); - break; + /* Nothing to do. */ + return 1; } msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis"); @@ -159,25 +156,33 @@ } } exit_conf_mode_ite(port); - break; - /* TODO: Handle more IT87xx if they support flash translation */ - default: - msg_pdbg("SuperI/O ID %04hx is not on the controller list.\n", id); - } - return flashport; + it8716f_flashport = flashport; + if (buses_supported & CHIP_BUSTYPE_SPI) + msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); + spi_controller = SPI_CONTROLLER_IT87XX; + buses_supported |= CHIP_BUSTYPE_SPI; + return 0; } -int it87spi_common_init(void) +int init_superio_ite(void) { if (superio.vendor != SUPERIO_VENDOR_ITE) return 1; - it8716f_flashport = find_ite_spi_flash_port(superio.port, superio.model); - - if (it8716f_flashport) - spi_controller = SPI_CONTROLLER_IT87XX; - - return (!it8716f_flashport); + switch (superio.model) { + case 0x8705: + return it8705f_write_enable(superio.port); + break; + case 0x8716: + case 0x8718: + case 0x8720: + return it87spi_probe(superio.port); + break; + default: + msg_pdbg("SuperI/O ID %04hx is not on the list of flash " + "capable controllers.\n", superio.model); + } + return 1; } @@ -188,7 +193,7 @@ get_io_perms(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); - ret = it87spi_common_init(); + ret = init_superio_ite(); if (!ret) { buses_supported = CHIP_BUSTYPE_SPI; } else { @@ -197,19 +202,6 @@ return ret; } -int it87xx_probe_spi_flash(const char *name) -{ - int ret; - - ret = it87spi_common_init(); - if (!ret) { - if (buses_supported & CHIP_BUSTYPE_SPI) - msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); - buses_supported |= CHIP_BUSTYPE_SPI; - } - return ret; -} - /* * The IT8716F only supports commands with length 1,2,4,5 bytes including * command byte and can not read more than 3 bytes from the device. Index: flashrom-it8705_autodetect/internal.c =================================================================== --- flashrom-it8705_autodetect/internal.c (revision 1033) +++ flashrom-it8705_autodetect/internal.c (working copy) @@ -223,8 +223,10 @@ } #if defined(__i386__) || defined(__x86_64__) - /* Probe for IT87* LPC->SPI translation unconditionally. */ - it87xx_probe_spi_flash(NULL); + /* Probe unconditionally for IT87* LPC->SPI translation and for + * IT87* Parallel write enable. + */ + init_superio_ite(); #endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-it8705_autodetect/board_enable.c =================================================================== --- flashrom-it8705_autodetect/board_enable.c (revision 1033) +++ flashrom-it8705_autodetect/board_enable.c (working copy) @@ -259,33 +259,92 @@ } /** - * + * Suited for all boards with IT8705F. + * The SIS950 Super I/O probably requires the same flash write enable. */ -static int it8705f_write_enable(uint8_t port, const char *name) +int it8705f_write_enable(uint8_t port) { + uint8_t tmp; + int ret = 0; + enter_conf_mode_ite(port); - sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */ + tmp = sio_read(port, 0x24); + /* Check if at least one flash segment is enabled. */ + if (tmp & 0xf0) { + /* The IT8705 will respond to LPC cycles and translate them. */ + buses_supported = CHIP_BUSTYPE_PARALLEL; + /* Flash ROM I/F Writes Enable */ + tmp |= 0x04; + msg_pdbg("Enabling IT8705 flash ROM interface write.\n"); + if (tmp & 0x02) { + /* The data sheet contradicts itself about max size. */ + max_rom_decode.parallel = 1024 * 1024; + msg_pinfo("IT8705 with very unusual settings. Please " + "send the output of \"flashrom -V\" to \n" + "flashrom(a)flashrom.org to help us finish " + "support for your Super I/O. Thanks.\n"); + ret = 1; + } else if (tmp & 0x08) { + max_rom_decode.parallel = 512 * 1024; + } else { + max_rom_decode.parallel = 256 * 1024; + } + /* Safety checks. */ + if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB but not 512 kB */ + (!(tmp & 0x10)) || /* Not even 128 kB. */ + (!(tmp & 0x10))) { /* Not even 256/512 kB. */ + msg_perr("Inconsistent IT8705 decode size!\n"); + ret = 1; + } + if (sio_read(port, 0x25) != 0) { + msg_perr("IT8705 flash data pins disabled!\n"); + ret = 1; + } + if (sio_read(port, 0x26) != 0) { + msg_perr("IT8705 flash address pins 0-7 disabled!\n"); + ret = 1; + } + if (sio_read(port, 0x27) != 0) { + msg_perr("IT8705 flash address pins 8-15 disabled!\n"); + ret = 1; + } + if ((sio_read(port, 0x29) & 0x10) != 0) { + msg_perr("IT8705 flash write enable pin disabled!\n"); + ret = 1; + } + if ((sio_read(port, 0x29) & 0x08) != 0) { + msg_perr("IT8705 flash chip select pin disabled!\n"); + ret = 1; + } + if ((sio_read(port, 0x29) & 0x04) != 0) { + msg_perr("IT8705 flash read strobe pin disabled!\n"); + ret = 1; + } + if ((sio_read(port, 0x29) & 0x03) != 0) { + msg_perr("IT8705 flash address pins 16-17 disabled!\n"); + ret = 1; + } + if ((sio_read(port, 0x29) & 0x08) != 0) { + msg_perr("IT8705 flash pin disabled!\n"); + ret = 1; + } + msg_pdbg("Maximum IT8705 parallel flash decode size is %u\n", + max_rom_decode.parallel); + if (ret) { + msg_pinfo("Not enabling IT8705 flash write.\n"); + } else { + sio_write(port, 0x24, tmp); + } + } else { + msg_pdbg("No IT8705 flash segment enabled.\n"); + /* Not sure if this is an error or not. */ + ret = 0; + } exit_conf_mode_ite(port); - return 0; + return ret; } -/** - * Suited for: - * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. - * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF - * - Elitegroup K7S6A: SiS745 + ITE IT8705F - * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F - * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 - * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F - * - * The SIS950 Super I/O probably requires the same flash write enable. - */ -static int it8705f_write_enable_2e(const char *name) -{ - return it8705f_write_enable(0x2e, name); -} - static int pc87360_gpio_set(uint8_t gpio, int raise) { static const int bankbase[] = {0, 4, 8, 10, 12}; @@ -1436,7 +1495,6 @@ {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, - {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, @@ -1456,14 +1514,11 @@ {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, - {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, - {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e}, - {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e}, + {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3}, - {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, @@ -1487,7 +1542,7 @@ {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, - {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, + {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, NULL}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, -- http://www.hailfinger.org/

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