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[commit] r1266 - trunk
by repository service 06 Mar '11

06 Mar '11

Author: mkarcher Date: Sun Mar 6 13:09:05 2011 New Revision: 1266 URL: http://flashrom.org/trac/flashrom/changeset/1266 Log: Board-enable for GA-K8N51GMF Gigabyte is not really helpful with their PCI IDs for us, the subsystem IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". We should investigate whether autodetection of this board is causing interference with other boards. real version 2: Extend list of PCI IDs for nvidia southbridges. flashrom -V: http://paste.flashrom.org/view.php?id=326 lspic: http://paste.flashrom.org/view.php?id=328 superiotool: http://paste.flashrom.org/view.php?id=329 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Mar 6 13:07:19 2011 (r1265) +++ trunk/board_enable.c Sun Mar 6 13:09:05 2011 (r1266) @@ -869,6 +869,7 @@ case 0x00E0: /* CK8 */ break; case 0x0260: /* MCP51 */ + case 0x0261: /* MCP51 */ case 0x0364: /* MCP55 */ /* find SMBus controller on *this* southbridge */ /* The infamous Tyan S2915-E has two south bridges; they are @@ -1029,7 +1030,8 @@ /* * Suited for: - * - GIGABYTE GA-K8N51GMF-9 + * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 + * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 */ static int nvidia_mcp_gpio3b_raise(void) { @@ -1954,6 +1956,7 @@ {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Mar 6 13:07:19 2011 (r1265) +++ trunk/print.c Sun Mar 6 13:09:05 2011 (r1266) @@ -482,6 +482,7 @@ B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), + B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL),

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[commit] r1265 - trunk
by repository service 06 Mar '11

06 Mar '11

Author: mkarcher Date: Sun Mar 6 13:07:19 2011 New Revision: 1265 URL: http://flashrom.org/trac/flashrom/changeset/1265 Log: Add HP e-Vectra P2706T Reported by: Michal Janke <jankeso(a)gmail.com> flashrom -V: http://paste.flashrom.org/view.php?id=370 lspci: http://paste.flashrom.org/view.php?id=371 superiotool: http://paste.flashrom.org/view.php?id=372 and http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Mar 5 17:31:57 2011 (r1264) +++ trunk/board_enable.c Sun Mar 6 13:07:19 2011 (r1265) @@ -543,7 +543,10 @@ return it8707f_write_enable(0x2e); } -static int pc87360_gpio_set(uint8_t gpio, int raise) +#define PC87360_ID 0xE1 +#define PC87364_ID 0xE4 + +static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise) { static const int bankbase[] = {0, 4, 8, 10, 12}; int gpio_bank = gpio / 8; @@ -552,13 +555,13 @@ uint8_t id, val; if (gpio_bank > 4) { - msg_perr("PC87360: Invalid GPIO %d\n", gpio); + msg_perr("PC8736x: Invalid GPIO %d\n", gpio); return -1; } id = sio_read(0x2E, 0x20); - if (id != 0xE1) { - msg_perr("PC87360: unexpected ID %02x\n", id); + if (id != chipid) { + msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n", id, chipid); return -1; } @@ -1483,9 +1486,22 @@ int ret; ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ if (!ret) - ret = pc87360_gpio_set(0x09, 1); /* #WP ? */ + ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */ + if (!ret) + ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */ + return ret; +} + +/* + * Suited for: + * - HP e-Vectra P2706T: 810E + ICH + PC87364 + */ +static int board_hp_p2706t(void) +{ + int ret; + ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1); if (!ret) - ret = pc87360_gpio_set(0x27, 1); /* #TBL */ + ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1); return ret; } @@ -1940,6 +1956,7 @@ {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, + {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable}, {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Mar 5 17:31:57 2011 (r1264) +++ trunk/print.c Sun Mar 6 13:07:19 2011 (r1265) @@ -493,6 +493,7 @@ B("GIGABYTE", "GA-MA78GPM-DS2H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2859", NULL), B("GIGABYTE", "GA-MA790FX-DQ6", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), B("GIGABYTE", "GA-MA790GP-DS4H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), + B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-33…", NULL), B("HP", "Puffer2-UL8E", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00300023", NULL),

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Re: [flashrom] [PATCH] kill central list of SPI programmers
by Carl-Daniel Hailfinger 06 Mar '11

06 Mar '11

Auf 18.07.2010 17:20, Michael Karcher schrieb: > This version really compiles. Forgot the forward declaration after > moving code initially. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > I like most ideas in there, and have some minor nitpicks. Using a registration function would allow us to handle multiple SPI programmers on one board (e.g. one in the EC and one in the southbridge), but some infrastructure changes elsewhere would be needed. We need that to handle stuff like the Google Cr-48 netbook sanely. One of my post-0.9.4 goals is to register programmer drivers for every bus, not just SPI. The idea is to be able to handle multiple flash chips behind LPC as well, e.g. if they have different base addresses. And stuff like switching between Dual BIOS chips with a GPIO line could be implemented under that scheme as well. > diff --git a/buspirate_spi.c b/buspirate_spi.c > index 55e71c2..36eaa9a 100644 > --- a/buspirate_spi.c > +++ b/buspirate_spi.c > @@ -44,6 +44,8 @@ static int buspirate_serialport_setup(char *dev) > #define sp_flush_incoming(...) 0 > #endif > > +static const struct spi_programmer spi_programmer_buspirate; > + > static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) > { > int i, ret = 0; > @@ -210,7 +212,7 @@ int buspirate_spi_init(void) > } > > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_BUSPIRATE; > + spi_programmer = &spi_programmer_buspirate; > You assign the spi_programmer variable directly. While that is a straightforward replacement of the current code, it would be cool if you could use a registration function instead: register_spi_programmer(&spi_programmer_buspirate); Depending on whether modification of the programmer-specific info is desired, it may also be possible to have that registration function copy the struct so later calls can make changes even if the original parameter is const. > > return 0; > } > @@ -250,7 +252,7 @@ int buspirate_spi_shutdown(void) > return 0; > } > > -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > static unsigned char *buf = NULL; > @@ -304,12 +306,20 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return ret; > } > > -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_read_chunked(flash, buf, start, len, 12); > } > > -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, 12); > } > + > +static const struct spi_programmer spi_programmer_buspirate = { > + .type = SPI_CONTROLLER_BUSPIRATE, > + .command = buspirate_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = buspirate_spi_read, > + .write_256 = buspirate_spi_write_256, > +}; > diff --git a/dediprog.c b/dediprog.c > index 0b92983..c21c801 100644 > --- a/dediprog.c > +++ b/dediprog.c > @@ -25,6 +25,7 @@ > > #define DEFAULT_TIMEOUT 3000 > static usb_dev_handle *dediprog_handle; > +static const struct spi_programmer spi_programmer_dediprog; > > #if 0 > /* Might be useful for other pieces of code as well. */ > @@ -145,14 +146,14 @@ static int dediprog_set_spi_speed(uint16_t speed) > } > #endif > > -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > msg_pspew("%s, start=0x%x, len=0x%x\n", __func__, start, len); > /* Chosen read length is 16 bytes for now. */ > return spi_read_chunked(flash, buf, start, len, 16); > } > > -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int ret; > @@ -318,7 +319,7 @@ int dediprog_init(void) > return 1; > > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_DEDIPROG; > + spi_programmer = &spi_programmer_dediprog; > Registration function. Same for all subsequent occurences. > > /* RE leftover, leave in until the driver is complete. */ > #if 0 > @@ -394,3 +395,11 @@ int dediprog_shutdown(void) > } > return 0; > } > + > +static const struct spi_programmer spi_programmer_dediprog = { > + .type = SPI_CONTROLLER_DEDIPROG, > + .command = dediprog_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = dediprog_spi_read, > + .write_256 = spi_chip_write_1_new, > +}; > diff --git a/dummyflasher.c b/dummyflasher.c > index 241dcee..b1bbcf2 100644 > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -25,6 +25,8 @@ > #include "flash.h" > #include "chipdrivers.h" > > +static const struct spi_programmer spi_programmer_dummy; > + > static void tolower_string(char *str) > { > for (; *str != '\0'; str++) > @@ -59,7 +61,7 @@ int dummy_init(void) > } > if (strstr(bustext, "spi")) { > buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_DUMMY; > + spi_programmer = &spi_programmer_dummy; > msg_pdbg("Enabling support for %s flash.\n", "SPI"); > } > if (buses_supported == CHIP_BUSTYPE_NONE) > @@ -140,7 +142,7 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) > return; > } > > -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -161,7 +163,7 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > /* Maximum read length is unlimited, use 64kB. */ > return spi_read_chunked(flash, buf, start, len, 64 * 1024); > @@ -171,7 +173,15 @@ int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > * never be successful, and the current frontend refuses to write in that case. > * Other frontends may allow writing even for non-detected chips, though. > */ > -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, 256); > } > + > +static const struct spi_programmer spi_programmer_dummy = { > + .type = SPI_CONTROLLER_DUMMY, > + .command = dummy_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = dummy_spi_read, > + .write_256 = dummy_spi_write_256, > +}; > diff --git a/flash.h b/flash.h > index 8ebea29..fb06207 100644 > --- a/flash.h > +++ b/flash.h > @@ -452,10 +452,6 @@ uint8_t dummy_chip_readb(const chipaddr addr); > uint16_t dummy_chip_readw(const chipaddr addr); > uint32_t dummy_chip_readl(const chipaddr addr); > void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); > -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > #endif > > /* nic3com.c */ > @@ -527,9 +523,6 @@ extern const struct pcidev_status ata_hpt[]; > #define FTDI_FT2232H 0x6010 > #define FTDI_FT4232H 0x6011 > int ft2232_spi_init(void); > -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); > -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* bitbang_spi.c */ > int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); > @@ -544,15 +537,10 @@ struct buspirate_spispeeds { > }; > int buspirate_spi_init(void); > int buspirate_spi_shutdown(void); > -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); > -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* dediprog.c */ > int dediprog_init(void); > int dediprog_shutdown(void); > -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); > -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* flashrom.c */ > enum write_granularity { > @@ -627,32 +615,18 @@ int handle_romentries(uint8_t *buffer, struct flashchip *flash); > > /* spi.c */ > enum spi_controller { > - SPI_CONTROLLER_NONE, > -#if CONFIG_INTERNAL == 1 > -#if defined(__i386__) || defined(__x86_64__) > SPI_CONTROLLER_ICH7, > SPI_CONTROLLER_ICH9, > SPI_CONTROLLER_IT87XX, > SPI_CONTROLLER_SB600, > SPI_CONTROLLER_VIA, > SPI_CONTROLLER_WBSIO, > -#endif > -#endif > -#if CONFIG_FT2232_SPI == 1 > SPI_CONTROLLER_FT2232, > -#endif > -#if CONFIG_DUMMY == 1 > SPI_CONTROLLER_DUMMY, > -#endif > -#if CONFIG_BUSPIRATE_SPI == 1 > SPI_CONTROLLER_BUSPIRATE, > -#endif > -#if CONFIG_DEDIPROG == 1 > SPI_CONTROLLER_DEDIPROG, > -#endif > - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ > Could you leave the #ifdefs in place for now? > }; > -extern const int spi_programmer_count; > + > struct spi_command { > unsigned int writecnt; > unsigned int readcnt; > @@ -660,6 +634,7 @@ struct spi_command { > unsigned char *readarr; > }; > struct spi_programmer { > + enum spi_controller type; > int (*command)(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int (*multicommand)(struct spi_command *cmds); > @@ -669,8 +644,8 @@ struct spi_programmer { > int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); > }; > > -extern enum spi_controller spi_controller; > -extern const struct spi_programmer spi_programmer[]; > +const struct spi_programmer *spi_programmer; > + > int spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int spi_send_multicommand(struct spi_command *cmds); > @@ -684,11 +659,6 @@ extern uint32_t ichspi_bbar; > void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > int ich_generation); > int via_init_spi(struct pci_dev * dev); > -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); > -int ich_spi_send_multicommand(struct spi_command *cmds); > > /* it87spi.c */ > void enter_conf_mode_ite(uint16_t port); > @@ -696,23 +666,12 @@ void exit_conf_mode_ite(uint16_t port); > struct superio probe_superio_ite(void); > int init_superio_ite(void); > int it87spi_init(void); > -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* sb600spi.c */ > void sb600_probe_spi(struct pci_dev * dev); > -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* wbsio_spi.c */ > int wbsio_check_for_spi(void); > -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* serprog.c */ > int serprog_init(void); > diff --git a/flashrom.c b/flashrom.c > index fe173a7..dc262d5 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1354,10 +1354,6 @@ int selfcheck(void) > msg_gerr("Programmer table miscompilation!\n"); > ret = 1; > } > - if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { > - msg_gerr("SPI programmer table miscompilation!\n"); > - ret = 1; > - } > for (flash = flashchips; flash && flash->name; flash++) > if (selfcheck_eraseblocks(flash)) > ret = 1; > diff --git a/ft2232_spi.c b/ft2232_spi.c > index c8711e9..b45ba42 100644 > --- a/ft2232_spi.c > +++ b/ft2232_spi.c > @@ -45,6 +45,7 @@ > #define BITMODE_BITBANG_NORMAL 1 > #define BITMODE_BITBANG_SPI 2 > > +static const struct spi_programmer spi_programmer_ft2232; > static struct ftdi_context ftdic_context; > > static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) > @@ -192,7 +193,7 @@ int ft2232_spi_init(void) > // msg_pdbg("\nft2232 chosen\n"); > > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_FT2232; > + spi_programmer = &spi_programmer_ft2232; > > return 0; > } > @@ -293,4 +294,12 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int l > return spi_write_chunked(flash, buf, start, len, 256); > } > > +static const struct spi_programmer spi_programmer_ft2232 = { > + .type = SPI_CONTROLLER_FT2232, > + .command = ft2232_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = ft2232_spi_read, > + .write_256 = ft2232_spi_write_256, > +}; > + > #endif > diff --git a/ichspi.c b/ichspi.c > index 246f3ae..ae9a5f4 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -106,6 +106,9 @@ static int ichspi_lock = 0; > uint32_t ichspi_bbar = 0; > > static void *ich_spibar = NULL; > +static const struct spi_programmer spi_programmer_ich7; > +static const struct spi_programmer spi_programmer_ich9; > +static const struct spi_programmer spi_programmer_via; > > typedef struct _OPCODE { > uint8_t opcode; //This commands spi opcode > @@ -234,7 +237,7 @@ static int generate_opcodes(OPCODES * op) > return -1; > } > > - switch (spi_controller) { > + switch (spi_programmer->type) { > We need to decide whether we want to access spi_programmer directly. It works in your patch, but if we go the route towards multiple SPI programmers on one board, we have to be sure to access the correct spi_programmer (maybe array member, maybe something else). If you have any neat ideas, please come forward. Otherwise I'd say your code is a good solution for now, and once we add support for registering multiple programmers, we'll notice this location because compilation will fail. > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_VIA: > preop = REGREAD16(ICH7_REG_PREOP); > @@ -309,7 +312,7 @@ int program_opcodes(OPCODES * op) > } > > msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_VIA: > REGWRITE16(ICH7_REG_PREOP, preop); > @@ -337,7 +340,7 @@ int program_opcodes(OPCODES * op) > */ > void ich_set_bbar(uint32_t minaddr) > { > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > mmio_writel(minaddr, ich_spibar + 0x50); > ichspi_bbar = mmio_readl(ich_spibar + 0x50); > @@ -448,19 +451,19 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > switch (ich_generation) { > case 7: > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH7; > + spi_programmer = &spi_programmer_ich7; > spibar_offset = 0x3020; > break; > case 8: > buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH9; > + spi_programmer = &spi_programmer_ich9; > spibar_offset = 0x3020; > break; > case 9: > case 10: > default: /* Future version might behave the same */ > buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH9; > + spi_programmer = &spi_programmer_ich9; > spibar_offset = 0x3800; > break; > } > @@ -471,7 +474,7 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > /* Assign Virtual Address */ > ich_spibar = rcrb + spibar_offset; > > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > msg_pdbg("0x00: 0x%04x (SPIS)\n", > mmio_readw(ich_spibar + 0)); > @@ -600,7 +603,7 @@ int via_init_spi(struct pci_dev * dev) > > /* Not sure if it speaks all these bus protocols. */ > buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_VIA; > + spi_programmer = &spi_programmer_via; > ich_init_opcodes(); > > return 0; > @@ -848,7 +851,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > static int run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data) > { > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_VIA: > if (datalength > 16) { > msg_perr("%s: Internal command size error for " > @@ -881,27 +884,27 @@ static int run_opcode(OPCODE op, uint32_t offset, > return -1; > } > > -int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) > +static int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) > { > int maxdata = 64; > > - if (spi_controller == SPI_CONTROLLER_VIA) > + if (spi_programmer->type == SPI_CONTROLLER_VIA) > maxdata = 16; > > return spi_read_chunked(flash, buf, start, len, maxdata); > } > > -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) > +static int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) > { > int maxdata = 64; > > - if (spi_controller == SPI_CONTROLLER_VIA) > + if (spi_programmer->type == SPI_CONTROLLER_VIA) > maxdata = 16; > > return spi_write_chunked(flash, buf, start, len, maxdata); > } > > -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int result; > @@ -966,7 +969,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { > addr = (writearr[1] << 16) | > (writearr[2] << 8) | (writearr[3] << 0); > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_ICH9: > if (addr < ichspi_bbar) { > @@ -1001,7 +1004,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return result; > } > > -int ich_spi_send_multicommand(struct spi_command *cmds) > +static int ich_spi_send_multicommand(struct spi_command *cmds) > { > int ret = 0; > int i; > @@ -1071,4 +1074,28 @@ int ich_spi_send_multicommand(struct spi_command *cmds) > return ret; > } > > +static const struct spi_programmer spi_programmer_ich7 = { > + .type = SPI_CONTROLLER_ICH7, > + .command = ich_spi_send_command, > + .multicommand = ich_spi_send_multicommand, > + .read = ich_spi_read, > + .write_256 = ich_spi_write_256, > +}; > + > +static const struct spi_programmer spi_programmer_ich9 = { > + .type = SPI_CONTROLLER_ICH9, > + .command = ich_spi_send_command, > + .multicommand = ich_spi_send_multicommand, > + .read = ich_spi_read, > + .write_256 = ich_spi_write_256, > +}; > + > +static const struct spi_programmer spi_programmer_via = { > + .type = SPI_CONTROLLER_VIA, > + .command = ich_spi_send_command, > + .multicommand = ich_spi_send_multicommand, > + .read = ich_spi_read, > + .write_256 = ich_spi_write_256, > +}; > + > #endif > diff --git a/it87spi.c b/it87spi.c > index cf3d3b9..dddb5a9 100644 > --- a/it87spi.c > +++ b/it87spi.c > @@ -34,6 +34,8 @@ > #define ITE_SUPERIO_PORT1 0x2e > #define ITE_SUPERIO_PORT2 0x4e > > +static const struct spi_programmer spi_programmer_it87xx; > + > uint16_t it8716f_flashport = 0; > /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ > static int fast_spi = 1; > @@ -175,7 +177,7 @@ static uint16_t it87spi_probe(uint16_t port) > it8716f_flashport = flashport; > if (buses_supported & CHIP_BUSTYPE_SPI) > msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); > - spi_controller = SPI_CONTROLLER_IT87XX; > + spi_programmer = &spi_programmer_it87xx; > buses_supported |= CHIP_BUSTYPE_SPI; > return 0; > } > @@ -227,7 +229,7 @@ int it87spi_init(void) > * commands with the address in inverse wire order. That's why the register > * ordering in case 4 and 5 may seem strange. > */ > -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > uint8_t busy, writeenc; > @@ -320,7 +322,7 @@ static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int s > * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles > * Need to read this big flash using firmware cycles 3 byte at a time. > */ > -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > int total_size = 1024 * flash->total_size; > fast_spi = 0; > @@ -334,7 +336,7 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int > return 0; > } > > -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > /* > * IT8716F only allows maximum of 512 kb SPI chip size for memory > @@ -371,4 +373,12 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, > return 0; > } > > +static const struct spi_programmer spi_programmer_it87xx = { > + .type = SPI_CONTROLLER_IT87XX, > + .command = it8716f_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = it8716f_spi_chip_read, > + .write_256 = it8716f_spi_chip_write_256, > +}; > + > #endif > diff --git a/sb600spi.c b/sb600spi.c > index e42b20b..866e309 100644 > --- a/sb600spi.c > +++ b/sb600spi.c > @@ -41,6 +41,7 @@ > */ > > static uint8_t *sb600_spibar = NULL; > +static const struct spi_programmer spi_programmer_sb600; > > void sb600_probe_spi(struct pci_dev * dev) > { > @@ -114,16 +115,16 @@ void sb600_probe_spi(struct pci_dev * dev) > return; > > buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_SB600; > + spi_programmer = &spi_programmer_sb600; > } > > -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > /* Maximum read length is 8 bytes. */ > return spi_read_chunked(flash, buf, start, len, 8); > } > > -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, 5); > } > @@ -144,7 +145,7 @@ static void execute_command(void) > ; > } > > -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int count; > @@ -227,4 +228,12 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > +static const struct spi_programmer spi_programmer_sb600 = { > + .type = SPI_CONTROLLER_SB600, > + .command = sb600_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = sb600_spi_read, > + .write_256 = sb600_spi_write_256, > +}; > + > #endif > diff --git a/spi.c b/spi.c > index 2b64463..dc4da9f 100644 > --- a/spi.c > +++ b/spi.c > @@ -27,129 +27,34 @@ > #include "chipdrivers.h" > #include "spi.h" > > -enum spi_controller spi_controller = SPI_CONTROLLER_NONE; > - > void spi_prettyprint_status_register(struct flashchip *flash); > > -const struct spi_programmer spi_programmer[] = { > - { /* SPI_CONTROLLER_NONE */ > - .command = NULL, > - .multicommand = NULL, > - .read = NULL, > - .write_256 = NULL, > - }, > - > -#if CONFIG_INTERNAL == 1 > -#if defined(__i386__) || defined(__x86_64__) > - { /* SPI_CONTROLLER_ICH7 */ > - .command = ich_spi_send_command, > - .multicommand = ich_spi_send_multicommand, > - .read = ich_spi_read, > - .write_256 = ich_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_ICH9 */ > - .command = ich_spi_send_command, > - .multicommand = ich_spi_send_multicommand, > - .read = ich_spi_read, > - .write_256 = ich_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_IT87XX */ > - .command = it8716f_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = it8716f_spi_chip_read, > - .write_256 = it8716f_spi_chip_write_256, > - }, > - > - { /* SPI_CONTROLLER_SB600 */ > - .command = sb600_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = sb600_spi_read, > - .write_256 = sb600_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_VIA */ > - .command = ich_spi_send_command, > - .multicommand = ich_spi_send_multicommand, > - .read = ich_spi_read, > - .write_256 = ich_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_WBSIO */ > - .command = wbsio_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = wbsio_spi_read, > - .write_256 = spi_chip_write_1_new, > - }, > -#endif > -#endif > - > -#if CONFIG_FT2232_SPI == 1 > - { /* SPI_CONTROLLER_FT2232 */ > - .command = ft2232_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = ft2232_spi_read, > - .write_256 = ft2232_spi_write_256, > - }, > -#endif > - > -#if CONFIG_DUMMY == 1 > - { /* SPI_CONTROLLER_DUMMY */ > - .command = dummy_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = dummy_spi_read, > - .write_256 = dummy_spi_write_256, > - }, > -#endif > - > -#if CONFIG_BUSPIRATE_SPI == 1 > - { /* SPI_CONTROLLER_BUSPIRATE */ > - .command = buspirate_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = buspirate_spi_read, > - .write_256 = buspirate_spi_write_256, > - }, > -#endif > - > -#if CONFIG_DEDIPROG == 1 > - { /* SPI_CONTROLLER_DEDIPROG */ > - .command = dediprog_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = dediprog_spi_read, > - .write_256 = spi_chip_write_1_new, > - }, > -#endif > - > - {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ > -}; > - > -const int spi_programmer_count = ARRAY_SIZE(spi_programmer); > +const struct spi_programmer *spi_programmer; > If someone forces a SPI access on a programmer which does not support SPI, this will explode AFAICS because it means following an uninitialized pointer to check for NULL in a struct member which does not exist. > > int spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > - if (!spi_programmer[spi_controller].command) { > + if (!spi_programmer->command) { > msg_perr("%s called, but SPI is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].command(writecnt, readcnt, > + return spi_programmer->command(writecnt, readcnt, > writearr, readarr); > } > > int spi_send_multicommand(struct spi_command *cmds) > { > - if (!spi_programmer[spi_controller].multicommand) { > + if (!spi_programmer->multicommand) { > msg_perr("%s called, but SPI is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].multicommand(cmds); > + return spi_programmer->multicommand(cmds); > } > > int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, > @@ -183,14 +88,14 @@ int default_spi_send_multicommand(struct spi_command *cmds) > > int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > - if (!spi_programmer[spi_controller].read) { > + if (!spi_programmer->read) { > msg_perr("%s called, but SPI read is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].read(flash, buf, start, len); > + return spi_programmer->read(flash, buf, start, len); > } > > /* > @@ -202,14 +107,14 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > /* real chunksize is up to 256, logical chunksize is 256 */ > int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len) > { > - if (!spi_programmer[spi_controller].write_256) { > + if (!spi_programmer->write_256) { > msg_perr("%s called, but SPI page write is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].write_256(flash, buf, start, len); > + return spi_programmer->write_256(flash, buf, start, len); > } > > /* Wrapper function until the generic code is converted to partial writes. */ > @@ -239,7 +144,7 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) > */ > uint32_t spi_get_valid_read_addr(void) > { > - switch (spi_controller) { > + switch (spi_programmer->type) { > #if CONFIG_INTERNAL == 1 > #if defined(__i386__) || defined(__x86_64__) > case SPI_CONTROLLER_ICH7: > diff --git a/spi25.c b/spi25.c > index 32bb73c..d9dae35 100644 > --- a/spi25.c > +++ b/spi25.c > @@ -177,7 +177,7 @@ int probe_spi_rdid4(struct flashchip *flash) > /* Some SPI controllers do not support commands with writecnt=1 and > * readcnt=4. > */ > - switch (spi_controller) { > + switch (spi_programmer->type) { > #if CONFIG_INTERNAL == 1 > #if defined(__i386__) || defined(__x86_64__) > case SPI_CONTROLLER_IT87XX: > @@ -1019,7 +1019,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) > .readarr = NULL, > }}; > > - switch (spi_controller) { > + switch (spi_programmer->type) { > #if CONFIG_INTERNAL == 1 > #if defined(__i386__) || defined(__x86_64__) > case SPI_CONTROLLER_IT87XX: > diff --git a/wbsio_spi.c b/wbsio_spi.c > index b8f8b38..6288340 100644 > --- a/wbsio_spi.c > +++ b/wbsio_spi.c > @@ -28,6 +28,7 @@ > #define WBSIO_PORT2 0x4e > > static uint16_t wbsio_spibase = 0; > +static const struct spi_programmer spi_programmer_wbsio; > > static uint16_t wbsio_get_spibase(uint16_t port) > { > @@ -68,7 +69,7 @@ int wbsio_check_for_spi(void) > msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); > > buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_WBSIO; > + spi_programmer = &spi_programmer_wbsio; > msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " > "1024 KB!\n", __func__); > max_rom_decode.spi = 1024 * 1024; > @@ -96,7 +97,7 @@ int wbsio_check_for_spi(void) > * Would one more byte of RAM in the chip (to get all 24 bits) really make > * such a big difference? > */ > -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -180,9 +181,18 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return read_memmapped(flash, buf, start, len); > } > > +static const struct spi_programmer spi_programmer_wbsio = { > + .type = SPI_CONTROLLER_WBSIO, > + .command = wbsio_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = wbsio_spi_read, > + .write_256 = spi_chip_write_1_new, > +}; > + > + > #endif > Looks good otherwise. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

SUCCESS: Gigabyte GA-M61P-S3
by Simon Elsbrock 05 Mar '11

05 Mar '11

http://paste.flashrom.org/view.php?id=384 http://paste.flashrom.org/view.php?id=385 http://paste.flashrom.org/view.php?id=386

1 0

[PATCH] Add mainboards to print.c and mark writing as tested on Winbond W25x80
by Yul Rottmann 05 Mar '11

05 Mar '11

Hello List, I successfully tested flashrom on my MSI MS-7596 (785GM-E51). Here is the patch to add it to the list of supported mainboards. Also I marked writing as tested on the flashchip that belongs to it. Earlier I reported the success of flashing my GIGABYTE GA-MA78G-DS3H. This patch makes clear that it is about the revision 1.0. I also tested flashing an ASRock 890GX Extreme3, which worked. I also added it to print.c. If you have questions, please contact me on my private e-mail adress since I haven't subscribed to the mailinglist. Thanks! Signed-off-by: Yul Rottmann <yulrottmann(a)bitel.net>

2 1

[commit] r1264 - trunk
by repository service 05 Mar '11

05 Mar '11

Author: hailfinger Date: Sat Mar 5 17:31:57 2011 New Revision: 1264 URL: http://flashrom.org/trac/flashrom/changeset/1264 Log: I tested a few mainboards and flash chips. Successfully tested MSI MS-7596 (785GM-E51). Successfully tested ASRock 890GX Extreme3. Successfully tested Winbond W25x80. Mention which GIGABYTE GA-MA78G-DS3H board revision was tested. Signed-off-by: Yul Rottmann <yulrottmann(a)bitel.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/print.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Mar 1 00:58:15 2011 (r1263) +++ trunk/flashchips.c Sat Mar 5 17:31:57 2011 (r1264) @@ -7597,7 +7597,7 @@ .total_size = 1024, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Mar 1 00:58:15 2011 (r1263) +++ trunk/print.c Sat Mar 5 17:31:57 2011 (r1264) @@ -358,6 +358,7 @@ B("Artec Group","DBE62", 1, "http://wiki.thincan.org/DBE62", NULL), B("ASI", "MB-5BLMP", 1, "http://www.hojerteknik.com/winnet.htm", "Used in the IGEL WinNET III thin client."), B("ASRock", "775i65G", 1, "http://www.asrock.com/mb/overview.asp?Model=775i65G", NULL), + B("ASRock", "890GX Extreme3", 1, "http://www.asrock.com/mb/overview.asp?Model=890GX%20Extreme3", NULL), B("ASRock", "939A785GMH/128M", 1, "http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939", NULL), B("ASRock", "A330GC", 1, "http://www.asrock.com/mb/overview.asp?Model=A330GC", NULL), B("ASRock", "A770CrossFire", 1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2%%2b", NULL), @@ -487,7 +488,7 @@ B("GIGABYTE", "GA-MA69VM-S2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2500", NULL), B("GIGABYTE", "GA-MA74GM-S2H (rev. 3.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3152", NULL), B("GIGABYTE", "GA-MA770T-UD3P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3096", NULL), - B("GIGABYTE", "GA-MA78G-DS3H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2800", NULL), /* TODO: Rev 1.x or 2.x? */ + B("GIGABYTE", "GA-MA78G-DS3H (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2800", NULL), B("GIGABYTE", "GA-MA78GM-S2H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2758", NULL), /* TODO: Rev. 1.0, 1.1, or 2.x? */ B("GIGABYTE", "GA-MA78GPM-DS2H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2859", NULL), B("GIGABYTE", "GA-MA790FX-DQ6", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), @@ -541,6 +542,7 @@ B("MSI", "MS-7345 (P35 Neo2-FIR)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1261", NULL), B("MSI", "MS-7368 (K9AG Neo2-Digital)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1241", NULL), B("MSI", "MS-7376 (K9A2 Platinum)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1332", NULL), + B("MSI", "MS-7596 (785GM-E51)", 1, "http://eu.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1866", NULL), B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=2012", NULL), B("NEC", "PowerMate 2000", 1, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), B("Nokia", "IP530", 1, NULL, NULL),

1 0

FAILED: Asus P5N-E SLI
by Segfault 04 Mar '11

04 Mar '11

Hi, I cannot flash the BIOS on my Asus P5N-E SLI. I am confident that I could reboot the computer without issues, as I have dumped before and after the error and the flash is unchanged. I still would like to have support for this motherboard. Here is the output of flashrom -V flashrom v0.9.3-r1262 on Linux 2.6.32-5-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1866M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1006 us, 10000 myus = 10003 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5N-E SLI" DMI string baseboard-version: "1.XX " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8718. Found chipset "NVIDIA MCP51", enabling flash write... chipset PCI ID is 10de:0260, OK. This chipset supports the following protocols: Non-SPI. No IT87* serial flash segment enabled. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A25L512, 64 KB: skipped. Probing for AMIC A25L010, 128 KB: skipped. Probing for AMIC A25L020, 256 KB: skipped. Probing for AMIC A25L040, 512 KB: skipped. Probing for AMIC A25L080, 1024 KB: skipped. Probing for AMIC A25L016, 2048 KB: skipped. Probing for AMIC A25L032, 4096 KB: skipped. Probing for AMIC A25LQ032, 4096 KB: skipped. Probing for AMIC A29002B, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF081A, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25DQ161, 2048 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49F020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Bright BM29F040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for EMST F25L008A, 1024 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for Hyundai HY29F002T, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Hyundai HY29F002B, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Hyundai HY29F040A, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Intel 28F001BN/BX-T, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: probe_82802ab: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: probe_82802ab: id1 0x21, id2 0x2d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: probe_82802ab: id1 0x21, id2 0x2d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L1635E, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29C51000T, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29C51400B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29C51400T, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29LC51000, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29LC51001, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29LC51002, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for Spansion S25FL032A, 4096 KB: skipped. Probing for Spansion S25FL064A, 8192 KB: skipped. Probing for SST SST25VF010.REMS, 128 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M25PX32, 4096 KB: skipped. Probing for ST M25PX64, 8192 KB: skipped. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0xe9, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x21, id2 0xac, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0x92, id2 0xb0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W29C020(C)/W29C022, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W29C040/P, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040C, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Found chip "Winbond W39V040C" (512 KB, LPC) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is active. Hardware remaining chip locking (#WP) is active.. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FB, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FC, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Found chip "Winbond W39V040FC" (512 KB, FWH) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is active. Hardware remaining chip locking (#WP) is active.. Lock status of block at 0x00000000 is Full Access. Lock status of block at 0x00010000 is Full Access. Lock status of block at 0x00020000 is Full Access. Lock status of block at 0x00030000 is Full Access. Lock status of block at 0x00040000 is Full Access. Lock status of block at 0x00050000 is Full Access. Lock status of block at 0x00060000 is Full Access. Lock status of block at 0x00070000 is Full Access. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W49F020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V080FA, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for Eon unknown Eon SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Multiple flash chips were detected: W39V040C W39V040FC Please specify which chip to use with the -c <chipname> option. Restoring PCI config space for 00:0a:0 reg 0x6d Here is the output when I specify either chip name: flashrom v0.9.3-r1262 on Linux 2.6.32-5-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1866M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1005 us, 10000 myus = 10003 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5N-E SLI" DMI string baseboard-version: "1.XX " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8718. Found chipset "NVIDIA MCP51", enabling flash write... chipset PCI ID is 10de:0260, OK. This chipset supports the following protocols: Non-SPI. No IT87* serial flash segment enabled. Probing for Winbond W39V040C, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Found chip "Winbond W39V040C" (512 KB, LPC) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is active. Hardware remaining chip locking (#WP) is active.. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling checks. Reading old flash chip contents... Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x00ffff:E Looking at blockwise erase function 1... trying... 0x000000-0x07ffff:E Looking at blockwise erase function 2... not defined. trying... Done. Verifying flash... Restoring PCI config space for 00:0a:0 reg 0x6d

2 3

FIXMEs
by Carl-Daniel Hailfinger 04 Mar '11

04 Mar '11

Hi, you may have noticed that many of my recent patches added FIXME comments to existing and new code. My goals related to those FIXMEs are threefold: - Give others a chance to grep for FIXME if they don't know what to contribute. - Mark places which either need bugfixes, design changes or which make assumptions which are not guaranteed to be valid in the future. - Provide hints for people refactoring code related to the snippet with FIXME. While I could probably fix most of the places instead of adding FIXMEs, my patches would grow to an unmanageable and unreviewable size. If you spot some problem and think fixing it is not super urgent, feel free to add a FIXME yourself. What do you think? Should I stop adding FIXMEs or are they valuable hints? Regards, Carl-Daniel -- http://www.hailfinger.org/

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UBW32 flashing LPC/FWH in 20us
by Joseph Smith 03 Mar '11

03 Mar '11

Hey the UBW32 (http://www.schmalzhaus.com/UBW32/) has enough I/O (78) pins to be able to flash LPC/FWH chips in programming mode or A/A Mux mode. In this mode you are able to flash in 8bit bytes instead of 4bit nibbles. A few of the datasheets I have seen says in this mode a 256K chip could be flashed in approx 20us. That is friggin fast!!! The only thing that would some what slow it down is USB. But, the UBW32 is detected as a USB HID device and you can do data transfers over serial console. I think this is a major discovery I will be looking into. Thoughts? Comments? FWI the UBW32 dev board from SparFun is $40 and has a built in 3.3v voltage regulator, mount it on a daughter board with a socket you would have a smoking fast programmer for about $50 :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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Re: [flashrom] Hmmm UBW?
by Joseph Smith 01 Mar '11

01 Mar '11

On Mon, 28 Feb 2011 22:12:37 -0600, Марко Краљевић <krasnaya.zvezda(a)gmail.com> wrote: > On Mon, Feb 28, 2011 at 17:08, Joseph Smith <joe(a)settoplinux.org> wrote: > >> http://www.schmalzhaus.com/UBW/ >> >> > This is probably pretty pokey? I was thinking of making something similar > with an AVR. I can't seem to find much information on speed capability of > USB CDC / ACM devices though? > If they only support 115k or whatnot as the top end, it'll be pretty > painful, I'd think. > > curious. I was looking at some of the UBW tutorials and it appears you can set the baudrate to pretty much what ever you want. It is set in the PIC's "bootloader" / firmware and of course your PC (that is what you mean by 115k correct?). The PIC18 runs at 48 MHz. There is also a UBW32 project that runs a PIC32 at 80 MHz but I am not sure if that would be a overkill and it costs more. Any ways there are sparkfun modules for both versions and the PIC18 chip itself only goes for around $6-7 dollars. I just think it is really cool that the UBW was orriginally designed as a parallel replacement for bit-banging over USB-> serial. I think it would be very easy to add flashrom support for this device and there is enough GPIO's on the PIC18 so you could support both LPC/FWH and SPI on the same device. I also like how "open" Microchip is with their products :-) Anyways I don't know alot about PIC devices but I thought I would throw it out there that it seems like 75% of the work has already been done on the UBW to make it a neat little cost effective external USB flashrom programmer. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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[commit] r1263 - trunk
by repository service 01 Mar '11

01 Mar '11

Author: hailfinger Date: Tue Mar 1 00:58:15 2011 New Revision: 1263 URL: http://flashrom.org/trac/flashrom/changeset/1263 Log: Update the ITE IT8500 EC support to match the current state of the flashrom-chromium tree. This code has been deployed and tested to work on the Cr-48. There are a few caveats, though: - The boot BIOS straps register must be modified to select LPC. This can be done with the "select_bbs.sh" script (Install iotools at http://code.google.com/p/iotools/ before using select_bbs). - It is very important to disable power management daemons before running flashrom on this EC. I commented out the brute force method we use in the Chromium OS branch that disables powerd, since IIRC Carl-Daniel has a better approach in the works. - Due to dependencies which may be introduced by the OEM/ODM EC firmware, the code is not guaranteed to work for anything other than the Cr-48. Signed-off-by: David Hendricks <dhendrix(a)google.com> Carl-Daniel comments: Code is not hooked up yet because probing needs to be sorted out. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile trunk/it85spi.c trunk/programmer.h trunk/spi.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Feb 22 18:16:34 2011 (r1262) +++ trunk/Makefile Tue Mar 1 00:58:15 2011 (r1263) @@ -184,7 +184,7 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o # FIXME: The PROGRAMMER_OBJS below should only be included on x86. -PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o NEED_PCI := yes endif Modified: trunk/it85spi.c ============================================================================== --- trunk/it85spi.c Tue Feb 22 18:16:34 2011 (r1262) +++ trunk/it85spi.c Tue Mar 1 00:58:15 2011 (r1263) @@ -27,18 +27,23 @@ #if defined(__i386__) || defined(__x86_64__) #include <string.h> +#include <stdio.h> #include <stdlib.h> #include "flash.h" #include "chipdrivers.h" #include "spi.h" #include "programmer.h" +#define MAX_TIMEOUT 100000 +#define MAX_TRY 5 + /* Constans for I/O ports */ #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e /* Legacy I/O */ -#define LEGACY_KBC_PORT 0x64 +#define LEGACY_KBC_PORT_DATA 0x60 +#define LEGACY_KBC_PORT_CMD 0x64 /* Constants for Logical Device registers */ #define LDNSEL 0x07 @@ -50,6 +55,13 @@ #define SHM_IO_BAD0 0x60 /* big-endian, this is high bits */ #define SHM_IO_BAD1 0x61 +/* 8042 keyboard controller uses an input buffer and an output buffer to + * communicate with host CPU. Both buffers are 1-byte depth. That means the + * IBF is set to 1 when host CPU sends a command to input buffer (standing on + * the EC side). IBF is cleared to 0 once the command is read by EC. */ +#define KB_IBF (1 << 1) /* Input Buffer Full */ +#define KB_OBF (1 << 0) /* Output Buffer Full */ + /* IT8502 supports two access modes: * LPC_MEMORY: through the memory window in 0xFFFFFxxx (follow mode) * LPC_IO: through I/O port (so called indirect memory) @@ -95,11 +107,11 @@ ret.model = probe_id_ite85(ret.port); switch (ret.model >> 8) { case 0x85: - msg_pinfo("Found EC: ITE85xx (Vendor:0x%02x,ID:0x%02x," - "Rev:0x%02x) on sio_port:0x%x.\n", - ret.model >> 8, ret.model & 0xff, - sio_read(ret.port, CHIP_CHIP_VER_REG), - ret.port); + msg_pdbg("Found EC: ITE85xx (Vendor:0x%02x,ID:0x%02x," + "Rev:0x%02x) on sio_port:0x%x.\n", + ret.model >> 8, ret.model & 0xff, + sio_read(ret.port, CHIP_CHIP_VER_REG), + ret.port); return ret; } } @@ -111,20 +123,147 @@ return ret; } -/* IT8502 employs a scratch rom when flash is updating. Call the following two - * functions before/after flash erase/program. */ +/* This function will poll the keyboard status register until either + * an expected value shows up, or + * timeout reaches. + * + * Returns: 0 -- the expected value has shown. + * 1 -- timeout reached. + */ +static int wait_for( + const unsigned int mask, + const unsigned int expected_value, + const int timeout, /* in usec */ + const char* error_message, + const char* function_name, + const int lineno +) { + int time_passed; + + for (time_passed = 0;; ++time_passed) { + if ((INB(LEGACY_KBC_PORT_CMD) & mask) == expected_value) + return 0; + if (time_passed >= timeout) + break; + programmer_delay(1); + } + if (error_message) + msg_perr("%s():%d %s", function_name, lineno, error_message); + return 1; +} + +/* IT8502 employs a scratch ram when flash is being updated. Call the following + * two functions before/after flash erase/program. */ void it85xx_enter_scratch_rom() { + int ret; + int tries; + + msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__); if (it85xx_scratch_rom_reenter > 0) return; - it85xx_scratch_rom_reenter++; - OUTB(0xb4, LEGACY_KBC_PORT); + +#if 0 + /* FIXME: this a workaround for the bug that SMBus signal would + * interfere the EC firmware update. Should be removed if + * we find out the root cause. */ + ret = system("stop powerd >&2"); + if (ret) { + msg_perr("Cannot stop powerd.\n"); + } +#endif + + for (tries = 0; tries < MAX_TRY; ++tries) { + /* Wait until IBF (input buffer) is not full. */ + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + "* timeout at waiting for IBF==0.\n", + __FUNCTION__, __LINE__)) + continue; + + /* Copy EC firmware to SRAM. */ + OUTB(0xb4, LEGACY_KBC_PORT_CMD); + + /* Confirm EC has taken away the command. */ + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + "* timeout at taking command.\n", + __FUNCTION__, __LINE__)) + continue; + + /* Waiting for OBF (output buffer) has data. + * Note sometimes the replied command might be stolen by kernel + * ISR so that it is okay as long as the command is 0xFA. */ + if (wait_for(KB_OBF, KB_OBF, MAX_TIMEOUT, NULL, NULL, 0)) + msg_pdbg("%s():%d * timeout at waiting for OBF.\n", + __FUNCTION__, __LINE__); + if ((ret = INB(LEGACY_KBC_PORT_DATA)) == 0xFA) { + break; + } else { + msg_perr("%s():%d * not run on SRAM ret=%d\n", + __FUNCTION__, __LINE__, ret); + continue; + } + } + + if (tries < MAX_TRY) { + /* EC already runs on SRAM */ + it85xx_scratch_rom_reenter++; + msg_pdbg("%s():%d * SUCCESS.\n", __FUNCTION__, __LINE__); + } else { + msg_perr("%s():%d * Max try reached.\n", + __FUNCTION__, __LINE__); + } } void it85xx_exit_scratch_rom() { +#if 0 + int ret; +#endif + int tries; + + msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__); if (it85xx_scratch_rom_reenter <= 0) return; - it85xx_scratch_rom_reenter = 0; - OUTB(0xfe, LEGACY_KBC_PORT); + + for (tries = 0; tries < MAX_TRY; ++tries) { + /* Wait until IBF (input buffer) is not full. */ + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + "* timeout at waiting for IBF==0.\n", + __FUNCTION__, __LINE__)) + continue; + + /* Exit SRAM. Run on flash. */ + OUTB(0xFE, LEGACY_KBC_PORT_CMD); + + /* Confirm EC has taken away the command. */ + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + "* timeout at taking command.\n", + __FUNCTION__, __LINE__)) { + /* We cannot ensure if EC has exited update mode. + * If EC is in normal mode already, a further 0xFE + * command will reboot system. So, exit loop here. */ + tries = MAX_TRY; + break; + } + + break; + } + + if (tries < MAX_TRY) { + it85xx_scratch_rom_reenter = 0; + msg_pdbg("%s():%d * SUCCESS.\n", __FUNCTION__, __LINE__); + } else { + msg_perr("%s():%d * Max try reached.\n", + __FUNCTION__, __LINE__); + } + +#if 0 + /* FIXME: this a workaround for the bug that SMBus signal would + * interfere the EC firmware update. Should be removed if + * we find out the root cause. */ + ret = system("start powerd >&2"); + if (ret) { + msg_perr("Cannot start powerd again.\n"); + } +#endif } int it85xx_spi_common_init(void) @@ -256,6 +395,14 @@ readarr[i] = *ce_low; #endif } +#ifdef LPC_IO + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); + INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ +#endif +#ifdef LPC_MEMORY + *ce_high = 0; +#endif + return 0; } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Tue Feb 22 18:16:34 2011 (r1262) +++ trunk/programmer.h Tue Mar 1 00:58:15 2011 (r1263) @@ -523,6 +523,7 @@ #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, @@ -583,6 +584,14 @@ int ich_spi_send_multicommand(struct spi_command *cmds); #endif +/* it85spi.c */ +struct superio probe_superio_ite85xx(void); +int it85xx_spi_init(void); +int it85xx_shutdown(void); +int it85xx_probe_spi_flash(const char *name); +int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Tue Feb 22 18:16:34 2011 (r1262) +++ trunk/spi.c Tue Mar 1 00:58:15 2011 (r1263) @@ -55,6 +55,13 @@ .write_256 = ich_spi_write_256, }, + { /* SPI_CONTROLLER_IT85XX */ + .command = it85xx_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, + }, + { /* SPI_CONTROLLER_IT87XX */ .command = it8716f_spi_send_command, .multicommand = default_spi_send_multicommand,

1 0

Hmmm
by Joseph Smith 01 Mar '11

01 Mar '11

http://www.schmalzhaus.com/UBW/ -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

1 0

LPC programmer over serial port
by Joseph Smith 28 Feb '11

28 Feb '11

I found this interesting... LPC programmer over serial port... http://interesting-devices.com/asp/product.asp?recorprod=1&product=318&cat=… -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

1 0

[patch] make EPoX EP-8NPA7I board enable actually work
by Jonathan A. Kollasch 27 Feb '11

27 Feb '11

The OEM BIOS on the EPoX EP-8PA7I clears byte 0x92 in the LPC bridge configuration space. Do the same for all CK804 chips, assuming this to be some sort of chipset-generic write-enable. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ---

3 2

intel 845grg (rebranded gateway)
by Jason Dravet 22 Feb '11

22 Feb '11

I have used flashrom on an intel 845grg motherboard. I had flashed it to an intel bios from a gateway bios, but I had to change it back and flashrom was the only program able to do the job. Here is the data that was requested. I used the -r option on one pc and -w on a second pc. If I could make a feature request: is there any way to change the serial number of the system and motherboard? I read the current bios from one pc and flashed it another unit and the old pc's serial number and serial number of the motherboard are in the new pc. The good news is the mac address didn't change. Thanks, Jason Dravet

1 0

Re: [flashrom] [PATCH] Initial ITE IT8500 EC support
by Carl-Daniel Hailfinger 22 Feb '11

22 Feb '11

Dear Donald, thanks a lot for your patch. I will review it as soon as possible, and I will work with you to ensure a speedy integration of the patch. Right now we are in the process of finalizing the flashrom 0.9.3 release, and such a big new feature needs to be reviewed in depth before being merged, so it won't be part of 0.9.3. I'm very confident this patch will be fully integrated before flashrom 0.9.4. On 09.08.2010 05:06, Donald.Huang(a)ite.com.tw wrote: > The attached patch adds generalized support for IT8500/IT8502 embedded controllers. > The patch was developed by Google for Flashrom r1082, but applies cleanly against r1130. > It was tested for IT8500E on a Chrome OS platform and may require modification > depending on ODM/OEM customization and EC firmware version. > > Signed-off by: Donald Huang (donald.huang(a)ite.com.tw) > Signed-off by: Yung-chieh Lo (yjlou(a)google.com) > Signed-off by: David Hendricks (dhendrix(a)google.com) > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

[commit] r1262 - trunk
by repository service 22 Feb '11

22 Feb '11

Author: hailfinger Date: Tue Feb 22 18:16:34 2011 New Revision: 1262 URL: http://flashrom.org/trac/flashrom/changeset/1262 Log: Add generalized support for ITE IT8500/IT8502 embedded controllers. The patch was developed by Google. It was tested for IT8500E on a Chrome OS platform and may require modification depending on ODM/OEM customization and EC firmware version. This patch is not officially supported by ITE Tech Inc. Signed-off-by: Donald Huang <donald.huang(a)ite.com.tw> Signed-off-by: Yung-chieh Lo <yjlou(a)google.com> Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/it85spi.c Added: trunk/it85spi.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/it85spi.c Tue Feb 22 18:16:34 2011 (r1262) @@ -0,0 +1,262 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger + * Copyright (C) 2008 Ronald Hoogenboom <ronald(a)zonnet.nl> + * Copyright (C) 2008 coresystems GmbH + * Copyright (C) 2010 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Contains the ITE IT85* SPI specific routines + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include <string.h> +#include <stdlib.h> +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" +#include "programmer.h" + +/* Constans for I/O ports */ +#define ITE_SUPERIO_PORT1 0x2e +#define ITE_SUPERIO_PORT2 0x4e + +/* Legacy I/O */ +#define LEGACY_KBC_PORT 0x64 + +/* Constants for Logical Device registers */ +#define LDNSEL 0x07 +#define CHIP_ID_BYTE1_REG 0x20 +#define CHIP_ID_BYTE2_REG 0x21 +#define CHIP_CHIP_VER_REG 0x22 + +/* These are standard Super I/O 16-bit base address registers */ +#define SHM_IO_BAD0 0x60 /* big-endian, this is high bits */ +#define SHM_IO_BAD1 0x61 + +/* IT8502 supports two access modes: + * LPC_MEMORY: through the memory window in 0xFFFFFxxx (follow mode) + * LPC_IO: through I/O port (so called indirect memory) + */ +#undef LPC_MEMORY +#define LPC_IO + +#ifdef LPC_IO +/* macro to fill in indirect-access registers. */ +#define INDIRECT_A0(base, value) OUTB(value, (base) + 0) /* little-endian */ +#define INDIRECT_A1(base, value) OUTB(value, (base) + 1) +#define INDIRECT_A2(base, value) OUTB(value, (base) + 2) +#define INDIRECT_A3(base, value) OUTB(value, (base) + 3) +#define INDIRECT_READ(base) INB((base) + 4) +#define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4) +#endif /* LPC_IO */ + +#ifdef LPC_IO +unsigned int shm_io_base; +#endif +unsigned char *ce_high, *ce_low; +static int it85xx_scratch_rom_reenter = 0; + +uint16_t probe_id_ite85(uint16_t port) +{ + uint16_t id; + + id = sio_read(port, CHIP_ID_BYTE1_REG) << 8 | + sio_read(port, CHIP_ID_BYTE2_REG); + + return id; +} + +struct superio probe_superio_ite85xx(void) +{ + struct superio ret = {}; + uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0}; + uint16_t *i = ite_ports; + + ret.vendor = SUPERIO_VENDOR_ITE; + for (; *i; i++) { + ret.port = *i; + ret.model = probe_id_ite85(ret.port); + switch (ret.model >> 8) { + case 0x85: + msg_pinfo("Found EC: ITE85xx (Vendor:0x%02x,ID:0x%02x," + "Rev:0x%02x) on sio_port:0x%x.\n", + ret.model >> 8, ret.model & 0xff, + sio_read(ret.port, CHIP_CHIP_VER_REG), + ret.port); + return ret; + } + } + + /* No good ID found. */ + ret.vendor = SUPERIO_VENDOR_NONE; + ret.port = 0; + ret.model = 0; + return ret; +} + +/* IT8502 employs a scratch rom when flash is updating. Call the following two + * functions before/after flash erase/program. */ +void it85xx_enter_scratch_rom() +{ + if (it85xx_scratch_rom_reenter > 0) return; + it85xx_scratch_rom_reenter++; + OUTB(0xb4, LEGACY_KBC_PORT); +} + +void it85xx_exit_scratch_rom() +{ + if (it85xx_scratch_rom_reenter <= 0) return; + it85xx_scratch_rom_reenter = 0; + OUTB(0xfe, LEGACY_KBC_PORT); +} + +int it85xx_spi_common_init(void) +{ + chipaddr base; + + msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__, + superio.vendor); + if (superio.vendor != SUPERIO_VENDOR_ITE) + return 1; + +#ifdef LPC_IO + /* Get LPCPNP of SHM. That's big-endian */ + sio_write(superio.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */ + shm_io_base = (sio_read(superio.port, SHM_IO_BAD0) << 8) + + sio_read(superio.port, SHM_IO_BAD1); + msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__, + shm_io_base); + + /* These pointers are not used directly. They will be send to EC's + * register for indirect access. */ + base = 0xFFFFF000; + ce_high = ((unsigned char*)base) + 0xE00; /* 0xFFFFFE00 */ + ce_low = ((unsigned char*)base) + 0xD00; /* 0xFFFFFD00 */ + + /* pre-set indirect-access registers since in most of cases they are + * 0xFFFFxx00. */ + INDIRECT_A0(shm_io_base, base & 0xFF); + INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF); + INDIRECT_A3(shm_io_base, (base >> 24)); +#endif +#ifdef LPC_MEMORY + base = (chipaddr)programmer_map_flash_region("flash base", 0xFFFFF000, + 0x1000); + msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, + (unsigned int)base); + ce_high = (unsigned char*)(base + 0xE00); /* 0xFFFFFE00 */ + ce_low = (unsigned char*)(base + 0xD00); /* 0xFFFFFD00 */ +#endif + + /* Set this as spi controller. */ + spi_controller = SPI_CONTROLLER_IT85XX; + + return 0; +} + +/* Called by programmer_entry .init */ +int it85xx_spi_init(void) +{ + int ret; + + get_io_perms(); + /* Probe for the Super I/O chip and fill global struct superio. */ + probe_superio(); + ret = it85xx_spi_common_init(); + if (!ret) { + buses_supported = CHIP_BUSTYPE_SPI; + } else { + buses_supported = CHIP_BUSTYPE_NONE; + } + return ret; +} + +/* Called by internal_init() */ +int it85xx_probe_spi_flash(const char *name) +{ + int ret; + + if (!(buses_supported & CHIP_BUSTYPE_FWH)) { + msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); + return 1; + } + ret = it85xx_spi_common_init(); + msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); + if (!ret) { + msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__, + buses_supported); + if (buses_supported & CHIP_BUSTYPE_FWH) + msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); + buses_supported |= CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + } + return ret; +} + +int it85xx_shutdown(void) +{ + msg_pdbg("%s():%d\n", __func__, __LINE__); + it85xx_exit_scratch_rom(); + return 0; +} + +/* According to ITE 8502 document, the procedure to follow mode is following: + * 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high) + * 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI + * with data) + * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get + * data from MISO) + */ +int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + int i; + + it85xx_enter_scratch_rom(); + /* exit scratch rom ONLY when programmer shuts down. Otherwise, the + * temporary flash state may halt EC. */ + +#ifdef LPC_IO + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); + INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); +#endif +#ifdef LPC_MEMORY + *ce_high = 0; +#endif + for (i = 0; i < writecnt; ++i) { +#ifdef LPC_IO + INDIRECT_WRITE(shm_io_base, writearr[i]); +#endif +#ifdef LPC_MEMORY + *ce_low = writearr[i]; +#endif + } + for (i = 0; i < readcnt; ++i) { +#ifdef LPC_IO + readarr[i] = INDIRECT_READ(shm_io_base); +#endif +#ifdef LPC_MEMORY + readarr[i] = *ce_low; +#endif + } + return 0; +} + +#endif

1 0

flashrom -V for N61PA-M2S
by Igor Murzich 22 Feb '11

22 Feb '11

info about chipset: DMI string system-manufacturer: "BIOSTAR Group" DMI string system-product-name: "N61PA-M2S" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "BIOSTAR Group" DMI string baseboard-product-name: "N61PA-M2S" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" -- Игорь. ICQ: 97236673 Home / 278240848 Work MailTo:IMurzich_NoSpam At GMail.com Не восхищайся прошлогодним небом, - Не возвращайся - где был рай когда-то, И брось дурить - иди туда, где не был! (С) Высоцкий "Цунами"

1 0

GIGABYTE GA-M565-S3: flashrom -Vr/VE/Vw
by Thomas Schneider 21 Feb '11

21 Feb '11

root@nataschaspc:~/work/flashrom-0.9.3# ./flashrom -Vr ~/bios > flashromVr root@nataschaspc:~/work/flashrom-0.9.3# ./flashrom -VE > flashromVE root@nataschaspc:~/work/flashrom-0.9.3# ./flashrom -Vw ~/bios > flashromVw

1 0

GIGABYTE GA-M565-S3: flashrom -V
by Thomas Schneider 21 Feb '11

21 Feb '11

flashrom v0.9.3-r1205 on Linux 2.6.32-28-generic (i686), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 2 usecs, 668M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 999 us, 10000 myus = 9996 us, 8 myus = 9 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." DMI string system-product-name: "M56S-S3" DMI string system-version: " " DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." DMI string baseboard-product-name: "GA-M56S-S3" DMI string baseboard-version: "x.x" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8716. Found chipset "NVIDIA MCP65", enabling flash write... chipset PCI ID is 10de:0441, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:0446 at 00:01:1 MCP SPI BAR is at 0xfec80000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled Serial flash pin 29 Serial flash port 0x0820 Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L05PU, 64 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L10PT, 128 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L10PU, 128 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L20PT, 256 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L20PU, 256 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L40PT, 512 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L40PU, 512 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L80P, 1024 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L16PT, 2048 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L16PU, 2048 KB: 4 byte RDID not supported on this SPI controller Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L4005" (512 KB, SPI) at physical address 0xfff80000. Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x12 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x12, id2 0x12 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x12 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040(F)B, 512 KB: probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040(F)C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x23, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: 4 byte RDID not supported on this SPI controller Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xc2, id2 0x12 === This flash part has status UNTESTED for operations: ERASE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified.

1 0

Re: [flashrom] MS-7250
by Idwer Vollering 20 Feb '11

20 Feb '11

2011/2/20 Raymond Hoogerdijk <raymond(a)hoogerdijk.org>: > Hello, > > I would like to flash my BIOS with Flashrom. However I noticed that for the chip on my mainboard write has a '?'. Will it not work then? > > I have enclosed the -Vr output for more information about my system. flashrom v0.9.3-r1250 on Linux 2.6.18-194.32.1.el5 (x86_64), built with > libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48), little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 2 usecs, 1196M loops per > second, 10 myus = 12 us, 100 myus = 101 us, 1000 myus = 997 us, 10000 myus = > 10143 us, 8 myus = 10 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "MSI" > DMI string system-product-name: "MS-7250" > DMI string system-version: "2.1" > DMI string baseboard-manufacturer: "MSI" > DMI string baseboard-product-name: "MS-7250" > DMI string baseboard-version: "2.1" > DMI string chassis-type: "Desktop" > Found chipset "NVIDIA MCP55", enabling flash write... chipset PCI ID is > 10de:0360, OK. > This chipset supports the following protocols: Non-SPI. > <snip> > Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e > Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address > 0xfff80000. > Works for me (I've just sent a patch too): flashrom v0.9.3-r1261 on Linux 2.6.37-ARCH (i686), built with libpci 3.1.7, GCC 4.5.2 20110127 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: FWH. Disabling flash write protection for board "ASUS P4P800-VM"... OK. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling checks. Erasing and writing flash chip... Done. Verifying flash... VERIFIED. > <snip> > === > This flash part has status UNTESTED for operations: WRITE > The test status of this chip may have been updated in the latest > development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above > operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, > -Vr, > -Vw, -VE), and mention which mainboard or programmer you tested. > Please mention your board in the subject line. Thanks for your help! > Reading flash... done. > Restoring PCI config space for 00:01:0 reg 0x6d > Restoring PCI config space for 00:01:0 reg 0x90 > Restoring PCI config space for 00:01:0 reg 0x8c > Restoring PCI config space for 00:01:0 reg 0x88 > > > Thanks for your help! > > Kind regards, > > Raymond > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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MS-7250
by Raymond Hoogerdijk 20 Feb '11

20 Feb '11

Hello, I would like to flash my BIOS with Flashrom. However I noticed that for the chip on my mainboard write has a '?'. Will it not work then? I have enclosed the -Vr output for more information about my system. Thanks for your help! Kind regards, Raymond

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oops ! - everything went fine, until...
by Jules Gosnell 20 Feb '11

20 Feb '11

late night session... feeling a little cavalier with some old hardware... ran 'flashrom' - seemed to be happy... made a backup of my existing bios - still happy... wrote my new bios - flashrom reported job done no problems...still happy... I reboot, kicking myself for hours of messing around with various versions of windows trying and failing to update my bios that way... suddenly - box NOT happy :-( three short beeps, pause, three short beeps... I power down, power up - three short beeps repeating - argh !!! M/B is/was? a Tyan Thunder, with a pair of old opterons on it. New bios version, carefully hunted down online was - 2885V208.rom. flashrom worked flawlessly, so no doubt this is pilot error - most likely I have installed the wrong image. Do I chuck the m/b and get another on eBay, or is it salvageable ? I think I saw someone online selling BIOS chips - maybe, if I knew which chip it was, I could unplug mine and plug a new one in - if it's not all soldered down... I'm afraid I don't know much about BIOSes. They are not something I play with every day. I was just trying to persuade my old box to see a new 2TB SATA drive so it could retire into my loft to run mythtvbackend... any help appreciated, regards. Jules

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ABIT AN8-SLI
by Gerad Munsch 19 Feb '11

19 Feb '11

Hello, This is unforgiven512 from #flashrom on irc.freenode.net. My board is an ABIT AN8-SLI. Here are the links with the relevant information for my board: http://paste.flashrom.org/view.php?id=357 < flashrom http://paste.flashrom.org/view.php?id=358 < lspci http://paste.flashrom.org/view.php?id=357 < superiotool If you require anymore information, please let me know. Thanks, Gerad Munsch

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As instructed by flashrom_bot
by Schnittchen 18 Feb '11

18 Feb '11

See pastie links. Hope it helps. Keep up the good work! Schnittchen Your paste can be seen at http://paste.flashrom.org/view.php?id=355 Your upload can be seen at http://paste.flashrom.org/view.php?id=356

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