- flashrom - mail.coreboot.org

[commit] r1837 - trunk
by repository service 05 Aug '14

05 Aug '14

Author: stefanct Date: Wed Aug 6 01:28:47 2014 New Revision: 1837 URL: http://flashrom.org/trac/flashrom/changeset/1837 Log: ichspi: fix missing set_addr on erases and possible crossings of 256 B boundaries. Apparently the erase function did never set any address before issuing the erase commands. How could this ever work? Also, according to PCH documentation crossing 256 byte boundaries is invalid and may cause wraparound due to the flash chip's pages. Check for this on reads as well as writes. Thanks to Vladimir 'φ-coder/phcoder' Serbinenko for noticing these issues and providing the initial patch. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed Aug 6 00:16:01 2014 (r1836) +++ trunk/ichspi.c Wed Aug 6 01:28:47 2014 (r1837) @@ -1272,6 +1272,7 @@ } msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + ich_hwseq_set_addr(addr); /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); @@ -1307,7 +1308,11 @@ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); while (len > 0) { + /* Obey programmer limit... */ block_len = min(len, flash->mst->opaque.max_data_read); + /* as well as flash chip page borders as demanded in the Intel datasheets. */ + block_len = min(block_len, 256 - (addr & 0xFF)); + ich_hwseq_set_addr(addr); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* set read operation */ @@ -1345,7 +1350,10 @@ while (len > 0) { ich_hwseq_set_addr(addr); + /* Obey programmer limit... */ block_len = min(len, flash->mst->opaque.max_data_write); + /* as well as flash chip page borders as demanded in the Intel datasheets. */ + block_len = min(block_len, 256 - (addr & 0xFF)); ich_fill_data(buf, block_len, ICH9_REG_FDATA0); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* clear operation */

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[commit] r1836 - trunk
by repository service 05 Aug '14

05 Aug '14

Author: stefanct Date: Wed Aug 6 00:16:01 2014 New Revision: 1836 URL: http://flashrom.org/trac/flashrom/changeset/1836 Log: linux_spi: properly convert pointers to kernel's u64. For arm64 with 32-bit userspace, pointers such as 0xff96ebf8 were incorrectly getting converted to u64_t 0xffffffffff96ebf8 in the spi_ioc_transfer struct which was causing ioctl()s to be rejected by the kernel. With this patch we first cast to uintptr_t (to avoid warnings on architectures where char * are not 64b wide) and then to uint64_t which is always big enough and does not produce warnings. This patch is taken from ChromiumOS' Change-Id: I5a15b4ca5d9657c3cb1ddccd42eafd91c852dd26 Signed-off-by: David Riley <davidriley(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/linux_spi.c Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Sun Aug 3 16:15:14 2014 (r1835) +++ trunk/linux_spi.c Wed Aug 6 00:16:01 2014 (r1836) @@ -142,11 +142,11 @@ int iocontrol_code; struct spi_ioc_transfer msg[2] = { { - .tx_buf = (uint64_t)(ptrdiff_t)txbuf, + .tx_buf = (uint64_t)(uintptr_t)txbuf, .len = writecnt, }, { - .rx_buf = (uint64_t)(ptrdiff_t)rxbuf, + .rx_buf = (uint64_t)(uintptr_t)rxbuf, .len = readcnt, }, };

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Re: [flashrom] Where is read lock typically implemented?
by Ross Amans 05 Aug '14

05 Aug '14

David - The PCH is enforcing all these write / read protections. The SPI controller lives in the PCH. Ross On Tue, Aug 5, 2014 at 12:23 PM, David Hendricks <dhendrix(a)google.com> wrote: > On Tue, Aug 5, 2014 at 9:55 AM, TR Reardon <thomas_reardon(a)hotmail.com> > wrote: > >> I tried looking for an answer to this but a quick one didn't surface: >> when flash regions are protected, is this implemented by the flash chip >> itself or by the SPI logic (ie ichspi for Intel programmer)? >> > > It can be implemented by either, though in most cases it's the SPI > controller on Intel systems. > > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom > -- Ross Amans Systems Engineer Newisys div of Sanmina 5385 Mark Dabling blvd Colorado Springs, CO 80918 719-884-8714 (work) 719-287-4446 (cell) CONFIDENTIALITY This e-mail message and any attachments thereto, is intended only for use by the addressee(s) named herein and may contain legally privileged and/or confidential information. If you are not the intended recipient of this e-mail message, you are hereby notified that any dissemination, distribution or copying of this e-mail message, and any attachments thereto, is strictly prohibited. If you have received this e-mail message in error, please immediately notify the sender and permanently delete the original and any copies of this email and any prints thereof. ABSENT AN EXPRESS STATEMENT TO THE CONTRARY HEREINABOVE, THIS E-MAIL IS NOT INTENDED AS A SUBSTITUTE FOR A WRITING. Notwithstanding the Uniform Electronic Transactions Act or the applicability of any other law of similar substance and effect, absent an express statement to the contrary hereinabove, this e-mail message its contents, and any attachments hereto are not intended to represent an offer or acceptance to enter into a contract and are not otherwise intended to bind the sender, Sanmina Corporation (or any of its subsidiaries), or any other person or entity.

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Where is read lock typically implemented?
by TR Reardon 05 Aug '14

05 Aug '14

I tried looking for an answer to this but a quick one didn't surface: when flash regions are protected, is this implemented by the flash chip itself or by the SPI logic (ie ichspi for Intel programmer)?

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Re: [flashrom] Avoton patches for flashrom
by TR Reardon 04 Aug '14

04 Aug '14

On Mon, Aug 4, 2014 at 7:49 PM, Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > On Mon, 4 Aug 2014 19:18:04 -0400 > TR Reardon <...> wrote: > >> cool, just tried and was enable to read the descriptor (64K) and then >> the actual BIOS (6MB). I had to edit out the write-only check in >> cli_classic.c, assumed that was relatively safe. > > I have no idea what you are talking about, sorry. > Er... flashrom currently only allows using the layout codepaths in write mode; there is a check for this in cli_classic.c, which I disabled. The log I sent previously described two regions, a "descriptor" region at 0-ffff (64K), and the BIOS itself at 200000-7fffff (6M). When I use --verify, unlike --read, it fails. The final line of output (the only difference) is: Verifying flash... FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x007fffff: 0x7d0bdf Logs attached

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Re: [flashrom] Avoton patches for flashrom
by Stefan Tauner 04 Aug '14

04 Aug '14

On Mon, 4 Aug 2014 19:18:04 -0400 TR Reardon <reardonia(a)gmail.com> wrote: > cool, just tried and was enable to read the descriptor (64K) and then > the actual BIOS (6MB). I had to edit out the write-only check in > cli_classic.c, assumed that was relatively safe. I have no idea what you are talking about, sorry. > The --verify function doesn't work per se, but the files I was able to > extract using --read matched. I'd be interested in details... like logs ;) > The BIOS files mostly seem to match what is posted by ASUS online. > That is, other than configuration areas which I don't understand. I > assume that when a tool like BUPDATER from Asus reads a BIOS update > file, it doesn't simply overwrite the entire BIOS area? I mean, there > are quite a few 64KB configuration areas containing things like the > motherboard name. Or is this relatively safe to overwrite? Only ASUS knows. It might be completely save to overwrite such areas if the firmware initializes them with a default configuration... but I would not try that without a way to recover (e.g. external programmer... which should be easy in your case because the flash is socketed). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Avoton patches for flashrom
by Stefan Tauner 04 Aug '14

04 Aug '14

On Mon, 4 Aug 2014 15:59:40 -0400 TR Reardon <reardonia(a)gmail.com> wrote: > Hi, I'm wondering if your patches from last fall for layout support for > read have been updated? I'd like to try with your Avoton patches but the > merge is non-trivial I have rebased my local branch to current HEAD for you. It compiles but I have not checked anything else -> no promises whatsoever. You can find it on my github: https://github.com/stefanct/flashrom/tree/layout They should not conflict with the Intel patches. Hope that helps. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Log from Intel Atom C2550
by Stefan Tauner 03 Aug '14

03 Aug '14

On Sun, 3 Aug 2014 00:57:55 -0400 TR Reardon <thomas_reardon(a)hotmail.com> wrote: > After last patch, working w log attached (but is flash chip detected > incorrectly?) Hi, that log looks perfectly reasonable including the detected flash chip. Why do you think it's a Macronix? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add support for S25FL128P and S25FL128P......0 chips.
by Stefan Tauner 03 Aug '14

03 Aug '14

Thanks for the test, there are two issues here. One is that I swapped the erase block sizes of the P models. This is clearly shown in your logs. The ...0 model should have 64 kB erase blocks, but does not: > Trying erase function 0... 0x000000-0x03ffff:EFAILED at 0x00010000! Expected=0xff, Found=0xe5 0x03ffff is 262143 in decimal... I have fixed that locally, but this is not the main problem here. The chip erase and the subsequent write should have worked, and your second try with the definition of the ...1 model too (because it contains the right block size). But both failed and I don't understand why yet. The first failed byte is equal in both cases but not all of them are (a different number of bytes fail in the two cases). This indicates that the behavior might be indeterministic. The contents of the "rog.bin" file were equal for both tries, right? What happens if you retry the second test again? /usr/src/flashrompatch/flashrom -p usbblaster_spi -o write2.log -c S25FL128P......1 -w rog.bin If you can not reproduce exactly the same output, i.e. Verifying flash... FAILED at 0x0000005b! Expected=0xd3, Found=0xfb, failed byte count from 0x00000000-0x00ffffff: 0xaf66ea Then we are on the right track. In that case I would ask you how the chip is connected exactly, especially how WP# and HOLD# are driven. PS: You dont need to install flashrom after recompiling. You can execute the built binary in the source directory (make; ./flashrom ...). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add support for a bunch of 29GL parallel flash chips.
by Stefan Tauner 03 Aug '14

03 Aug '14

On Wed, 30 Jul 2014 01:06:20 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > 29GL chips use a new 3-Byte device ID probing function at addresses > 0x01, 0x0E, 0x0F. > > Flash chip families supported by this method include... > - EON EN29GL > - Gigadevice GD29GL (if they really exist) > - ISSI (PMC) IS29GL > - Macronix MX29GL (+MX68GL1G0F) > - Spansion S29GL (+S70GL02G) > - Winbond W29GL > > This patch adds respective flash chip definitions for chips up to 16 MB from > Eon, ISSI, Macronix and Winbond. Bigger chips as well as those from > Gigadevice and Spansion are left out. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Self-acked and committed in r1835. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1835 - trunk
by repository service 03 Aug '14

03 Aug '14

Author: stefanct Date: Sun Aug 3 16:15:14 2014 New Revision: 1835 URL: http://flashrom.org/trac/flashrom/changeset/1835 Log: Add support for a bunch of 29GL parallel flash chips. 29GL chips use a new 3-Byte device ID probing function at addresses 0x01, 0x0E, 0x0F. Flash chip families supported by this method include... - EON EN29GL - Gigadevice GD29GL (if they really exist) - ISSI (PMC) IS29GL - Macronix MX29GL (+MX68GL1G0F) - Spansion S29GL (+S70GL02G) - Winbond W29GL This patch adds respective flash chip definitions for chips up to 16 MB from Eon, ISSI, Macronix and Winbond. Bigger chips as well as those from Gigadevice and Spansion are left out. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipdrivers.h trunk/flashchips.c trunk/flashchips.h trunk/jedec.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sun Aug 3 15:05:45 2014 (r1834) +++ trunk/chipdrivers.h Sun Aug 3 16:15:14 2014 (r1835) @@ -139,6 +139,7 @@ void toggle_ready_jedec(const struct flashctx *flash, chipaddr dst); void data_polling_jedec(const struct flashctx *flash, chipaddr dst, uint8_t data); int probe_jedec(struct flashctx *flash); +int probe_jedec_29gl(struct flashctx *flash); int write_jedec(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int write_jedec_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int erase_sector_jedec(struct flashctx *flash, unsigned int page, unsigned int pagesize); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Aug 3 15:05:45 2014 (r1834) +++ trunk/flashchips.c Sun Aug 3 16:15:14 2014 (r1835) @@ -4892,6 +4892,120 @@ }, { + .vendor = "Eon", + .name = "EN29GL064(A)B", + .bustype = BUS_PARALLEL, + .manufacture_id = EON_ID, + .model_id = EON_EN29GL064B, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 127}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN29GL064(A)T", + .bustype = BUS_PARALLEL, + .manufacture_id = EON_ID, + .model_id = EON_EN29GL064T, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 127}, + {8 * 1024, 8}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN29GL064H/L", + .bustype = BUS_PARALLEL, + .manufacture_id = EON_ID, + .model_id = EON_EN29GL064HL, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN29GL128", + .bustype = BUS_PARALLEL, + .manufacture_id = EON_ID, + .model_id = EON_EN29GL128HL, + .total_size = 16384, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {128 * 1024, 128} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { .vendor = "Fujitsu", .name = "MBM29F004BC", .bustype = BUS_PARALLEL, @@ -6093,6 +6207,120 @@ }, { + .vendor = "ISSI", + .name = "IS29GL064B", + .bustype = BUS_PARALLEL, + .manufacture_id = ISSI_ID, + .model_id = ISSI_PMC_IS29GL064B, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 127}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "ISSI", + .name = "IS29GL064T", + .bustype = BUS_PARALLEL, + .manufacture_id = ISSI_ID, + .model_id = ISSI_PMC_IS29GL064T, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 127}, + {8 * 1024, 8}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "ISSI", + .name = "IS29GL064H/L", + .bustype = BUS_PARALLEL, + .manufacture_id = ISSI_ID, + .model_id = ISSI_PMC_IS29GL064HL, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "ISSI", + .name = "IS29GL128H/L", + .bustype = BUS_PARALLEL, + .manufacture_id = ISSI_ID, + .model_id = ISSI_PMC_IS29GL128HL, + .total_size = 16384, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {128 * 1024, 128} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { .vendor = "Macronix", .name = "MX23L3254", .bustype = BUS_SPI, @@ -7199,6 +7427,207 @@ { .vendor = "Macronix", + .name = "MX29GL320EB", + .bustype = BUS_PARALLEL, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX29GL320EB, + .total_size = 4096, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 63}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX29GL320ET", + .bustype = BUS_PARALLEL, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX29GL320ET, + .total_size = 4096, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 63}, + {8 * 1024, 8}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX29GL320EH/L", + .bustype = BUS_PARALLEL, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX29GL320EHL, + .total_size = 4096, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX29GL640EB", + .bustype = BUS_PARALLEL, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX29GL640EB, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 127}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX29GL640ET", + .bustype = BUS_PARALLEL, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX29GL640ET, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 127}, + {8 * 1024, 8}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX29GL640EH/L", + .bustype = BUS_PARALLEL, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX29GL640EHL, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX29GL128F", + .bustype = BUS_PARALLEL, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX29GL128F, + .total_size = 16384, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {128 * 1024, 128} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", .name = "MX29LV040", .bustype = BUS_PARALLEL, .manufacture_id = MACRONIX_ID, @@ -13054,6 +13483,207 @@ }, { + .vendor = "Winbond", + .name = "W29GL032CB", + .bustype = BUS_PARALLEL, + .manufacture_id = AMD_ID, /* WTF: "Industry Standard compatible Manufacturer ID code of 01h" */ + .model_id = WINBOND_W29GL032CB, + .total_size = 4096, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 63}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", + .name = "W29GL032CT", + .bustype = BUS_PARALLEL, + .manufacture_id = AMD_ID, /* WTF: "Industry Standard compatible Manufacturer ID code of 01h" */ + .model_id = WINBOND_W29GL032CT, + .total_size = 4096, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 63}, + {8 * 1024, 8}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", + .name = "W29GL032CH/L", + .bustype = BUS_PARALLEL, + .manufacture_id = AMD_ID, /* WTF: "Industry Standard compatible Manufacturer ID code of 01h" */ + .model_id = WINBOND_W29GL032CHL, + .total_size = 4096, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", + .name = "W29GL064CB", + .bustype = BUS_PARALLEL, + .manufacture_id = AMD_ID, /* WTF: "Industry Standard compatible Manufacturer ID code of 01h" */ + .model_id = WINBOND_W29GL064CB, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 127}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", + .name = "W29GL064CT", + .bustype = BUS_PARALLEL, + .manufacture_id = AMD_ID, /* WTF: "Industry Standard compatible Manufacturer ID code of 01h" */ + .model_id = WINBOND_W29GL064CT, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 127}, + {8 * 1024, 8}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", + .name = "W29GL064CH/L", + .bustype = BUS_PARALLEL, + .manufacture_id = AMD_ID, /* WTF: "Industry Standard compatible Manufacturer ID code of 01h" */ + .model_id = WINBOND_W29GL064CHL, + .total_size = 8192, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", + .name = "W29GL128C", + .bustype = BUS_PARALLEL, + .manufacture_id = AMD_ID, /* WTF: "Industry Standard compatible Manufacturer ID code of 01h" */ + .model_id = WINBOND_W29GL128CHL, + .total_size = 16384, + .page_size = 128 * 1024, /* actual page size is 16 */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec_29gl, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {128 * 1024, 128} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { .vendor = "Winbond", .name = "W39F010", .bustype = BUS_PARALLEL, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Aug 3 15:05:45 2014 (r1834) +++ trunk/flashchips.h Sun Aug 3 16:15:14 2014 (r1835) @@ -29,9 +29,9 @@ * entry of each section should be the manufacturer ID, followed by the * list of devices from that manufacturer (sorted by device IDs). * - * All LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no + * Most LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no * continuation code. - * SPI parts have 16-bit device IDs if they support RDID. + * SPI parts have at least 16-bit device IDs if they support RDID. */ #define GENERIC_MANUF_ID 0xFFFF /* Check if there is a vendor ID */ @@ -290,6 +290,11 @@ #define EON_EN29LV640B 0xCB #define EON_EN29F002T 0x7F92 /* Same as EN29F002A */ #define EON_EN29F002B 0x7F97 /* Same as EN29F002AN */ +#define EON_EN29GL064HL 0x7E0C01 /* Uniform Sectors, WP protects Top OR Bottom sector */ +#define EON_EN29GL064T 0x7E1001 /* Same ID as EN29GL064AT */ +#define EON_EN29GL064B 0x7E1000 /* Same ID as EN29GL064AB */ +#define EON_EN29GL128HL 0x7F2101 /* Uniform Sectors, WP protects Top OR Bottom sector */ +#define EON_EN29GL256HL 0x7F2201 /* Uniform Sectors, WP protects Top OR Bottom sector */ #define EXCEL_ID 0x7F7F7F7F4A /* Excel Semiconductor Inc. (ESI) resides in bank 5 */ #define EXCEL_ID_NOPREFIX 0x4A /* ESI, missing 0x7F prefix */ @@ -356,6 +361,7 @@ #define GIGADEVICE_GD25LQ32 0x6016 #define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ #define GIGADEVICE_GD25LQ128 0x6018 +#define GIGADEVICE_GD29GL064CAB 0x7E0601 #define HYUNDAI_ID 0xAD /* Hyundai */ #define HYUNDAI_HY29F400T 0x23 /* Same as HY29F400AT */ @@ -424,7 +430,14 @@ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ -#define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ +#define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions, see also PMC. */ +#define ISSI_PMC_IS29GL032B 0xF9 +#define ISSI_PMC_IS29GL032T 0xF6 +#define ISSI_PMC_IS29GL064B 0x7E1000 +#define ISSI_PMC_IS29GL064T 0x7E1001 +#define ISSI_PMC_IS29GL064HL 0x7E0C01 +#define ISSI_PMC_IS29GL128HL 0x7E2101 +#define ISSI_PMC_IS29GL256HL 0x7E2201 #define MACRONIX_ID 0xC2 /* Macronix (MX) */ /* Mask ROMs */ @@ -468,6 +481,16 @@ #define MACRONIX_MX29F400T 0x23 /* Same as MX29F400CT */ #define MACRONIX_MX29F800B 0x58 #define MACRONIX_MX29F800T 0xD6 +#define MACRONIX_MX29GL320EB 0x7E1A00 +#define MACRONIX_MX29GL320ET 0x7E1A01 +#define MACRONIX_MX29GL320EHL 0x7E1D00 +#define MACRONIX_MX29GL640EB 0x7E1000 +#define MACRONIX_MX29GL640ET 0x7E1001 +#define MACRONIX_MX29GL640EHL 0x7E0C01 +#define MACRONIX_MX29GL128F 0x7E2101 /* Same as MX29GL128E */ +#define MACRONIX_MX29GL256F 0x7E2201 /* Same as MX29GL256E */ +#define MACRONIX_MX29GL512F 0x7E2301 +#define MACRONIX_MX68GL1G0F 0x7E2801 #define MACRONIX_MX29LV002CB 0x5A #define MACRONIX_MX29LV002CT 0x59 #define MACRONIX_MX29LV004B 0xB6 /* Same as MX29LV004CB */ @@ -506,8 +529,9 @@ /* * Programmable Micro Corp is listed in JEP106W in bank 2, so it should * have a 0x7F continuation code prefix. - * Apparently this name is owned by "Chingis Technology Corporation" http://www.chingistek.com which is now a - * subsidiary of ISSI. They continue to use the PMC manufacturer ID nevertheless. + * Apparently PMC was renamed to "Chingis Technology Corporation" http://www.chingistek.com which is now a + * subsidiary of ISSI. They continue to use the PMC manufacturer ID (instead of ISSI's) nevertheless, even for + * new chips with IS* model numbers. */ #define PMC_ID 0x7F9D /* PMC */ #define PMC_ID_NOPREFIX 0x9D /* PMC, missing 0x7F prefix */ @@ -557,12 +581,10 @@ #define SHARP_LHF00L02 0xC9 /* Same as LHF00L06/LHF00L07 */ #define SHARP_LHF00L04 0xCF /* Same as LHF00L03/LHF00L05 */ -/* - * Spansion was previously a joint venture of AMD and Fujitsu. - * S25 chips are SPI. The first device ID byte is memory type and - * the second device ID byte is memory capacity. - */ +/* Spansion was previously a joint venture of AMD and Fujitsu. */ #define SPANSION_ID 0x01 /* Spansion, same ID as AMD */ +/* S25 chips are SPI. The first device ID byte is memory type and + * the second device ID byte is memory capacity. */ #define SPANSION_S25FL004A 0x0212 #define SPANSION_S25FL008A 0x0213 #define SPANSION_S25FL016A 0x0214 @@ -577,6 +599,40 @@ #define SPANSION_S25FL132K 0x4016 #define SPANSION_S25FL164K 0x4017 +/* Spansion 29GL families got a suffix indicating the process technology but share the same 3-Byte IDs. They can + * however be differentiated by CFI byte 45h. Some versions exist which have special top or bottom boot sectors + * and various WP configurations (not heeded in the table below). + * + * Suf. Process Sector Sz Rd Page Wr Page Data Width OTP Sz Min Size Max Size + * A 200 nm 64 kB 8 B 32 B x8/x16 256 B 16Mb/ 2MB 64Mb/ 8MB + * M 230 nm 64 kB 8 B 32 B x8/x16 256 B 32Mb/ 4MB 256Mb/ 32MB + * N* 110 nm 64 kB 16 B 32 B x8/x16 256 B 32Mb/ 4MB 64Mb/ 8MB + * N* 110 nm 128 kB 16 B 32 B x8/x16 256 B 128Mb/16MB 256Mb/ 64MB + * P 90 nm 128 kB 16 B 64 B x8/x16 256 B 128Mb/16MB 2Gb/256MB + * S 65 nm 128 kB 32 B 512 B x8 only 512 B 128Mb/16MB 2Gb/256MB + * + * For the N series there are two subgroups: the 4 and 8MB devices (S29GL032N, S29GL064N) have 64 kB erase + * sectors while the bigger chips got 128 kB sectors. + * Each series includes multiple models varying in speedgrade, boot block configurations etc. + */ +#define SPANSION_S29GL016_1 0xC4 /* Top Boot Sector, WP protects Top 2 sectors */ +#define SPANSION_S29GL016_2 0x49 /* Bottom Boot Sector, WP protects Bottom 2 sectors */ +/* Same IDs for S29GL032A, S29GL032M, S29GL032N (variations) */ +#define SPANSION_S29GL032_1289 0x7E1D00 /* Uniform Sectors, WP protects Top OR Bottom sector */ +#define SPANSION_S29GL032_3 0x7E1A01 /* Top Boot Sector, WP protects Top 2 sectors */ +#define SPANSION_S29GL032_4 0x7E1A00 /* Bottom Boot Sector, WP protects Bottom 2 sectors */ +/* Same IDs for S29GL064A, S29GL064M, S29GL064N, S29GL064S (variations) */ +#define SPANSION_S29GL064_1289 0x7E0C01 /* Uniform Sectors, WP protects Top OR Bottom sector */ +#define SPANSION_S29GL064_3 0x7E1001 /* Top Boot Sector, WP protects Top 2 sectors */ +#define SPANSION_S29GL064_4 0x7E1000 /* Bottom Boot Sector, WP protects Bottom 2 sectors */ +#define SPANSION_S29GL064_567 0x7E1301 /* x16 only, Uniform Sectors */ + +#define SPANSION_S29GL128 0x7E2101 /* Same ID for S29GL128M, S29GL128N, S29GL128P, S29GL128S */ +#define SPANSION_S29GL256 0x7E2201 /* Same ID for S29GL256M, S29GL256N, S29GL256P, S29GL256S */ +#define SPANSION_S29GL512 0x7E2301 /* Same ID for S29GL512P, S29GL512S */ +#define SPANSION_S29GL01G 0x7E2801 /* Same ID for S29GL01GP, S29GL01GS */ +#define SPANSION_S70GL02G 0x7E4801 /* Same ID for S70GL02GP, S70GL02GS; based on two S29GL01G dies respectively */ + /* * SST25 chips are SPI, first byte of device ID is memory type, second * byte of device ID is related to log(bitsize) at least for some chips. @@ -776,6 +832,14 @@ #define WINBOND_W29C020 0x45 /* Same as W29C020C, W29C022 and ASD AE29F2008 */ #define WINBOND_W29C040 0x46 /* Same as W29C040P */ #define WINBOND_W29C512A 0xC8 /* Same as W29EE512 */ +#define WINBOND_W29GL032CHL 0x7E1D01 /* Uniform Sectors, WP protects Top OR Bottom sector */ +#define WINBOND_W29GL032CB 0x7E1A00 /* Top Boot Sector, WP protects Top 2 sectors */ +#define WINBOND_W29GL032CT 0x7E1A01 /* Bottom Boot Sector, WP protects Bottom 2 sectors */ +#define WINBOND_W29GL064CHL 0x7E0C01 /* Uniform Sectors, WP protects Top OR Bottom sector */ +#define WINBOND_W29GL064CB 0x7E1000 /* Top Boot Sector, WP protects Top 2 sectors */ +#define WINBOND_W29GL064CT 0x7E1001 /* Bottom Boot Sector, WP protects Bottom 2 sectors */ +#define WINBOND_W29GL128CHL 0x7E2101 /* Uniform Sectors, WP protects Top OR Bottom sector */ +#define WINBOND_W29GL256HL 0x7E2201 /* Same ID for W29GL0256P and W29GL0256S; uniform Sectors, WP protects Top OR Bottom sector */ #define WINBOND_W39F010 0xA1 #define WINBOND_W39L010 0x31 #define WINBOND_W39L020 0xB5 Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Sun Aug 3 15:05:45 2014 (r1834) +++ trunk/jedec.c Sun Aug 3 16:15:14 2014 (r1835) @@ -121,6 +121,55 @@ chip_writeb(flash, 0xA0, bios + (0x5555 & mask)); } +int probe_jedec_29gl(struct flashctx *flash) +{ + unsigned int mask = getaddrmask(flash->chip); + chipaddr bios = flash->virtual_memory; + const struct flashchip *chip = flash->chip; + + /* Reset chip to a clean slate */ + chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); + + /* Issue JEDEC Product ID Entry command */ + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x90, bios + (0x5555 & mask)); + + /* Read product ID */ + // FIXME: Continuation loop, second byte is at word 0x100/byte 0x200 + uint32_t man_id = chip_readb(flash, bios + 0x00); + uint32_t dev_id = (chip_readb(flash, bios + 0x01) << 16) | + (chip_readb(flash, bios + 0x0E) << 8) | + (chip_readb(flash, bios + 0x0F) << 0); + + /* Issue JEDEC Product ID Exit command */ + chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); + + msg_cdbg("%s: man_id 0x%02x, dev_id 0x%06x", __func__, man_id, dev_id); + if (!oddparity(man_id)) + msg_cdbg(", man_id parity violation"); + + /* Read the product ID location again. We should now see normal flash contents. */ + uint32_t flashcontent1 = chip_readb(flash, bios + 0x00); // FIXME: Continuation loop + uint32_t flashcontent2 = (chip_readb(flash, bios + 0x01) << 16) | + (chip_readb(flash, bios + 0x0E) << 8) | + (chip_readb(flash, bios + 0x0F) << 0); + + if (man_id == flashcontent1) + msg_cdbg(", man_id seems to be normal flash content"); + if (dev_id == flashcontent2) + msg_cdbg(", dev_id seems to be normal flash content"); + + msg_cdbg("\n"); + if (man_id != chip->manufacture_id || dev_id != chip->model_id) + return 0; + + if (chip->feature_bits & FEATURE_REGISTERMAP) + map_flash_registers(flash); + + return 1; +} + static int probe_jedec_common(struct flashctx *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory;

1 0

Re: [flashrom] [PATCH 2/2] fixup! Add support for Atmel AT49LH004.
by Stefan Tauner 03 Aug '14

03 Aug '14

I have committed both patches in r1833 and r1834 because I don't expect a timely review or tests without this being in trunk. Also, I want to rebase the probing patch set on top of it and I don't want to let this bitrot forever (again). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[commit] r1834 - trunk
by repository service 03 Aug '14

03 Aug '14

Author: stefanct Date: Sun Aug 3 15:05:45 2014 New Revision: 1834 URL: http://flashrom.org/trac/flashrom/changeset/1834 Log: Add support for Atmel AT49LH004 and AT49LH00B4. Also, slightly refine the definition of AT49LH002. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Aug 3 15:05:34 2014 (r1833) +++ trunk/flashchips.c Sun Aug 3 15:05:45 2014 (r1834) @@ -3049,10 +3049,10 @@ .model_id = ATMEL_AT49LH002, .total_size = 256, .page_size = 0, /* unused */ - .feature_bits = FEATURE_REGISTERMAP, /* TODO: LPC OK too? */ + .feature_bits = FEATURE_REGISTERMAP, .tested = TEST_UNTESTED, - .probe = probe_82802ab, /* TODO: 0xff cmd not documented? */ - .probe_timing = TIMING_FIXME, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, .block_erasers = { { @@ -3062,16 +3062,88 @@ {8 * 1024, 2}, {16 * 1024, 1}, }, - .block_erase = erase_block_82802ab, + .block_erase = NULL, /* TODO: Implement. */ }, { .eraseblocks = { {64 * 1024, 4}, }, + .block_erase = erase_block_82802ab, + }, + }, + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, + .write = write_82802ab, + .read = read_memmapped, + .voltage = {3000, 3600}, + }, + + { + .vendor = "Atmel", + .name = "AT49LH00B4", + .bustype = BUS_LPC | BUS_FWH, /* A/A Mux */ + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT49LH00B4, + .total_size = 512, + .page_size = 0, /* unused */ + .feature_bits = FEATURE_REGISTERMAP, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 2}, + {16 * 1024, 1}, + {32 * 1024, 1}, + {64 * 1024, 7}, + }, + .block_erase = NULL, /* TODO: Implement. */ + }, { + .eraseblocks = { + {64 * 1024, 8}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, + .write = write_82802ab, + .read = read_memmapped, + .voltage = {3000, 3600}, + }, + + { + .vendor = "Atmel", + .name = "AT49LH004", + .bustype = BUS_LPC | BUS_FWH, /* A/A Mux */ + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT49LH004, + .total_size = 512, + .page_size = 0, /* unused */ + .feature_bits = FEATURE_REGISTERMAP, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 7}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_block_82802ab, + }, { + .eraseblocks = { + {64 * 1024, 8}, + }, .block_erase = NULL, /* TODO: Implement. */ }, }, - .printlock = NULL, /* TODO */ - .unlock = NULL, /* unlock_82802ab() not correct(?) */ + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Aug 3 15:05:34 2014 (r1833) +++ trunk/flashchips.h Sun Aug 3 15:05:45 2014 (r1834) @@ -190,6 +190,8 @@ #define ATMEL_AT49BV512 0x03 #define ATMEL_AT49F002N 0x07 /* for AT49F002(N) */ #define ATMEL_AT49LH002 0xE9 +#define ATMEL_AT49LH00B4 0xED +#define ATMEL_AT49LH004 0xEE #define ATMEL_AT49F002NT 0x08 /* for AT49F002(N)T */ #define ATMEL_AT49F010 0x17 /* Same as AT49HF010 */ #define ATMEL_AT49F020 0x0B

1 0

[commit] r1833 - trunk
by repository service 03 Aug '14

03 Aug '14

Author: stefanct Date: Sun Aug 3 15:05:34 2014 New Revision: 1833 URL: http://flashrom.org/trac/flashrom/changeset/1833 Log: Refactor unlocking of many chips with locking at register space address +2. This includes PMC Pm49*, SST 49LF00*, ST M50* and Winbond W39* families. The erase and write test status bits of all affected chips have been reset. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Deleted: trunk/pm49fl00x.c Modified: trunk/82802ab.c trunk/Makefile trunk/chipdrivers.h trunk/flashchips.c trunk/jedec.c trunk/sst49lfxxxc.c trunk/stm50.c trunk/w39.c Modified: trunk/82802ab.c ============================================================================== --- trunk/82802ab.c Mon Jul 28 22:35:21 2014 (r1832) +++ trunk/82802ab.c Sun Aug 3 15:05:34 2014 (r1833) @@ -108,17 +108,6 @@ return status; } -int unlock_82802ab(struct flashctx *flash) -{ - int i; - //chipaddr wrprotect = flash->virtual_registers + page + 2; - - for (i = 0; i < flash->chip->total_size * 1024; i+= flash->chip->page_size) - chip_writeb(flash, 0, flash->virtual_registers + i + 2); - - return 0; -} - int erase_block_82802ab(struct flashctx *flash, unsigned int page, unsigned int pagesize) { Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Mon Jul 28 22:35:21 2014 (r1832) +++ trunk/Makefile Sun Aug 3 15:05:34 2014 (r1833) @@ -351,7 +351,7 @@ # Flash chip drivers and bus support infrastructure. CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ - sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ + sst28sf040.o m29f400bt.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o \ opaque.o sfdp.o en29lv640b.o at45db.o Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Mon Jul 28 22:35:21 2014 (r1832) +++ trunk/chipdrivers.h Sun Aug 3 15:05:34 2014 (r1833) @@ -131,7 +131,6 @@ int erase_block_82802ab(struct flashctx *flash, unsigned int page, unsigned int pagesize); int write_82802ab(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); void print_status_82802ab(uint8_t status); -int unlock_82802ab(struct flashctx *flash); int unlock_28f004s5(struct flashctx *flash); int unlock_lh28f008bjt(struct flashctx *flash); @@ -146,15 +145,20 @@ int erase_block_jedec(struct flashctx *flash, unsigned int page, unsigned int blocksize); int erase_chip_block_jedec(struct flashctx *flash, unsigned int page, unsigned int blocksize); +int unlock_regspace2_uniform_32k(struct flashctx *flash); +int unlock_regspace2_uniform_64k(struct flashctx *flash); +int unlock_regspace2_block_eraser_0(struct flashctx *flash); +int unlock_regspace2_block_eraser_1(struct flashctx *flash); +int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); +int printlock_regspace2_uniform_64k(struct flashctx *flash); +int printlock_regspace2_block_eraser_0(struct flashctx *flash); +int printlock_regspace2_block_eraser_1(struct flashctx *flash); + /* m29f400bt.c */ int probe_m29f400bt(struct flashctx *flash); int write_m29f400bt(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); void protect_m29f400bt(struct flashctx *flash, chipaddr bios); -/* pm49fl00x.c */ -int unlock_49fl00x(struct flashctx *flash); -int lock_49fl00x(struct flashctx *flash); - /* sst28sf040.c */ int erase_chip_28sf040(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int erase_sector_28sf040(struct flashctx *flash, unsigned int address, unsigned int sector_size); @@ -164,7 +168,6 @@ /* sst49lfxxxc.c */ int erase_sector_49lfxxxc(struct flashctx *flash, unsigned int address, unsigned int sector_size); -int unlock_49lfxxxc(struct flashctx *flash); /* sst_fwhub.c */ int printlock_sst_fwhub(struct flashctx *flash); @@ -184,8 +187,6 @@ int printlock_w39v080a(struct flashctx *flash); int printlock_w39v080fa(struct flashctx *flash); int printlock_w39v080fa_dual(struct flashctx *flash); -int unlock_w39v040fb(struct flashctx *flash); -int unlock_w39v080fa(struct flashctx *flash); int printlock_at49f(struct flashctx *flash); /* w29ee011.c */ @@ -193,8 +194,6 @@ /* stm50.c */ int erase_sector_stm50(struct flashctx *flash, unsigned int block, unsigned int blocksize); -int unlock_stm50_uniform(struct flashctx *flash); -int unlock_stm50_nonuniform(struct flashctx *flash); /* en29lv640b.c */ int probe_en29lv640b(struct flashctx *flash); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Mon Jul 28 22:35:21 2014 (r1832) +++ trunk/flashchips.c Sun Aug 3 15:05:34 2014 (r1833) @@ -1382,7 +1382,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* routine is wrapper to probe_jedec (pm49fl00x.c) */ .block_erasers = @@ -1395,7 +1395,7 @@ .block_erase = erase_chip_block_jedec, } }, - .unlock = unlock_49fl00x, + .unlock = unlock_regspace2_uniform_64k, .write = write_jedec_1, .read = read_memmapped, .voltage = {3000, 3600}, @@ -5979,7 +5979,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine does not use probe_timing (82802ab.c) */ .block_erasers = @@ -5989,7 +5989,7 @@ .block_erase = erase_block_82802ab, }, }, - .unlock = unlock_82802ab, + .unlock = unlock_regspace2_uniform_64k, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, @@ -6014,7 +6014,7 @@ .block_erase = erase_block_82802ab, }, }, - .unlock = unlock_82802ab, + .unlock = unlock_regspace2_uniform_64k, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, @@ -9202,7 +9202,7 @@ .total_size = 256, .page_size = 16 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* routine is wrapper to probe_jedec (pm49fl00x.c) */ .block_erasers = @@ -9218,7 +9218,7 @@ .block_erase = erase_chip_block_jedec, } }, - .unlock = unlock_49fl00x, + .unlock = unlock_regspace2_uniform_32k, .write = write_jedec_1, .read = read_memmapped, .voltage = {3000, 3600}, @@ -9233,7 +9233,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* routine is wrapper to probe_jedec (pm49fl00x.c) */ .block_erasers = @@ -9249,7 +9249,7 @@ .block_erase = erase_chip_block_jedec, } }, - .unlock = unlock_49fl00x, + .unlock = unlock_regspace2_uniform_64k, .write = write_jedec_1, .read = read_memmapped, .voltage = {3000, 3600}, @@ -9562,7 +9562,7 @@ .block_erase = NULL, /* 30 D0, only in A/A mux mode */ }, }, - .unlock = unlock_82802ab, + .unlock = unlock_regspace2_uniform_64k, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, @@ -11104,7 +11104,8 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_49lfxxxc, + .printlock = printlock_regspace2_block_eraser_1, + .unlock = unlock_regspace2_block_eraser_1, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, @@ -11169,7 +11170,8 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_49lfxxxc, + .printlock = printlock_regspace2_block_eraser_1, + .unlock = unlock_regspace2_block_eraser_1, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, @@ -11184,7 +11186,7 @@ .total_size = 2048, .page_size = 4 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (sst49lfxxxc.c) */ .block_erasers = @@ -11202,7 +11204,8 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_49lfxxxc, + .printlock = printlock_regspace2_block_eraser_1, + .unlock = unlock_regspace2_block_eraser_1, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, @@ -11307,7 +11310,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_EITHER_RESET | FEATURE_REGISTERMAP, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = 1, /* 150ns */ .block_erasers = @@ -11323,7 +11326,7 @@ .block_erase = NULL, } }, - .unlock = unlock_82802ab, + .unlock = unlock_regspace2_uniform_64k, .write = write_jedec_1, .read = read_memmapped, .voltage = {3000, 3600}, @@ -11368,7 +11371,7 @@ .total_size = 2048, .page_size = 4 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PR, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (sst49lfxxxc.c) */ .block_erasers = @@ -11386,7 +11389,8 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_49lfxxxc, + .printlock = printlock_regspace2_block_eraser_1, + .unlock = unlock_regspace2_block_eraser_1, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, @@ -11654,7 +11658,7 @@ } }, .write = write_82802ab, - .unlock = unlock_stm50_uniform, + .unlock = unlock_regspace2_uniform_64k, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ }, @@ -11687,7 +11691,7 @@ } }, .write = write_82802ab, - .unlock = unlock_stm50_uniform, + .unlock = unlock_regspace2_uniform_64k, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ }, @@ -11701,7 +11705,7 @@ .total_size = 1024, .page_size = 0, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PR, .probe = probe_82802ab, .probe_timing = TIMING_FIXME, .block_erasers = @@ -11719,7 +11723,8 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_stm50_nonuniform, + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ @@ -11752,7 +11757,8 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_stm50_nonuniform, + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ @@ -11767,9 +11773,9 @@ .total_size = 256, .page_size = 0, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_82802ab, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (sst49lfxxxc.c) */ + .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (82802ab.c) */ .block_erasers = { { @@ -11780,9 +11786,13 @@ {16 * 1024, 1}, }, .block_erase = erase_block_82802ab, + }, { + .eraseblocks = { {256 * 1024, 1}, }, + .block_erase = NULL, /* Only in A/A mux mode */ } }, - .unlock = unlock_stm50_nonuniform, + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ @@ -11807,7 +11817,7 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_stm50_uniform, + .unlock = unlock_regspace2_uniform_64k, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ @@ -11832,7 +11842,7 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_stm50_uniform, + .unlock = unlock_regspace2_uniform_64k, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ @@ -11847,7 +11857,7 @@ .total_size = 1024, .page_size = 0, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (82802ab.c) */ .block_erasers = @@ -11857,7 +11867,7 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_stm50_uniform, + .unlock = unlock_regspace2_uniform_64k, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ @@ -11882,7 +11892,7 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_stm50_uniform, + .unlock = unlock_regspace2_uniform_64k, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ @@ -11913,7 +11923,8 @@ .block_erase = erase_block_82802ab, } }, - .unlock = unlock_stm50_nonuniform, + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ @@ -13181,7 +13192,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = 10, .block_erasers = @@ -13198,7 +13209,7 @@ } }, .printlock = printlock_w39v040fa, - .unlock = unlock_sst_fwhub, + .unlock = unlock_regspace2_uniform_64k, .write = write_jedec_1, .read = read_memmapped, .voltage = {3000, 3600}, @@ -13213,7 +13224,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = 10, .block_erasers = @@ -13227,7 +13238,7 @@ } }, .printlock = printlock_w39v040fb, - .unlock = unlock_w39v040fb, + .unlock = unlock_regspace2_uniform_64k, .write = write_jedec_1, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ @@ -13418,7 +13429,7 @@ .total_size = 1024, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = 10, .block_erasers = @@ -13432,7 +13443,7 @@ } }, .printlock = printlock_w39v080fa, - .unlock = unlock_w39v080fa, + .unlock = unlock_regspace2_uniform_64k, .write = write_jedec_1, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Mon Jul 28 22:35:21 2014 (r1832) +++ trunk/jedec.c Sun Aug 3 15:05:34 2014 (r1833) @@ -4,8 +4,9 @@ * Copyright (C) 2000 Silicon Integrated System Corporation * Copyright (C) 2006 Giampiero Giancipoli <gianci(a)email.it> * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> - * Copyright (C) 2007 Carl-Daniel Hailfinger + * Copyright (C) 2007, 2011 Carl-Daniel Hailfinger * Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com> + * Copyright (C) 2014 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -510,3 +511,185 @@ mask = getaddrmask(flash->chip); return erase_chip_jedec_common(flash, mask); } + +struct unlockblock { + unsigned int size; + unsigned int count; +}; + +typedef int (*unlockblock_func)(const struct flashctx *flash, chipaddr offset); +static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struct unlockblock *block, unlockblock_func func) +{ + chipaddr off = flash->virtual_registers + 2; + while (block->count != 0) { + unsigned int j; + for (j = 0; j < block->count; j++) { + if (func(flash, off)) + return -1; + off += block->size; + } + block++; + } + return 0; +} + +#define REG2_RWLOCK ((1 << 2) | (1 << 0)) +#define REG2_LOCKDOWN (1 << 1) +#define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) + +static int printlock_regspace2_block(const struct flashctx *flash, chipaddr offset) +{ + chipaddr wrprotect = flash->virtual_registers + offset + 2; + uint8_t state = chip_readb(flash, wrprotect); + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, offset); + switch (state & REG2_MASK) { + case 0: + msg_cdbg("Full Access.\n"); + break; + case 1: + msg_cdbg("Write Lock (Default State).\n"); + break; + case 2: + msg_cdbg("Locked Open (Full Access, Locked Down).\n"); + break; + case 3: + msg_cdbg("Write Lock, Locked Down.\n"); + break; + case 4: + msg_cdbg("Read Lock.\n"); + break; + case 5: + msg_cdbg("Read/Write Lock.\n"); + break; + case 6: + msg_cdbg("Read Lock, Locked Down.\n"); + break; + case 7: + msg_cdbg("Read/Write Lock, Locked Down.\n"); + break; + } + return 0; +} + +int printlock_regspace2_blocks(const struct flashctx *flash, const struct unlockblock *blocks) +{ + return regspace2_walk_unlockblocks(flash, blocks, &printlock_regspace2_block); +} + +static int printlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) +{ + const unsigned int elems = flash->chip->total_size * 1024 / block_size; + struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; + return regspace2_walk_unlockblocks(flash, blocks, &printlock_regspace2_block); +} + +int printlock_regspace2_uniform_64k(struct flashctx *flash) +{ + return printlock_regspace2_uniform(flash, 64 * 1024); +} + +int printlock_regspace2_block_eraser_0(struct flashctx *flash) +{ + // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). + const struct unlockblock *unlockblocks = + (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; + return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); +} + +int printlock_regspace2_block_eraser_1(struct flashctx *flash) +{ + // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). + const struct unlockblock *unlockblocks = + (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; + return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); +} + +static int changelock_regspace2_block(const struct flashctx *flash, chipaddr offset, uint8_t new_bits) +{ + chipaddr wrprotect = flash->virtual_registers + offset + 2; + uint8_t old; + + if (new_bits & ~REG2_MASK) { + msg_cerr("Invalid locking change 0x%02x requested at 0x%0*" PRIxPTR "! " + "Please report a bug at flashrom(a)flashrom.org\n", + new_bits, PRIxPTR_WIDTH, offset); + return -1; + } + old = chip_readb(flash, wrprotect); + /* Early exist if no change (of read/write/lockdown) was requested. */ + if (((old ^ new_bits) & REG2_MASK) == 0) { + msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not changed\n", PRIxPTR_WIDTH, offset); + return 0; + } + /* Normally lockdowns can not be cleared. Try nevertheless if requested. */ + if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { + chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); + if (chip_readb(flash, wrprotect) != (old & ~REG2_LOCKDOWN)) { + msg_cerr("Lockdown can't be removed at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + return -1; + } + } + /* Change read or write lock? */ + if ((old ^ new_bits) & REG2_RWLOCK) { + /* Do not lockdown yet. */ + msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); + chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); + if (chip_readb(flash, wrprotect) != (new_bits & REG2_RWLOCK)) { + msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + return -1; + } + } + /* Enable lockdown if requested. */ + if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { + msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", PRIxPTR_WIDTH, offset); + chip_writeb(flash, new_bits, wrprotect); + if (chip_readb(flash, wrprotect) != new_bits) { + msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + return -1; + } + } + + return 0; +} + +int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) +{ + chipaddr wrprotect = flash->virtual_registers + off + 2; + uint8_t old = chip_readb(flash, wrprotect); + /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ + return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); +} + +static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) +{ + const unsigned int elems = flash->chip->total_size * 1024 / block_size; + struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; + return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block); +} + +int unlock_regspace2_uniform_64k(struct flashctx *flash) +{ + return unlock_regspace2_uniform(flash, 64 * 1024); +} + +int unlock_regspace2_uniform_32k(struct flashctx *flash) +{ + return unlock_regspace2_uniform(flash, 32 * 1024); +} + +int unlock_regspace2_block_eraser_0(struct flashctx *flash) +{ + // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). + const struct unlockblock *unlockblocks = + (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); +} + +int unlock_regspace2_block_eraser_1(struct flashctx *flash) +{ + // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). + const struct unlockblock *unlockblocks = + (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); +} + Modified: trunk/sst49lfxxxc.c ============================================================================== --- trunk/sst49lfxxxc.c Mon Jul 28 22:35:21 2014 (r1832) +++ trunk/sst49lfxxxc.c Sun Aug 3 15:05:34 2014 (r1833) @@ -23,45 +23,6 @@ #include "flash.h" #include "chipdrivers.h" -static int write_lockbits_block_49lfxxxc(struct flashctx *flash, - unsigned long address, - unsigned char bits) -{ - unsigned long lock = flash->virtual_registers + address + 2; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", lock, - chip_readb(flash, lock)); - chip_writeb(flash, bits, lock); - - return 0; -} - -static int write_lockbits_49lfxxxc(struct flashctx *flash, unsigned char bits) -{ - chipaddr registers = flash->virtual_registers; - unsigned int i, left = flash->chip->total_size * 1024; - unsigned long address; - - msg_cdbg("\nbios=0x%08" PRIxPTR "\n", registers); - for (i = 0; left > 65536; i++, left -= 65536) { - write_lockbits_block_49lfxxxc(flash, i * 65536, bits); - } - address = i * 65536; - write_lockbits_block_49lfxxxc(flash, address, bits); - address += 32768; - write_lockbits_block_49lfxxxc(flash, address, bits); - address += 8192; - write_lockbits_block_49lfxxxc(flash, address, bits); - address += 8192; - write_lockbits_block_49lfxxxc(flash, address, bits); - - return 0; -} - -int unlock_49lfxxxc(struct flashctx *flash) -{ - return write_lockbits_49lfxxxc(flash, 0); -} - int erase_sector_49lfxxxc(struct flashctx *flash, unsigned int address, unsigned int sector_size) { Modified: trunk/stm50.c ============================================================================== --- trunk/stm50.c Mon Jul 28 22:35:21 2014 (r1832) +++ trunk/stm50.c Sun Aug 3 15:05:34 2014 (r1833) @@ -27,63 +27,8 @@ */ #include "flash.h" -#include "flashchips.h" #include "chipdrivers.h" -static int stm50_unlock_address(struct flashctx *flash, int offset) -{ - chipaddr wrprotect = flash->virtual_registers + 2; - static const uint8_t unlock_sector = 0x00; - msg_cdbg("unlocking at 0x%x\n", offset); - chip_writeb(flash, unlock_sector, wrprotect + offset); - if (chip_readb(flash, wrprotect + offset) != unlock_sector) { - msg_cerr("Cannot unlock address 0x%x\n", offset); - return -1; - } - return 0; -} - -/* Chips known to use a non-uniform block and sector layout for locking (as well as for erasing): - * Name Size Address range of lock registers - * M50FLW080A 1MB FFB00002 - FFBFF002 - * M50FLW080B 1MB FFB00002 - FFBFF002 - * M50FW002 256k FFBC0002 - FFBFC002 - * M50LPW116 2MB FFA00002 - FFBFC002 - */ -int unlock_stm50_nonuniform(struct flashctx *flash) -{ - int i; - struct eraseblock *eraseblocks = flash->chip->block_erasers[0].eraseblocks; - unsigned int done = 0; - for (i = 0; i < NUM_ERASEREGIONS && eraseblocks[i].count != 0; i++) { - unsigned int block_size = eraseblocks[i].size; - unsigned int block_count = eraseblocks[i].count; - - int j; - for (j = 0; j < block_count; j++) { - if (stm50_unlock_address(flash, done)) { - msg_cerr("UNLOCK FAILED!\n"); - return -1; - } - done += block_count * block_size; - } - } - return 0; -} - -/* Unlocking for uniform 64 kB blocks starting at offset 2 of the feature registers. */ -int unlock_stm50_uniform(struct flashctx *flash) -{ - int i; - for (i = 0; i < flash->chip->total_size * 1024; i+= 64 * 1024) { - if (stm50_unlock_address(flash, i)) { - msg_cerr("UNLOCK FAILED!\n"); - return -1; - } - } - return 0; -} - static int stm50_erase_sector(struct flashctx *flash, unsigned int addr) { chipaddr bios = flash->virtual_memory + addr; Modified: trunk/w39.c ============================================================================== --- trunk/w39.c Mon Jul 28 22:35:21 2014 (r1832) +++ trunk/w39.c Sun Aug 3 15:05:34 2014 (r1833) @@ -20,65 +20,7 @@ */ #include "flash.h" - -static int printlock_w39_fwh_block(struct flashctx *flash, unsigned int offset) -{ - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t locking; - - locking = chip_readb(flash, wrprotect); - msg_cdbg("Lock status of block at 0x%08x is ", offset); - switch (locking & 0x7) { - case 0: - msg_cdbg("Full Access.\n"); - break; - case 1: - msg_cdbg("Write Lock (Default State).\n"); - break; - case 2: - msg_cdbg("Locked Open (Full Access, Lock Down).\n"); - break; - case 3: - msg_cerr("Error: Write Lock, Locked Down.\n"); - break; - case 4: - msg_cdbg("Read Lock.\n"); - break; - case 5: - msg_cdbg("Read/Write Lock.\n"); - break; - case 6: - msg_cerr("Error: Read Lock, Locked Down.\n"); - break; - case 7: - msg_cerr("Error: Read/Write Lock, Locked Down.\n"); - break; - } - - /* Read or write lock present? */ - return (locking & ((1 << 2) | (1 << 0))) ? -1 : 0; -} - -static int unlock_w39_fwh_block(struct flashctx *flash, unsigned int offset) -{ - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t locking; - - locking = chip_readb(flash, wrprotect); - /* Read or write lock present? */ - if (locking & ((1 << 2) | (1 << 0))) { - /* Lockdown active? */ - if (locking & (1 << 1)) { - msg_cerr("Can't unlock block at 0x%08x!\n", offset); - return -1; - } else { - msg_cdbg("Unlocking block at 0x%08x\n", offset); - chip_writeb(flash, 0, wrprotect); - } - } - - return 0; -} +#include "chipdrivers.h" static uint8_t w39_idmode_readb(struct flashctx *flash, unsigned int offset) { @@ -145,30 +87,6 @@ return printlock_w39_tblwp(lock); } -static int printlock_w39_fwh(struct flashctx *flash) -{ - unsigned int i, total_size = flash->chip->total_size * 1024; - int ret = 0; - - /* Print lock status of the complete chip */ - for (i = 0; i < total_size; i += flash->chip->page_size) - ret |= printlock_w39_fwh_block(flash, i); - - return ret; -} - -static int unlock_w39_fwh(struct flashctx *flash) -{ - unsigned int i, total_size = flash->chip->total_size * 1024; - - /* Unlock the complete chip */ - for (i = 0; i < total_size; i += flash->chip->page_size) - if (unlock_w39_fwh_block(flash, i)) - return -1; - - return 0; -} - int printlock_w39f010(struct flashctx *flash) { uint8_t lock; @@ -267,7 +185,7 @@ int ret = 0; ret = printlock_w39v040a(flash); - ret |= printlock_w39_fwh(flash); + ret |= printlock_regspace2_uniform_64k(flash); return ret; } @@ -277,7 +195,7 @@ int ret = 0; ret = printlock_w39v040b(flash); - ret |= printlock_w39_fwh(flash); + ret |= printlock_regspace2_uniform_64k(flash); return ret; } @@ -288,7 +206,7 @@ /* W39V040C and W39V040FC use different WP/TBL offsets. */ ret = printlock_w39_common(flash, 0x7fff2); - ret |= printlock_w39_fwh(flash); + ret |= printlock_regspace2_uniform_64k(flash); return ret; } @@ -303,7 +221,7 @@ int ret = 0; ret = printlock_w39v080a(flash); - ret |= printlock_w39_fwh(flash); + ret |= printlock_regspace2_uniform_64k(flash); return ret; } @@ -316,26 +234,6 @@ return -1; } -int unlock_w39v040fb(struct flashctx *flash) -{ - if (unlock_w39_fwh(flash)) - return -1; - if (printlock_w39_common(flash, 0x7fff2)) - return -1; - - return 0; -} - -int unlock_w39v080fa(struct flashctx *flash) -{ - if (unlock_w39_fwh(flash)) - return -1; - if (printlock_w39_common(flash, 0xffff2)) - return -1; - - return 0; -} - int printlock_at49f(struct flashctx *flash) { uint8_t lock = w39_idmode_readb(flash, 0x00002);

1 0

Re: [flashrom] Log from Intel Atom C2550
by Stefan Tauner 02 Aug '14

02 Aug '14

On Sat, 2 Aug 2014 21:06:16 -0400 TR Reardon <thomas_reardon(a)hotmail.com> wrote: > Updated with patchset from 2-Aug-2014 Thanks... stupid error: != instead of == :) Attached is a new version of the second patch (also pushed to github). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

ichspi: fix missing set_addr and crossing of 256 boundary
by Vladimir 'φ-coder/phcoder' Serbinenko 02 Aug '14

02 Aug '14

Accoring to PCH documentation crossing 256-byte boundary is invalid and causes wraparound. Please apply attached patch

2 1

Re: [flashrom] Log from Intel Atom C2550
by TR Reardon 02 Aug '14

02 Aug '14

Updated with patchset from 2-Aug-2014 +Reardon On Sat, Aug 2, 2014 at 8:46 PM, Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > On Sat, 2 Aug 2014 20:21:44 -0400 > TR Reardon <thomas_reardon(a)hotmail.com> wrote: > >> For what it's worth, the unrecognized flash chip on this ASUS >> motherboard is Macronix MX25L25735EMI > > Thanks! I could not figure it out immediately... I think it might be > more obvious if I could see the output of the current patch set. > Clearly the chipset enable function does not register an SPI master in > your version of the patch... but it may work correctly in the current > version (at least up to that point). Sorry for the inconvenience :) > > -- > Kind regards/Mit freundlichen Grüßen, Stefan Tauner >

1 0

Re: [flashrom] Log from Intel Atom C2550
by Stefan Tauner 02 Aug '14

02 Aug '14

On Sat, 2 Aug 2014 20:21:44 -0400 TR Reardon <thomas_reardon(a)hotmail.com> wrote: > For what it's worth, the unrecognized flash chip on this ASUS > motherboard is Macronix MX25L25735EMI Thanks! I could not figure it out immediately... I think it might be more obvious if I could see the output of the current patch set. Clearly the chipset enable function does not register an SPI master in your version of the patch... but it may work correctly in the current version (at least up to that point). Sorry for the inconvenience :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Log from Intel Atom C2550
by TR Reardon 02 Aug '14

02 Aug '14

For what it's worth, the unrecognized flash chip on this ASUS motherboard is Macronix MX25L25735EMI

1 0

Re: [flashrom] [whitelist/flashrom]: Lenovo T530
by Stefan Tauner 02 Aug '14

02 Aug '14

On Mon, 9 Jun 2014 13:49:31 +1000 "Edward O'Callaghan" <eocallaghan(a)alterapraxis.com> wrote: > Hi Stefan, > > Attached is a patch to whitelist the Lenovo T530 laptop. > Here is the dump from # flashrom -p internal -V > https://gist.github.com/victoredwardocallaghan/a8455b5f6fd8cd165989 > > Sorry, I really didn't want to join the mailing list (too much mail) > for a one liner. Also I did not know if this was you? > pub 4096R/023DF00B 2013-07-09 Stefan Tauner <stefan.tauner(a)gmx.at> Thanks for the patch. I have added the change to my tested_stuff branch but included also an entry in print.c with a note that it only works well with coreboot... I should probably do the same thing with the x60x thinkpads some day... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

New mainboard - Shuttle AB61
by olofolleola4_pub＠riseup.net 02 Aug '14

02 Aug '14

Hello! I've tested flashrom v0.9.7-r1832 with this mainboard. The factory BIOS image had this: DMI string chassis-type: "Unknown". When I tried flashrom with the factory image applied to the flash chip, I needed to specify this line 'internal:laptop=this_is_not_a_laptop' When I updated the BIOS for this mainboard to the latest version with flashrom, the BIOS image now have this instead: DMI string chassis-type: "Desktop". This means that the latest BIOS image doesn't require any extra information (internal:laptop=this_is_not_a_laptop) specified with flashrom. This mainboard works fine. Original flash chip on this mainboard: SST SST39SF020A Mainboard URL: http://www.shuttle.eu/_archive/older/de/ab61.htm I've attached several logs in this e-mail.

2 1

[PATCH 3/3] Add support for Intel Wildcat Point PCH.
by Stefan Tauner 01 Aug '14

01 Aug '14

The Wildcat Point PCH can be paired with Broadwell or Haswell. This patch was essentially backported from ChromiumOS commit 9bd2af8. Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- chipset_enable.c | 19 +++++++++++++++++-- ich_descriptors.c | 5 ++++- ich_descriptors.h | 2 +- programmer.h | 1 + util/ich_descriptors_tool/ich_descriptors_tool.c | 4 ++++ 5 files changed, 27 insertions(+), 4 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 767afd3..9a74392 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -594,7 +594,7 @@ static void enable_flash_ich_handle_gcs(struct pci_dev *dev, enum ich_chipset ic static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" }; static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; - static const char *const straps_names_pch8_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; + static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; @@ -623,8 +623,9 @@ static void enable_flash_ich_handle_gcs(struct pci_dev *dev, enum ich_chipset ic straps_names = straps_names_pch567; break; case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_9_SERIES_WILDCAT_POINT: case CHIPSET_BAYTRAIL: - straps_names = straps_names_pch8_baytrail; + straps_names = straps_names_pch89_baytrail; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: straps_names = straps_names_pch8_lp; @@ -776,6 +777,12 @@ static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name) return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); } +/* Wildcat Point */ +static int enable_flash_pch9(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); +} + /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. * @@ -1759,6 +1766,14 @@ const struct penable chipset_enables[] = { {0x8086, 0x8d5d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, {0x8086, 0x8d5e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, {0x8086, 0x8d5f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9}, + {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9}, + {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9}, + {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9}, + {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9}, + {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9}, + {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9}, + {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index 8d52c7e..9a5e509 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -139,7 +139,8 @@ static const char *pprint_density(enum ich_chipset cs, const struct ich_descript case CHIPSET_8_SERIES_LYNX_POINT: case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: - case CHIPSET_8_SERIES_WELLSBURG: { + case CHIPSET_8_SERIES_WELLSBURG: + case CHIPSET_9_SERIES_WILDCAT_POINT: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.new.comp1_density; @@ -182,6 +183,7 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value) case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: + case CHIPSET_9_SERIES_WILDCAT_POINT: return freq_str[value]; case CHIPSET_ICH_UNKNOWN: default: @@ -823,6 +825,7 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: + case CHIPSET_9_SERIES_WILDCAT_POINT: if (idx == 0) { size_enc = desc->component.new.comp1_density; } else { diff --git a/ich_descriptors.h b/ich_descriptors.h index b9213c8..5b8b7f4 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -117,7 +117,7 @@ struct ich_desc_component { * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? */ struct { - uint32_t :17, + uint32_t :17, freq_read :3, fastread :1, freq_fastread :3, diff --git a/programmer.h b/programmer.h index 8dd6c85..cb2e7db 100644 --- a/programmer.h +++ b/programmer.h @@ -604,6 +604,7 @@ enum ich_chipset { CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */ CHIPSET_8_SERIES_LYNX_POINT_LP, CHIPSET_8_SERIES_WELLSBURG, + CHIPSET_9_SERIES_WILDCAT_POINT, }; /* ichspi.c */ diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 9f58633..1b1f0ac 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -123,6 +123,7 @@ static void usage(char *argv[], char *error) "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" "\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" +"\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -205,6 +206,9 @@ int main(int argc, char *argv[]) cs = CHIPSET_8_SERIES_LYNX_POINT; else if ((strcmp(csn, "silvermont") == 0)) cs = CHIPSET_BAYTRAIL; + else if ((strcmp(csn, "9") == 0) || + (strcmp(csn, "wildcat") == 0)) + cs = CHIPSET_9_SERIES_WILDCAT_POINT; } ret = read_ich_descriptors_from_dump(buf, len, &desc); -- Kind regards, Stefan Tauner

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[PATCH 2/3] Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton.
by Stefan Tauner 01 Aug '14

01 Aug '14

The core of this patch to support Bay Trail originally came from the Chromiumos flashrom repo and was modified by Sage to support the Rangeley/Avoton parts as well. Because that was not complicated enough already Stefan Tauner refactored and refined everything. Bay Trail seems to be the first Atom SoC able to support hwseq. No SPI Programming Guide could be obtained so it is handled similarly to Lynx Point which seems to be its nearest relative. Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- chipset_enable.c | 229 +++++++++++++++++------ ich_descriptors.c | 3 + ichspi.c | 14 +- programmer.h | 1 + util/ich_descriptors_tool/ich_descriptors_tool.c | 3 + 5 files changed, 191 insertions(+), 59 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 37a718f..767afd3 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -260,9 +260,13 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name) return 0; } -/* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom +/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space + * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'. + * + * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */ -static int enable_flash_ich_bios_cntl(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr, + struct pci_dev *dev, uint8_t bios_cntl) { uint8_t old, new, wanted; @@ -273,8 +277,8 @@ static int enable_flash_ich_bios_cntl(struct pci_dev *dev, enum ich_chipset ich_ case CHIPSET_ICH: case CHIPSET_ICH2345: break; - /* Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to what - * other SPI-capable chipsets have at DCh. + /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to + * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register. * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it * mentions that the prefetching and caching does only happen for direct memory reads. * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the @@ -285,9 +289,13 @@ static int enable_flash_ich_bios_cntl(struct pci_dev *dev, enum ich_chipset ich_ old = pci_read_byte(dev, bios_cntl + 1); msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); break; + case CHIPSET_BAYTRAIL: case CHIPSET_ICH7: default: /* Future version might behave the same */ - old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3; + if (ich_generation == CHIPSET_BAYTRAIL) + old = (mmio_readl(addr) >> 2) & 0x3; + else + old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3; msg_pdbg("SPI Read Configuration: "); if (old == 3) msg_pdbg("invalid prefetching/caching settings, "); @@ -297,7 +305,11 @@ static int enable_flash_ich_bios_cntl(struct pci_dev *dev, enum ich_chipset ich_ (old & 0x1) ? "dis" : "en"); } - wanted = old = pci_read_byte(dev, bios_cntl); + if (ich_generation == CHIPSET_BAYTRAIL) + wanted = old = mmio_readl(addr); + else + wanted = old = pci_read_byte(dev, bios_cntl); + /* * Quote from the 6 Series datasheet (Document Number: 324645-004): * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP) @@ -327,8 +339,13 @@ static int enable_flash_ich_bios_cntl(struct pci_dev *dev, enum ich_chipset ich_ /* Only write the register if it's necessary */ if (wanted != old) { - rpci_write_byte(dev, bios_cntl, wanted); - new = pci_read_byte(dev, bios_cntl); + if (ich_generation == CHIPSET_BAYTRAIL) { + rmmio_writel(wanted, addr); + new = mmio_readl(addr); + } else { + rpci_write_byte(dev, bios_cntl, wanted); + new = pci_read_byte(dev, bios_cntl); + } } else new = old; @@ -349,10 +366,22 @@ static int enable_flash_ich_bios_cntl(struct pci_dev *dev, enum ich_chipset ich_ return 0; } +static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation, + uint8_t bios_cntl) +{ + return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl); +} + +static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr) +{ + return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0); +} + static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation) { uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */ bool implemented = 0; + void *ilb = NULL; /* Only for Baytrail */ switch (ich_generation) { case CHIPSET_ICH: /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB @@ -373,6 +402,19 @@ static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich case CHIPSET_CENTERTON: /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */ break; + case CHIPSET_BAYTRAIL: { + uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */ + if (ilb_base == 0) { + msg_perr("Error: Invalid ILB_BASE_ADDRESS\n"); + return ERROR_FATAL; + } + ilb = rphysmap("BYT IBASE", ilb_base, 512); + fwh_sel1 = 0x18; + fwh_dec_en_lo = 0xd8; + fwh_dec_en_hi = 0xd9; + implemented = 1; + break; + } case CHIPSET_ICH6: case CHIPSET_ICH7: default: /* Future version might behave the same */ @@ -397,17 +439,27 @@ static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n"); goto idsel_garbage_out; } - if (fwh_idsel & 0xffff000000000000ULL) { + uint64_t fwh_mask = 0xffffffff; + if (fwh_sel2 > 0) + fwh_mask |= (0xffffULL << 32); + if (fwh_idsel & ~fwh_mask) { msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n"); goto idsel_garbage_out; } - uint64_t fwh_idsel_old = pci_read_long(dev, fwh_sel1); - fwh_idsel_old <<= 16; - fwh_idsel_old |= pci_read_word(dev, fwh_sel2); + uint64_t fwh_idsel_old; + if (ich_generation == CHIPSET_BAYTRAIL) { + fwh_idsel_old = mmio_readl(ilb + fwh_sel1); + rmmio_writel(fwh_idsel, ilb + fwh_sel1); + } else { + fwh_idsel_old = pci_read_long(dev, fwh_sel1) << 16; + rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); + if (fwh_sel2 > 0) { + fwh_idsel_old |= pci_read_word(dev, fwh_sel2); + rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); + } + } msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n", fwh_idsel_old, fwh_idsel); - rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); - rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); /* FIXME: Decode settings are not changed. */ } else if (idsel) { msg_perr("Error: fwh_idsel= specified, but no value given.\n"); @@ -429,7 +481,12 @@ idsel_garbage_out: */ int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; bool contiguous = 1; - uint32_t fwh_conf = pci_read_long(dev, fwh_sel1); + uint32_t fwh_conf; + if (ich_generation == CHIPSET_BAYTRAIL) + fwh_conf = mmio_readl(ilb + fwh_sel1); + else + fwh_conf = pci_read_long(dev, fwh_sel1); + int i; /* FWH_SEL1 */ for (i = 7; i >= 0; i--) { @@ -444,18 +501,20 @@ idsel_garbage_out: contiguous = 0; } } - /* FWH_SEL2 */ - fwh_conf = pci_read_word(dev, fwh_sel2); - for (i = 3; i >= 0; i--) { - int tmp = (fwh_conf >> (i * 4)) & 0xf; - msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", - (0xff4 + i) * 0x100000, - (0xff0 + i) * 0x100000, - tmp); - if ((tmp == 0) && contiguous) { - max_decode_fwh_idsel = (8 - i) * 0x100000; - } else { - contiguous = 0; + if (fwh_sel2 > 0) { + /* FWH_SEL2 */ + fwh_conf = pci_read_word(dev, fwh_sel2); + for (i = 3; i >= 0; i--) { + int tmp = (fwh_conf >> (i * 4)) & 0xf; + msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", + (0xff4 + i) * 0x100000, + (0xff0 + i) * 0x100000, + tmp); + if ((tmp == 0) && contiguous) { + max_decode_fwh_idsel = (8 - i) * 0x100000; + } else { + contiguous = 0; + } } } contiguous = 1; @@ -502,7 +561,7 @@ static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_genera return err; internal_buses_supported = BUS_FWH; - return enable_flash_ich_bios_cntl(dev, ich_generation, bios_cntl); + return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl); } static int enable_flash_ich0(struct pci_dev *dev, const char *name) @@ -525,14 +584,17 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8); } -static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +static void enable_flash_ich_handle_gcs(struct pci_dev *dev, enum ich_chipset ich_generation, uint32_t gcs, bool top_swap) { + msg_pdbg("GCS = 0x%x: ", gcs); + msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); + static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" }; static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" }; static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; - static const char *const straps_names_pch8[] = { "LPC", "reserved", "reserved", "SPI" }; + static const char *const straps_names_pch8_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; @@ -561,7 +623,8 @@ static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_genera straps_names = straps_names_pch567; break; case CHIPSET_8_SERIES_LYNX_POINT: - straps_names = straps_names_pch8; + case CHIPSET_BAYTRAIL: + straps_names = straps_names_pch8_baytrail; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: straps_names = straps_names_pch8_lp; @@ -576,40 +639,40 @@ static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_genera break; } - /* Get physical address of Root Complex Register Block */ - uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; - msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra); - - /* Map RCBA to virtual memory */ - void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); - if (rcrb == ERROR_PTR) - return ERROR_FATAL; - - uint32_t gcs = mmio_readl(rcrb + 0x3410); - msg_pdbg("GCS = 0x%x: ", gcs); - msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); - uint8_t bbs; switch (ich_generation) { case CHIPSET_TUNNEL_CREEK: bbs = (gcs >> 1) & 0x1; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: - case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet - /* Lynx Point LP uses a single bit for GCS */ + /* Lynx Point LP uses a single bit for BBS */ bbs = (gcs >> 10) & 0x1; break; default: - /* Older chipsets use two bits for GCS */ + /* Other chipsets use two bits for BBS */ bbs = (gcs >> 10) & 0x3; break; } msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); - if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) { - uint8_t buc = mmio_readb(rcrb + 0x3414); - msg_pdbg("Top Swap : %s\n", (buc & 1) ? "enabled (A16(+) inverted)" : "not enabled"); - } + /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */ + if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) + msg_pdbg("Top Swap : %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled"); +} + +static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +{ + + /* Get physical address of Root Complex Register Block */ + uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; + msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra); + + /* Map RCBA to virtual memory */ + void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); + if (rcrb == ERROR_PTR) + return ERROR_FATAL; + + enable_flash_ich_handle_gcs(dev, ich_generation, mmio_readl(rcrb + 0x3410), mmio_readb(rcrb + 0x3414)); /* Handle FWH-related parameters and initialization */ int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl); @@ -619,6 +682,7 @@ static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_genera /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */ uint16_t spibar_offset; switch (ich_generation) { + case CHIPSET_BAYTRAIL: case CHIPSET_ICH_UNKNOWN: return ERROR_FATAL; case CHIPSET_ICH7: @@ -712,6 +776,57 @@ static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name) return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); } +/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. + * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. + * + * Differences include: + * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB. + * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410). + * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414). + * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800). + * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC). + */ +static int enable_flash_silvermont(struct pci_dev *dev, const char *name) +{ + enum ich_chipset ich_generation = CHIPSET_BAYTRAIL; + + /* Get physical address of Root Complex Register Block */ + uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00; + msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba); + + /* Handle GCS (in RCRB) */ + void *rcrb = physmap("BYT RCRB", rcba, 4); + uint32_t gcs = mmio_readl(rcrb + 0); + enable_flash_ich_handle_gcs(dev, ich_generation, gcs, gcs & 0x2); + physunmap(rcrb, 4); + + /* Handle fwh_idsel parameter */ + int ret = enable_flash_ich_fwh_decode(dev, ich_generation); + if (ret != ERROR_FATAL) + return ret; + + internal_buses_supported = BUS_FWH; + + /* Get physical address of SPI Base Address and map it */ + uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; + msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); + void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ + + /* Enable Flash Writes. + * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). + */ + enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC); + + int ret_spi = ich_init_spi(dev, spibar, ich_generation); + if (ret_spi == ERROR_FATAL) + return ret_spi; + + if (ret || ret_spi) + return ERROR_NONFATAL; + + return 0; +} + static int via_no_byte_merge(struct pci_dev *dev, const char *name) { uint8_t val; @@ -1471,6 +1586,10 @@ const struct penable chipset_enables[] = { {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, + {0x8086, 0x0f1c, NT, "Intel", "Bay Trail", enable_flash_silvermont}, + {0x8086, 0x0f1d, NT, "Intel", "Bay Trail", enable_flash_silvermont}, + {0x8086, 0x0f1e, NT, "Intel", "Bay Trail", enable_flash_silvermont}, + {0x8086, 0x0f1f, NT, "Intel", "Bay Trail", enable_flash_silvermont}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, {0x8086, 0x1c44, DEP, "Intel", "Z68", enable_flash_pch6}, @@ -1505,7 +1624,11 @@ const struct penable chipset_enables[] = { {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7}, {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7}, {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7}, - {0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7}, + {0x8086, 0x1f38, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7}, {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0}, @@ -1567,7 +1690,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, - {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_tunnelcreek}, + {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek}, {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8}, {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 3977a4b..8d52c7e 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -137,6 +137,7 @@ static const char *pprint_density(enum ich_chipset cs, const struct ich_descript return size_str[size_enc]; } case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: { uint8_t size_enc; @@ -178,6 +179,7 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value) case CHIPSET_6_SERIES_COUGAR_POINT: case CHIPSET_7_SERIES_PANTHER_POINT: case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: return freq_str[value]; @@ -818,6 +820,7 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors size_max = 5; break; case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: if (idx == 0) { diff --git a/ichspi.c b/ichspi.c index 6744bef..65caf1d 100644 --- a/ichspi.c +++ b/ichspi.c @@ -612,7 +612,8 @@ static void ich_set_bbar(uint32_t min_addr) bbar_off = 0x50; break; case CHIPSET_ICH8: - msg_perr("BBAR offset is unknown on ICH8!\n"); + case CHIPSET_BAYTRAIL: + msg_pdbg("BBAR offset is unknown!\n"); return; case CHIPSET_ICH9: default: /* Future version might behave the same */ @@ -1731,9 +1732,12 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) msg_pdbg("VSCC: "); prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); } else { - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); + if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) { + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + ich_set_bbar(0); + } if (desc_valid) { tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); @@ -1749,10 +1753,8 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); } - ich_set_bbar(0); } - msg_pdbg("\n"); if (desc_valid) { if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(ich_gen, &desc); diff --git a/programmer.h b/programmer.h index 3ad553a..8dd6c85 100644 --- a/programmer.h +++ b/programmer.h @@ -601,6 +601,7 @@ enum ich_chipset { CHIPSET_6_SERIES_COUGAR_POINT, CHIPSET_7_SERIES_PANTHER_POINT, CHIPSET_8_SERIES_LYNX_POINT, + CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */ CHIPSET_8_SERIES_LYNX_POINT_LP, CHIPSET_8_SERIES_WELLSBURG, }; diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 4c1f05c..9f58633 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -118,6 +118,7 @@ static void usage(char *argv[], char *error) "\t- \"ich8\",\n" "\t- \"ich9\",\n" "\t- \"ich10\",\n" +"\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" @@ -202,6 +203,8 @@ int main(int argc, char *argv[]) else if ((strcmp(csn, "8") == 0) || (strcmp(csn, "lynx") == 0)) cs = CHIPSET_8_SERIES_LYNX_POINT; + else if ((strcmp(csn, "silvermont") == 0)) + cs = CHIPSET_BAYTRAIL; } ret = read_ich_descriptors_from_dump(buf, len, &desc); -- Kind regards, Stefan Tauner

1 0

[PATCH 1/3] Refine Flash Component descriptor handling.
by Stefan Tauner 01 Aug '14

01 Aug '14

Possible values as well as encodings have changed in newer chipsets as follows. - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all operations - Since Cougar Point the chipsets support dual output fast reads (encoded in bit 30). - Flash component density encoding has changed from 3 to 4 bits with Lynx Point, currently allowing for up to 64 MB chips. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- ich_descriptors.c | 182 +++++++++++++++++------ ich_descriptors.h | 39 ++++- ichspi.c | 24 ++- util/ich_descriptors_tool/ich_descriptors_tool.c | 4 + 4 files changed, 193 insertions(+), 56 deletions(-) diff --git a/ich_descriptors.c b/ich_descriptors.c index 528717b..3977a4b 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -64,7 +64,7 @@ void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) { prettyprint_ich_descriptor_content(&desc->content); - prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_component(cs, desc); prettyprint_ich_descriptor_region(desc); prettyprint_ich_descriptor_master(&desc->master); #ifdef ICH_DESCRIPTORS_FROM_DUMP @@ -98,28 +98,97 @@ void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) msg_pdbg2("\n"); } -void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) +static const char *pprint_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx) +{ + if (idx > 1) { + msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); + return NULL; + } + + if (desc->content.NC == 0 && idx > 0) + return "unused"; + + static const char * const size_str[] = { + "512 kB", /* 0000 */ + "1 MB", /* 0001 */ + "2 MB", /* 0010 */ + "4 MB", /* 0011 */ + "8 MB", /* 0100 */ + "16 MB", /* 0101 */ /* Maximum up to Lynx Point (excl.) */ + "32 MB", /* 0110 */ + "64 MB", /* 0111 */ + }; + + switch (cs) { + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: + case CHIPSET_7_SERIES_PANTHER_POINT: { + uint8_t size_enc; + if (idx == 0) { + size_enc = desc->component.old.comp1_density; + } else { + size_enc = desc->component.old.comp2_density; + } + if (size_enc > 5) + return "reserved"; + return size_str[size_enc]; + } + case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_WELLSBURG: { + uint8_t size_enc; + if (idx == 0) { + size_enc = desc->component.new.comp1_density; + } else { + size_enc = desc->component.new.comp2_density; + } + if (size_enc > 7) + return "reserved"; + return size_str[size_enc]; + } + case CHIPSET_ICH_UNKNOWN: + default: + return "unknown"; + } +} + +static const char *pprint_freq(enum ich_chipset cs, uint8_t value) { static const char * const freq_str[8] = { "20 MHz", /* 000 */ "33 MHz", /* 001 */ "reserved", /* 010 */ "reserved", /* 011 */ - "50 MHz", /* 100 */ + "50 MHz", /* 100 */ /* New since Ibex Peak */ "reserved", /* 101 */ "reserved", /* 110 */ "reserved" /* 111 */ }; - static const char * const size_str[8] = { - "512 kB", /* 000 */ - " 1 MB", /* 001 */ - " 2 MB", /* 010 */ - " 4 MB", /* 011 */ - " 8 MB", /* 100 */ - " 16 MB", /* 101 */ - "reserved", /* 110 */ - "reserved", /* 111 */ - }; + + switch (cs) { + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: + if (value > 1) + return "reserved"; + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: + case CHIPSET_7_SERIES_PANTHER_POINT: + case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_WELLSBURG: + return freq_str[value]; + case CHIPSET_ICH_UNKNOWN: + default: + return "unknown"; + } +} + +void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc) +{ msg_pdbg2("=== Component Section ===\n"); msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); @@ -127,24 +196,21 @@ void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); - msg_pdbg2("Component 1 density: %s\n", - size_str[desc->component.comp1_density]); + msg_pdbg2("Component 1 density: %s\n", pprint_density(cs, desc, 0)); if (desc->content.NC) - msg_pdbg2("Component 2 density: %s\n", - size_str[desc->component.comp2_density]); + msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1)); else msg_pdbg2("Component 2 is not used.\n"); - msg_pdbg2("Read Clock Frequency: %s\n", - freq_str[desc->component.freq_read]); - msg_pdbg2("Read ID and Status Clock Freq.: %s\n", - freq_str[desc->component.freq_read_id]); - msg_pdbg2("Write and Erase Clock Freq.: %s\n", - freq_str[desc->component.freq_write]); - msg_pdbg2("Fast Read is %ssupported.\n", - desc->component.fastread ? "" : "not "); - if (desc->component.fastread) + msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.common.freq_read)); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_read_id)); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_write)); + msg_pdbg2("Fast Read is %ssupported.\n", desc->component.common.fastread ? "" : "not "); + if (desc->component.common.fastread) msg_pdbg2("Fast Read Clock Frequency: %s\n", - freq_str[desc->component.freq_fastread]); + pprint_freq(cs, desc->component.common.freq_fastread)); + if (cs > CHIPSET_6_SERIES_COUGAR_POINT) + msg_pdbg2("Dual Output Fast Read Support: %sabled\n", + desc->component.new.dual_output ? "dis" : "en"); if (desc->component.FLILL == 0) msg_pdbg2("No forbidden opcodes.\n"); else { @@ -273,7 +339,7 @@ static void prettyprint_ich_descriptor_straps_56_pciecs(uint8_t conf, uint8_t of msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1); off *= 4; - switch(conf){ + switch (conf){ case 0: msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off); break; @@ -723,29 +789,57 @@ int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struc #else /* ICH_DESCRIPTORS_FROM_DUMP */ /** Returns the integer representation of the component density with index -idx in bytes or 0 if a correct size can not be determined. */ -int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx) +\em idx in bytes or -1 if the correct size can not be determined. */ +int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx) { + if (idx > 1) { + msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); + return -1; + } + + if (desc->content.NC == 0 && idx > 0) + return 0; + uint8_t size_enc; - - switch(idx) { - case 0: - size_enc = desc->component.comp1_density; + uint8_t size_max; + + switch (cs) { + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: + case CHIPSET_7_SERIES_PANTHER_POINT: + if (idx == 0) { + size_enc = desc->component.old.comp1_density; + } else { + size_enc = desc->component.old.comp2_density; + } + size_max = 5; break; - case 1: - if (desc->content.NC == 0) - return 0; - size_enc = desc->component.comp2_density; + case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_WELLSBURG: + if (idx == 0) { + size_enc = desc->component.new.comp1_density; + } else { + size_enc = desc->component.new.comp2_density; + } + size_max = 7; break; + case CHIPSET_ICH_UNKNOWN: default: - msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); - return 0; + msg_pwarn("Density encoding is unknown on this chipset.\n"); + return -1; } - if (size_enc > 5) { - msg_perr("Density of ICH SPI component with index %d is invalid. Encoded density is 0x%x.\n", - idx, size_enc); - return 0; + + if (size_enc > size_max) { + msg_perr("Density of ICH SPI component with index %d is invalid." + "Encoded density is 0x%x while maximum allowed is 0x%x.\n", + idx, size_enc, size_max); + return -1; } + return (1 << (19 + size_enc)); } diff --git a/ich_descriptors.h b/ich_descriptors.h index 3a44740..b9213c8 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -102,17 +102,44 @@ struct ich_desc_content { struct ich_desc_component { union { /* 0x00 */ uint32_t FLCOMP; /* Flash Components Register */ + /* FLCOMP encoding on various generations: + * + * Chipset/Generation max_speed dual_output density + * [MHz] bits max. bits + * ICH8: 33 N/A 5 0:2, 3:5 + * ICH9: 33 N/A 5 0:2, 3:5 + * ICH10: 33 N/A 5 0:2, 3:5 + * Ibex Peak/5: 50 N/A 5 0:2, 3:5 + * Cougar Point/6: 50 30 5 0:2, 3:5 + * Patsburg: 50 30 5 0:2, 3:5 + * Panther Point/7 50 30 5 0:2, 3:5 + * Lynx Point/8: 50 30 7 0:3, 4:7 + * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? + */ struct { - uint32_t comp1_density :3, - comp2_density :3, - :11, + uint32_t :17, freq_read :3, fastread :1, freq_fastread :3, freq_write :3, freq_read_id :3, :2; - }; + } common; + struct { + uint32_t comp1_density :3, + comp2_density :3, + :11, + :13, + :2; + } old; + struct { + uint32_t comp1_density :4, /* new since Lynx Point/8 */ + comp2_density :4, + :9, + :13, + dual_output :1, /* new since Cougar Point/6 */ + :1; + } new; }; union { /* 0x04 */ uint32_t FLILL; /* Flash Invalid Instructions Register */ @@ -555,7 +582,7 @@ struct ich_descriptors { void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc); void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); -void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc); void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); @@ -568,7 +595,7 @@ int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struc #else /* ICH_DESCRIPTORS_FROM_DUMP */ int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); -int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx); +int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx); #endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* __ICH_DESCRIPTORS_H__ */ diff --git a/ichspi.c b/ichspi.c index 90bb0de..6744bef 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1754,10 +1754,9 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) msg_pdbg("\n"); if (desc_valid) { - if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == - ICH_RET_OK) - prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, - &desc); + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) + prettyprint_ich_descriptors(ich_gen, &desc); + /* If the descriptor is valid and indicates multiple * flash devices we need to use hwseq to be able to * access the second flash device. @@ -1783,8 +1782,21 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) "valid. Aborting.\n"); return ERROR_FATAL; } - hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); - hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); + + int tmpi = getFCBA_component_density(ich_generation, &desc, 0); + if (tmpi < 0) { + msg_perr("Could not determine density of flash component %d.\n", 0); + return ERROR_FATAL; + } + hwseq_data.size_comp0 = tmpi; + + tmpi = getFCBA_component_density(ich_generation, &desc, 1); + if (tmpi < 0) { + msg_perr("Could not determine density of flash component %d.\n", 1); + return ERROR_FATAL; + } + hwseq_data.size_comp1 = tmpi; + register_opaque_master(&opaque_master_ich_hwseq); } else { register_spi_master(&spi_master_ich9); diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 00ad1f3..4c1f05c 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -121,6 +121,7 @@ static void usage(char *argv[], char *error) "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -198,6 +199,9 @@ int main(int argc, char *argv[]) else if ((strcmp(csn, "7") == 0) || (strcmp(csn, "panther") == 0)) cs = CHIPSET_7_SERIES_PANTHER_POINT; + else if ((strcmp(csn, "8") == 0) || + (strcmp(csn, "lynx") == 0)) + cs = CHIPSET_8_SERIES_LYNX_POINT; } ret = read_ich_descriptors_from_dump(buf, len, &desc); -- Kind regards, Stefan Tauner

1 0

[PATCH 0/3] Descriptor updates, support for Silvermont and Wildcat Point
by Stefan Tauner 01 Aug '14

01 Aug '14

I have digged a bit further... the second patch still needs a sign-off from Martin (or anybody else at Sage) and all of this should be tested on real hardware. I don't trust this code without it... I have tested most of the descriptor handling by using binary images from various vendors and generations, but the consequences on flashrom execution and the whole Silvermont code flow are untested. Stefan Tauner (3): Refine Flash Component descriptor handling. Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton. Add support for Intel Wildcat Point PCH. chipset_enable.c | 244 ++++++++++++++++++----- ich_descriptors.c | 188 +++++++++++++---- ich_descriptors.h | 39 +++- ichspi.c | 38 ++-- programmer.h | 2 + util/ich_descriptors_tool/ich_descriptors_tool.c | 11 + 6 files changed, 407 insertions(+), 115 deletions(-) -- Kind regards, Stefan Tauner

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