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[PATCH] Board: Add Abit AN-M2.
by Luc Verhaegen 03 Dec '09

03 Dec '09

--- board_enable.c | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 44b1a67..2773473 100644 --- a/board_enable.c +++ b/board_enable.c @@ -434,6 +434,24 @@ static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) } /** + * Suited for the Abit AN-M2: nVidia MCP67. + */ +static int board_abit_an_m2(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x10DE, 0x0542); /* nVidia MCP67 SMBus */ + if (!dev) { + fprintf(stderr, "\nERROR: nVidia MCP67 SMBUS not found.\n"); + return -1; + } + + nvidia_mcp_gpio_raise(dev, 0x02); + + return 0; +} + +/** * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. */ static int board_ga_k8n_sli(const char *name) @@ -1137,6 +1155,7 @@ static int board_asus_a7v600x(const char *name) /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ + {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, "Abit", "AN-M2", board_abit_an_m2}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise}, {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, -- 1.6.0.2 --0F1p//8PRICkK4MW--

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We have a FOSDEM DevRoom!
by Luc Verhaegen 03 Dec '09

03 Dec '09

The kind FOSDEM organizers have given us a DevRoom on saturday the 6th of February, as requested. We got room AW.124, in the AW building on the other side of the campus road from the main building. A "smallish" room at 60 seats, the perfect size for coreboot, and we will have like a window for ventilation and such, which is a nice luxury. Some key european developers are already coming; Carl-Daniel Hailfinger, Peter Stuge and Rudolf Marek, and i hope many more will spend a bit of time and a bit of money (FOSDEM is all free, but travel costs money) on coming to the greatest open source event in europe. We have a total of 6 slots available, two of which should be filled with an "introductory" talk about coreboot and one about flashrom. Introductory here means "this is what $project is, and now we dive straight into the gory details." So there are 4 more which i would like to see filled up in the next month. The page where fosdem info will be kept for coreboot is: http://www.coreboot.org/FOSDEM_2010 Hope to see many of you there! Luc Verhaegen.

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Verbose output of lspci, superiotool and flashrom - AsRock P55 Pro (unsupported)
by Adrian Glaubitz 02 Dec '09

02 Dec '09

Hi, here's the verbose output of lspci, flashrom (r791) and superiotool for the AsRock P55 Pro. The mainboard is not yet supported. root@karl:..src/flashrom> ./flashrom -V > flashrom_p55pro.txt root@karl:..src/flashrom> superiotool -dV > superiotool_p55pro.txt root@karl:..src/flashrom> lspci -nnvvvxxx > lspci_p55pro.txt Adrian

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Mark three boards "known good"
by Idwer Vollering 01 Dec '09

01 Dec '09

See patch. http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html http://www.flashrom.org/pipermail/flashrom/2009-November/000965.html http://www.flashrom.org/pipermail/flashrom/2009-November/001059.html

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[commit] r791 - trunk
by svn＠flashrom.org 01 Dec '09

01 Dec '09

Author: uwe Date: 2009-12-01 13:55:18 +0100 (Tue, 01 Dec 2009) New Revision: 791 Modified: trunk/print.c trunk/print_wiki.c Log: Mark the following boards as OK (no board-enable needed): - AsRock K8S8X (reported by Adrian Glaubitz <adrian.glaubitz(a)gmail.com>) http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html - ASUS K8V-X SE (reported by Adrian Glaubitz <adrian.glaubitz(a)gmail.com>) http://www.flashrom.org/pipermail/flashrom/2009-November/000965.html - DFI Blood-Iron P35 T2RL (reported by Erno Vaurio <ernovaur(a)gmail.com>) http://www.flashrom.org/pipermail/flashrom/2009-November/001059.html Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-11-29 01:19:25 UTC (rev 790) +++ trunk/print.c 2009-12-01 12:55:18 UTC (rev 791) @@ -252,6 +252,7 @@ { "Advantech", "PCM-5820", }, { "ASI", "MB-5BLMP", }, { "ASRock", "A770CrossFire", }, + { "ASRock", "K8S8X", }, { "ASUS", "A7N8X Deluxe", }, { "ASUS", "A7N8X-E Deluxe", }, { "ASUS", "A7V400-MX", }, @@ -265,6 +266,7 @@ { "ASUS", "A8V-E SE", }, { "ASUS", "K8V", }, { "ASUS", "K8V SE Deluxe", }, + { "ASUS", "K8V-X SE", }, { "ASUS", "M2A-MX", }, { "ASUS", "M2A-VM", }, { "ASUS", "M2N-E", }, @@ -281,6 +283,7 @@ { "ASUS", "P6T Deluxe V2", }, { "A-Trend", "ATC-6220", }, { "BCOM", "WinNET100", }, + { "DFI", "Blood-Iron P35 T2RL", }, { "Elitegroup", "K7S5A", }, { "Elitegroup", "P6VAP-A+", }, { "GIGABYTE", "GA-6BXC", }, Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-11-29 01:19:25 UTC (rev 790) +++ trunk/print_wiki.c 2009-12-01 12:55:18 UTC (rev 791) @@ -104,6 +104,7 @@ { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm" }, { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b" }, + { "ASRock", "K8S8X", "http://www.asrock.com/mb/overview.asp?Model=K8S8X" }, { "ASUS", "A7N8X Deluxe", "http://www.asus.com/Product.aspx?P_ID=wAsRYm41KTp78MFC" }, { "ASUS", "A7N8X-E Deluxe", "http://www.asus.com/products.aspx?l1=3&l2=13&l3=56&l4=0&model=217&modelmenu…" }, { "ASUS", "A7V400-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=63&l4=0&model=228&modelm…" }, @@ -117,6 +118,7 @@ { "ASUS", "A8V-E SE", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=576&model…" }, { "ASUS", "K8V", "http://www.asus.com/product.aspx?P_ID=fG2KZOWF7v6MRFRm" }, { "ASUS", "K8V SE Deluxe", "http://www.asus.com/product.aspx?P_ID=65HeDI8XM1u6Uy6o" }, + { "ASUS", "K8V-X SE", "http://asus.com/product.aspx?P_ID=lzDXlbBVHkdckHVr" }, { "ASUS", "M2A-MX", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=583&l4=0&model=1909&modelm…" }, { "ASUS", "M2A-VM", "http://www.asus.com.tw/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&mod…" }, { "ASUS", "M2N-E", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=308&l4=0&model=1181&modelm…" }, @@ -133,6 +135,7 @@ { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100" }, + { "DFI", "Blood-Iron P35 T2RL", "http://lp.lanparty.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWin…" }, { "Elitegroup", "K7S5A", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=279&…" }, { "Elitegroup", "P6VAP-A+", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…" }, { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, @@ -282,6 +285,7 @@ const struct board_info_notes boards_notes[] = { /* Verified working boards that don't need write-enables. */ { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, + { "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." }, { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, { "ASUS", "M2A-VM", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html." }, { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." },

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[PATCH] TotalPhase Cheetah support stub
by Carl-Daniel Hailfinger 30 Nov '09

30 Nov '09

I wrote this Cheetah support stub months ago and carried it forward over various interface changes. I don't have the hardware, so I'm not really motivated to finish this. This patch does: - Hook up Cheetah support in the generic code - Make sure it is disabled by default (zero footprint in the binary) - Provide some #if 0 code as a good starting point - Provide a compilable skeleton to be filled in TODO for anyone who cares about Cheetah support: - Implement cheetah_spi_init - Implement cheetah_spi_shutdown - Add an #include for the cheetah headers - Change #if 0 to #if 1. Given that this patch makes sure to have zero impact on the binary (because it is compiled out by default) and because it lowers the barrier for someone else to come and implement the rest of cheetah support, I'm for merging. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-cheetah/flashrom.8 =================================================================== --- flashrom-cheetah/flashrom.8 (Revision 777) +++ flashrom-cheetah/flashrom.8 (Arbeitskopie) @@ -154,6 +154,8 @@ .sp .BR "* buspiratespi" " (for flash ROMs attached to a Bus Pirate)" .sp +.BR "* cheetah" " (for flash ROMs attached to a TotalPhase Cheetah SPI programmer)" +.sp The dummy programmer has an optional parameter specifying the bus types it should support. For that you have to use the .B "flashrom -p dummy:type" Index: flashrom-cheetah/flash.h =================================================================== --- flashrom-cheetah/flash.h (Revision 777) +++ flashrom-cheetah/flash.h (Arbeitskopie) @@ -107,6 +107,9 @@ #if BUSPIRATE_SPI_SUPPORT == 1 PROGRAMMER_BUSPIRATESPI, #endif +#if CHEETAH_SUPPORT == 1 + PROGRAMMER_CHEETAH, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -497,6 +500,14 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +/* cheetah.c */ +int cheetah_spi_init(void); +int cheetah_spi_shutdown(void); +int cheetah_spi_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +int cheetah_spi_write_256(struct flashchip *flash, uint8_t *buf); +int cheetah_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); + /* flashrom.c */ extern char *programmer_param; extern int verbose; @@ -538,6 +549,9 @@ #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif +#if CHEETAH_SUPPORT == 1 + SPI_CONTROLLER_CHEETAH, +#endif #if DUMMY_SUPPORT == 1 SPI_CONTROLLER_DUMMY, #endif Index: flashrom-cheetah/spi.c =================================================================== --- flashrom-cheetah/spi.c (Revision 777) +++ flashrom-cheetah/spi.c (Arbeitskopie) @@ -91,6 +91,15 @@ }, #endif +#if CHEETAH_SUPPORT == 1 + { /* SPI_CONTROLLER_CHEETAH */ + .command = cheetah_spi_command, + .multicommand = default_spi_send_multicommand, + .read = cheetah_spi_read, + .write_256 = spi_chip_write_1, + }, +#endif + #if DUMMY_SUPPORT == 1 { /* SPI_CONTROLLER_DUMMY */ .command = dummy_spi_send_command, @@ -316,6 +325,9 @@ #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif +#if CHEETAH_SUPPORT == 1 + case SPI_CONTROLLER_CHEETAH: +#endif #if DUMMY_SUPPORT == 1 case SPI_CONTROLLER_DUMMY: #endif Index: flashrom-cheetah/Makefile =================================================================== --- flashrom-cheetah/Makefile (Revision 777) +++ flashrom-cheetah/Makefile (Arbeitskopie) @@ -71,6 +71,9 @@ # Bitbanging SPI infrastructure is not used yet. CONFIG_BITBANG_SPI ?= no +# Cheetah support is unfinished. +CONFIG_CHEETAH ?= no + # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes @@ -108,6 +111,11 @@ OBJS += bitbang_spi.o endif +ifeq ($(CONFIG_CHEETAH), yes) +FEATURE_CFLAGS += -D'CHEETAH_SUPPORT=1' +OBJS += cheetah.o +endif + ifeq ($(CONFIG_NIC3COM), yes) FEATURE_CFLAGS += -D'NIC3COM_SUPPORT=1' OBJS += nic3com.o Index: flashrom-cheetah/cheetah.c =================================================================== --- flashrom-cheetah/cheetah.c (Revision 0) +++ flashrom-cheetah/cheetah.c (Revision 0) @@ -0,0 +1,72 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * As a special exception, you may also incorporate this code into programs + * licensed under later versions of the GNU GPL provided your changes to + * this code are made available under the same conditions as the original code. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <stdlib.h> +#include "flash.h" + +int cheetah_spi_init(void) +{ + printf("Cheetah support not yet implemented completely.\n"); + buses_supported = CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_CHEETAH; + return 0; +} + +int cheetah_spi_shutdown(void) +{ + return 0; +} + +int cheetah_spi_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + unsigned char *bufout = malloc(writecnt + readcnt); + unsigned char *bufin = malloc(writecnt + readcnt); + memcpy(bufout, writearr, writecnt); + /* Shift out 0x00 while reading data. */ + memset(bufout + writecnt, 0x00, readcnt); + /* Make sure any non-read data is 0xff. */ + memset(bufin + writecnt, 0xff, readcnt); +#if 0 + ch_spi_queue_clear(handle); + ch_spi_queue_oe(handle, 1); + ch_spi_queue_ss(handle, 1); + ch_spi_queue_array(handle, writecnt + readcnt, bufout); + ch_spi_queue_ss(handle, 0); + ch_spi_queue_oe(handle, 0); + ch_spi_batch_shift(handle, writecnt + readcnt, bufin); + ch_spi_queue_clear(handle); +#endif + memcpy(readarr, bufin + writecnt, readcnt); + free(bufout); + free(bufin); + return 0; +} + +int cheetah_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* Maximum read length is 256 bytes. */ + return spi_read_chunked(flash, buf, start, len, 256); +} + +/* We could do 256-byte writes, but for now we use the generic 1-byte code. */ Index: flashrom-cheetah/flashrom.c =================================================================== --- flashrom-cheetah/flashrom.c (Revision 777) +++ flashrom-cheetah/flashrom.c (Arbeitskopie) @@ -223,6 +223,25 @@ }, #endif +#if CHEETAH_SUPPORT == 1 + { + .name = "cheetah", + .init = cheetah_spi_init, + .shutdown = cheetah_spi_shutdown, + .map_flash_region = dummy_map, + .unmap_flash_region = dummy_unmap, + .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

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SST SST49LF160C not working
by Kevin O'Connor 29 Nov '09

29 Nov '09

Hi, I have an "SST SST49LF160C" part that I've tried to use in my epia-cn board (Jetway). Reading seems to work okay, but erase and write fail. My other parts (winbond based bios savior, a winbond chip, and an "SST SST49LF080A") all work okay in the board. Attached are some logs. These were taken over ssh and without the bios savior installed. I tried writing and erasing on the console and see the same failure. On IRC, Uwe mentioned there may be a problem with the southbridge only mapping 1MB. Also, with Uwe's advise, I tried writing a variety of images (eg, all 0xff, all 0x00, etc.) but no luck. -Kevin

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[commit] r790 - trunk
by svn＠flashrom.org 29 Nov '09

29 Nov '09

Author: libv Date: 2009-11-29 02:19:25 +0100 (Sun, 29 Nov 2009) New Revision: 790 Modified: trunk/board_enable.c Log: Board enable for Shuttle AK31. All AK31 versions, 1.x, 2.x and 3.x are supported by this board enable. Sadly this board can not be autodetected. Re-uses the epox ep 8k5a2 board enable, which now lost its check for the VT8235 ISA bridge and got renamed to w836xx_memw_enable_2e. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Mateusz Murawski <matowy(a)tlen.pl> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-11-28 21:12:58 UTC (rev 789) +++ trunk/board_enable.c 2009-11-29 01:19:25 UTC (rev 790) @@ -297,18 +297,13 @@ } /** - * Suited for EPoX EP-8K5A2 and Albatron PM266A Pro. + * Suited for: + * - EPoX EP-8K5A2: VIA KT333 + VT8235. + * - Albatron PM266A Pro: VIA P4M266A + VT8235. + * - Shuttle AK31 (all versions): VIA KT266 + VT8233. */ -static int board_epox_ep_8k5a2(const char *name) +static int w836xx_memw_enable_2e(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n"); - return -1; - } - w836xx_memw_enable(0x2E); return 0; @@ -1146,7 +1141,7 @@ {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, @@ -1161,7 +1156,7 @@ {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, - {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, + {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, @@ -1186,6 +1181,7 @@ {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, + {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca},

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non-working board report for Asrock K7S41GX with flashrom r711
by Putlinuxonit 28 Nov '09

28 Nov '09

Hi, Just want to report a non-working board - the Asrock K7S41GX, tested with flashrom r711 and superiotool r4623. first some brief details ... Board: Asrock K7S1GX Bios Vendor: AMI Bios Version: P1.90 root@ubuntu:~# lspci 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 741/741GX/M741 Host (rev 03) 00:01.0 PCI bridge: Silicon Integrated Systems [SiS] SiS AGP Port (virtual PCI-to-PCI bridge) 00:02.0 ISA bridge: Silicon Integrated Systems [SiS] SiS963 [MuTIOL Media IO] (rev 25) 00:02.1 SMBus: Silicon Integrated Systems [SiS] SiS961/2 SMBus Controller 00:02.5 IDE interface: Silicon Integrated Systems [SiS] 5513 [IDE] 00:02.7 Multimedia audio controller: Silicon Integrated Systems [SiS] AC'97 Sound Controller (rev a0) 00:03.0 USB Controller: Silicon Integrated Systems [SiS] USB 1.1 Controller (rev 0f) 00:03.1 USB Controller: Silicon Integrated Systems [SiS] USB 1.1 Controller (rev 0f) 00:03.2 USB Controller: Silicon Integrated Systems [SiS] USB 2.0 Controller 00:04.0 Ethernet controller: Silicon Integrated Systems [SiS] SiS900 PCI Fast Ethernet (rev 90) 01:00.0 VGA compatible controller: Silicon Integrated Systems [SiS] 661/741/760 PCI/AGP or 662/761Gx PCIE VGA Display Adapter flashrom v0.9.1-r711 No coreboot table found. This chipset supports the following protocols: Non-SPI. WARNING: No chipset found. Flash detection will most likely fail. Calibrating delay loop... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. root@ubuntu:~# ./superiotool/superiotool superiotool r4623 Found Winbond W83697HF/F/HG (id=0x60, rev=0x12) at 0x2e Cheers, -- Udu Ogah .~~~~~~~~~~.

3 6

[Patch] Boards: Fix up MSI KT4V.
by Luc Verhaegen 28 Nov '09

28 Nov '09

Luc Verhaegen.

2 2

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