flashrom

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9189 discussions

Re: [flashrom] [PATCH] MCP67 SPI detection/debugging
by Carl-Daniel Hailfinger 04 Dec '09

04 Dec '09

Hi Alex, On 04.12.2009 13:51, Alessandro Polverini wrote: > may I use a standard flashrom (0.9.1) to capture the output or you > need latest one with this patch applied? I think you need latest flashrom for this to work. If this is indeed a machine which you can't power off because it acts as a server, tests with this patch are still useful in theory, but the results might be garbage. Not sure yet. I can't make any guarantees, but the patch should be safe to test (unless the GPIO read has side effects, but that is unlikely). Regards, Carl-Daniel > Carl-Daniel Hailfinger wrote: >> First attempt at shedding some light on the MCP67 SPI situation. >> Huge thanks to Michael Karcher for reverse engineering the chipset and >> writing a spec. Due to this, we were able to use the chinese wall >> technique for 100% clean room reverse engineering. >> >> This patch doesn't touch any of the new registers, it only reads them. >> Assuming that read has no side effects, this patch is a no-op and safe. >> >> We need "flashrom -V" output from MCP67 boards with SPI flash and from >> boards with LPC flash. Note: That output is only helpful if it is >> created with patched flashrom and if is from the first run of flashrom >> after a cold boot (reset or Ctrl-Alt-Del is not sufficient). I hope to >> see a pattern based on which we can detect which flash type is present >> on the board. >> >> Alex, we need this output (as described above) from your Asus M2N68-VM >> board. >> >> I'd like to merge this ASAP and then ping everyone who had this chipset >> to get flashrom -V output. >> >> Signed-off-by: Carl-Daniel Hailfinger >> <c-d.hailfinger.devel.2006(a)gmx.net> -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

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Re: [flashrom] Unable to flash bios on a Asus M2N68-VM
by Carl-Daniel Hailfinger 04 Dec '09

04 Dec '09

Hi Alex, I found a few high-resolution photos for the M2N68-VM. It is the 8-pin chip in a socket with a yellow dot in the middle of the lower edge of the board here: http://img24.imageshack.us/img24/7444/m2n68vmfull2.jpg It is the 8-pin chip in a socket with a blue dot in the lower left corner of the image here: http://img524.imageshack.us/img524/9926/img1447r.jpg Probably a MX 25L8005 chip if the photos are any indication. Regards, Carl-Daniel On 04.12.2009 09:05, Alessandro Polverini wrote: > powering off my server is not very practical at the moment, I've a lot > of tasks running on it. > I could try to see inside it without powering it off, but I need some > hint on where to look. > I found this picture of the mainboard: > http://www.asus.com/websites/Global/products/TtvnYkYtXtRgFXG3/TtjG7ja5aSlRe… > > maybe you are to understand which chip it may be? -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

1 0

acer extensa
by Charlie Watson 03 Dec '09

03 Dec '09

I was updating my Acer Extensa 5630z with the latest update vs 1.36 and webshots desktop interupted the update. Acer's winflash only works in Windows and restarted the computer automatically (wouldnt even let me cancel). I cannot boot to windows anymore. cant even boot to my miniPE rescue disk. luckily i can at least boot to ubuntu but im not that good with linux. Could someone make a zip file that i could extract to my usb memory and try to flash it back? http://gd.panam.acer.com/home/ i want to try and put 1.30 back on it. i tried using wine but that didnt work. _________________________________________________________________ Chat with Messenger straight from your Hotmail inbox. http://www.microsoft.com/windows/windowslive/hotmail_bl1/hotmail_bl1.aspx?o…

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[Patch] Boards: Add general nVidia MCP gpio routine.
by Luc Verhaegen 03 Dec '09

03 Dec '09

2 2

[commit] r792 - trunk
by svn＠flashrom.org 03 Dec '09

03 Dec '09

Author: libv Date: 2009-12-03 13:25:34 +0100 (Thu, 03 Dec 2009) New Revision: 792 Modified: trunk/board_enable.c Log: Boards: Add general nVidia MCP gpio routine. Turns out that the AMD 8111 datasheet describes this bit of the MCP perfectly. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-01 12:55:18 UTC (rev 791) +++ trunk/board_enable.c 2009-12-03 12:25:34 UTC (rev 792) @@ -415,76 +415,65 @@ } /** - * No docs, so we are just guessing that these might be individual gpio lines. + * Very similar to AMD 8111 IO Hub. */ -static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) +static int nvidia_mcp_gpio_set(int gpio, int raise) { + struct pci_dev *dev; uint16_t base; uint8_t tmp; - base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + if ((gpio < 0) || (gpio > 31)) { + fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); + return -1; + } - base += 0xC0; - - /* if anyone knows more about nvidia mcps, feel free to explain this */ - tmp = INB(base + offset); - tmp &= ~0x0F; - tmp |= 0x05; - OUTB(tmp, base + offset); -} - -/** - * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. - */ -static int board_ga_k8n_sli(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA LPC bridge not found.\n"); + dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + switch (dev->device_id) { + case 0x0030: /* CK804 */ + case 0x0050: /* MCP04 */ + case 0x0060: /* MCP2 */ + break; + default: + fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n"); return -1; } - nvidia_mcp_gpio_raise(dev, 0x21); + base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + base += 0xC0; + tmp = INB(base + gpio); + tmp &= ~0x0F; /* null lower nibble */ + tmp |= 0x04; /* gpio -> output. */ + if (raise) + tmp |= 0x01; + OUTB(tmp, base + gpio); + return 0; } /** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ -static int board_asus_p5nd2_sli(const char *name) +static int nvidia_mcp_gpio10_raise(const char *name) { - struct pci_dev *dev; + return nvidia_mcp_gpio_set(0x10, 1); +} - dev = pci_dev_find(0x10DE, 0x0030); /* NVIDIA nForce4 ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n"); - return -1; - } - - nvidia_mcp_gpio_raise(dev, 0x10); - - return 0; +/** + * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. + */ +static int nvidia_mcp_gpio21_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x21, 0x01); } /** * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2. */ -static int board_epox_ep_8rda3plus(const char *name) +static int nvidia_mcp_gpio31_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x10DE, 0x0060); /* NVIDIA nForce2 ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n"); - return -1; - } - - nvidia_mcp_gpio_raise(dev, 0x31); - - return 0; + return nvidia_mcp_gpio_set(0x31, 0x01); } static int board_hp_dl145_g3_enable(const char *name) @@ -1152,16 +1141,16 @@ {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, - {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, + {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e}, - {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, + {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable}, - {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", board_ga_k8n_sli}, + {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", nvidia_mcp_gpio21_raise}, {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash},

1 0

[PATCH] Boards: Add general nVidia MCP gpio routine.
by Luc Verhaegen 03 Dec '09

03 Dec '09

Turns out that the AMD 8111 datasheet describes this bit of the MCP perfectly. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 87 ++++++++++++++++++++++++------------------------------- 1 files changed, 38 insertions(+), 49 deletions(-) diff --git a/board_enable.c b/board_enable.c index 44b1a67..96d764f 100644 --- a/board_enable.c +++ b/board_enable.c @@ -415,38 +415,39 @@ static int board_shuttle_fn25(const char *name) } /** - * No docs, so we are just guessing that these might be individual gpio lines. + * Very similar to AMD 8111 IO Hub. */ -static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) +static int nvidia_mcp_gpio_set(int gpio, int raise) { + struct pci_dev *dev; uint16_t base; uint8_t tmp; - base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ - - base += 0xC0; - - /* if anyone knows more about nvidia mcps, feel free to explain this */ - tmp = INB(base + offset); - tmp &= ~0x0F; - tmp |= 0x05; - OUTB(tmp, base + offset); -} - -/** - * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. - */ -static int board_ga_k8n_sli(const char *name) -{ - struct pci_dev *dev; + if ((gpio < 0) || (gpio > 31)) { + fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); + return -1; + } - dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA LPC bridge not found.\n"); + dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + switch (dev->device_id) { + case 0x0030: /* CK804 */ + case 0x0050: /* MCP04 */ + case 0x0060: /* MCP2 */ + break; + default: + fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n"); return -1; } - nvidia_mcp_gpio_raise(dev, 0x21); + base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + base += 0xC0; + + tmp = INB(base + gpio); + tmp &= ~0x0F; /* null lower nibble */ + tmp |= 0x04; /* gpio -> output. */ + if (raise) + tmp |= 0x01; + OUTB(tmp, base + gpio); return 0; } @@ -454,37 +455,25 @@ static int board_ga_k8n_sli(const char *name) /** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ -static int board_asus_p5nd2_sli(const char *name) +static int nvidia_mcp_gpio10_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x10DE, 0x0030); /* NVIDIA nForce4 ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n"); - return -1; - } - - nvidia_mcp_gpio_raise(dev, 0x10); + return nvidia_mcp_gpio_set(0x10, 1); +} - return 0; +/** + * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. + */ +static int nvidia_mcp_gpio21_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x21, 0x01); } /** * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2. */ -static int board_epox_ep_8rda3plus(const char *name) +static int nvidia_mcp_gpio31_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x10DE, 0x0060); /* NVIDIA nForce2 ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n"); - return -1; - } - - nvidia_mcp_gpio_raise(dev, 0x31); - - return 0; + return nvidia_mcp_gpio_set(0x31, 0x01); } static int board_hp_dl145_g3_enable(const char *name) @@ -1152,16 +1141,16 @@ struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, - {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, + {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e}, - {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, + {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable}, - {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", board_ga_k8n_sli}, + {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", nvidia_mcp_gpio21_raise}, {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash}, -- 1.6.0.2 --CE+1k2dSO48ffgeK--

1 0

[PATCH] Board: Add Tyan S2915.
by Luc Verhaegen 03 Dec '09

03 Dec '09

Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 44b1a67..5d8ac92 100644 --- a/board_enable.c +++ b/board_enable.c @@ -434,6 +434,24 @@ static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) } /** + * Suited for the Tyan S2915: nVidia MCP55. + */ +static int board_tyan_s2915(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x10DE, 0x0368); /* NVIDIA MCP55 SMBus */ + if (!dev) { + fprintf(stderr, "\nERROR: nVidia MCP55 SMBus not found.\n"); + return -1; + } + + nvidia_mcp_gpio_raise(dev, 0x04); + + return 0; +} + +/** * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. */ static int board_ga_k8n_sli(const char *name) @@ -1186,6 +1204,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, + {0x10DE, 0x0369, 0x10F1, 0x2915, 0x10DE, 0x0364, 0x10F1, 0x2915, NULL, NULL, "Tyan", "S2915", board_tyan_s2915}, {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, "via", "epia-n", "VIA", "EPIA-N/NL", board_via_epia_n}, /* TODO: remove coreboot ids */ -- 1.6.0.2 --gKMricLos+KVdGMg--

1 0

Is K7S6A supported by flashrom?
by spirals 03 Dec '09

03 Dec '09

Hi, Ran flashrom and it reports "No EEPROM/flash device found", same with -m ecs:k7s5a. Any suggestions how I can test further. I am running Lenny and my cpu [an AMD 2600] is being mis-reported as 1406? regards, Dave (dja.)

4 6

Re: [flashrom] [coreboot] We have a FOSDEM DevRoom!
by Luc Verhaegen 03 Dec '09

03 Dec '09

On Wed, Dec 02, 2009 at 11:09:04PM +0000, joe(a)settoplinux.org wrote: > > According to the wiki it looks like you want to get into bios security a bit. > This may be an opritune time to introduce SerialICE??? If we can get Stepan to talk about it on FOSDEM, sure :) Luc Verhaegen.

1 0

Unsupportet motherboard Shuttle FS51
by Emil Oehlschläger 03 Dec '09

03 Dec '09

Hi, carldani asked me to send this Mail - so i did. Both files attached to this mail explain themselfs i think and here is link to the motherboard: http://eu.shuttle.com/archive/en/fs51.htm#mainboardfs5 Thanks and good luck, Emil

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