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Re: [flashrom] [PATCH 3/8] ichspi: don't touch the nonexistent(?) BBAR register on ICH8
by Carl-Daniel Hailfinger 18 Sep '11

18 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > There is no sign of BBAR (BIOS Base Address Configuration Register) > in the public datasheet (or specification update) of the ICH8. Also, > the offset of that register has changed between ICH7 (SPIBAR + 50h) > and ICH9 (SPIBAR + A0h), so we have no clue if or where it is on > ICH8. Better don't try to touch it at all and assume/hope it is 0. Just a short comment about this: Can we create a TODO.txt or UNKNOWN.txt file in the flashrom source which lists all such questions and similar assumptions? That way we know which questions we can ask Intel if one of their engineers talks to us. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 7/8] ichspi: unlock PR register restrictions if not locked down
by Carl-Daniel Hailfinger 18 Sep '11

18 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> with comments. > diff --git a/ichspi.c b/ichspi.c > index c38fbfc..a9327de 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -1507,6 +1507,24 @@ static void prettyprint_ich9_reg_pr(int i) > msg_pdbg(", unused)\n"); > } > > +/* Set the read and write protection enable bits of PR register @i according to Change "Set" to "Set/clear". > + * @read_prot and @write_prot. */ > +static void ich8_set_pr(int i, int read_prot, int write_prot) > +{ > + void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4); > + uint32_t pr = mmio_readl(addr); > + > + msg_gspew("PR%u is 0x%08x, ", i, pr); > + pr &= ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF)); > + if (read_prot) > + pr |= (1 << PR_RP_OFF); > + if (write_prot) > + pr |= (1 << PR_WP_OFF); Having some logic which eliminated unnecessary changes of pr would be nice. You could even print "unchanged\n" for that case. > + msg_gspew("trying to set it to 0x%08x ", pr); > + mmio_writel(pr, addr); Really not rmmio_writel? We want to undo all non-permanent config changes on shutdown. > + msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); > +} > + > static const struct spi_programmer spi_programmer_ich7 = { > .type = SPI_CONTROLLER_ICH7, > .max_data_read = 64, > @@ -1648,6 +1666,10 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > for(i = 0; i < 5; i++) > do_ich9_spi_frap(tmp, i); > > + /* try to disable PR locks before printing them */ > + if (!ichspi_lock) > + for(i = 0; i < 5; i++) > + ich8_set_pr(i, 0, 0); ich8_ is an unusual prefix. Most other names use either ich7_ or ich9_ prefixes even if the functionality is present in ICH8. > for(i = 0; i < 5; i++) > prettyprint_ich9_reg_pr(i); > -- http://www.hailfinger.org/

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[commit] r1447 - trunk
by repository service 18 Sep '11

18 Sep '11

Author: stefanct Date: Sun Sep 18 00:21:55 2011 New Revision: 1447 URL: http://flashrom.org/trac/flashrom/changeset/1447 Log: ichspi: unlock PR register restrictions on ICH8+ if not locked down Tested-by: Shailendra Sodhi (predecessor/proof of concept patch) http://www.flashrom.org/pipermail/flashrom/2011-August/007717.html Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Sep 17 23:21:48 2011 (r1446) +++ trunk/ichspi.c Sun Sep 18 00:21:55 2011 (r1447) @@ -1200,6 +1200,29 @@ msg_pdbg2(", unused)\n"); } +/* Set/Clear the read and write protection enable bits of PR register @i + * according to @read_prot and @write_prot. */ +static void ich9_set_pr(int i, int read_prot, int write_prot) +{ + void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4); + uint32_t old = mmio_readl(addr); + uint32_t new; + + msg_gspew("PR%u is 0x%08x", i, old); + new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF)); + if (read_prot) + new |= (1 << PR_RP_OFF); + if (write_prot) + new |= (1 << PR_WP_OFF); + if (old == new) { + msg_gspew(" already.\n"); + return; + } + msg_gspew(", trying to set it to 0x%08x ", new); + rmmio_writel(new, addr); + msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); +} + static const struct spi_programmer spi_programmer_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, @@ -1320,6 +1343,10 @@ for(i = 0; i < 5; i++) do_ich9_spi_frap(tmp, i); + /* try to disable PR locks before printing them */ + if (!ichspi_lock) + for(i = 0; i < 5; i++) + ich9_set_pr(i, 0, 0); for(i = 0; i < 5; i++) prettyprint_ich9_reg_pr(i);

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Re: [flashrom] [PATCH 6/8] ichspi: add prettyprinting for PR registers
by Carl-Daniel Hailfinger 17 Sep '11

17 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> with comments. > --- > ichspi.c | 45 +++++++++++++++++++++++++++++++-------------- > 1 files changed, 31 insertions(+), 14 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index 61c0825..c38fbfc 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -73,10 +73,8 @@ > #define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */ > > #define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */ > -#define ICH9_REG_PR1 0x78 /* 32 Bytes Protected Range 1 */ > -#define ICH9_REG_PR2 0x7c /* 32 Bytes Protected Range 2 */ > -#define ICH9_REG_PR3 0x80 /* 32 Bytes Protected Range 3 */ > -#define ICH9_REG_PR4 0x84 /* 32 Bytes Protected Range 4 */ > +#define PR_WP_OFF 31 /* 31: write protection enable */ > +#define PR_RP_OFF 15 /* 15: read protection enable */ > > #define ICH9_REG_SSFS 0x90 /* 08 Bits */ > #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ > @@ -1482,6 +1480,33 @@ static void do_ich9_spi_frap(uint32_t frap, int i) > > } > > + /* In contrast to FRAP and the master section of the descriptor the bits > + * in the PR registers have an inverted meaning. The bits in FRAP > + * indicate read and write access _grant_. Here they indicate read > + * and write _protection_ respectively. If both bits are 0 the address > + * bits are ignored. > + */ > +#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \ > + ((~((pr) >> PR_WP_OFF) & 1) << 1)) > + > +static void prettyprint_ich9_reg_pr(int i) > +{ > + static const char *const access_names[4] = { > + "locked", "read-only", "write-only", "read-write" > + }; > + uint8_t off = ICH9_REG_PR0 + (i * 4); > + uint32_t pr = mmio_readl(ich_spibar + off); > + int rwperms = ICH_PR_PERMS(pr); > + > + msg_pdbg("0x%02X: 0x%08x (PR%u", off, pr, i); > + if (rwperms != 0x3) > + msg_pdbg(")\n0x%08x-0x%08x is %s\n", (ICH_FREG_BASE(pr) << 12), > + (ICH_FREG_LIMIT(pr) << 12) | 0x0fff, > + access_names[rwperms]); > + else > + msg_pdbg(", unused)\n"); dbg2 IMHO. And why do you need two lines of output per PR register? > +} > + > static const struct spi_programmer spi_programmer_ich7 = { > .type = SPI_CONTROLLER_ICH7, > .max_data_read = 64, > @@ -1623,16 +1648,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > for(i = 0; i < 5; i++) > do_ich9_spi_frap(tmp, i); > > - msg_pdbg("0x74: 0x%08x (PR0)\n", > - mmio_readl(ich_spibar + ICH9_REG_PR0)); > - msg_pdbg("0x78: 0x%08x (PR1)\n", > - mmio_readl(ich_spibar + ICH9_REG_PR1)); > - msg_pdbg("0x7C: 0x%08x (PR2)\n", > - mmio_readl(ich_spibar + ICH9_REG_PR2)); > - msg_pdbg("0x80: 0x%08x (PR3)\n", > - mmio_readl(ich_spibar + ICH9_REG_PR3)); > - msg_pdbg("0x84: 0x%08x (PR4)\n", > - mmio_readl(ich_spibar + ICH9_REG_PR4)); > + for(i = 0; i < 5; i++) > + prettyprint_ich9_reg_pr(i); IIRC some chipset generations only support PR0-PR3. Besides that, it would be nice to have those prettyprinters for ICH7 as well if possible/applicable. > > tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); > msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 3/8] ichspi: don't touch the nonexistent(?) BBAR register on ICH8
by Carl-Daniel Hailfinger 17 Sep '11

17 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > Until now we implicitly accessed it via the ICH9 offset. I think > this is an evident sign that the naming of the spi controller types > in ichspi.c (SPI_CONTROLLER_VIA, SPI_CONTROLLER_ICH7, > SPI_CONTROLLER_ICH9) might not cut it and we should think about > introducing a special ICH8 one, even if its struct is identical to > the ICH9. having most of the ICH8 code path guarded/controlled by > SPI_CONTROLLER_ICH7 or SPI_CONTROLLER_ICH9 (depending on which is > more similar in one situation), is an open invitation to similar > bugs because one easily forgets that ICH8 is very special. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> with comments. > diff --git a/ichspi.c b/ichspi.c > index 343a0af..d51a6b2 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -558,20 +558,19 @@ static int program_opcodes(OPCODES *op, int enable_undo) > * Try to set BBAR (BIOS Base Address Register), but read back the value in case > * it didn't stick. > */ > -static void ich_set_bbar(uint32_t min_addr) > +static void ich_set_bbar(int ich_generation, uint32_t min_addr) > { > int bbar_off; > - switch (spi_programmer->type) { > - case SPI_CONTROLLER_ICH7: > - case SPI_CONTROLLER_VIA: > + switch (ich_generation) { > + case 7: > bbar_off = 0x50; Would be nice to have a #define for that. > break; > - case SPI_CONTROLLER_ICH9: > + case 8: > + msg_perr("BBAR offset is unknown on ICH8!\n"); > + return; > + default: /* Future version might behave the same */ > bbar_off = ICH9_REG_BBAR; > break; > - default: > - msg_perr("Unknown chipset for BBAR setting!\n"); > - return; > } > > ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK; > @@ -589,6 +588,8 @@ static void ich_set_bbar(uint32_t min_addr) > */ > if (ichspi_bbar != min_addr) > msg_perr("Setting BBAR failed!\n"); > + else > + msg_pspew("Setting BBAR succeeded!\n"); Do we really need that message? It should be implicit from the absence of "...failed", and msg_pspew is used almost never nowadays, so it mostly bloats the binary without real benefit. > } > > /* Read len bytes from the fdata/spid register into the data array. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1446 - trunk
by repository service 17 Sep '11

17 Sep '11

Author: stefanct Date: Sat Sep 17 23:21:48 2011 New Revision: 1446 URL: http://flashrom.org/trac/flashrom/changeset/1446 Log: ichspi: add prettyprinting for PR registers on ICH8+ Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Sep 17 23:21:42 2011 (r1445) +++ trunk/ichspi.c Sat Sep 17 23:21:48 2011 (r1446) @@ -70,10 +70,8 @@ #define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */ #define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */ -#define ICH9_REG_PR1 0x78 /* 32 Bytes Protected Range 1 */ -#define ICH9_REG_PR2 0x7c /* 32 Bytes Protected Range 2 */ -#define ICH9_REG_PR3 0x80 /* 32 Bytes Protected Range 3 */ -#define ICH9_REG_PR4 0x84 /* 32 Bytes Protected Range 4 */ +#define PR_WP_OFF 31 /* 31: write protection enable */ +#define PR_RP_OFF 15 /* 15: read protection enable */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ @@ -1176,6 +1174,32 @@ access_names[rwperms]); } + /* In contrast to FRAP and the master section of the descriptor the bits + * in the PR registers have an inverted meaning. The bits in FRAP + * indicate read and write access _grant_. Here they indicate read + * and write _protection_ respectively. If both bits are 0 the address + * bits are ignored. + */ +#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \ + ((~((pr) >> PR_WP_OFF) & 1) << 1)) + +static void prettyprint_ich9_reg_pr(int i) +{ + static const char *const access_names[4] = { + "locked", "read-only", "write-only", "read-write" + }; + uint8_t off = ICH9_REG_PR0 + (i * 4); + uint32_t pr = mmio_readl(ich_spibar + off); + int rwperms = ICH_PR_PERMS(pr); + + msg_pdbg2("0x%02X: 0x%08x (PR%u", off, pr, i); + if (rwperms != 0x3) + msg_pdbg2(")\n0x%08x-0x%08x is %s\n", ICH_FREG_BASE(pr), + ICH_FREG_LIMIT(pr) | 0x0fff, access_names[rwperms]); + else + msg_pdbg2(", unused)\n"); +} + static const struct spi_programmer spi_programmer_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, @@ -1296,16 +1320,8 @@ for(i = 0; i < 5; i++) do_ich9_spi_frap(tmp, i); - msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(ich_spibar + ICH9_REG_PR0)); - msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(ich_spibar + ICH9_REG_PR1)); - msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(ich_spibar + ICH9_REG_PR2)); - msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(ich_spibar + ICH9_REG_PR3)); - msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(ich_spibar + ICH9_REG_PR4)); + for(i = 0; i < 5; i++) + prettyprint_ich9_reg_pr(i); tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff);

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[commit] r1445 - trunk
by repository service 17 Sep '11

17 Sep '11

Author: stefanct Date: Sat Sep 17 23:21:42 2011 New Revision: 1445 URL: http://flashrom.org/trac/flashrom/changeset/1445 Log: ichspi: don't touch the nonexistent(?) BBAR register on ICH8 There is no sign of BBAR (BIOS Base Address Configuration Register) in the public datasheet (or specification update) of the ICH8. Also, the offset of that register has changed between ICH7 (SPIBAR + 50h) and ICH9 (SPIBAR + A0h), so we have no clue if or where it is on ICH8. Better don't try to touch it at all and assume/hope it is 0. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Sep 17 21:53:11 2011 (r1444) +++ trunk/ichspi.c Sat Sep 17 23:21:42 2011 (r1445) @@ -570,20 +570,19 @@ * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -static void ich_set_bbar(uint32_t min_addr) +static void ich_set_bbar(int ich_generation, uint32_t min_addr) { int bbar_off; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case 7: bbar_off = 0x50; break; - case SPI_CONTROLLER_ICH9: + case 8: + msg_perr("BBAR offset is unknown on ICH8!\n"); + return; + default: /* Future version might behave the same */ bbar_off = ICH9_REG_BBAR; break; - default: - msg_perr("Unknown chipset for BBAR setting!\n"); - return; } ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK; @@ -600,7 +599,8 @@ * failed, the restore will fail as well, so no problem there. */ if (ichspi_bbar != min_addr) - msg_perr("Setting BBAR failed!\n"); + msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n", + min_addr, ichspi_bbar); } /* Read len bytes from the fdata/spid register into the data array. @@ -669,11 +669,6 @@ msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done, 1); - /* Technically not part of opcode init, but it allows opcodes - * to run without transaction errors by setting the lowest - * allowed address to zero. - */ - ich_set_bbar(0); } if (rc) { @@ -1270,6 +1265,7 @@ msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + ich_set_bbar(ich_generation, 0); ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: @@ -1351,6 +1347,7 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + ich_set_bbar(ich_generation, 0); } msg_pdbg("\n"); @@ -1439,6 +1436,7 @@ ichspi_lock = 1; } + ich_set_bbar(7, 0); ich_init_opcodes(); return 0;

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Re: [flashrom] [PATCH 4/8] ichspi: improve prettyprint_opcodes
by Carl-Daniel Hailfinger 17 Sep '11

17 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > add headers for the columns and some decoding into human readable format. > > --- > before: > […] > Reading OPCODES... done > preop0=0x06, preop1=0x50 > op[0]=0x02, 3, 0 > op[1]=0x03, 2, 0 > op[2]=0x20, 3, 0 > op[3]=0x05, 0, 0 > op[4]=0x9f, 0, 1 > op[5]=0x20, 1, 2 > op[6]=0x01, 1, 0 > op[7]=0x06, 0, 0 > > SPI Read Configuration: prefetching disabled, caching enabled, OK. > This chipset supports the following protocols: FWH, SPI. > […] > > after: > […] > Reading OPCODES... done > OP Type Pre-OP > op[0]: 0x02, write w/ addr, none > op[1]: 0x03, read w/ addr, none > op[2]: 0x20, write w/ addr, none > op[3]: 0x05, read w/o addr, none > op[4]: 0x9f, read w/o addr, none > op[5]: 0x20, write w/o addr, 1 > op[6]: 0x01, write w/o addr, 2 > op[7]: 0x06, read w/o addr, none > Pre-OP 0: 0x06, Pre-OP 1: 0x50 > > SPI Read Configuration: prefetching disabled, caching enabled, OK. Can you kill the empty line above? Besides that, the whole stuff should be dbg2 instead of dbg. My hope is to have a usable progress printing (which is done with dbg) without flooding the user with useless (for him) messages before. > This chipset supports the following protocols: FWH, SPI. > […] > > i could also print the preops directly in the preop column instead of > using that redirection. but i think as debug output it is better to > know the index of the two preops too. > > side note: does it make sense to create an opcode -> string decoder > for flashrom-wide usage in user output (in spi25.c)? > an erase opcode -> function pointer decoder is used in sfdp, that could > also be generalized like that. Yes, that may make sense. How do you handle conflicting definitions for opcodes? That's my biggest worry with such a decoder. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> with the comments above. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1444 - trunk
by repository service 17 Sep '11

17 Sep '11

Author: stefanct Date: Sat Sep 17 21:53:11 2011 New Revision: 1444 URL: http://flashrom.org/trac/flashrom/changeset/1444 Log: ichspi: improve prettyprint_opcodes add headers for the columns and some decoding into human readable format. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Sep 16 01:52:55 2011 (r1443) +++ trunk/ichspi.c Sat Sep 17 21:53:11 2011 (r1444) @@ -294,22 +294,34 @@ /* pretty printing functions */ static void prettyprint_opcodes(OPCODES *ops) { - if(ops == NULL) - return; - - msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], - ops->preop[1]); - OPCODE oc; + const char *t; + const char *a; uint8_t i; + static const char *const spi_type[4] = { + "read w/o addr", + "write w/o addr", + "read w/ addr", + "write w/ addr" + }; + static const char *const atomic_type[3] = { + "none", + " 0 ", + " 1 " + }; + + if (ops == NULL) + return; + + msg_pdbg2(" OP Type Pre-OP\n"); for (i = 0; i < 8; i++) { oc = ops->opcode[i]; - msg_pdbg("op[%d]=0x%02x, %d, %d\n", - i, - oc.opcode, - oc.spi_type, - oc.atomic); + t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type]; + a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic]; + msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a); } + msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0], + ops->preop[1]); } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) @@ -672,7 +684,6 @@ curopcodes = curopcodes_done; msg_pdbg("done\n"); prettyprint_opcodes(curopcodes); - msg_pdbg("\n"); return 0; } }

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Re: [flashrom] [PATCH 6/8] ichspi: add prettyprinting for PR registers
by Stefan Tauner 17 Sep '11

17 Sep '11

On Sat, 20 Aug 2011 12:39:46 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > + if (rwperms != 0x3) > + msg_pdbg(")\n0x%08x-0x%08x is %s\n", (ICH_FREG_BASE(pr) << 12), > + (ICH_FREG_LIMIT(pr) << 12) | 0x0fff, > + access_names[rwperms]); this is wrong. i have rebased these patches onto hwseq and forgot that the FREG macros have changed (no more shifting needed). depending on what gets acked when, i will fix this one way or another... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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