flashrom

flashrom@flashrom.org

3 participants
9189 discussions

Truncating flash for oversized image
by Rob Shore 01 Nov '21

01 Nov '21

Hello! I've just discovered Flashrom as a way to use a Dediprog SPI programmer with MacOS, which is awesome. I've got a bit of a strange question though: I've got a 1Mbit rom on a board, but the image I was given for it is for a 2Mbit part. The firmware itself in the raw image is < 1Mbit, but the file is still larger than my ROM. Flashrom won't run the flash saying "Error: Image size (262144 B) doesn't match the flash chip's size (131072 B)!", which is technically correct. Is there a way to force the flash, and just have the process end after the first 131072B, which would result in the data I need being on the ROM? Thanks, and looking forward to using this tool some more! --Rob

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Flashrom Sucess on GIGABYTE Z390 AORUS MASTER mainboard
by melvyn2 30 Oct '21

30 Oct '21

I was successfully able to flash OEM and modified firmwares using the internal programmer of the GIGABYTE Z390 AORUS MASTER mainboard. I was also able to consistently read and verify firmware from the mainboard. Attached is a verbose log of the programmer probe.

2 1

FAILED : Rikor r-bd-e5r-v4-16.ea v1.1 !
by son nguyentruong 29 Oct '21

29 Oct '21

Dear, I had upgrade bios on mainboard Rikor r-bd-e5r-v4-16.ea v1.1 using ubuntu 16.04 command: flashrom -p internal -w r-bd-e5r_BIOS_release.fd and error in attach picture . Please help me!!!!!! Thank so much ! -- nguyen truong son

1 0

Reading from multiple die stacked NAND flssh memory with flashrom
by s3th_0x 29 Oct '21

29 Oct '21

Hi all, I'm interested in reading from a Winbond's NAND Flash Memory W25M02GV <https://www.winbond.com/resource-files/W25M02GV%20Rev%20I%20051721.pdf>, but unfortunately flashrom does not support this chip yet. There are few differences between this chip and those already available in the flashchips.h from Winbond. It uses a SpiStack technology, which means stacking multiple die in one, in this case two nand 1G each. The ID for this nand is W25N01GV <https://www.winbond.com/resource-files/W25M02GV%20Rev%20I%20051721.pdf>. Actually the W25M02GV <https://www.winbond.com/resource-files/W25M02GV%20Rev%20I%20051721.pdf> is composed by two W25N01GV <https://www.winbond.com/resource-files/W25M02GV%20Rev%20I%20051721.pdf> NAND. this chip, for almost every instruction, has one or more dummy bytes after the instruction. This feature seems not to be implemented in any chip currently listed in flashrom. Also, my fault, I admit that I don't fully understand all the differences that could be hidden in having more than one die (perhaps more than the ones I mentioned above), and consequently the implications that it could entail in the implementation. I hope someone will be interested in developing this ability and can help me. Thanks, s3th0x References: Datasheet: https://www.winbond.com/resource-files/W25M02GV%20Rev%20I%20051721.pdf Linux Kernel MTD: https://elixir.bootlin.com/linux/latest/source/drivers/mtd/nand/spi/winbond… Arduino Library: https://github.com/squaresausage/WinbondW25N

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unsupported SPI EON (cFeon) on Acer E1-572G 4th gen Intel from 2013
by Roberto Eick 27 Oct '21

27 Oct '21

Follows screen: *reick87@AO722*:*~/Área de trabalho/Arduino Bios Prog/extract/hexed*$ sudo flashrom -p serprog:dev=/dev/ttyUSB0:2000000 -w V5WE2X64.FD flashrom v1.2 on Linux 5.14.0-3-amd64 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). serprog: Programmer name is "frser-duino" serprog: requested mapping AT45CS1282 is incompatible: 0x1080000 bytes at 0x00000000fef80000. serprog: requested mapping GD25Q256D is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping IS25LP256 is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping IS25WP256 is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping MX25L25635F/MX25L25645G is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping MX25U25635F is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping MX25U51245G is incompatible: 0x4000000 bytes at 0x00000000fc000000. serprog: requested mapping MX66L51235F/MX25L51245G is incompatible: 0x4000000 bytes at 0x00000000fc000000. serprog: requested mapping N25Q00A..1G is incompatible: 0x8000000 bytes at 0x00000000f8000000. serprog: requested mapping N25Q00A..3G is incompatible: 0x8000000 bytes at 0x00000000f8000000. serprog: requested mapping N25Q256..1E is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping N25Q256..3E is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping N25Q512..1G is incompatible: 0x4000000 bytes at 0x00000000fc000000. serprog: requested mapping N25Q512..3G is incompatible: 0x4000000 bytes at 0x00000000fc000000. serprog: requested mapping MT25QL01G is incompatible: 0x8000000 bytes at 0x00000000f8000000. serprog: requested mapping MT25QU01G is incompatible: 0x8000000 bytes at 0x00000000f8000000. serprog: requested mapping MT25QL02G is incompatible: 0x10000000 bytes at 0x00000000f0000000. serprog: requested mapping MT25QU02G is incompatible: 0x10000000 bytes at 0x00000000f0000000. serprog: requested mapping MT25QL256 is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping MT25QU256 is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping MT25QL512 is incompatible: 0x4000000 bytes at 0x00000000fc000000. serprog: requested mapping MT25QU512 is incompatible: 0x4000000 bytes at 0x00000000fc000000. serprog: requested mapping S25FL256S......0 is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping S25FL512S is incompatible: 0x4000000 bytes at 0x00000000fc000000. serprog: requested mapping W25Q256.V is incompatible: 0x2000000 bytes at 0x00000000fe000000. serprog: requested mapping W25Q256JV_M is incompatible: 0x2000000 bytes at 0x00000000fe000000. Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI) on serprog. === This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Error: Image size (8388608 B) doesn't match the flash chip's size (0 B)! Compal schemmatic mentions EN25QH64-104HIP_SO8 chip reference. With the eyes is hard to see, says cFeon, the numbers are too small. Maybe this and similar Acer laptop SPIs can be included in FLASHROM? Best regards! -- --------------------------------------------- Roberto Eick - Electrical Engineer Santa Cruz do Sul, RS, Brazil Email: eick.roberto(a)gmail.com

1 0

Chrome OS Flash
by Jacobb Faucher 26 Oct '21

26 Oct '21

I was wondering if I could get assistance on how to disable Write Protection (WP) on Chrome OS. My Chromebook is the Acer Chromebook 311 (CB311-9H).

3 2

Adding write protect/lock support to flashrom
by ln2＠mailo.com 18 Oct '21

18 Oct '21

Hi all, I would like to see the following feature added to flashrom: https://github.com/flashrom/flashrom/issues/185 If someone implemented it, would the idea (at least) be accepted? Is anyone interested in implementing it and claiming the $100 bounty? Text of the issue, for people too lazy to click: Some chips require certain bits (and similar features) be set before the hardware write-protect pins can be used. Flashrom doesn't currently support setting these bits, which makes it impossible to e.g hardware write-protect a BIOS chip after flashing Coreboot. I would like to see Flashrom add support for this. Attached is a patch which was written by someone else (they can identify themselves if they like) to toggle the relevant bits for a particular flash chip, each time flashrom is run, and tell the user what's going on. Your task, if you want to claim the bounty, is to: 1- Add some UI sugar so that the user can choose to set the appropriate bits (or not), and any other "features" needed to enable hardware write-protect, via the command line 2- Ensure the necessary bits and features can be set for a specified set of chips (see below), so Flashrom supports hardware write protect for at least all of the listed chips, and 3- Get your patch accepted and merged (it may be wise to first check with the maintainers that they are willing to add this feature) using Gerrit or the mailing list as per the official process If $100 isn't enough to make this attractive, I am open to increasing the bounty. I am also happy to escrow it if need be. Payment will be in Bitcoin.

2 2

Flashrom High CPU utilization
by Pheba Philip 17 Oct '21

17 Oct '21

Hi, Is it expected behavior for flashrom to have high cpu utilization for bios verification.

3 4

34C02
by W.H. 17 Oct '21

17 Oct '21

I tried to read (and possibly program) a 34C02, using a CH341A programmer. I found that this IC is possibly not supported. Will there be a support for this device in future? Best regards Wolfgang

2 1

flashrom error report
by astanek 13 Oct '21

13 Oct '21

Sent with ProtonMail Secure Email.

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