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[PATCH 4/5] Add spi_block_erase_62.
by Stefan Tauner 15 Feb '12

15 Feb '12

This is used by the AT25F series (only?), but is generic enough to reside in spi25.c. The only currently supported chip is the AT25F512B. Other members of that series need some additional infrastructure code, hence this patch adds the erase function to the AT25F512B only. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 1 + flashchips.c | 3 +++ spi.h | 5 +++++ spi25.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 0 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 420564d..44eca65 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -40,6 +40,7 @@ int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int b int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); diff --git a/flashchips.c b/flashchips.c index 3656794..80f29f6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1679,6 +1679,9 @@ const struct flashchip flashchips[] = { }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_62, } }, .printlock = spi_prettyprint_status_register_at25f512b, diff --git a/spi.h b/spi.h index b908603..adb9109 100644 --- a/spi.h +++ b/spi.h @@ -61,6 +61,11 @@ #define JEDEC_CE_60_OUTSIZE 0x01 #define JEDEC_CE_60_INSIZE 0x00 +/* Chip Erase 0x62 is supported by Atmel AT25F chips. */ +#define JEDEC_CE_62 0x62 +#define JEDEC_CE_62_OUTSIZE 0x01 +#define JEDEC_CE_62_INSIZE 0x00 + /* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */ #define JEDEC_CE_C7 0xc7 #define JEDEC_CE_C7_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index 5c5048d..0d02559 100644 --- a/spi25.c +++ b/spi25.c @@ -488,6 +488,43 @@ int spi_chip_erase_60(struct flashctx *flash) return 0; } +int spi_chip_erase_62(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_62_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_62 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", + __func__); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 2-5 s, so wait in 100 ms steps. + */ + /* FIXME: We assume spi_read_status_register will never fail. */ + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + int spi_chip_erase_c7(struct flashctx *flash) { int result; @@ -712,6 +749,16 @@ int spi_block_erase_60(struct flashctx *flash, unsigned int addr, return spi_chip_erase_60(flash); } +int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + if ((addr != 0) || (blocklen != flash->total_size * 1024)) { + msg_cerr("%s called with incorrect arguments\n", + __func__); + return -1; + } + return spi_chip_erase_62(flash); +} + int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { -- 1.7.1

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[PATCH 3/5] Rename AT25F512B-specific code.
by Stefan Tauner 15 Feb '12

15 Feb '12

The AT25F512B is quite different from the other (older and yet unsupported) chips in the AT25F* familiy, hence rename 512B-specific stuff to make room for the generic AT25F* code Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- at25.c | 4 ++-- chipdrivers.h | 4 ++-- flashchips.c | 5 +++-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/at25.c b/at25.c index 817e769..803e7e4 100644 --- a/at25.c +++ b/at25.c @@ -86,7 +86,7 @@ int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash) return spi_prettyprint_status_register_at25df(flash); } -int spi_prettyprint_status_register_at25f(struct flashctx *flash) +int spi_prettyprint_status_register_at25f512b(struct flashctx *flash) { uint8_t status; @@ -202,7 +202,7 @@ int spi_disable_blockprotect_at25df_sec(struct flashctx *flash) return spi_disable_blockprotect_at25df(flash); } -int spi_disable_blockprotect_at25f(struct flashctx *flash) +int spi_disable_blockprotect_at25f512b(struct flashctx *flash) { /* spi_disable_blockprotect_at25df is not really the right way to do * this, but the side effects of said function work here as well. diff --git a/chipdrivers.h b/chipdrivers.h index b20030b..420564d 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -73,13 +73,13 @@ int spi_prettyprint_status_register_amic_a25lq032(struct flashctx *flash); /* at25.c */ int spi_prettyprint_status_register_at25df(struct flashctx *flash); int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash); -int spi_prettyprint_status_register_at25f(struct flashctx *flash); +int spi_prettyprint_status_register_at25f512b(struct flashctx *flash); int spi_prettyprint_status_register_at25fs010(struct flashctx *flash); int spi_prettyprint_status_register_at25fs040(struct flashctx *flash); int spi_prettyprint_status_register_atmel_at26df081a(struct flashctx *flash); int spi_disable_blockprotect_at25df(struct flashctx *flash); int spi_disable_blockprotect_at25df_sec(struct flashctx *flash); -int spi_disable_blockprotect_at25f(struct flashctx *flash); +int spi_disable_blockprotect_at25f512b(struct flashctx *flash); int spi_disable_blockprotect_at25fs010(struct flashctx *flash); int spi_disable_blockprotect_at25fs040(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index ca1c57f..3656794 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1657,6 +1657,7 @@ const struct flashchip flashchips[] = { .model_id = ATMEL_AT25F512B, .total_size = 64, .page_size = 256, + /* TODO: chip features 128-byte one-time programmable region */ .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, @@ -1680,8 +1681,8 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_at25f, - .unlock = spi_disable_blockprotect_at25f, + .printlock = spi_prettyprint_status_register_at25f512b, + .unlock = spi_disable_blockprotect_at25f512b, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, -- 1.7.1

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[PATCH 2/5] Refine messages of SPI block protection disables.
by Stefan Tauner 15 Feb '12

15 Feb '12

Make them real progress indicators with a final "done" message on success. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- at25.c | 21 ++++++++++++--------- spi25.c | 5 +++-- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/at25.c b/at25.c index 8891e2b..817e769 100644 --- a/at25.c +++ b/at25.c @@ -164,7 +164,7 @@ int spi_disable_blockprotect_at25df(struct flashctx *flash) if ((status & (3 << 2)) == 0) return 0; - msg_cdbg("Some block protection in effect, disabling\n"); + msg_cdbg("Some block protection in effect, disabling... "); if (status & (1 << 7)) { msg_cdbg("Need to disable Sector Protection Register Lock\n"); if ((status & (1 << 4)) == 0) { @@ -175,7 +175,7 @@ int spi_disable_blockprotect_at25df(struct flashctx *flash) /* All bits except bit 7 (SPRL) are readonly. */ result = spi_write_status_register(flash, status & ~(1 << 7)); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } @@ -183,7 +183,7 @@ int spi_disable_blockprotect_at25df(struct flashctx *flash) /* Global unprotect. Make sure to mask SPRL as well. */ result = spi_write_status_register(flash, status & ~0xbc); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } status = spi_read_status_register(flash); @@ -191,6 +191,7 @@ int spi_disable_blockprotect_at25df(struct flashctx *flash) msg_cerr("Block protection could not be disabled!\n"); return 1; } + msg_cdbg("done.\n"); return 0; } @@ -219,20 +220,20 @@ int spi_disable_blockprotect_at25fs010(struct flashctx *flash) if ((status & 0x6c) == 0) return 0; - msg_cdbg("Some block protection in effect, disabling\n"); + msg_cdbg("Some block protection in effect, disabling... "); if (status & (1 << 7)) { msg_cdbg("Need to disable Status Register Write Protect\n"); /* Clear bit 7 (WPEN). */ result = spi_write_status_register(flash, status & ~(1 << 7)); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } } /* Global unprotect. Make sure to mask WPEN as well. */ result = spi_write_status_register(flash, status & ~0xec); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } status = spi_read_status_register(flash); @@ -240,6 +241,7 @@ int spi_disable_blockprotect_at25fs010(struct flashctx *flash) msg_cerr("Block protection could not be disabled!\n"); return 1; } + msg_cdbg("done.\n"); return 0; } @@ -253,20 +255,20 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash) if ((status & 0x7c) == 0) return 0; - msg_cdbg("Some block protection in effect, disabling\n"); + msg_cdbg("Some block protection in effect, disabling... "); if (status & (1 << 7)) { msg_cdbg("Need to disable Status Register Write Protect\n"); /* Clear bit 7 (WPEN). */ result = spi_write_status_register(flash, status & ~(1 << 7)); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } } /* Global unprotect. Make sure to mask WPEN as well. */ result = spi_write_status_register(flash, status & ~0xfc); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } status = spi_read_status_register(flash); @@ -274,5 +276,6 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash) msg_cerr("Block protection could not be disabled!\n"); return 1; } + msg_cdbg("done.\n"); return 0; } diff --git a/spi25.c b/spi25.c index eaae204..5c5048d 100644 --- a/spi25.c +++ b/spi25.c @@ -951,10 +951,10 @@ int spi_disable_blockprotect(struct flashctx *flash) if ((status & 0x3c) == 0) return 0; - msg_cdbg("Some block protection in effect, disabling\n"); + msg_cdbg("Some block protection in effect, disabling... "); result = spi_write_status_register(flash, status & ~0x3c); if (result) { - msg_cerr("spi_write_status_register failed\n"); + msg_cerr("spi_write_status_register failed.\n"); return result; } status = spi_read_status_register(flash); @@ -962,6 +962,7 @@ int spi_disable_blockprotect(struct flashctx *flash) msg_cerr("Block protection could not be disabled!\n"); return 1; } + msg_cdbg("done.\n"); return 0; } -- 1.7.1

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[PATCH 1/5] Clean up a25.c, at25.c, spi25.c.
by Stefan Tauner 15 Feb '12

15 Feb '12

- introduce spi_prettyprint_status_register_atmel_at25_wpen() - use spi_prettyprint_status_register_bit() where possible - generify spi_prettyprint_status_register_bp3210 and use it in at25.c too Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- a25.c | 8 ++++---- at25.c | 31 +++++++++++-------------------- chipdrivers.h | 2 +- spi25.c | 15 +++++++++------ 4 files changed, 25 insertions(+), 31 deletions(-) diff --git a/a25.c b/a25.c index b0c6b90..8c38f87 100644 --- a/a25.c +++ b/a25.c @@ -40,7 +40,7 @@ int spi_prettyprint_status_register_amic_a25l05p(struct flashctx *flash) spi_prettyprint_status_register_bit(status, 6); spi_prettyprint_status_register_bit(status, 5); spi_prettyprint_status_register_bit(status, 4); - spi_prettyprint_status_register_bp3210(status, 1); + spi_prettyprint_status_register_bp(status, 1); spi_prettyprint_status_register_welwip(status); return 0; } @@ -55,7 +55,7 @@ int spi_prettyprint_status_register_amic_a25l40p(struct flashctx *flash) spi_prettyprint_status_register_amic_a25_srwd(status); spi_prettyprint_status_register_bit(status, 6); spi_prettyprint_status_register_bit(status, 5); - spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_bp(status, 2); spi_prettyprint_status_register_welwip(status); return 0; } @@ -72,7 +72,7 @@ int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash) "is %i KB\n", (status & (1 << 6)) ? 4 : 64); msg_cdbg("Chip status register: Top/Bottom (TB) " "is %s\n", (status & (1 << 5)) ? "bottom" : "top"); - spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_bp(status, 2); spi_prettyprint_status_register_welwip(status); msg_cdbg("Chip status register 2 is NOT decoded!\n"); return 0; @@ -90,7 +90,7 @@ int spi_prettyprint_status_register_amic_a25lq032(struct flashctx *flash) "is %i KB\n", (status & (1 << 6)) ? 4 : 64); msg_cdbg("Chip status register: Top/Bottom (TB) " "is %s\n", (status & (1 << 5)) ? "bottom" : "top"); - spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_bp(status, 2); spi_prettyprint_status_register_welwip(status); msg_cdbg("Chip status register 2 is NOT decoded!\n"); return 0; diff --git a/at25.c b/at25.c index ec9b4b6..8891e2b 100644 --- a/at25.c +++ b/at25.c @@ -23,6 +23,12 @@ /* Prettyprint the status register. Works for Atmel A25/A26 series. */ +static void spi_prettyprint_status_register_atmel_at25_wpen(uint8_t status) +{ + msg_cdbg("Chip status register: Write Protect Enable (WPEN) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); +} + static void spi_prettyprint_status_register_atmel_at25_srpl(uint8_t status) { msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) " @@ -91,10 +97,7 @@ int spi_prettyprint_status_register_at25f(struct flashctx *flash) spi_prettyprint_status_register_bit(status, 6); spi_prettyprint_status_register_atmel_at25_epewpp(status); spi_prettyprint_status_register_bit(status, 3); - msg_cdbg("Chip status register: Block Protect 0 (BP0) is " - "%sset, %s sectors are protected\n", - (status & (1 << 2)) ? "" : "not ", - (status & (1 << 2)) ? "all" : "no"); + spi_prettyprint_status_register_bp(status, 0); spi_prettyprint_status_register_welwip(status); return 0; } @@ -106,14 +109,12 @@ int spi_prettyprint_status_register_at25fs010(struct flashctx *flash) status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); - msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); + spi_prettyprint_status_register_atmel_at25_wpen(status); msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " "%sset\n", (status & (1 << 6)) ? "" : "not "); msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); + spi_prettyprint_status_register_bit(status, 4); msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " "%sset\n", (status & (1 << 3)) ? "" : "not "); msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " @@ -130,18 +131,8 @@ int spi_prettyprint_status_register_at25fs040(struct flashctx *flash) status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); - msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); + spi_prettyprint_status_register_atmel_at25_wpen(status); + spi_prettyprint_status_register_bp(status, 4); /* FIXME: Pretty-print detailed sector protection status. */ spi_prettyprint_status_register_welwip(status); return 0; diff --git a/chipdrivers.h b/chipdrivers.h index a1d0cd9..b20030b 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -47,7 +47,7 @@ int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, int uint8_t spi_read_status_register(struct flashctx *flash); int spi_write_status_register(struct flashctx *flash, int status); void spi_prettyprint_status_register_bit(uint8_t status, int bit); -void spi_prettyprint_status_register_bp3210(uint8_t status, int bp); +void spi_prettyprint_status_register_bp(uint8_t status, int bp); void spi_prettyprint_status_register_welwip(uint8_t status); int spi_prettyprint_status_register(struct flashctx *flash); int spi_disable_blockprotect(struct flashctx *flash); diff --git a/spi25.c b/spi25.c index 3ce7f08..eaae204 100644 --- a/spi25.c +++ b/spi25.c @@ -327,21 +327,24 @@ void spi_prettyprint_status_register_welwip(uint8_t status) } /* Prettyprint the status register. Common definitions. */ -void spi_prettyprint_status_register_bp3210(uint8_t status, int bp) +void spi_prettyprint_status_register_bp(uint8_t status, int bp) { switch (bp) { /* Fall through. */ + case 4: + msg_cdbg("Chip status register: Block Protect 4 (BP4) " + "is %sset\n", (status & (1 << 5)) ? "" : "not "); case 3: - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) " + msg_cdbg("Chip status register: Block Protect 3 (BP3) " "is %sset\n", (status & (1 << 5)) ? "" : "not "); case 2: - msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) " + msg_cdbg("Chip status register: Block Protect 2 (BP2) " "is %sset\n", (status & (1 << 4)) ? "" : "not "); case 1: - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) " + msg_cdbg("Chip status register: Block Protect 1 (BP1) " "is %sset\n", (status & (1 << 3)) ? "" : "not "); case 0: - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) " + msg_cdbg("Chip status register: Block Protect 0 (BP0) " "is %sset\n", (status & (1 << 2)) ? "" : "not "); } } @@ -355,7 +358,7 @@ void spi_prettyprint_status_register_bit(uint8_t status, int bit) static void spi_prettyprint_status_register_common(uint8_t status) { - spi_prettyprint_status_register_bp3210(status, 3); + spi_prettyprint_status_register_bp(status, 3); spi_prettyprint_status_register_welwip(status); } -- 1.7.1

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[PATCH 0/5] AT25F* 3.0
by Stefan Tauner 15 Feb '12

15 Feb '12

Rebased this old series... 2/5 is new. The bunch of block protection disables may be valid target for refactoring because they share lots of code, but have slightly different constants… Stefan Tauner (5): Clean up a25.c, at25.c, spi25.c. Refine messages of SPI block protection disables. Rename AT25F512B-specific code. Add spi_block_erase_62. Add support for Atmel's AT25F series of SPI flash chips. a25.c | 8 ++-- at25.c | 154 +++++++++++++++++++++++++++++++++++++++++++++----------- chipdrivers.h | 6 ++- flashchips.c | 94 +++++++++++++++++++++++++++++++++++ flashchips.h | 10 ++-- spi.h | 14 ++++-- spi25.c | 67 ++++++++++++++++++++++--- 7 files changed, 299 insertions(+), 54 deletions(-)

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Re: [flashrom] FAILED: FR597AA-AKD m9360.pl (FR597AA#AKD)
by Michael Karcher 15 Feb '12

15 Feb '12

Am Dienstag, den 14.02.2012, 11:39 +0100 schrieb Mariusz Cygan: >> Verifying flash... VERIFY FAILED at 0x00011a00! Expected=0x05, Read=0xff, >> failed byte count from 0x00000000-0x000fffff: 0x1f8 >> Your flash chip is in an unknown state. >> Get help on IRC at irc.freenode.net (channel #flashrom) or >> mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! > :( and now I have to pay for the reprogramming of bone BIOS. Restored > back however, and so does not work. I don't completely understand what you mean by "restore back", if it means "reboot", you are right, the chip likely needs to be reprogrammed outside of that mainboard. In case of a desktop, the chip is likely socketed (8-pin DIP) and easily replaceable. Also, as only a low amount of bytes failed to get reprogrammed, chances are good that some flash recovery mode (if supported by that BIOS) kicks in if you try to power on the machine. On the other hand, if "restore back" means restoring the old bios (a backup you did with flashrom) and the thus the upgrade didn't work, please give it a second try. As I read the error message, writing the new image *nearly* worked, only around 500 bytes mismatched, and at least the first byte mismatch is likely explained by missing programming of a "page" of 256 bytes. Many flash chips are quite picky on how the write instruction is issued, and it might be that flashrom is slightly unreliable in getting it completely right so the flash chip ignored the write instruction if something looks fishy. I have to admit I don't know what exactly might cause such a failure, though. If that theory is indeed right, just retrying to write NT35.bin a second time would likely have fixed the situation too, especially as flashrom detects what areas really need to be reprogrammed and leaves the correctly written areas alone. If restoring the old BIOS worked as I guessed in the three steps above, I would encourage you to try writing the new image again, please run flashrom in verbose mode (add -V) and send the output to the mailing list. If writing fails again, please retry with the same image, and attach the log of the write process to the mail, too. Regards, Michael Karcher

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Re: [flashrom] [PATCH] ichspi.c: warn user when a protected region is detected
by Stefan Tauner 14 Feb '12

14 Feb '12

On Sun, 27 Nov 2011 11:48:51 -0800 David Hendricks <david.hendricks(a)gmail.com> wrote: > On Sat, Nov 26, 2011 at 3:35 PM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > > > This includes the notorious read-only flash descriptors and locked ME > > regions. > > --- > > non-verbose sample output from my laptop: > > […] > > Found chipset "Intel QS57". Enabling flash write... WARNING: SPI > > Configuration Lockdown activated. > > WARNING: Flash Descriptor region is not fully accessible and flashrom can > > not deal with this correctly yet. Intel does not provide us the necessary > > documention to support this. > > > To be fair, I think Intel documents it fine. That depends on what 'it' is. The limitations and the influence of FDOPSS on that limitation are well defined in public documentation. But the unlocking process is not documented at all publicly. We know from different leaked documents and also from the fact that vendor tools exist, that unlocking can be done by software only and without touching the FDOPSS pin by sending the "HMRFPO Enable" command via HECI/MEI to the ME. The details are documented in the BIOS writer guide(s) (which are "restricted secret" level(?)) > I think what we've got to do > is checking the flash descriptor override pin strap status (FDOPSS). If it > is cleared then we can ignore the descriptor, otherwise if it is set then > we need to avoid locked regions. I would not call it 'ignoring'. We should be aware, that the limitation do not apply (we do print a message to the user already in that case), but we could and should use the regions where it makes sense (e.g. automatic creation of layout (file)s. > It's really just a pain in the ass and, as you pointed out, may leave the > BIOS/ME firmware blobs in an inconsistent or incompatible state. So the > onus is on the user to ensure a safe upgrade path if only part of the ROM > can be updated. It's probably worth displaying a warning and requiring > "--force" or something in that scenario. As a first step yes. IIRC i have sent a patch that does that when active PR protections are found(?), but i think it is not in/reviewed yet. I agree, we should set write_allowed = 0 (or whatever it was) and rephrase the warning to include that. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Reformat the internal programmer section in the man page.
by Stefan Tauner 14 Feb '12

14 Feb '12

The section describing the various options of the internal programmer has grown out of proportions and it has become confusing. This patch adds some headlines to devide the unrelated topics a bit. --- I would also like to make the syntax examples non-bold so that the headlines stick out more (TBH i don't see the point in making the examples stick out that much by making them bold and reside on their own line at all). The dummy programmer probably needs something similar rather sooner than later. Opinions and other format command suggestions are very welcome! Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.8 | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/flashrom.8 b/flashrom.8 index 9ffd788..367a0a9 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -225,6 +225,9 @@ programmers use a key/value interface in which the key and value is separated by an equal sign and different pairs are separated by a comma or a colon. .TP .BR "internal " programmer +.sp +.B * Board Enables +.sp Some mainboards require to run mainboard specific code to enable flash erase and write support (and probe support on old systems with parallel flash). The mainboard brand and model (if it requires specific code) is usually @@ -275,6 +278,8 @@ has been written because it is known that writing/erasing without the board enable is going to fail. In any case (success or failure), please report to the flashrom mailing list, see below. .sp +.B * Coreboot +.sp On systems running coreboot, flashrom checks whether the desired image matches your mainboard. This needs some special board ID to be present in the image. If flashrom detects that the image you want to write and the current board @@ -282,6 +287,8 @@ do not match, it will refuse to write the image unless you specify .sp .B " flashrom \-p internal:boardmismatch=force" .sp +.B * ITE IT87 Super I/O +.sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, flashrom should autodetect that configuration. If you want to set the I/O base port of the IT87 series SPI controller manually instead of @@ -295,6 +302,8 @@ is the I/O port number (must be a multiple of 8). In the unlikely case flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem. .sp +.B * Intel chipsets +.sp If you have an Intel chipset with an ICH8 or later southbridge with SPI flash attached, and if a valid descriptor was written to it (e.g. by the vendor), the chipset provides an alternative way to access the flash chip(s) named @@ -332,6 +341,8 @@ settings. The default value for ICH7 is given in the example below. Example: .B "flashrom \-p internal:fwh_idsel=0x001122334567" .sp +.B * Laptops +.sp Using flashrom on laptops is dangerous and may easily make your hardware unusable (see also the .B BUGS -- 1.7.1

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Re: [flashrom] FAILED: FR597AA-AKD m9360.pl (FR597AA#AKD)
by Stefan Tauner 14 Feb '12

14 Feb '12

On Tue, 14 Feb 2012 09:58:08 +0100 Mariusz Cygan <itcygan(a)gmail.com> wrote: > flashrom -c W25X80 -w NT35.bin > flashrom v0.9.4-r1394 on Linux 3.0.0-16-generic (x86_64), built with libpci > 3.1.7, GCC 4.6.1, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found chipset "NVIDIA MCP61". > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... This chipset is not really supported yet. > Guesswork... > SPI on this chipset is WIP. Please report any success or failure by mailing > us the verbose output to flashrom(a)flashrom.org, thanks! > Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. > Please send the output of "flashrom -V" to flashrom(a)flashrom.org with > your board name: flashrom -V as the subject to help us finish support for > your > chipset. Thanks. > OK. > This chipset supports the following protocols: SPI. > Found Winbond flash chip "W25X80" (1024 kB, SPI) at physical address > 0xfff00000. > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Erase/write done. > Verifying flash... VERIFY FAILED at 0x00011a00! Expected=0x05, Read=0xff, > failed byte count from 0x00000000-0x000fffff: 0x1f8 > Your flash chip is in an unknown state. > Get help on IRC at irc.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! > ------------------------------------------------------------------------------- > DO NOT REBOOT OR POWEROFF! > > Hello Mariusz, i am not very familiar with the chipset, so i cant really help by fixing the problem. It seems that the addressing is somehow broken: I know that because erase and write succeeds. It does only succeed, if it can verify the contents of every block it wrote to be correct. After the whole process it does read the whole chip again and checks if it equals the image. Now if the addressing of the blocks wraps somewhere then the erase/write code will overwrite some blocks without noticing it (the block itself looks correct to it), but verification will fail at the end. Someone will have to look at it later. They will probably want to look at least at a verbose log, so please post the output of flashrom -V (and additionally maybe even with -VVV). The output of lspci -nnvvxxx (run as root) may also be useful. To get your board back to a consistent state, you could try flashing the backup you made with the -r/--read option (you DID make a backup, right?). But i fear it may also fail... in that case or if you do not have a backup please join IRC and most importantly: DO NOT REBOOT OR POWER OFF! We really mean it. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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FAILED: FR597AA-AKD m9360.pl (FR597AA#AKD)
by Mariusz Cygan 14 Feb '12

14 Feb '12

flashrom -c W25X80 -w NT35.bin flashrom v0.9.4-r1394 on Linux 3.0.0-16-generic (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP61". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Found Winbond flash chip "W25X80" (1024 kB, SPI) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFY FAILED at 0x00011a00! Expected=0x05, Read=0xff, failed byte count from 0x00000000-0x000fffff: 0x1f8 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! -- Serdecznie pozdrawiam Mariusz Cygan Specjalista IT / Administrator / Help Desk

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