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Re: [flashrom] [PATCH 1/5] rayer_spi: Create list of programmer types
by Kyösti Mälkki 02 Apr '13

02 Apr '13

-------- Forwarded Message -------- From: Andrew Tarabaras <andytara12(a)gmail.com> To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Subject: Re: [PATCH 1/5] rayer_spi: Create list of programmer types Date: Tue, 2 Apr 2013 13:21:09 +1100 Hi Kyösti, I finally got to testing and it works fine. I used a xilinx buffered DLC5 Parallel 3 cable with rayer_spi driver. I also programmed an unsupported SPI Eprom. a PMC PM25LD010, I just copied the PM25LV010 definition and renamed it to PM25LD010 and read / write / erase is verified to work. I would like to contribute more but I just dont have the time to be submitting patches. Best Regards Andrew On Fri, Mar 8, 2013 at 3:39 AM, Andrew Tarabaras <andytara12(a)gmail.com> wrote: Hi, Forgot to get back to your last email. Sorry. I will test it in a few days. Regards Andrew On 08/03/2013 3:18 AM, "Kyösti Mälkki" <kyosti.malkki(a)gmail.com> wrote: Hi It would be great if you can test the updated patchset with new rayer_spi pinouts on actual hardware. https://bitbucket.org/kmalkki/flashrom/get/rayer_spi.tar.bz2 or git clone -b rayer_spi https://bitbucket.org/kmalkki/flashrom.git Thanks, Kyösti

2 1

Intel H61 locked board
by radocea bogdan 02 Apr '13

02 Apr '13

Hi. Here is another locked board (I attached the log too): sudo flashrom --programmer=internal -VV flashrom v0.9.6.1-runknown on Linux 3.7.0-7-generic (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, GCC 4.7.2, little endian Command line (2 args): flashrom --programmer=internal -VV Calibrating delay loop... OS timer resolution is 1 usecs, 3207M loops per second, 10 myus = 10 us, 100 myus = 115 us, 1000 myus = 1022 us, 10000 myus = 10029 us, 4 myus = 11 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Dell Inc." DMI string system-product-name: "Inspiron 620 " DMI string system-version: "00" DMI string baseboard-manufacturer: "Dell Inc." DMI string baseboard-product-name: "0GDG8Y " DMI string baseboard-version: "A00" DMI string chassis-type: "Desktop" Found chipset "Intel H61" with PCI ID 8086:1c5c. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0xc00: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0xd8, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x90, read w/ addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x9f, read w/o addr, none op[7]: 0xc7, write w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x03ff0180 FREG1: BIOS region (0x00180000-0x003fffff) is read-write. 0x5C: 0x017f0001 FREG2: Warning: Management Engine region (0x00001000-0x0017ffff) is locked. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf84130 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=3, DBC=1, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00002005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300013 FLILL 0x00000000 --- Details --- Component 1 density: 4 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x03ff0180 FLREG2 0x017f0001 FLREG3 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00180000 - 0x003fffff Region 2 (ME ) 0x00001000 - 0x0017ffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0x0a0b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw ME r rw rw GbE rw SPI Read Configuration: prefetching disabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25F512, 64 kB: program_opcodes: preop=5006 optype=460b opmenu=05150302c79f0190 on-the-fly OPCODE (0x15) re-programmed, op-pos=2 probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512A, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25F1024(A), 128 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F2048, 256 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F4096, 512 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ESMT F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q80(B), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q32(B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q64(B), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q128B, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L512(E)/MX25V512(C), 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1005(C)/MX25L1006E, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L2005(C), 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L4005(A/C), 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L8005/MX25V8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605A/MX25L1606E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605D/MX25L1608D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Found Macronix flash chip "MX25L3205(A)" (4096 kB, SPI) at physical address 0xffc00000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Found Macronix flash chip "MX25L3205D/MX25L3208D" (4096 kB, SPI) at physical address 0xffc00000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Macronix MX25L3206E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Found Macronix flash chip "MX25L3206E" (4096 kB, SPI) at physical address 0xffc00000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Multiple flash chips were detected: "MX25L3205(A)", "MX25L3205D/MX25L3208D", "MX25L3206E" Please specify which chip to use with the -c <chipname> option. Restoring MMIO space at 0x7f1b2b5588a0 Restoring MMIO space at 0x7f1b2b55889c Restoring MMIO space at 0x7f1b2b558898 Restoring MMIO space at 0x7f1b2b558896 Restoring MMIO space at 0x7f1b2b558894 Restoring PCI config space for 00:1f:0 reg 0xdc Please let me know if I can write to this board. Thanks -- Radocea Bogdan System Admin, BetBrain BetBrain — Odds on your side iGB Best Sportsbook Affiliate 2008, 2009 & 2010 London — Bucharest — Copenhagen — Changsha — Oslo Telephone: +40735194165 Address: 5 Sirenelor Street, Sector 5, 050855 Bucharest, Romania E-Mail: rbp(a)betbrain.com Skype: radocea_bogdan

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[PATCH 2/2] Add support for PMC Pm25LD series.
by Stefan Tauner 02 Apr '13

02 Apr '13

This patch adds support for - Pm25LD256C - Pm25LD512(C) - Pm25LD010(C) - Pm25LD020(C) - Pm25LD040(C) These seem to be the successors of the Pm25LV series. The main difference seems to be the dual I/O and additional erase opcodes. Some support an additional, complex locking register (maybe all of the above, but available datahsheets do not indicate it for all). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 189 +++++++++++++++++++++++++++++++++++++++++++++++++++++ flashchips.h | 7 +- spi25_statusreg.c | 1 + 3 files changed, 196 insertions(+), 1 deletion(-) diff --git a/flashchips.c b/flashchips.c index 342fcea..37167e6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6562,6 +6562,195 @@ const struct flashchip flashchips[] = { { .vendor = "PMC", + .name = "Pm25LD256C", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LD256C, + .total_size = 32, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 8} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {32 * 1024, 1} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ + .voltage = {2700, 3600}, + }, + { + .vendor = "PMC", + .name = "Pm25LD512(C)", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LD512, + .total_size = 64, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, /* FIXME: C version supports "Safe Guard" */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ + .voltage = {2300, 3600}, + }, + + { + .vendor = "PMC", + .name = "Pm25LD010(C)", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LD010, + .total_size = 128, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, /* FIXME: C version supports "Safe Guard" */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ + .voltage = {2700, 3600}, /* 2.3-3.6V for Pm25LD010 */ + }, + + { + .vendor = "PMC", + .name = "Pm25LD020(C)", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LD020, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, /* FIXME: C version supports "Safe Guard" */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ + .voltage = {2700, 3600}, /* 2.3-3.6V for Pm25LD020 */ + }, + + { + .vendor = "PMC", + .name = "Pm25LD040(C)", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LV040, + .total_size = 512, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ + .voltage = {2700, 3600}, /* 2.3-3.6V for Pm25LD040 */ + }, + + { + .vendor = "PMC", .name = "Pm25LV512", .bustype = BUS_SPI, .manufacture_id = PMC_ID_NOPREFIX, diff --git a/flashchips.h b/flashchips.h index bbad7ec..4da4868 100644 --- a/flashchips.h +++ b/flashchips.h @@ -450,13 +450,18 @@ /* * Programmable Micro Corp is listed in JEP106W in bank 2, so it should * have a 0x7F continuation code prefix. + * Apparently this name is owned by "Chingis Technology Corporation" http://www.chingistek.com. */ #define PMC_ID 0x7F9D /* PMC */ #define PMC_ID_NOPREFIX 0x9D /* PMC, missing 0x7F prefix */ +#define PMC_PM25LD256C 0x2F +#define PMC_PM25LD512 0x20 /* Same as Pm25LD512C, but the latter has more locking options. */ +#define PMC_PM25LD010 0x21 /* Same as Pm25LD010C, but the latter has more locking options. */ +#define PMC_PM25LD020 0x22 /* Same as Pm25LD020C, but the latter has more locking options. */ #define PMC_PM25LV512 0x7B /* Same as Pm25LV512A, but the latter does not support any sane probing. */ #define PMC_PM25LV010 0x7C /* Same as Pm25LV010A, but the latter uses the continuation prefix. */ #define PMC_PM25LV020 0x7D -#define PMC_PM25LV040 0x7E +#define PMC_PM25LV040 0x7E /* Same as PM25LD040(C), but the latter supports more features. */ #define PMC_PM25LV080B 0x13 #define PMC_PM25LV016B 0x14 #define PMC_PM29F002T 0x1D diff --git a/spi25_statusreg.c b/spi25_statusreg.c index c089157..53952fe 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -262,6 +262,7 @@ int spi_prettyprint_status_register_default_bp1(struct flashctx *flash) /* Works for many chips of the * AMIC A25L series + * PMC Pm25LD series */ int spi_prettyprint_status_register_default_bp2(struct flashctx *flash) { -- Kind regards, Stefan Tauner

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help
by Pinery. 02 Apr '13

02 Apr '13

hello! my,, EEPROM ID (7F,9D20) : PMC Pm25Ld512 2.7-3.6V 512Kx1S, page This can support ? Thank you!

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Re: [flashrom] [PATCH] Refine granularity handling in preparation of AT45DB series support.
by Carl-Daniel Hailfinger 02 Apr '13

02 Apr '13

Hi Mark, allow me to explain. You may want to run away screaming and I can't blame you. page_size is a historical concept in flashrom created when flashrom was an ad-hoc collection of flashing routines for maybe 5 chips. It had a number of different meanings depending on the chip with no clear rules whatsoever. We even abused it for erase block sizes and block locking. It doesn't help that datasheets have verying definitions of the meaning of page size as well. A flash chip has certain write/erase/read properties, and those differ between NAND and NOR flash. Right now flashrom only supports NOR flash with certain characteristics (power-of-two sizes for min write size / max write size / chip size). The growing pains start with Atmel AT45* chips which are different. Properties of a flash chip: - Total size (Must be a multiple of 1024 bytes right now, easily fixable.) - Erase block sizes (Arbitrary sizes and multiple erase methods are supported for that, no need to change anything.) - Addressing -- Address size (3-byte vs. 4-byte addresses for SPI flash. Patches exist, have to be reviewed.) -- Address space contiguousness (Does the address space have holes? Are holes present in the read result if someone does a read/write from address A to B with an address space hole in the middle?) -- Address granularity (Can individual bytes be addressed directly or is there a need for sub-addresses like byte selection for old 16-bit word parallel flash?) - Reading -- Maximum read size -- Minimum read size (Can individual bytes be read from the chip like for most NOR flash?) - Writing (Multiple write methods, characteristics below are per-method.) -- Maximum write size in one meta-command (Meta-command is a single command for unrelated write commands or group of related write commands for stuff like AAI with a begin and end command.) -- Maximum (or fixed) write size in one sub-command (Sub-command is a single command for unrelated write commands or a single command for stuff like AAI.) -- Minimum write size (Minimum number of bits/bytes to be written so that no undefined results happen.) -- Write wraparound (Whether writes starting in the middle of a "page" wrap around to the start of the page, this is avoided in flashrom code and thus not relevant here.) - Block locking (Not directly relevant to this discussion except that we abused page_size for that in the past.) - Command set (Not relevant except for commands needed for above properties.) - Buses (Not relevant here.) - Voltage (Not relevant here.) - Timing (Not relevant here.) At various times during flashrom development, page_size has been used for pretty much every single item listed above. Some strange uses remain. Let me illustrate the properties above with a few sample chips: ST/Numonyx/Micron M25P32: (no surprises) - Total size: 4096 kByte - Erase block sizes: 64 kByte for command 0xd8, 4 MByte for command 0xc7 - Addressing -- Address size: 3-Byte -- Address space contiguousness: No holes -- Address granularity: Direct Byte access - Reading -- Minimum read size: 1 Byte -- Maximum read size: unlimited - Writing: Only one write method: Page write -- Maximum write size in one meta-command: 256 Bytes -- Maximum (or fixed) write size in one sub-command: 256 Bytes -- Minimum write size: 1 Byte Micron N25Q256: (4-byte addresses) - Total size: 32 MByte - Erase block sizes: 4 kByte for command 0x20, 64 kByte for command 0xd8, 32 MByte for command 0xc7 - Addressing -- Address size: 3-byte with Extended Address register for upper bit or 4-byte, switchable with Flag Status Register and/or command set -- Address space contiguousness: No holes -- Address granularity: Direct byte access - Reading -- Minimum read size: 1 byte -- Maximum read size: unlimited (unless non-default wrap mode is active) - Writing: -- Maximum write size in one meta-command: 256 Bytes -- Maximum (or fixed) write size in one sub-command: 256 Bytes -- Minimum write size: 1 Byte Atmel AT45DB041D (256-byte page mode): - Total size: 512 kByte - Erase block sizes: 256 Byte for command 0x81, 2 kByte for command 0x50, 2/64 kByte for command 0x7c (not all regions erasable), 512 kByte for command 0xc794809a - Addressing -- Address size: 3-byte -- Address space contiguousness: No holes -- Address granularity: Direct byte access (other options exist) - Reading -- Minimum read size: 1 Byte -- Maximum read size: unlimited - Writing: -- Maximum write size in one meta-command: 256 Bytes -- Maximum (or fixed) write size in one sub-command: 256 Bytes -- Minimum write size: 256 Bytes (unusual for other SPI chips) Atmel AT45DB041D (264-byte page mode): - Total size: 528 kByte - Erase block sizes: 264 Byte for command 0x81, 2112 Byte for command 0x50, 2112/67584 Byte for command 0x7c (not all regions erasable), 528 kByte for command 0xc794809a - Addressing -- Address size: 3-byte -- Address space contiguousness: With holes -- Address granularity: Direct byte access (other options exist) - Reading -- Minimum read size: 1 Byte (mind the holes in address space) -- Maximum read size: unlimited (mind the holes in address space for initial address, but the read result will have no holes even for reads spanning holes) - Writing: -- Maximum write size in one meta-command: 264 Bytes -- Maximum (or fixed) write size in one sub-command: 264 Bytes -- Minimum write size: 264 Bytes (unusual for other SPI chips) SST SST25VF016B: (AAI) - Total size: 2048 kByte - Erase block sizes: 4 kByte for command 0x20, 32 kByte for command 0x52, 64 kByte for command 0xd8, 2 MByte for commands 0x60/0xc7 - Addressing -- Address size: 3-Byte -- Address space contiguousness: No holes -- Address granularity: Direct Byte access - Reading -- Minimum read size: 1 Byte -- Maximum read size: unlimited - Writing: Write method: Byte write -- Maximum write size in one meta-command: 1 Byte -- Maximum (or fixed) write size in one sub-command: 1 Byte -- Minimum write size: 1 Byte - Writing: Write method: AAI write -- Maximum write size in one meta-command: 2097152 Bytes (chip size) -- Maximum (or fixed) write size in one sub-command: 2 Bytes -- Minimum write size: 2 Bytes The "write_granularity" we have in our tree is the minimum write size. Depending on the datasheet author, "page size" can be a minimum write size, maximum write size, minimum read size, maximum read size or largest contiguous chunk in the address space. The most prudent thing would probably be to rename chip->gran to chip->write_min_size, as well as add veriables chip->write_max_size and chip->address_holes_after (264 bytes for AT45DB041D in 264-byte page mode). We'll also need a function chip->linear_to_physical_address function. I'll try to answer your questions below. Am 28.03.2013 11:41 schrieb Mark Marshall: > I'm currently struggling to understand what the write granularity is for > and how it > interacts with the page size? > I'm also a little confused by flashrom's use of page size? > > I am mainly interested in SPI flash chips. For most SPI chips the "page > size" is 256 bytes. > I have a chip where the page size is 512 bytes. > > The "page size" is the amount that writes using the PP command have to be > chunked by. > So "spi_nbyte_program" must be used to write no more than "page size" bytes > and must > not cross a "page size" boundary. Yes. With my new terminology, this would be write_max_size instead of page_size. > So far this all makes sense, apart from the "spi_chip_write_256" function, > which should > be named "spi_chip_write_page"? (as all chips currently have a page size > of 256 this is > correct at the moment, but I'm about to add one that doesn't). Correct. > I think that the "chunksize" parameter in spi_write_chunked is to do with > possible restrictions > of some programmer hardware? This also makes sense, apart from all of the > comments which > are very out of date? Yes. > According to the manuals of the SPI Flash chips I've looked at, when using > the PP command > you can program any part of a page, and the correct thing will happen (1's > can only be written > to 0's). So I don't see how this matches up with "write granularity", > which claims that the other > bytes in the granularity region will be "undefined"? If you can write a single byte multiple times as long as you never try to set a 0 bit to 1, you have 1-bit granularity. If you can write a single byte just once, you have 1-byte granularity. If you can only write multiple bytes at once (e.g. 264 bytes for AT45* in some modes) and non-written bytes of a "page" end up undefined, you have n-byte granularity. > Is write granularity for something else? No, it's just really complicated. > Is there a post somewhere that I missed that explains all of this? No post anywhere, and your mail prompted me to write something up. Hope it helped. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] Successful read on HP ProBook 4320s (HM57)
by Stefan Tauner 01 Apr '13

01 Apr '13

On Wed, 20 Mar 2013 21:12:51 +0400 Vasiliy Vylegzhanin <coder(a)npo-echelon.ru> wrote: > Hi, > appying patches from http://patchwork.coreboot.org/user/bundle/37/ > makes it possible to read non-blocked regions on HP ProBook 4320s. Thanks, I hope to get them merged in the next weeks eventually. > HM57 is marked untested, so here is read log (attached). Our policy is to mark them tested only when we get successful *writes*. In the case of Intel chipsets the policy and the whole status is rather useless though. The will (most probably) all work, but only if the configuration allows to access all regions... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Refine granularity handling in preparation of AT45DB series support.
by Carl-Daniel Hailfinger 01 Apr '13

01 Apr '13

Am 14.03.2013 12:13 schrieb Stefan Tauner: > This adds a number of new granularities in a rather inelegant way. > Until we figure out how to better handle various granularities this has > to be accepted. I think it's pretty good and I definitely don't consider it to be inelegant. > It also refactors the handling of n-byte granularities by extracting the > checking code into a helper function which reduces the pain of the above > significantly. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> with one small change (see below). > --- > This is one possibility to solve the granularity issue and i think the > most likely to get the patch series in fastest... > > --- a/flashrom.c > +++ b/flashrom.c > @@ -676,6 +676,23 @@ out_free: > return ret; > } > > +/* Helper function for need_erase() that focuses on granularities of n bytes. */ > +static int need_erase_n_bytes(uint8_t *have, uint8_t *want, unsigned int len, unsigned int n) Can you please rename n to gran or something similar (don't forget the comment as well)? That would improve readability. No need to repost. > +{ > + unsigned int i, j, limit; > + for (j = 0; j < len / n; j++) { > + limit = min (n, len - j * n); > + /* Are 'have' and 'want' identical? */ > + if (!memcmp(have + j * n, want + j * n, limit)) > + continue; > + /* have needs to be in erased state. */ > + for (i = 0; i < limit; i++) > + if (have[j * n + i] != 0xff) > + return 1; > + } > + return 0; > +} > + > /* > * Check if the buffer @have can be programmed to the content of @want without > * erasing. This is only possible if all chunks of size @gran are either kept > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1666 - trunk
by repository service 01 Apr '13

01 Apr '13

Author: stefanct Date: Mon Apr 1 21:34:53 2013 New Revision: 1666 URL: http://flashrom.org/trac/flashrom/changeset/1666 Log: Refine granularity handling in preparation of AT45DB series support. This adds a number of new granularitie and refines the handling of n-byte granularities by extracting the respective code into a helper function which reduces the pain of the above significantly. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flash.h trunk/flashrom.c Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Mon Apr 1 02:46:05 2013 (r1665) +++ trunk/flash.h Mon Apr 1 21:34:53 2013 (r1666) @@ -59,18 +59,22 @@ }; /* - * The following write granularities are known: - * - 1 bit: Each bit can be cleared individually. - * - 1 byte: A byte can be written once. Further writes to an already written byte cause its contents to be - * either undefined or to stay unchanged. - * - 128 bytes: If less than 128 bytes are written, the rest will be erased. Each write to a 128-byte region - * will trigger an automatic erase before anything is written. Very uncommon behaviour. - * - 256 bytes: If less than 256 bytes are written, the contents of the unwritten bytes are undefined. + * The following enum defines possible write granularities of flash chips. These tend to reflect the properties + * of the actual hardware not necesserily the write function(s) defined by the respective struct flashchip. + * The latter might (and should) be more precisely specified, e.g. they might bail out early if their execution + * would result in undefined chip contents. */ enum write_granularity { - write_gran_256bytes = 0, /* We assume 256 byte granularity by default. */ - write_gran_1bit, - write_gran_1byte, + /* We assume 256 byte granularity by default. */ + write_gran_256bytes = 0,/* If less than 256 bytes are written, the unwritten bytes are undefined. */ + write_gran_1bit, /* Each bit can be cleared individually. */ + write_gran_1byte, /* A byte can be written once. Further writes to an already written byte cause + * its contents to be either undefined or to stay unchanged. */ + write_gran_264bytes, /* If less than 264 bytes are written, the unwritten bytes are undefined. */ + write_gran_512bytes, /* If less than 512 bytes are written, the unwritten bytes are undefined. */ + write_gran_528bytes, /* If less than 528 bytes are written, the unwritten bytes are undefined. */ + write_gran_1024bytes, /* If less than 1024 bytes are written, the unwritten bytes are undefined. */ + write_gran_1056bytes, /* If less than 1056 bytes are written, the unwritten bytes are undefined. */ }; /* Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Mon Apr 1 02:46:05 2013 (r1665) +++ trunk/flashrom.c Mon Apr 1 21:34:53 2013 (r1666) @@ -688,6 +688,23 @@ return ret; } +/* Helper function for need_erase() that focuses on granularities of gran bytes. */ +static int need_erase_gran_bytes(uint8_t *have, uint8_t *want, unsigned int len, unsigned int gran) +{ + unsigned int i, j, limit; + for (j = 0; j < len / gran; j++) { + limit = min (gran, len - j * gran); + /* Are 'have' and 'want' identical? */ + if (!memcmp(have + j * gran, want + j * gran, limit)) + continue; + /* have needs to be in erased state. */ + for (i = 0; i < limit; i++) + if (have[j * gran + i] != 0xff) + return 1; + } + return 0; +} + /* * Check if the buffer @have can be programmed to the content of @want without * erasing. This is only possible if all chunks of size @gran are either kept @@ -705,7 +722,7 @@ int need_erase(uint8_t *have, uint8_t *want, unsigned int len, enum write_granularity gran) { int result = 0; - unsigned int i, j, limit; + unsigned int i; switch (gran) { case write_gran_1bit: @@ -723,20 +740,22 @@ } break; case write_gran_256bytes: - for (j = 0; j < len / 256; j++) { - limit = min (256, len - j * 256); - /* Are 'have' and 'want' identical? */ - if (!memcmp(have + j * 256, want + j * 256, limit)) - continue; - /* have needs to be in erased state. */ - for (i = 0; i < limit; i++) - if (have[j * 256 + i] != 0xff) { - result = 1; - break; - } - if (result) - break; - } + result = need_erase_gran_bytes(have, want, len, 256); + break; + case write_gran_264bytes: + result = need_erase_gran_bytes(have, want, len, 264); + break; + case write_gran_512bytes: + result = need_erase_gran_bytes(have, want, len, 512); + break; + case write_gran_528bytes: + result = need_erase_gran_bytes(have, want, len, 528); + break; + case write_gran_1024bytes: + result = need_erase_gran_bytes(have, want, len, 1024); + break; + case write_gran_1056bytes: + result = need_erase_gran_bytes(have, want, len, 1056); break; default: msg_cerr("%s: Unsupported granularity! Please report a bug at " @@ -784,6 +803,21 @@ case write_gran_256bytes: stride = 256; break; + case write_gran_264bytes: + stride = 264; + break; + case write_gran_512bytes: + stride = 512; + break; + case write_gran_528bytes: + stride = 528; + break; + case write_gran_1024bytes: + stride = 1024; + break; + case write_gran_1056bytes: + stride = 1056; + break; default: msg_cerr("%s: Unsupported granularity! Please report a bug at " "flashrom(a)flashrom.org\n", __func__);

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[PATCH] Bus Pirate UART speedup.
by Stefan Tauner 01 Apr '13

01 Apr '13

Increase PIC/FT232 UART speed to 2 Mbaud (instead of 115200 baud) in firmware 5.5 and newer. Given that UART speed is the biggest bottleneck for Bus Pirate communication (right now 90% of the read time is caused by slow BP<->host communication), this patch is absolutely needed to get any decent speed out of the Bus Pirate. WARNING: This patch may hang flashrom or corrupt data for any non-v3 Bus Pirate model. I haven't tested such models, and it might work without problems. Who knows. We would have to find someone with a v2 (or earlier) Bus Pirate and a firmware version >=v5.5 to test this. For Bus Pirate model v4 this patch may be completely superfluous. Anyway, activating fast UART only for some models is probably the way to go. We already have code to determine the hardware model in the init function, this just needs to be stored in some variable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- buspirate_spi.c | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/buspirate_spi.c b/buspirate_spi.c index d2ebc75..57da63a 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -178,7 +178,10 @@ static int buspirate_spi_shutdown(void *data) } /* Reset Bus Pirate (return to user terminal) */ bp_commbuf[0] = 0x0f; - ret = buspirate_sendrecv(bp_commbuf, 1, 0); + if ((ret = buspirate_sendrecv(bp_commbuf, 1, 0))) + goto out_shutdown; + if ((ret = serialport_config(sp_fd, 115200))) + goto out_shutdown; out_shutdown: /* Shut down serial port communication */ @@ -365,6 +368,45 @@ int buspirate_spi_init(void) spi_programmer_buspirate.command = buspirate_spi_send_command_v1; } + /* Increase PIC/FT232 UART speed to 2 Mbaud (instead of 115200 baud) in firmware 5.5 and newer. + * Although this is already possible in firmware 5.2, fast UART in combination with the old SPI + * command set causes hangs for bigger transactions. This is caused by a UART buffer overrun + * in the PIC, and all firmware versions up to (hopefully not including) 6.2 are affected. + */ + if (BP_FWVERSION(fw_version_major, fw_version_minor) >= BP_FWVERSION(5, 5)) { + // FIXME: Do this only for USB-based Bus Pirates... unless you're sure the UART can handle more. + int cmdlen; + /* Request setting the UART baud rate. */ + cmdlen = snprintf((char *)bp_commbuf, DEFAULT_BUFSIZE, "b\n"); + if ((ret = buspirate_sendrecv(bp_commbuf, cmdlen, 0))) + return ret; + if ((ret = buspirate_wait_for_string(bp_commbuf, ">"))) + return ret; + /* Request setting the UART clock divisor manually. */ + cmdlen = snprintf((char *)bp_commbuf, DEFAULT_BUFSIZE, "10\n"); + if ((ret = buspirate_sendrecv(bp_commbuf, cmdlen, 0))) + return ret; + if ((ret = buspirate_wait_for_string(bp_commbuf, ">"))) + return ret; + /* Set the UART clock divisor. New clock is 4000000/(divisor+1). */ + cmdlen = snprintf((char *)bp_commbuf, DEFAULT_BUFSIZE, "%i\n", 1); + if ((ret = buspirate_sendrecv(bp_commbuf, cmdlen, 0))) + return ret; + sleep(1); + if (serialport_config(sp_fd, 115200) != 0) + return 1; + bp_commbuf[0] = ' '; + if ((ret = buspirate_sendrecv(bp_commbuf, 1, 0))) + return ret; + if ((ret = buspirate_wait_for_string(bp_commbuf, "HiZ>"))) + return ret; + msg_pdbg("Using fast 2 Mbaud for Bus Pirate <-> host communication.\n"); + } else { + msg_pinfo("Bus Pirate firmware 5.4 and older does not support fast Bus Pirate <-> host " + "communication. Limiting UART speed to 115200 Baud.\n"); + msg_pinfo("It is recommended to upgrade to firmware 6.2 or newer.\n"); + } + /* Workaround for broken speed settings in firmware 6.1 and older. */ if (BP_FWVERSION(fw_version_major, fw_version_minor) < BP_FWVERSION(6, 2)) if (spispeed > 0x4) { -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH 0/7] Port serprog to Windows 2.0
by Stefan Tauner 01 Apr '13

01 Apr '13

On Thu, 3 Jan 2013 21:37:18 +0100 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Developing cross-platform is great! > If you look at 1/7 and have to puke, please don't blame me. > I got the win32 calls right eventually and tested this with wine > and my serprog flasher (which uses serial over USB). > I repeat: I used serial over USB inside wine to talk serprog. haha. > Tests with programmers using serial.c (e.g. buspirate) on all platforms > warmly welcomed. > > Stefan Tauner (7): > serial.c: abstract system error printing. > serial.c: round baudrates to valid ones. > Replace sp_sync_read_timeout() with serialport_read_nonblock(). > Introduce serialport_write_nonblock(). > Replace native calls in serprog with wrapper calls. > serial.c: be more pedantic. > Enable serprog on Windows. Self-acked and committed in r1659 to r1665 after testing it on real windows too. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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