I've just updated my solution to _the_ layout problem that I wrote last
year . I'm not asking for a review at this moment. There are at least
two competing approaches that I want to discuss first (I couldn't start
a discussion before I wrote it, due to time constraints).
1) walk over the given layout regions in an outer loop and
walk over the erase blocks in each region in an inner loop
This is how my patch tackles it.
2) walk over all erase blocks in an outer loop and
walk over the touched layout regions in an inner loop
Both sounds easy to do but it gets really complicated when you account
for a) regions that are not erase block aligned, b) our fallback to dif-
ferent erase functions (and blocks thereby) and c) read-locks that might
render a) impossible.
a) will always be the case when b) results in the erase chip function.
One pretty simple solution would be to exclude unaligned layout regions.
How about this? anybody ever needed it?
Another related thing is an optimization that I have in mind since ever
I used flashrom: Selection of the biggest possible erase block size.
Currently, if we erase/write say 16 blocks of 4KiB, we waste a lot of
time because most chips would erase a 64KiB block much faster. If we
ever add something like this, I guess it would be easier with approach
1). But maybe it'd be so invasive that it doesn't matter much...
Hello and thanks for your software.
Motherboard: MSI H87-G43 ( https://msi.com/Motherboard/H87-G43.html )
Old BIOS version: 2.2
New BIOS version: 2.A (2.10)
Remarks: Just followed your instructions, created backup of old ROM and
then wrote new image. No troubles at all. Did not save logs of flashrom,
so sorry if you would like to see them.