On Mon, 9 May 2016 20:46:18 -0700
David Hendricks <dhendrix(a)google.com> wrote:
> Hi Victor,
> From Flashrom's software perspective all chips with the same ID are
> indistinguishable.
>
> Part number often includes characteristics such as package and thermal
> tolerance which do not affect software compatibility.
However, we will add the new names to the in-program (and hence
wiki) database so that this new information becomes public. Thanks for
the heads up, Victor.
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner
Hi,
we're hitting the 80 column limit in our code in ways which actually
reduce readability for the code. Examples are various multiline messages
and complicated nested code where refactoring to a separate function
doesn't make sense.
Keeping the old 80 column limit is not really an option anymore.
Standard terminal sizes have one of 80, 100 or 132 columns.
Given the monitor resolutions many people have nowadays, I think it is
safe to say that you can fit two xterms with 100 columns horizonally
next to each other. 100 columns should also be sufficient for a msg_p*
of roughly 80 columns of text.
132 columns provide more leeway, but IMHO that would be too wide for
good readability (and my screen can't fit two xterms side-by-side anymore).
Of course some files have sections where any column limit is not
acceptable (board lists etc.), but the column limit violations should be
limited to the affected file sections, not whole files.
Comments?
I'd like to get this decided today or tomorrow so we know where we need
line breaks in Stefan Tauner's new struct flashchip patch.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
I have a spansion S25FL128P......X chip and can do some tests.
The "problem" is that i don't know if its an 0 or an 1.
On the chip i see only "FL128PIF" and one line lower i see "00299012 C".
Probing works (id1 0x01, id2 0x2018):
Calibrating delay loop... OK.
serprog: Programmer name is "serprog-duino"
Found Spansion flash chip "S25FL128P......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128P......1" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128S......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128S......1" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL129P......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL129P......1" (16384 kB, SPI) on serprog.
Multiple flash chip definitions match the detected chip(s):
"S25FL128P......0", "S25FL128P......1", "S25FL128S......0",
"S25FL128S......1", "S25FL129P......0", "S25FL129P......1"
Please specify which chip definition to use with the -c <chipname> option.
BTW: Chip was fund on a Dell-Systemboard.
Dear folks,
i am interested in using coreboot with a MacMini 2007 (core2duo). It
uses the same chipset (GM945) as the macbook2.1 which supported yet.
I managed to read infos about the BIOS with flashrom.
The verbose output is in the appendix.
Is there a chance, that coreboot could be ported to MacMini2007?
Bye
Micha
Dear Flashrom Hackers,
I wanted to put Libreboot for my GA-G41M-ES2L motherboard,
I downloaded the newest Libreboot rom and burned into the flashchip
from Debian Jessie, unfortunately my system don't boot anymore.
I have a backup from vendor BIOS from the 2 BIOS chips, I had made it
before flashing.
I know, I shouldn't reboot after this message(below the email) but I do
that, it was a mistake.
What was the problem:
1. Flashrom bug ?
2. Bad Libreboot rom file ?
----
I bought another GA-G41M-ES2L motherboard.
I plan to put a Coreboot to that with the latest flasrom. I compile
everything based on coreboot wiki.
https://www.coreboot.org/Board:gigabyte/ga-g41m-es2l
3. What do you suggest I do or I don't ?
4. Flashrom will kill the second one motherboard too ?
5. For the old one can I buy flashrom chips anywhere on the net ?
(I can't use external programmer, but I know guy who can change the bad
chip to a new one.)
-----------
I plan a 2. coreboot machine this board is: GA-945GCM-S2L motherboard.
6. Can I put a coreboot for that based this action on Coreboot wiki ?
https://www.coreboot.org/Board:gigabyte/ga-945gcm-s2l
Thanks for your help!
Zsolt
----------------------------------------------------------------------------------------------------------------------------------------------------------------
root@debian:/home/zsolt/BACKUP# flashrom -p internal:dualbiosindex=0 -w
ga-g41m-es2l_usqwerty_txtmode.rom
flashrom v0.9.7-r1782 on Linux 3.16.0-4-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
Found chipset "Intel ICH7/ICH7R". Enabling flash write... OK.
DualBIOS: Selected chip: 0
Found Macronix flash chip "MX25L8005/MX25V8005" (1024 kB, SPI) at
physical address 0xfff00000.
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Reading old flash chip contents... done.
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
root@debian:/home/zsolt/BACKUP# flashrom -p internal:dualbiosindex=1 -w
ga-g41m-es2l_usqwerty_txtmode.rom
flashrom v0.9.7-r1782 on Linux 3.16.0-4-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
Found chipset "Intel ICH7/ICH7R". Enabling flash write... OK.
DualBIOS: Selected chip: 1
Found Macronix flash chip "MX25L8005/MX25V8005" (1024 kB, SPI) at
physical address 0xfff00000.
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Trying to unmap a nonexisting mapping!
Please report a bug at flashrom(a)flashrom.org
Reading old flash chip contents... done.
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
flashrom v0.9.9-r1955 on Linux 4.10.3-1-zen (x86_64)
flashrom is free software, get the source code at https://flashrom.org
flashrom was built with libpci 3.4.1, GCC 5.3.0, little endian
Command line (5 args): flashrom -r test --programmer internal -VV
Calibrating delay loop... OS timer resolution is 1 usecs, 2662M loops
per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 990 us, 10000
myus = 9914 us, 4 myus = 4 us, OK.
Initializing internal programmer
No coreboot table found.
Using Internal DMI decoder.
No DMI table found.
W836xx enter config mode worked or we were already in config mode.
W836xx leave config mode had no effect.
Active config mode, unknown reg 0x20 ID: 85.
Found ITE EC, ID 0x8528, Rev 0x0a on port 0x4e.
Found chipset "Intel Broadwell U Premium" with PCI ID 8086:9cc3.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware
with it,
then please email a report to flashrom(a)flashrom.org including a verbose
(-V) log.
Thank you!
Enabling flash write... Root Complex Register Block address = 0xfed1c000
GCS = 0x61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (LPC)
Top Swap: enabled (A16(+) inverted)
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode enabled
0xffe00000/0xffa00000 FWH decode enabled
0xffd80000/0xff980000 FWH decode enabled
0xffd00000/0xff900000 FWH decode enabled
0xffc80000/0xff880000 FWH decode enabled
0xffc00000/0xff800000 FWH decode enabled
0xff700000/0xff300000 FWH decode enabled
0xff600000/0xff200000 FWH decode enabled
0xff500000/0xff100000 FWH decode enabled
0xff400000/0xff000000 FWH decode enabled
Maximum FWH chip size: 0x100000 bytes
SPI Read Configuration: prefetching enabled, caching enabled,
BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
SPIBAR = 0x00007fc4b0c76000 + 0x3800
0x04: 0xe008 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1
Reading OPCODES... done
OP Type Pre-OP
op[0]: 0x02, write w/ addr, none
op[1]: 0x3b, read w/ addr, none
op[2]: 0x20, write w/ addr, none
op[3]: 0x05, read w/o addr, none
op[4]: 0x9f, read w/o addr, none
op[5]: 0x01, write w/o addr, none
op[6]: 0x00, read w/o addr, none
op[7]: 0x00, read w/o addr, none
Pre-OP 0: 0x06, Pre-OP 1: 0x00
0x06: 0x3f00 (HSFC)
HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0
0x08: 0x00001000 (FADDR)
0x50: 0x00004a4b (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x4a, BRRA 0x4b
0x54: 0x00000000 0x58: 0x07ff01a0 FREG1: BIOS region
(0x001a0000-0x007fffff) is read-write.
0x5C: 0x019f0001 0x60: 0x00007fff FREG3: Gigabit Ethernet region is unused.
0x64: 0x00007fff FREG4: Platform Data region is unused.
0x74: 0x00000000 (PR0 is unused)
0x78: 0x00000000 (PR1 is unused)
0x7C: 0x00000000 (PR2 is unused)
0x80: 0x00000000 (PR3 is unused)
0x84: 0x00000000 (PR4 is unused)
Writes have been disabled for safety reasons. You can enforce write
support with the ich_spi_force programmer option, but you will most likely
harm your hardware! If you force flashrom you will get no support if
something breaks. On a few mainboards it is possible to enable write
access by setting a jumper (see its documentation or the board itself).
0x90: 0xc0 (SSFS)
SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
0x91: 0xf84010 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=0
0x94: 0x0006 (PREOP)
0x96: 0x043b (OPTYPE)
0x98: 0x05203b02 (OPMENU)
0x9C: 0x0000019f (OPMENU+4)
0xA0: 0x00000000 (BBAR)
0xC4: 0x80802025 (LVSCC)
LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xC8: 0x00002025 (UVSCC)
UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
0xD0: 0x50444653 (FPB)
Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.
=== Content Section ===
FLVALSIG 0x0ff0a55a
FLMAP0 0x02040003
FLMAP1 0x15100206
FLMAP2 0x00210120
--- Details ---
NR (Number of Regions): 3
FRBA (Flash Region Base Address): 0x040
NC (Number of Components): 1
FCBA (Flash Component Base Address): 0x030
ISL (ICH/PCH Strap Length): 21
FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100
NM (Number of Masters): 3
FMBA (Flash Master Base Address): 0x060
MSL/PSL (MCH/PROC Strap Length): 1
FMSBA (Flash MCH/PROC Strap Base Address): 0x200
=== Component Section ===
FLCOMP 0x40300044
FLILL 0xad604221
--- Details ---
Component 1 density: 8 MB
Component 2 is not used.
Read Clock Frequency: 20 MHz
Read ID and Status Clock Freq.: 20 MHz
Write and Erase Clock Freq.: 20 MHz
Fast Read is supported.
Fast Read Clock Frequency: 33 MHz
Dual Output Fast Read Support: disabled
Invalid instruction 0: 0x21
Invalid instruction 1: 0x42
Invalid instruction 2: 0x60
Invalid instruction 3: 0xad
=== Region Section ===
FLREG0 0x00000000
FLREG1 0x07ff01a0
FLREG2 0x019f0001
FLREG3 0x00007fff
FLREG4 0x00007fff
--- Details ---
Region 0 (Descr.) 0x00000000 - 0x00000fff
Region 1 (BIOS ) 0x001a0000 - 0x007fffff
Region 2 (ME ) 0x00001000 - 0x0019ffff
Region 3 (GbE ) is unused.
Region 4 (Platf.) is unused.
=== Master Section ===
FLMSTR1 0x0a0b0000
FLMSTR2 0x0c0d0000
FLMSTR3 0x08080118
--- Details ---
Descr. BIOS ME GbE Platf.
BIOS r rw rw
ME r rw rw
GbE rw
Enabling hardware sequencing because some important opcode is locked.
OK.
Super I/O ID 0x8528 is not on the list of flash-capable controllers.
The following protocols are supported: FWH, Programmer-specific.
Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing
reports 1 attached SPI flash chip with a density of 8192 kB.
The flash address space (0x000000 - 0x7fffff) is divided at address
0x653000 in two partitions.
The first partition ranges from 0x000000 to 0x652fff.
In that range are 1619 erase blocks with 4096 B each.
The second partition ranges from 0x653000 to 0x7fffff.
In that range are 429 erase blocks with 4096 B each.
Found Programmer flash chip "Opaque flash chip" (8192 kB,
Programmer-specific) mapped at physical address 0x0000000000000000.
Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xf3, id2
0xab, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xf3,
id2 0xab, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common:
id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content,
id2 is normal flash content
Found Programmer flash chip "Opaque flash chip" (8192 kB,
Programmer-specific).
Reading flash... Reading 8388608 bytes starting at 0x000000.
HSFS: FDONE=1, FCERR=1, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1
HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0
FAILED.
Restoring MMIO space at 0x7fc4b0c798a0
--
Cheers,
Umang Raghuvanshi.
Hi Zak,
please always keep the mailing list in CC, you will get less attention
otherwise.
On 23.03.2017 12:16, Nico Huber wrote:
>
> -------- Forwarded Message --------
> Subject: Re: [flashrom] Problem with flashrom and FT2232 Port B
> Date: Wed, 22 Mar 2017 18:01:18 +0100
> From: Zak <zackwarrior(a)gmail.com>
> To: Nico Huber <nico.huber(a)secunet.com>
>
> Yeah of course if another program is trying to access the device it can
> explain the error but i would not be able to get the port a either,
> since the device is used with another app, and i tryed it on few
> different computers and still get the same error
I was just guessing. The FT2232H has two separate USB interfaces, but
maybe it's impossible to block one interface without the other, idk.
>
> It's only on the port B, I already submitted this error a year aggo or
> more but wasn't patched
It's working fine on ArchLinux here (see attached log). I don't have
access to a Windows installation and no intend to fix anything there.
It's possible that you ask for something that only you are interested
in. I guess you have to fix it by yourself then.
Nico
Hi,
I added PCI ID for my chipset, but I can't access/ read FLash chip. Any
idea how to proceed?
Regards,
Michael!
[root@revo flashrom]# diff chipset_enable.c.bak chipset_enable.c
1783a1784
> {0x8086, 0xa144, NT, "Intel", "Sunrise Point-H",
enable_flash_pch9},
-------------------------------------------------------
[root@revo flashrom]# ./flashrom -V -p internal
flashrom v0.9.9-r1954 on Linux 4.9.13-201.fc25.x86_64 (x86_64)
flashrom is free software, get the source code at https://flashrom.org
flashrom was built with libpci 3.5.4, GCC 6.3.1 20161221 (Red Hat
6.3.1-1), little endian
Command line (3 args): ./flashrom -V -p internal
Calibrating delay loop... OS timer resolution is 1 usecs, 2789M loops
per second, 10 myus = 10 us, 100 myus = 104 us, 1000 myus = 1014 us,
10000 myus = 10007 us, 4 myus = 4 us, OK.
Initializing internal programmer
No coreboot table found.
Using Internal DMI decoder.
DMI string chassis-type: "Desktop"
DMI string system-manufacturer: "Shuttle Inc."
DMI string system-product-name: "XH170"
DMI string system-version: "V1.0"
DMI string baseboard-manufacturer: "Shuttle Inc."
DMI string baseboard-product-name: "FH170"
DMI string baseboard-version: "1.0"
Found ITE Super I/O, ID 0x8772 on port 0x2e
Found chipset "Intel Sunrise Point-H" with PCI ID 8086:a144.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware
with it,
then please email a report to flashrom(a)flashrom.org including a verbose
(-V) log.
Thank you!
Enabling flash write... Root Complex Register Block address = 0x0
Error accessing ICH RCRB, 0x4000 bytes at 0x0000000000000000
/dev/mem mmap failed: Resource temporarily unavailable
FAILED!
FATAL ERROR!
Error: Programmer initialization failed.
