flashrom April 2016

flashrom@flashrom.org

28 participants
35 discussions

by Antonio Estrada Respeto

I have tried the below flashrom option (code tested) in order to find a right response on my no name VT6421A pci sata card, but no luck. Environment is Freedos in an usb boot sdcard device in a standard PC. Address was from 0xffff0000 to others. The card is found by flashrom at 1106:3249 BDF 02:0b.0 . The card has an Eprom flashable sst39Vf512 at is printed in top of it. Final messages are: Requested bar is of type rom. Error: No suported PCI found. Error: Program initialization failed. I managed flashrom to work with my 3C905TX and do it in the same environment as a charm. I know VT6421A hardware is very tricky depending on every pci maker. The final goal is to flash a 64k boot rom ins this card. Any help will be wellcome. Thanks in advance. The code tested: flashrom –p atavia offset=(different address) –V

5 years

Re: [flashrom] [PATCH] 4 byte address mode for Macronix MX25L25735F

by Tim Chick

Hi David, There was a mistake in the logic, which I have corrected. I was also asked by someone else on the list if it worked with the MX25L25635F, which is 32Mbytes, but uses 3-byte addressing by default. So I made the attached changes, which switch the chip to 4-byte mode. It also has some dedicated 4-byte commands, and a BAR register, but it seemed easiest to just use what I had tested for the MX25L25735F. I can’t actually test the MX25L25635F though, as I don’t have one. Thanks, Tim From: David Hendricks [mailto:dhendrix@google.com] Sent: 04 April 2016 23:21 To: Tim Chick Cc: flashrom(a)flashrom.org Subject: Re: [flashrom] [PATCH] 4 byte address mode for Macronix MX25L25735F On Thu, Mar 31, 2016 at 8:21 AM, Tim Chick <Tim.Chick(a)mediatek.com<mailto:Tim.Chick@mediatek.com>> wrote: Hi List, Flashrom would not detect this chip. When the definition was added, everything failed as the chip only supports 4 byte address operation. Interesting - I didn't know such chips existed. The ones I've used have backwards-compatible commands that support 3-byte addresses. FYI - Some other high-capacity chips have 4-byte address enable bit in a config register that will make the usual read/write/erase instructions accept 4 byte addresses. And yet other large chips have alternative instructions that function the same but only accept a 4-byte address. The attached patch adds 4 byte address support for 4 byte only chips, as determined by the JEDEC flash parameter table, and support for this chip specifically. I’ve only allowed it to work with the SPI_CONTROLLER_FT2232 controller, as that is the only one I have to test. I’ve also only ported spi_block_erase_20 – the other block erase functions will fail. Please let me know what you think! Good stuff! FWIW, I have a work-in-progress patch on chromium.org<http://chromium.org> (https://chromium-review.googlesource.com/#/c/323359/) for the other types of high-capacity flash chips. I've tested on a Spansion S25FS256 using linux_spi and ft2232. It needs a lot of clean-up, but might be of help. Most of the changes were to convert read/write/erase functions to use allocated buffers whose length depends on whether we're using a 3- or 4-byte address. I'll borrow some ideas from your patch as well to support the "4-byte address only" chips. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

5 years

[PATCH] 4 byte address mode for Macronix MX25L25735F

by Tim Chick

Hi List, Flashrom would not detect this chip. When the definition was added, everything failed as the chip only supports 4 byte address operation. The attached patch adds 4 byte address support for 4 byte only chips, as determined by the JEDEC flash parameter table, and support for this chip specifically. I've only allowed it to work with the SPI_CONTROLLER_FT2232 controller, as that is the only one I have to test. I've also only ported spi_block_erase_20 - the other block erase functions will fail. Please let me know what you think! Thanks, Tim

5 years

[PATCH] Add support for GD25Q21B, GD25Q41B, GD25Q80C and GD25Q16C

by Hatim Kanchwala

Hello, This patch supersedes the corresponding one I sent earlier as part of a chain (http://patchwork.coreboot.org/patch/4420). Stefan's suggestions on previous patches (discussed on list and IRC) are incorporated. The new definitions are combined with their counterparts. Thanks. :) Signed-off-by: Hatim Kanchwala <hatim(a)hatimak.me> --- flashchips.c | 28 ++++++++++++++++------------ flashchips.h | 4 ++-- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/flashchips.c b/flashchips.c index 40b6b8e..7947256 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5933,37 +5933,38 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_60, }, { .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_bp4_srwd, .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25Q20(B)", + .name = "GD25Q20(B)/GD25Q21B", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q20, .total_size = 256, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP (GD25Q21B only): 1536B total; read 0x48, write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 64} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 8} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 4} }, .block_erase = spi_block_erase_d8, }, { @@ -5971,76 +5972,78 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_60, }, { .eraseblocks = { {256 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_bp4_srwd, .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25Q40(B)", + .name = "GD25Q40(B)/GD25Q41B", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q40, .total_size = 512, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + /* OTP (GD25Q41B only): 1536B total; read 0x48, write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 16} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 8} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_bp4_srwd, .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25Q80(B)", + .name = "GD25Q80(B)(C)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q80, .total_size = 1024, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 (B version only) */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + /* OTP: 1024B total; read 0x48, write 0x42, erase 0x44 (B and C revisions only) */ + /* supports SFDP (C revision only) */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 256} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 32} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 16} }, .block_erase = spi_block_erase_d8, }, { @@ -6048,38 +6051,39 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_60, }, { .eraseblocks = { {1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_bp4_srwd, .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25Q16(B)", + .name = "GD25Q16(B)(C)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q16, - .total_size = 2048, + .total_size = 2* 1024, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 (B version only) */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + /* OTP: 1024B total; read 0x48, write 0x42, erase 0x44 (B and C revisions only) */ + /* supports SFDP (C revision only) */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 512} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 64} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 32} }, .block_erase = spi_block_erase_d8, }, { diff --git a/flashchips.h b/flashchips.h index 9ffb30f..997b3cb 100644 --- a/flashchips.h +++ b/flashchips.h @@ -353,32 +353,32 @@ #define FUJITSU_MBM29LV008TA 0x3E #define FUJITSU_MBM29LV080A 0x38 #define FUJITSU_MBM29LV200BC 0xBF #define FUJITSU_MBM29LV200TC 0x3B #define FUJITSU_MBM29LV400BC 0xBA #define FUJITSU_MBM29LV400TC 0xB9 #define FUJITSU_MBM29LV800BA 0x5B /* Same as MBM29LV800BE */ #define FUJITSU_MBM29LV800TA 0xDA /* Same as MBM29LV800TE */ #define FUJITSU_MBM29LV160BE 0x49 /* 16 b mode 0x2249 */ #define FUJITSU_MBM29LV160TE 0xC4 /* 16 b mode 0x22C4 */ #define GIGADEVICE_ID 0xC8 /* GigaDevice */ #define GIGADEVICE_GD25T80 0x3114 #define GIGADEVICE_GD25Q512 0x4010 #define GIGADEVICE_GD25Q10 0x4011 -#define GIGADEVICE_GD25Q20 0x4012 /* Same as GD25QB */ -#define GIGADEVICE_GD25Q40 0x4013 /* Same as GD25QB */ +#define GIGADEVICE_GD25Q20 0x4012 /* Same as GD25Q21B which supports OTP */ +#define GIGADEVICE_GD25Q40 0x4013 /* Same as GD25Q41B which supports OTP */ #define GIGADEVICE_GD25Q80 0x4014 /* Same as GD25Q80B (which has OTP) */ #define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */ #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B and GD25Q128C only, can be distinguished by SFDP */ #define GIGADEVICE_GD25VQ21B 0x4212 #define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ #define GIGADEVICE_GD25VQ80C 0x4214 #define GIGADEVICE_GD25VQ16C 0x4215 #define GIGADEVICE_GD25LQ40 0x6013 #define GIGADEVICE_GD25LQ80 0x6014 #define GIGADEVICE_GD25LQ16 0x6015 #define GIGADEVICE_GD25LQ32 0x6016 #define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ #define GIGADEVICE_GD25LQ128 0x6018 -- Regards, Hatim Kanchwala http://hatimak.me B. Tech. Electrical Engineering Indian Institute of Technology Patna

5 years

Programming N25Q128

by Steve Miller

FYI, This is informational only. I can program the ROM. When programming the N25Q128 from the Raspberry PI, I will get verification errors. If I push it up the hill several times, it will eventually pass. The N25Q128 remains on the target board, I am hold the ARM processor on that board in RESET. The Raspberry PI is attached via a ribbon cable and 100 ohm series resistors. Since my system is unique, it is entirely possible that this is just an artifact of my setup. However, the message as pasted below, asked me to report it, so I am doing that. I tried both the release and the latest snapshot. Both seem to operate the same. I tried three different target boards with the N25Q128 and all operate the same. Verification fails, but if I repeat the programming operation several times, it will pass. Please note the message at the end. The previous program and verify attempt failed. However, when I tried again, it aborted early because what I was attempting to program into the part already matched the parts contents. AKA, nothing to do. ---- Steve ************************************************************************************************************* Verifying flash... FAILED at 0x00022f00! Expected=0x61, Found=0xff, failed byte count from 0x00000000-0x00ffffff: 0x100 Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! Verifying flash... FAILED at 0x0001cc92! Expected=0x83, Found=0x9f, failed byte count from 0x00000000-0x00ffffff: 0x68 Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! Warning: Chip content is identical to the requested image. Erase/write done.

5 years

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flashrom April 2016