flashrom April 2015

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W836xx: GIGABYTE GA-MA785GMT-UD2H rev 1.1 : flashrom -V
by George Chriss 04 Apr '15

04 Apr '15

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Re: [flashrom] [PATCH] add support for Pm25LQ032
by Stefan Tauner 04 Apr '15

04 Apr '15

On Sat, 14 Mar 2015 15:00:10 +0000 Steven Honeyman <stevenhoneyman(a)gmail.com> wrote: > I found this in a Chinese router, read tested (twice, successful) but > not yet write/erase tested. > Based on information from the datasheet at > http://www.chingistek.com/img/Product_Files/Pm25LQ032C%20datasheet%20v1.6.1… > > Signed-off-by: Steven Honeyman <stevenhoneyman(a)gmail.com> Hi Steven, thanks for your patch. There are a number of similar chips (Pm25LQ020, Pm25LQ040, Pm25LQ080, Pm25LQ016). Do you want to add support for them too? > Index: flashchips.c > =================================================================== > --- flashchips.c (revision 1888) > +++ flashchips.c (working copy) > @@ -9708,8 +9708,46 @@ > .voltage = {2700, 3600}, /* 2.3-3.6V for Pm25LD040 */ > }, > > -{ > + { > .vendor = "PMC", > + .name = "Pm25LQ032", Have you found any traces of a Pm25LQ032 without a C suffix? I don't and would rather add the C suffix here (and in the ID macro) until we have proof they really exist. > + .bustype = BUS_SPI, > + .manufacture_id = PMC_ID, > + .model_id = PMC_PM25LQ032, > + .total_size = 4096, > + .page_size = 256, > + .feature_bits = FEATURE_WRSR_WREN, Missing OTP flag and information. > + .tested = TEST_OK_PR, > + .probe = probe_spi_rdid, > + .probe_timing = TIMING_ZERO, > + .block_erasers = > + { > + { > + .eraseblocks = { {4 * 1024, 1024} }, > + .block_erase = spi_block_erase_20, /* sector erase */ All these comments are redundant. Experienced flashrom hacker will instantly deduce that from the erase block size(s). > + }, { > + .eraseblocks = { {4 * 1024, 1024} }, > + .block_erase = spi_block_erase_d7, /* sector erase */ > + }, { > + .eraseblocks = { {64 * 1024, 64} }, > + .block_erase = spi_block_erase_d8, /* block erase */ > + }, { > + .eraseblocks = { {4096 * 1024, 1} }, > + .block_erase = spi_block_erase_60, /* chip erase */ > + }, { > + .eraseblocks = { {4096 * 1024, 1} }, > + .block_erase = spi_block_erase_c7, /* chip erase */ > + } > + }, > + .printlock = spi_prettyprint_status_register_bp3_srwd, bit 6 is quad enable > + .unlock = spi_disable_blockprotect_bp3_srwd, > + .write = spi_chip_write_256, > + .read = spi_chip_read, /* Fast read (0x0B), dual I/O > supported */ Actually it supports even multi I/O > + .voltage = {2700, 3600}, /* 2.7-3.6V for Pm25Q032 */ The comment there is redundant (and contains a typo). We only comment the cases where multiple chips share the same ID but have different voltage ranges. The smaller range goes into the code, the broader one gets commented. > + }, > + > + { > + .vendor = "PMC", > .name = "Pm25LV512(A)", > .bustype = BUS_SPI, > .manufacture_id = PMC_ID_NOPREFIX, > Index: flashchips.h > =================================================================== > --- flashchips.h (revision 1888) > +++ flashchips.h (working copy) > @@ -560,6 +560,7 @@ > #define PMC_PM25LD512 0x20 /* Same as Pm25LD512C, but the > latter has more locking options. */ > #define PMC_PM25LD010 0x21 /* Same as Pm25LD010C, but the > latter has more locking options. */ > #define PMC_PM25LD020 0x22 /* Same as Pm25LD020C, but the > latter has more locking options. */ > +#define PMC_PM25LQ032 0x46 > #define PMC_PM25LV512 0x7B /* Same as Pm25LV512A */ > #define PMC_PM25LV010 0x7C /* Same as Pm25LV010A, but the > former does not support RDID but RES3 only. */ > #define PMC_PM25LV020 0x7D The important parts are all correct and I think erase/write should just work, thank you. If you plan to add the other members of this chip's family please supersede this patch with the new one and include the corrections mentioned above. If you do not want to add them please say so and I'll correct it myself before committing. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Results for "AT45DB321D"
by The Raven 04 Apr '15

04 Apr '15

Hi All Operations work fine! Chip can be marked as tested.

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Re: [flashrom] Intel 28F001BN/BX-T erase/write operation verified on 3C905B-TXNM
by Stefan Tauner 04 Apr '15

04 Apr '15

On Sun, 4 Jan 2015 01:36:53 +0800 Lu Xie <lxie1(a)andrew.cmu.edu> wrote: > Hi, > > I performed another erase and 5 write operations on that chip with the same > network adapter. Hopefully it has some useful data here. > I flashed the chip with different BIOS's and they work on their desired > boards. Hello Lu, thanks for your effort! I just wanted to make sure everything is fine, hence my question. I have marked the flash chip as fully tested and will commit that later together with other small changes. Sorry for the delay. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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my new motherboard
by Big Valley Radio 04 Apr '15

04 Apr '15

so new it does not work! I need sound for Rivendell. Everything else seems to function. Attached file should have what you need to know. ASROCK H81M-DGS R2.0 Intel CPU thanks for being there! I spent a few days on this regards Robert Jeffares

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Re: [flashrom] [PATCH] New GigaDevice chips
by Stefan Tauner 03 Apr '15

03 Apr '15

On Mon, 9 Mar 2015 10:18:36 +1000 Roman Titov <titovroman(a)gmail.com> wrote: Hello Roman! > Well, I think this could be the result of my inexperience with svn > (and git-svn). > > So, here's my steps: > 1. git svn clone -rHEAD (r1887, to be exact) flashrom-trunk (I have an > error, when I'm trying to make full git svn clone, looks like git bug > :/) > 2. *code* > 3. make 2 local commits > 4. git format-patch, and it throw me 2 patches for 2 latest commits > not over current origin (and I think thats is the reason) > 5. send patches to mailing list That's perfectly fine and how I work too (well, I use git send-email for 4 and 5). > My suggestions would be: > 1. shallow copying broke smth (idea, that git svn could bond git stuff > to full svn history stuff came to me just right now) > 2. formating 2 patches broke smth > 3. both? The problem is/was the last hunk. I guess you have opened the patch file in an editor that removes white space at the end of lines. The patch application does not seem to care but git-am does. Anyway, here is a list of things I have noticed in the patch. > From 3612049b7f6b2283ae4e593e66f369144b9e997b Mon Sep 17 00:00:00 2001 > From: Roman Titov <titovroman(a)gmail.com> > Date: Fri, 6 Mar 2015 17:18:43 +1000 > Subject: [PATCH 1/2] flashchips: new GigaDevice chips (GD25LQ40, GD25LQ80, > GD25LQ16, GD25LQ64(B), GD25LQ128) > > Signed-off-by: Roman Titov <titovroman(a)gmail.com> > > --- > flashchips.c | 197 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 196 insertions(+), 1 deletion(-) > > diff --git a/flashchips.c b/flashchips.c > index 8b5d1ec..31541ea 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -5466,6 +5466,123 @@ const struct flashchip flashchips[] = { > > { > .vendor = "GigaDevice", > + .name = "GD25LQ40", > + .bustype = BUS_SPI, > + .manufacture_id = GIGADEVICE_ID, > + .model_id = GIGADEVICE_GD25LQ40, > + .total_size = 512, > + .page_size = 256, > + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ > + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, > + .tested = TEST_OK_PREW, According to the line above and the respective ones later, you had all that hardware at hand and tested it successfully. Correct me if I am wrong, but I don't think that's the case ;) > + .probe = probe_spi_rdid, > + .probe_timing = TIMING_ZERO, > + .block_erasers = > + { > + { > + .eraseblocks = { {4 * 1024, 128} }, > + .block_erase = spi_block_erase_20, > + }, { > + .eraseblocks = { {32 * 1024, 16} }, > + .block_erase = spi_block_erase_52, > + }, { > + .eraseblocks = { {64 * 1024, 8} }, > + .block_erase = spi_block_erase_d8, > + }, { > + .eraseblocks = { {512 * 1024, 1} }, > + .block_erase = spi_block_erase_60, > + }, { > + .eraseblocks = { {512 * 1024, 1} }, > + .block_erase = spi_block_erase_c7, > + } > + }, > + .printlock = spi_prettyprint_status_register_bp4_srwd, > + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ > + .write = spi_chip_write_256, > + .read = spi_chip_read, The chips support multiple read and opcodes (unlike flashrom yet!). We note that at least for new chips by adding a comment like this: /* Fast read (0x0B) and multi I/O supported */ (cf. with similar comments throughout the file). > + .voltage = {1700, 1950}, It should actually be 1695, 1950 instead. This is also an error in the existing definition of the GD25LQ32. Apart from these repeated copy & paste errors it looks good. Please fix them so that I can commit your first flashrom contribution, thanks! Have you noticed any differences between the GD25LQ64 and its B revision? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1889 - trunk
by repository service 03 Apr '15

03 Apr '15

Author: stefanct Date: Fri Apr 3 23:29:04 2015 New Revision: 1889 URL: http://flashrom.org/trac/flashrom/changeset/1889 Log: Add support for more GigaDevice GD25LQ chips. Namely GD25LQ40, GD25LQ80, GD25LQ16, GD25LQ64(B), GD25LQ128. Signed-off-by: Roman Titov <titovroman(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Mar 1 23:12:16 2015 (r1888) +++ trunk/flashchips.c Fri Apr 3 23:29:04 2015 (r1889) @@ -5466,6 +5466,123 @@ { .vendor = "GigaDevice", + .name = "GD25LQ40", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ40, + .total_size = 512, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1695, 1950}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25LQ80", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ80, + .total_size = 1024, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1695, 1950}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25LQ16", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ16, + .total_size = 2048, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1695, 1950}, + }, + + { + .vendor = "GigaDevice", .name = "GD25LQ32", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, @@ -5499,8 +5616,86 @@ .printlock = spi_prettyprint_status_register_bp4_srwd, .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {1700, 1950}, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1695, 1950}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25LQ64(B)", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ64, + .total_size = 8192, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1695, 1950}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25LQ128", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ128, + .total_size = 16384, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1695, 1950}, }, {

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Re: [flashrom] Macronix MX23L6454 probe/read success (buspirate_spi)
by Stefan Tauner 03 Apr '15

03 Apr '15

On Sat, 14 Mar 2015 14:40:37 +0000 Steven Honeyman <stevenhoneyman(a)gmail.com> wrote: > On 8 March 2015 at 04:48, Steven Honeyman <stevenhoneyman(a)gmail.com> wrote: > > On 8 March 2015 at 00:46, Steven Honeyman <stevenhoneyman(a)gmail.com> wrote: > > > > ...ok definitely a false positive on the "works OK" status! > > 3rd resolder, 8th read attempt now. I haven't got two matching files > > yet. It keeps missing chunks out, at regular intervals, but different > > positions each time. > > > > I'm happy to upload/send the files & logs somewhere if they'd be useful to you? > > > > Tomorrow I'll try and find something else that will recognise & read > > this. The chip came from a working board so I know the ROM is good. > > OK, I finally got chance to make a little adapter board for > buspirate->soic16 spi... success! > It would seem that a set of ~20cm BP wires are too long for this to > work reliably, because with the adapter it worked first/every time: > > (the two other identical files came from a 'universal programmer' and > its own software) > […] > Found Macronix flash chip "MX23L6454" (8192 kB, SPI). > This chip's main memory can not be erased/written by design. > === > This flash part has status UNTESTED for operations: PROBE READ > The test status of this chip may have been updated in the latest development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above operations > work correctly for you with this flash chip. Please include the flashrom log > file for all operations you tested (see the man page for details), and mention > which mainboard or programmer you tested in the subject line. > Thanks for your help! > Reading flash... done. > Raw bitbang mode version 1 > Bus Pirate shutdown completed. > > > $ md5sum *.bin* > 6d7cf06448bd5ea941a4b458b6067e5f 25l6445.bin > 6d7cf06448bd5ea941a4b458b6067e5f 25l6465.bin > 6d7cf06448bd5ea941a4b458b6067e5f flashrom_mx23l6454.bin > 6d7cf06448bd5ea941a4b458b6067e5f flashrom_mx23l6454.bin2 Thanks for the update. I have marked the flash chip as tested and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Support for AT25080
by Roy Krikke 03 Apr '15

03 Apr '15

I know C coding and I also know some thing or two about hardware. But tip on how to add this specific device to flashrom are welcome. On 18-3-2015 22:42, Idwer Vollering wrote: > 2015-03-18 22:24 GMT+01:00 Roy Krikke <roykrikke(a)gmail.com>: >> Hello, >> >> I have compiled the latest version of flashrom (flashrom v0.9.8-r1887) and >> hoped to flash my AT25080. But without suc6. > flashrom does not (yet) support this chip. We like patches :) > >> I have connected a new AT25080 to a Raspberry Pi and hoped to flash the >> device with in system programming (ISP) mode. >> >> First erasing the device with sudo flashrom -E -V -p >> linux_spi:dev=/dev/spidev0.0 > The command line command looks just fine, but flashrom doesn't support > this particular flash chip, > >> No luke :( >> >> snapshot of flashrom below: >> Probing for Generic unknown SPI chip (RDID), 0 kB: RDID byte 0 parity >> violation. probe_spi_rdid_generic: id1 0x00, id2 0x00 >> Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI) on linux_spi. >> Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0x0, >> id2 0x0 >> Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI). >> === >> This flash part has status NOT WORKING for operations: PROBE READ ERASE >> WRITE >> The test status of this chip may have been updated in the latest development >> version of flashrom. If you are running the latest development version, >> please email a report to flashrom(a)flashrom.org if any of the above >> operations >> work correctly for you with this flash chip. Please include the flashrom log >> file for all operations you tested (see the man page for details), and >> mention >> which mainboard or programmer you tested in the subject line. >> Thanks for your help! >> Read is not working on this chip. Aborting. >> >> Any kind of help is welcome, tips on how best to proceed! >> >> >> Thank you very much, >> >> Roy >> >> >> >> My previous post >> -------------------------------------------------------------------------------- >> Hello, >> >> Is there support for the AT25080B device from ATMEL? It is not in the >> supported device list. >> >> http://www.atmel.com/Images/Atmel-5228-SEEPROM-AT25080B-160B-Datasheet.pdf >> >> Need to flash the AT25080B which is connected to a 82574L from intel. There >> are two 82574L with two AT25080B on my board. If I read from the first >> AT25080B the data is fine and I can also flash is. But the second one is not >> working at all. >> >> I compared/checked the SPI communication of the first one with the second >> one. This looks the same. So I thought maybe the second AT25080B is broken. >> After replacing it, still the same result. >> >> I hope to get is to work if I could flash is not by the SPI interface of the >> 82574L, but by an in system programming (ISP). Example shown in >> http://satxhackers.org/wp/hack-content/uploads/2013/04/rPI_flashrom.pdf >> >> Any kind of help is welcome. >> >> Thanks, >> >> Roy >> >> >> >> >> _______________________________________________ >> flashrom mailing list >> flashrom(a)flashrom.org >> http://www.flashrom.org/mailman/listinfo/flashrom > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom

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Re: [flashrom] Flashrom not finding BIOS flash on HP DL585 G2
by Stefan Tauner 03 Apr '15

03 Apr '15

On Thu, 19 Mar 2015 21:27:18 +0000 Paul Lalonde <Paul.Lalonde(a)telecomcomputer.com> wrote: > Unless there is another way to perform a BIOS flash backup of an HP ProLiant DL585 G2 server, I'd like to use flashrom for this. > > Results of flashrom -V -p internal, lspci, and superiotool are attached. Hi, I think you have found an old but still unsupported flash chip in that server. From some lines in the log output I think it is plausible that it is a Macronix MX29LV320DT or MX29LV321DT. It would be great if you could verify that visually if that's possible. I can probably add support for the chip without too much problems... but I am not sure if you would want to test it on that hardware if it is somewhat important to you...? :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom April 2015