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August 2014
- 34 participants
- 110 discussions
Begin to move functions that clearly belong to the (command line)
user interface out of flashrom's core files like flashrom.c.
- Refine messages within check_chip_supported() and move it to newly
created cli_common.c.
- Move flashbuses_to_text() to cli_common.c as well.
- Move global verbosity variables to cli_output.c.
---
Other things that should be moved elsewhere because they do not embody
core functionality but dictate command syntax and thereby become part of
the UI:
board_parse_parameter(),
all code regarding extract_programmer_param (the parameters should be
stored in a machine-readable form in struct flashctx instead),
TBC
Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at>
---
Makefile | 2 +-
cli_common.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
cli_output.c | 3 ++
flash.h | 9 +++--
flashrom.c | 70 -----------------------------------
print.c | 33 -----------------
programmer.h | 1 -
7 files changed, 127 insertions(+), 108 deletions(-)
create mode 100644 cli_common.c
diff --git a/Makefile b/Makefile
index d0d6454..98230a5 100644
--- a/Makefile
+++ b/Makefile
@@ -363,7 +363,7 @@ LIB_OBJS = layout.o flashrom.o udelay.o programmer.o helpers.o
###############################################################################
# Frontend related stuff.
-CLI_OBJS = cli_classic.o cli_output.o print.o
+CLI_OBJS = cli_classic.o cli_output.o cli_common.o print.o
# Set the flashrom version string from the highest revision number of the checked out flashrom files.
# Note to packagers: Any tree exported with "make export" or "make tarball"
diff --git a/cli_common.c b/cli_common.c
new file mode 100644
index 0000000..078c1f8
--- /dev/null
+++ b/cli_common.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de>
+ * Copyright (C) 2009 Carl-Daniel Hailfinger
+ * Copyright (C) 2011-2014 Stefan Tauner
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include "flash.h"
+
+/*
+ * Return a string corresponding to the bustype parameter.
+ * Memory is obtained with malloc() and must be freed with free() by the caller.
+ */
+char *flashbuses_to_text(enum chipbustype bustype)
+{
+ char *ret = calloc(1, 1);
+ /*
+ * FIXME: Once all chipsets and flash chips have been updated, NONSPI
+ * will cease to exist and should be eliminated here as well.
+ */
+ if (bustype == BUS_NONSPI) {
+ ret = strcat_realloc(ret, "Non-SPI, ");
+ } else {
+ if (bustype & BUS_PARALLEL)
+ ret = strcat_realloc(ret, "Parallel, ");
+ if (bustype & BUS_LPC)
+ ret = strcat_realloc(ret, "LPC, ");
+ if (bustype & BUS_FWH)
+ ret = strcat_realloc(ret, "FWH, ");
+ if (bustype & BUS_SPI)
+ ret = strcat_realloc(ret, "SPI, ");
+ if (bustype & BUS_PROG)
+ ret = strcat_realloc(ret, "Programmer-specific, ");
+ if (bustype == BUS_NONE)
+ ret = strcat_realloc(ret, "None, ");
+ }
+ /* Kill last comma. */
+ ret[strlen(ret) - 2] = '\0';
+ ret = realloc(ret, strlen(ret) + 1);
+ return ret;
+}
+
+
+void check_chip_supported(const struct flashchip *chip)
+{
+ if (chip->feature_bits & FEATURE_OTP) {
+ msg_cdbg("This chip may contain one-time programmable memory. flashrom cannot read\n"
+ "and may never be able to write it, hence it may not be able to completely\n"
+ "clone the contents of this chip (see man page for details).\n");
+ }
+
+ if ((chip->tested.erase == NA) && (chip->tested.write == NA)) {
+ msg_cdbg("This chip's main memory can not be erased/written by design.\n");
+ }
+
+ if ((chip->tested.probe == BAD) || (chip->tested.probe == NT) ||
+ (chip->tested.read == BAD) || (chip->tested.read == NT) ||
+ (chip->tested.erase == BAD) || (chip->tested.erase == NT) ||
+ (chip->tested.write == BAD) || (chip->tested.write == NT)){
+ msg_cinfo("===\n");
+ if ((chip->tested.probe == BAD) ||
+ (chip->tested.read == BAD) ||
+ (chip->tested.erase == BAD) ||
+ (chip->tested.write == BAD)) {
+ msg_cinfo("This flash part has status NOT WORKING for operations:");
+ if (chip->tested.probe == BAD)
+ msg_cinfo(" PROBE");
+ if (chip->tested.read == BAD)
+ msg_cinfo(" READ");
+ if (chip->tested.erase == BAD)
+ msg_cinfo(" ERASE");
+ if (chip->tested.write == BAD)
+ msg_cinfo(" WRITE");
+ msg_cinfo("\n");
+ }
+ if ((chip->tested.probe == NT) ||
+ (chip->tested.read == NT) ||
+ (chip->tested.erase == NT) ||
+ (chip->tested.write == NT)) {
+ msg_cinfo("This flash part has status UNTESTED for operations:");
+ if (chip->tested.probe == NT)
+ msg_cinfo(" PROBE");
+ if (chip->tested.read == NT)
+ msg_cinfo(" READ");
+ if (chip->tested.erase == NT)
+ msg_cinfo(" ERASE");
+ if (chip->tested.write == NT)
+ msg_cinfo(" WRITE");
+ msg_cinfo("\n");
+ }
+ msg_cinfo("The test status of this chip may have been updated in the latest development\n"
+ "version of flashrom. If you are running the latest development version,\n"
+ "please email a report to flashrom(a)flashrom.org if any of the above operations\n"
+ "work correctly for you with this flash chip. Please include the flashrom log\n"
+ "file for all operations you tested (see the man page for details), and mention\n"
+ "which mainboard or programmer you tested in the subject line.\n"
+ "Thanks for your help!\n");
+ }
+}
+
diff --git a/cli_output.c b/cli_output.c
index 5eff1c0..feafbd2 100644
--- a/cli_output.c
+++ b/cli_output.c
@@ -25,6 +25,9 @@
#include <errno.h>
#include "flash.h"
+int verbose_screen = MSG_INFO;
+int verbose_logfile = MSG_DEBUG2;
+
#ifndef STANDALONE
static FILE *logfile = NULL;
diff --git a/flash.h b/flash.h
index 8271da9..82a8b74 100644
--- a/flash.h
+++ b/flash.h
@@ -238,7 +238,6 @@ uint32_t chip_readl(const struct flashctx *flash, const chipaddr addr);
void chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
/* print.c */
-char *flashbuses_to_text(enum chipbustype bustype);
int print_supported(void);
void print_supported_wiki(void);
@@ -251,8 +250,6 @@ char *strcat_realloc(char *dest, const char *src);
void tolower_string(char *str);
/* flashrom.c */
-extern int verbose_screen;
-extern int verbose_logfile;
extern const char flashrom_version[];
extern const char *chip_to_probe;
void map_flash_registers(struct flashctx *flash);
@@ -285,7 +282,13 @@ int write_buf_to_file(const unsigned char *buf, unsigned long size, const char *
*/
#define ERROR_FLASHROM_LIMIT -201
+/* cli_common.c */
+char *flashbuses_to_text(enum chipbustype bustype);
+void check_chip_supported(const struct flashchip *chip);
+
/* cli_output.c */
+extern int verbose_screen;
+extern int verbose_logfile;
#ifndef STANDALONE
int open_logfile(const char * const filename);
int close_logfile(void);
diff --git a/flashrom.c b/flashrom.c
index 3f29e6d..eeed90b 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -42,11 +42,8 @@
const char flashrom_version[] = FLASHROM_VERSION;
const char *chip_to_probe = NULL;
-int verbose_screen = MSG_INFO;
-int verbose_logfile = MSG_DEBUG2;
static enum programmer programmer = PROGRAMMER_INVALID;
-
static const char *programmer_param = NULL;
/*
@@ -1783,73 +1780,6 @@ int selfcheck(void)
return ret;
}
-void check_chip_supported(const struct flashchip *chip)
-{
- if (chip->feature_bits & FEATURE_OTP) {
- msg_cdbg("This chip may contain one-time programmable memory. "
- "flashrom cannot read\nand may never be able to write "
- "it, hence it may not be able to completely\n"
- "clone the contents of this chip (see man page for "
- "details).\n");
- }
-
- if ((chip->tested.erase == NA) && (chip->tested.write == NA)) {
- msg_cdbg("This chip's main memory can not be erased/written by design.\n");
- }
-
- if ((chip->tested.probe == BAD) || (chip->tested.probe == NT) ||
- (chip->tested.read == BAD) || (chip->tested.read == NT) ||
- (chip->tested.erase == BAD) || (chip->tested.erase == NT) ||
- (chip->tested.write == BAD) || (chip->tested.write == NT)){
- msg_cinfo("===\n");
- if ((chip->tested.probe == BAD) ||
- (chip->tested.read == BAD) ||
- (chip->tested.erase == BAD) ||
- (chip->tested.write == BAD)) {
- msg_cinfo("This flash part has status NOT WORKING for operations:");
- if (chip->tested.probe == BAD)
- msg_cinfo(" PROBE");
- if (chip->tested.read == BAD)
- msg_cinfo(" READ");
- if (chip->tested.erase == BAD)
- msg_cinfo(" ERASE");
- if (chip->tested.write == BAD)
- msg_cinfo(" WRITE");
- msg_cinfo("\n");
- }
- if ((chip->tested.probe == NT) ||
- (chip->tested.read == NT) ||
- (chip->tested.erase == NT) ||
- (chip->tested.write == NT)) {
- msg_cinfo("This flash part has status UNTESTED for operations:");
- if (chip->tested.probe == NT)
- msg_cinfo(" PROBE");
- if (chip->tested.read == NT)
- msg_cinfo(" READ");
- if (chip->tested.erase == NT)
- msg_cinfo(" ERASE");
- if (chip->tested.write == NT)
- msg_cinfo(" WRITE");
- msg_cinfo("\n");
- }
- /* FIXME: This message is designed towards CLI users. */
- msg_cinfo("The test status of this chip may have been updated "
- "in the latest development\n"
- "version of flashrom. If you are running the latest "
- "development version,\n"
- "please email a report to flashrom(a)flashrom.org if "
- "any of the above operations\n"
- "work correctly for you with this flash part. Please "
- "include the flashrom\n"
- "output with the additional -V option for all "
- "operations you tested (-V, -Vr,\n"
- "-VE, -Vw), and mention which mainboard or "
- "programmer you tested.\n"
- "Please mention your board in the subject line. "
- "Thanks for your help!\n");
- }
-}
-
/* FIXME: This function signature needs to be improved once doit() has a better
* function signature.
*/
diff --git a/print.c b/print.c
index b1faea7..243aa49 100644
--- a/print.c
+++ b/print.c
@@ -59,39 +59,6 @@ static const char *test_state_to_text(enum test_state test_state)
}
}
-/*
- * Return a string corresponding to the bustype parameter.
- * Memory is obtained with malloc() and must be freed with free() by the caller.
- */
-char *flashbuses_to_text(enum chipbustype bustype)
-{
- char *ret = calloc(1, 1);
- /*
- * FIXME: Once all chipsets and flash chips have been updated, NONSPI
- * will cease to exist and should be eliminated here as well.
- */
- if (bustype == BUS_NONSPI) {
- ret = strcat_realloc(ret, "Non-SPI, ");
- } else {
- if (bustype & BUS_PARALLEL)
- ret = strcat_realloc(ret, "Parallel, ");
- if (bustype & BUS_LPC)
- ret = strcat_realloc(ret, "LPC, ");
- if (bustype & BUS_FWH)
- ret = strcat_realloc(ret, "FWH, ");
- if (bustype & BUS_SPI)
- ret = strcat_realloc(ret, "SPI, ");
- if (bustype & BUS_PROG)
- ret = strcat_realloc(ret, "Programmer-specific, ");
- if (bustype == BUS_NONE)
- ret = strcat_realloc(ret, "None, ");
- }
- /* Kill last comma. */
- ret[strlen(ret) - 2] = '\0';
- ret = realloc(ret, strlen(ret) + 1);
- return ret;
-}
-
static int print_supported_chips(void)
{
const char *delim = "/";
diff --git a/programmer.h b/programmer.h
index 3ad553a..62acfeb 100644
--- a/programmer.h
+++ b/programmer.h
@@ -513,7 +513,6 @@ struct decode_sizes {
extern struct decode_sizes max_rom_decode;
extern int programmer_may_write;
extern unsigned long flashbase;
-void check_chip_supported(const struct flashchip *chip);
int check_max_decode(enum chipbustype buses, uint32_t size);
char *extract_programmer_param(const char *param_name);
--
Kind regards, Stefan Tauner
1
0
While creating a sane foundation to build the new probing upon the
following patches were conceived. I'll rebase my probing patches on
top of them hence they need to be reviewed before the refined
probing patches to come. Especially the last one is rather important
anyway because it fixes the problem of wrongly mapped flash memory
ranges for SPI chips that provokes nasty warnings since a while ago.
Stefan Tauner (3):
Refactor some CLI-relevant parts.
Refine handling chips that exceed maximum programmer sizes.
Refine physical address mapping of flash chips.
82802ab.c | 2 -
Makefile | 2 +-
cli_classic.c | 16 ++++--
cli_common.c | 117 ++++++++++++++++++++++++++++++++++++++
cli_output.c | 3 +
flash.h | 10 ++--
flashrom.c | 176 +++++++++++++++++++++++-----------------------------------
jedec.c | 6 --
print.c | 33 -----------
programmer.h | 3 +-
10 files changed, 210 insertions(+), 158 deletions(-)
create mode 100644 cli_common.c
--
Kind regards, Stefan Tauner
1
0
# flashrom
flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
Found chipset "NVIDIA MCP61". Enabling flash write... This chipset is
not really supported yet. Guesswork...
Please send the output of "flashrom -V" to flashrom(a)flashrom.org with
your board name: flashrom -V as the subject to help us finish support
for your
chipset. Thanks.
OK.
WARNING: unexpected second chipset match: "NVIDIA MCP61"
ignoring, please report lspci and board URL to flashrom(a)flashrom.org
with 'CHIPSET: your board name' in the subject line.
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
#
#
#
# lspci
00:00.0 RAM memory: NVIDIA Corporation MCP61 Host Bridge (rev a1)
00:01.0 ISA bridge: NVIDIA Corporation MCP61 LPC Bridge (rev a2)
00:01.1 SMBus: NVIDIA Corporation MCP61 SMBus (rev a2)
00:01.2 RAM memory: NVIDIA Corporation MCP61 Memory Controller (rev a2)
00:02.0 USB controller: NVIDIA Corporation MCP61 USB 1.1 Controller (rev a3)
00:02.1 USB controller: NVIDIA Corporation MCP61 USB 2.0 Controller (rev a3)
00:04.0 PCI bridge: NVIDIA Corporation MCP61 PCI bridge (rev a1)
00:05.0 Audio device: NVIDIA Corporation MCP61 High Definition Audio
(rev a2)
00:06.0 IDE interface: NVIDIA Corporation MCP61 IDE (rev a2)
00:07.0 Bridge: NVIDIA Corporation MCP61 Ethernet (rev a2)
00:08.0 IDE interface: NVIDIA Corporation MCP61 SATA Controller (rev a2)
00:08.1 IDE interface: NVIDIA Corporation MCP61 SATA Controller (rev a2)
00:09.0 PCI bridge: NVIDIA Corporation MCP61 PCI Express bridge (rev a2)
00:0b.0 PCI bridge: NVIDIA Corporation MCP61 PCI Express bridge (rev a2)
00:0c.0 PCI bridge: NVIDIA Corporation MCP61 PCI Express bridge (rev a2)
00:0d.0 VGA compatible controller: NVIDIA Corporation C61 [GeForce 7025
/ nForce 630a] (rev a2)
00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h
Processor HyperTransport Configuration
00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h
Processor Address Map
00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h
Processor DRAM Controller
00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h
Processor Miscellaneous Control
00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h
Processor Link Control
01:0a.0 Ethernet controller: Qualcomm Atheros AR5212/AR5213 Wireless
Network Adapter (rev 01)
#
1
0
# flashrom
flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
Found chipset "NVIDIA MCP61". Enabling flash write... This chipset is
not really supported yet. Guesswork...
Please send the output of "flashrom -V" to flashrom(a)flashrom.org with
your board name: flashrom -V as the subject to help us finish support
for your
chipset. Thanks.
OK.
WARNING: unexpected second chipset match: "NVIDIA MCP61"
ignoring, please report lspci and board URL to flashrom(a)flashrom.org
with 'CHIPSET: your board name' in the subject line.
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
#
#
#
# flashrom -V
flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org
flashrom was built with libpci 3.1.7, GCC 4.6.2, little endian
Command line (1 args): flashrom -V
Calibrating delay loop... OS timer resolution is 1 usecs, 1392M loops
per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 995 us, 10000
myus = 10085 us, 4 myus = 4 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "To Be Filled By O.E.M."
DMI string system-product-name: "To Be Filled By O.E.M."
DMI string system-version: "To Be Filled By O.E.M."
DMI string baseboard-manufacturer: "ASRock"
DMI string baseboard-product-name: "N68-S"
DMI string baseboard-version: " "
DMI string chassis-type: "Desktop"
Found chipset "NVIDIA MCP61" with PCI ID 10de:03e1. Enabling flash
write... This chipset is not really supported yet. Guesswork...
ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0
Flash bus type is LPC
Found SMBus device 10de:03eb at 00:01:1
MCP SPI BAR is at 0xfec80000
Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI
enabled.
Please send the output of "flashrom -V" to flashrom(a)flashrom.org with
your board name: flashrom -V as the subject to help us finish support
for your
chipset. Thanks.
OK.
WARNING: unexpected second chipset match: "NVIDIA MCP61"
ignoring, please report lspci and board URL to flashrom(a)flashrom.org
with 'CHIPSET: your board name' in the subject line.
The following protocols are supported: LPC.
Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
Restoring PCI config space for 00:01:0 reg 0x6d
Restoring PCI config space for 00:01:0 reg 0x90
Restoring PCI config space for 00:01:0 reg 0x8c
Restoring PCI config space for 00:01:0 reg 0x88
#
1
0
Aug. 8, 2014
On Thu, 7 Aug 2014 23:49:57 +0200
Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote:
> Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use
> normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit)
> for 8-bit mode. Some programmers can access them in 16-bit mode, but on
> all flashrom-supported programmers so far, we access them in 8-bit mode.
> This means we have to shift the addresses but apart from the addresses
> we can share the code.
>
> This patch makes this possible by checking the chip's FEATURE_ADDR_SHIFTED
> flag in common JEDEC functions and applying the right addresses respectively.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at>
> ---
>
> I have removed the obsolete code, changed the probe_timing field to 10
> plus a comment explaining it where relevant, applied the changes to a
> few other chips that probably were not there before, and refined the
> shift handling as discussed on IRC.
Acked by Carl-Daniel and committed in r1840.
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner
1
0
Hello!
I have recently used flashrom on Asus M4N78SE motherboard. Flashrom advised
me to send logs. Everything worked as expected.
--
Sincerelly yours
2
3
Author: stefanct
Date: Fri Aug 8 10:33:01 2014
New Revision: 1840
URL: http://flashrom.org/trac/flashrom/changeset/1840
Log:
Unify non-shifted and shifted JEDEC access.
Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use
normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit)
for 8-bit mode. Some programmers can access them in 16-bit mode, but on
all flashrom-supported programmers so far, we access them in 8-bit mode.
This means we have to shift the addresses but apart from the addresses
we can share the code.
This patch makes this possible by checking the chip's FEATURE_ADDR_SHIFTED
flag in common JEDEC functions and applying the right addresses respectively.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Deleted:
trunk/m29f400bt.c
Modified:
trunk/82802ab.c
trunk/Makefile
trunk/chipdrivers.h
trunk/en29lv640b.c
trunk/flashchips.c
trunk/jedec.c
Modified: trunk/82802ab.c
==============================================================================
--- trunk/82802ab.c Wed Aug 6 17:09:15 2014 (r1839)
+++ trunk/82802ab.c Fri Aug 8 10:33:01 2014 (r1840)
@@ -44,7 +44,7 @@
{
chipaddr bios = flash->virtual_memory;
uint8_t id1, id2, flashcontent1, flashcontent2;
- int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) != 0;
+ int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0;
/* Reset to get a clean state */
chip_writeb(flash, 0xFF, bios);
Modified: trunk/Makefile
==============================================================================
--- trunk/Makefile Wed Aug 6 17:09:15 2014 (r1839)
+++ trunk/Makefile Fri Aug 8 10:33:01 2014 (r1840)
@@ -351,7 +351,7 @@
# Flash chip drivers and bus support infrastructure.
CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \
- sst28sf040.o m29f400bt.o 82802ab.o \
+ sst28sf040.o 82802ab.o \
sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o \
opaque.o sfdp.o en29lv640b.o at45db.o
Modified: trunk/chipdrivers.h
==============================================================================
--- trunk/chipdrivers.h Wed Aug 6 17:09:15 2014 (r1839)
+++ trunk/chipdrivers.h Fri Aug 8 10:33:01 2014 (r1840)
@@ -155,10 +155,6 @@
int printlock_regspace2_block_eraser_0(struct flashctx *flash);
int printlock_regspace2_block_eraser_1(struct flashctx *flash);
-/* m29f400bt.c */
-int probe_m29f400bt(struct flashctx *flash);
-int write_m29f400bt(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
-
/* sst28sf040.c */
int erase_chip_28sf040(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
int erase_sector_28sf040(struct flashctx *flash, unsigned int address, unsigned int sector_size);
@@ -197,8 +193,6 @@
/* en29lv640b.c */
int probe_en29lv640b(struct flashctx *flash);
-int erase_block_shifted_jedec(struct flashctx *flash, unsigned int start, unsigned int len);
-int erase_chip_block_shifted_jedec(struct flashctx *flash, unsigned int start, unsigned int len);
int write_en29lv640b(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
#endif /* !__CHIPDRIVERS_H__ */
Modified: trunk/en29lv640b.c
==============================================================================
--- trunk/en29lv640b.c Wed Aug 6 17:09:15 2014 (r1839)
+++ trunk/en29lv640b.c Fri Aug 8 10:33:01 2014 (r1840)
@@ -85,51 +85,3 @@
return 0;
}
-
-static int erase_chip_shifted_jedec(struct flashctx *flash)
-{
- chipaddr bios = flash->virtual_memory;
-
- chip_writeb(flash, 0xAA, bios + 0xAAA);
- chip_writeb(flash, 0x55, bios + 0x555);
- chip_writeb(flash, 0x80, bios + 0xAAA);
-
- chip_writeb(flash, 0xAA, bios + 0xAAA);
- chip_writeb(flash, 0x55, bios + 0x555);
- chip_writeb(flash, 0x10, bios + 0xAAA);
-
- programmer_delay(10);
- toggle_ready_jedec(flash, bios);
-
- /* FIXME: Check the status register for errors. */
- return 0;
-}
-
-int erase_block_shifted_jedec(struct flashctx *flash, unsigned int start, unsigned int len)
-{
- chipaddr bios = flash->virtual_memory;
- chipaddr dst = bios + start;
-
- chip_writeb(flash, 0xAA, bios + 0xAAA);
- chip_writeb(flash, 0x55, bios + 0x555);
- chip_writeb(flash, 0x80, bios + 0xAAA);
-
- chip_writeb(flash, 0xAA, bios + 0xAAA);
- chip_writeb(flash, 0x55, bios + 0x555);
- chip_writeb(flash, 0x30, dst);
-
- programmer_delay(10);
- toggle_ready_jedec(flash, bios);
-
- /* FIXME: Check the status register for errors. */
- return 0;
-}
-
-int erase_chip_block_shifted_jedec(struct flashctx *flash, unsigned int address, unsigned int blocklen)
-{
- if ((address != 0) || (blocklen != flash->chip->total_size * 1024)) {
- msg_cerr("%s called with incorrect arguments\n", __func__);
- return -1;
- }
- return erase_chip_shifted_jedec(flash);
-}
Modified: trunk/flashchips.c
==============================================================================
--- trunk/flashchips.c Wed Aug 6 17:09:15 2014 (r1839)
+++ trunk/flashchips.c Fri Aug 8 10:33:01 2014 (r1840)
@@ -4869,7 +4869,7 @@
.model_id = EON_EN29LV640B,
.total_size = 8192,
.page_size = 8192,
- .feature_bits = 0,
+ .feature_bits = FEATURE_ADDR_SHIFTED,
.tested = TEST_OK_PREW,
.probe = probe_en29lv640b,
.probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
@@ -4880,10 +4880,10 @@
{8 * 1024, 8},
{64 * 1024, 127},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_block_jedec,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
},
},
.write = write_en29lv640b,
@@ -5078,10 +5078,10 @@
.model_id = FUJITSU_MBM29F400BC,
.total_size = 512,
.page_size = 64 * 1024,
- .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET,
+ .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET,
.tested = TEST_UNTESTED,
- .probe = probe_m29f400bt,
- .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */
+ .probe = probe_jedec,
+ .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt
.block_erasers =
{
{
@@ -5091,13 +5091,13 @@
{32 * 1024, 1},
{64 * 1024, 7},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
},
},
- .write = write_m29f400bt,
+ .write = write_jedec_1,
.read = read_memmapped,
.voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */
},
@@ -5110,10 +5110,10 @@
.model_id = FUJITSU_MBM29F400TC,
.total_size = 512,
.page_size = 64 * 1024,
- .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET,
+ .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_AAA | FEATURE_EITHER_RESET,
.tested = TEST_UNTESTED,
- .probe = probe_m29f400bt,
- .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */
+ .probe = probe_jedec,
+ .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt
.block_erasers =
{
{
@@ -5123,13 +5123,13 @@
{8 * 1024, 2},
{16 * 1024, 1},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
},
},
- .write = write_m29f400bt,
+ .write = write_jedec_1,
.read = read_memmapped,
.voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */
},
@@ -5144,8 +5144,8 @@
.page_size = 0,
.feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_SHORT_RESET,
.tested = TEST_UNTESTED,
- .probe = probe_m29f400bt,
- .probe_timing = TIMING_IGNORED,
+ .probe = probe_jedec,
+ .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt
.block_erasers =
{
{
@@ -5155,13 +5155,13 @@
{32 * 1024, 1},
{64 * 1024, 31},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_block_jedec,
}, {
.eraseblocks = { {2048 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
},
},
- .write = write_m29f400bt, /* Supports a fast mode too */
+ .write = write_jedec_1, /* Supports a fast mode too */
.read = read_memmapped,
.voltage = {3000, 3600}, /* 3.0-3.6V for type -70, others 2.7-3.6V */
},
@@ -5176,8 +5176,8 @@
.page_size = 0,
.feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_SHORT_RESET,
.tested = TEST_UNTESTED,
- .probe = probe_m29f400bt,
- .probe_timing = TIMING_IGNORED,
+ .probe = probe_jedec,
+ .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt
.block_erasers =
{
{
@@ -5187,13 +5187,13 @@
{8 * 1024, 2},
{16 * 1024, 1},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_block_jedec,
}, {
.eraseblocks = { {2048 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
},
},
- .write = write_m29f400bt, /* Supports a fast mode too */
+ .write = write_jedec_1, /* Supports a fast mode too */
.read = read_memmapped,
.voltage = {3000, 3600}, /* 3.0-3.6V for type -70, others 2.7-3.6V */
},
@@ -12178,10 +12178,10 @@
.model_id = ST_M29F400BB,
.total_size = 512,
.page_size = 64 * 1024,
- .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET,
+ .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET,
.tested = TEST_UNTESTED,
- .probe = probe_m29f400bt,
- .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */
+ .probe = probe_jedec,
+ .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt
.block_erasers =
{
{
@@ -12191,13 +12191,13 @@
{32 * 1024, 1},
{64 * 1024, 7},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
}
},
- .write = write_m29f400bt,
+ .write = write_jedec_1,
.read = read_memmapped,
.voltage = {4500, 5500},
},
@@ -12210,10 +12210,10 @@
.model_id = ST_M29F400BT,
.total_size = 512,
.page_size = 64 * 1024,
- .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET,
+ .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET,
.tested = TEST_UNTESTED,
- .probe = probe_m29f400bt,
- .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */
+ .probe = probe_jedec,
+ .probe_timing = 10, // FIXME: check datasheet. Using the 10 us from probe_m29f400bt
.block_erasers =
{
{
@@ -12223,13 +12223,13 @@
{8 * 1024, 2},
{16 * 1024, 1},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
}
},
- .write = write_m29f400bt,
+ .write = write_jedec_1,
.read = read_memmapped,
.voltage = {4500, 5500},
},
Modified: trunk/jedec.c
==============================================================================
--- trunk/jedec.c Wed Aug 6 17:09:15 2014 (r1839)
+++ trunk/jedec.c Fri Aug 8 10:33:01 2014 (r1840)
@@ -4,7 +4,7 @@
* Copyright (C) 2000 Silicon Integrated System Corporation
* Copyright (C) 2006 Giampiero Giancipoli <gianci(a)email.it>
* Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de>
- * Copyright (C) 2007, 2011 Carl-Daniel Hailfinger
+ * Copyright (C) 2007-2012 Carl-Daniel Hailfinger
* Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com>
* Copyright (C) 2014 Stefan Tauner
*
@@ -116,9 +116,11 @@
static void start_program_jedec_common(const struct flashctx *flash, unsigned int mask)
{
chipaddr bios = flash->virtual_memory;
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
- chip_writeb(flash, 0xA0, bios + (0x5555 & mask));
+ bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
+
+ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
+ chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
+ chip_writeb(flash, 0xA0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
}
int probe_jedec_29gl(struct flashctx *flash)
@@ -174,6 +176,7 @@
{
chipaddr bios = flash->virtual_memory;
const struct flashchip *chip = flash->chip;
+ bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
uint8_t id1, id2;
uint32_t largeid1, largeid2;
uint32_t flashcontent1, flashcontent2;
@@ -203,31 +206,31 @@
/* Reset chip to a clean slate */
if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
{
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_exit)
programmer_delay(10);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
if (probe_timing_exit)
programmer_delay(10);
}
- chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_exit)
programmer_delay(probe_timing_exit);
/* Issue JEDEC Product ID Entry command */
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_enter)
programmer_delay(10);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
if (probe_timing_enter)
programmer_delay(10);
- chip_writeb(flash, 0x90, bios + (0x5555 & mask));
+ chip_writeb(flash, 0x90, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_enter)
programmer_delay(probe_timing_enter);
/* Read product ID */
- id1 = chip_readb(flash, bios);
- id2 = chip_readb(flash, bios + 0x01);
+ id1 = chip_readb(flash, bios + (0x00 << shifted));
+ id2 = chip_readb(flash, bios + (0x01 << shifted));
largeid1 = id1;
largeid2 = id2;
@@ -246,14 +249,14 @@
/* Issue JEDEC Product ID Exit command */
if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
{
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_exit)
programmer_delay(10);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
if (probe_timing_exit)
programmer_delay(10);
}
- chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_exit)
programmer_delay(probe_timing_exit);
@@ -262,8 +265,8 @@
msg_cdbg(", id1 parity violation");
/* Read the product ID location again. We should now see normal flash contents. */
- flashcontent1 = chip_readb(flash, bios);
- flashcontent2 = chip_readb(flash, bios + 0x01);
+ flashcontent1 = chip_readb(flash, bios + (0x00 << shifted));
+ flashcontent2 = chip_readb(flash, bios + (0x01 << shifted));
/* Check if it is a continuation ID, this should be a while loop. */
if (flashcontent1 == 0x7F) {
@@ -294,21 +297,23 @@
unsigned int pagesize, unsigned int mask)
{
chipaddr bios = flash->virtual_memory;
+ bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
unsigned int delay_us = 0;
+
if(flash->chip->probe_timing != TIMING_ZERO)
delay_us = 10;
/* Issue the Sector Erase command */
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x80, bios + (0x5555 & mask));
+ chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us);
chip_writeb(flash, 0x30, bios + page);
programmer_delay(delay_us);
@@ -324,21 +329,23 @@
unsigned int blocksize, unsigned int mask)
{
chipaddr bios = flash->virtual_memory;
+ bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
unsigned int delay_us = 0;
+
if(flash->chip->probe_timing != TIMING_ZERO)
delay_us = 10;
/* Issue the Sector Erase command */
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x80, bios + (0x5555 & mask));
+ chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us);
chip_writeb(flash, 0x50, bios + block);
programmer_delay(delay_us);
@@ -353,23 +360,25 @@
static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask)
{
chipaddr bios = flash->virtual_memory;
+ bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
unsigned int delay_us = 0;
+
if(flash->chip->probe_timing != TIMING_ZERO)
delay_us = 10;
/* Issue the JEDEC Chip Erase command */
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x80, bios + (0x5555 & mask));
+ chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x10, bios + (0x5555 & mask));
+ chip_writeb(flash, 0x10, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us);
toggle_ready_jedec_slow(flash, bios);
1
0
Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use
normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit)
for 8-bit mode. Some programmers can access them in 16-bit mode, but on
all flashrom-supported programmers so far, we access them in 8-bit mode.
This means we have to shift the addresses.
Untested, should work. This is a patch written shortly after r886 was
committed, and it has been forward-ported.
Missing from this patch is the deletion of now-unused code.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-jedec_shifted/jedec.c
===================================================================
--- flashrom-jedec_shifted/jedec.c (Revision 1818)
+++ flashrom-jedec_shifted/jedec.c (Arbeitskopie)
@@ -4,7 +4,7 @@
* Copyright (C) 2000 Silicon Integrated System Corporation
* Copyright (C) 2006 Giampiero Giancipoli <gianci(a)email.it>
* Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de>
- * Copyright (C) 2007 Carl-Daniel Hailfinger
+ * Copyright (C) 2007-2012 Carl-Daniel Hailfinger
* Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -115,15 +115,18 @@
static void start_program_jedec_common(const struct flashctx *flash, unsigned int mask)
{
chipaddr bios = flash->virtual_memory;
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
- chip_writeb(flash, 0xA0, bios + (0x5555 & mask));
+ int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0;
+
+ chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask));
+ chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask));
+ chip_writeb(flash, 0xA0, bios + ((0x5555 << shifted) & mask));
}
static int probe_jedec_common(struct flashctx *flash, unsigned int mask)
{
chipaddr bios = flash->virtual_memory;
const struct flashchip *chip = flash->chip;
+ int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0;
uint8_t id1, id2;
uint32_t largeid1, largeid2;
uint32_t flashcontent1, flashcontent2;
@@ -153,31 +156,31 @@
/* Reset chip to a clean slate */
if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
{
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask));
if (probe_timing_exit)
programmer_delay(10);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask));
if (probe_timing_exit)
programmer_delay(10);
}
- chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xF0, bios + ((0x5555 << shifted) & mask));
if (probe_timing_exit)
programmer_delay(probe_timing_exit);
/* Issue JEDEC Product ID Entry command */
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask));
if (probe_timing_enter)
programmer_delay(10);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask));
if (probe_timing_enter)
programmer_delay(10);
- chip_writeb(flash, 0x90, bios + (0x5555 & mask));
+ chip_writeb(flash, 0x90, bios + ((0x5555 << shifted) & mask));
if (probe_timing_enter)
programmer_delay(probe_timing_enter);
/* Read product ID */
- id1 = chip_readb(flash, bios);
- id2 = chip_readb(flash, bios + 0x01);
+ id1 = chip_readb(flash, bios + (0x00 << shifted));
+ id2 = chip_readb(flash, bios + (0x01 << shifted));
largeid1 = id1;
largeid2 = id2;
@@ -196,14 +199,14 @@
/* Issue JEDEC Product ID Exit command */
if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
{
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask));
if (probe_timing_exit)
programmer_delay(10);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask));
if (probe_timing_exit)
programmer_delay(10);
}
- chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xF0, bios + ((0x5555 << shifted) & mask));
if (probe_timing_exit)
programmer_delay(probe_timing_exit);
@@ -212,8 +215,8 @@
msg_cdbg(", id1 parity violation");
/* Read the product ID location again. We should now see normal flash contents. */
- flashcontent1 = chip_readb(flash, bios);
- flashcontent2 = chip_readb(flash, bios + 0x01);
+ flashcontent1 = chip_readb(flash, bios + (0x00 << shifted));
+ flashcontent2 = chip_readb(flash, bios + (0x01 << shifted));
/* Check if it is a continuation ID, this should be a while loop. */
if (flashcontent1 == 0x7F) {
@@ -244,21 +247,23 @@
unsigned int pagesize, unsigned int mask)
{
chipaddr bios = flash->virtual_memory;
+ int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0;
unsigned int delay_us = 0;
+
if(flash->chip->probe_timing != TIMING_ZERO)
delay_us = 10;
/* Issue the Sector Erase command */
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x80, bios + (0x5555 & mask));
+ chip_writeb(flash, 0x80, bios + ((0x5555 << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask));
programmer_delay(delay_us);
chip_writeb(flash, 0x30, bios + page);
programmer_delay(delay_us);
@@ -274,21 +279,23 @@
unsigned int blocksize, unsigned int mask)
{
chipaddr bios = flash->virtual_memory;
+ int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0;
unsigned int delay_us = 0;
+
if(flash->chip->probe_timing != TIMING_ZERO)
delay_us = 10;
/* Issue the Sector Erase command */
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x80, bios + (0x5555 & mask));
+ chip_writeb(flash, 0x80, bios + ((0x5555 << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask));
programmer_delay(delay_us);
chip_writeb(flash, 0x50, bios + block);
programmer_delay(delay_us);
@@ -303,23 +310,25 @@
static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask)
{
chipaddr bios = flash->virtual_memory;
+ int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0;
unsigned int delay_us = 0;
+
if(flash->chip->probe_timing != TIMING_ZERO)
delay_us = 10;
/* Issue the JEDEC Chip Erase command */
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x80, bios + (0x5555 & mask));
+ chip_writeb(flash, 0x80, bios + ((0x5555 << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
+ chip_writeb(flash, 0xAA, bios + ((0x5555 << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
+ chip_writeb(flash, 0x55, bios + ((0x2AAA << shifted) & mask));
programmer_delay(delay_us);
- chip_writeb(flash, 0x10, bios + (0x5555 & mask));
+ chip_writeb(flash, 0x10, bios + ((0x5555 << shifted) & mask));
programmer_delay(delay_us);
toggle_ready_jedec_slow(flash, bios);
Index: flashrom-jedec_shifted/82802ab.c
===================================================================
--- flashrom-jedec_shifted/82802ab.c (Revision 1818)
+++ flashrom-jedec_shifted/82802ab.c (Arbeitskopie)
@@ -44,7 +44,7 @@
{
chipaddr bios = flash->virtual_memory;
uint8_t id1, id2, flashcontent1, flashcontent2;
- int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) != 0;
+ int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0;
/* Reset to get a clean state */
chip_writeb(flash, 0xFF, bios);
Index: flashrom-jedec_shifted/flashchips.c
===================================================================
--- flashrom-jedec_shifted/flashchips.c (Revision 1818)
+++ flashrom-jedec_shifted/flashchips.c (Arbeitskopie)
@@ -4892,10 +4892,10 @@
.model_id = FUJITSU_MBM29F400BC,
.total_size = 512,
.page_size = 64 * 1024,
- .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET,
+ .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET,
.tested = TEST_UNTESTED,
- .probe = probe_m29f400bt,
- .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */
+ .probe = probe_jedec,
+ .probe_timing = TIMING_FIXME,
.block_erasers =
{
{
@@ -4905,13 +4905,13 @@
{32 * 1024, 1},
{64 * 1024, 7},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
},
},
- .write = write_m29f400bt,
+ .write = write_jedec_1,
.read = read_memmapped,
.voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */
},
@@ -4924,10 +4924,10 @@
.model_id = FUJITSU_MBM29F400TC,
.total_size = 512,
.page_size = 64 * 1024,
- .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET,
+ .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_AAA | FEATURE_EITHER_RESET,
.tested = TEST_UNTESTED,
- .probe = probe_m29f400bt,
- .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */
+ .probe = probe_jedec,
+ .probe_timing = TIMING_FIXME,
.block_erasers =
{
{
@@ -4937,13 +4937,13 @@
{8 * 1024, 2},
{16 * 1024, 1},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
},
},
- .write = write_m29f400bt,
+ .write = write_jedec_1,
.read = read_memmapped,
.voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */
},
@@ -11388,10 +11388,10 @@
.model_id = ST_M29F400BB,
.total_size = 512,
.page_size = 64 * 1024,
- .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET,
+ .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET,
.tested = TEST_UNTESTED,
- .probe = probe_m29f400bt,
- .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */
+ .probe = probe_jedec,
+ .probe_timing = TIMING_FIXME,
.block_erasers =
{
{
@@ -11401,13 +11401,13 @@
{32 * 1024, 1},
{64 * 1024, 7},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
}
},
- .write = write_m29f400bt,
+ .write = write_jedec_1,
.read = read_memmapped,
.voltage = {4500, 5500},
},
@@ -11420,10 +11420,10 @@
.model_id = ST_M29F400BT,
.total_size = 512,
.page_size = 64 * 1024,
- .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_EITHER_RESET,
+ .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_ADDR_2AA | FEATURE_EITHER_RESET,
.tested = TEST_UNTESTED,
- .probe = probe_m29f400bt,
- .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (m29f400bt.c) */
+ .probe = probe_jedec,
+ .probe_timing = TIMING_FIXME,
.block_erasers =
{
{
@@ -11433,13 +11433,13 @@
{8 * 1024, 2},
{16 * 1024, 1},
},
- .block_erase = erase_block_shifted_jedec,
+ .block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
- .block_erase = erase_chip_block_shifted_jedec,
+ .block_erase = erase_chip_block_jedec,
}
},
- .write = write_m29f400bt,
+ .write = write_jedec_1,
.read = read_memmapped,
.voltage = {4500, 5500},
},
--
http://www.hailfinger.org/
2
3
Dear Sir/ Madam
My name is Thinh, I am a student In Vietnam.
I have a topic to reseach how does deaign flashrom so i searched on internet but i could not find any doument related that topic.
can you help me some document or book on line so i can lear them my topic?
Thank for your support
Thinh
1
0
Author: stefanct
Date: Wed Aug 6 17:09:15 2014
New Revision: 1839
URL: http://flashrom.org/trac/flashrom/changeset/1839
Log:
Add a bunch of new/tested stuff and various small changes 21.
Tested mainboards:
OK:
- ASUS F2A85-M
Reported by various corebooters
- ASUS M2N-MX SE Plus
Reported by Antonio
- ASUS P5LD2
Reported by François Revol
- Lenovo ThinkPad T530
Reported and partially authored by Edward O'Callaghan
- MSI MS-7502 (Medion MD8833)
Reported by naq on IRC
- Shuttle AB61
Reported by olofolleola4
- ZOTAC IONITX-F-E
Reported by Bernardo Kuri
Flash chips:
- Atmel AT45DB021D to PREW (+PREW)
Reported by The Raven
- Atmel AT25F4096 to PREW (+PREW)
Reported by 공준혁
- GigaDevice GD25Q16(B) to PREW (+PREW)
Reported by luxflow(a)live.com using a GD25Q16BSIG
- Catalyst CAT28F512
Mark erase and write as known bad (not implemented)
Miscellaneous:
- Various spelling corrections by Daniele Forsi.
- Added and refined a bunch of chips originally investigated by Carl-Daniel.
- Marked the ARM-USB-OCD-H programmer as tested
(reported by Ruud Schramp).
- Tiny other stuff.
Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at>
Modified:
trunk/Documentation/serprog-protocol.txt
trunk/atavia.c
trunk/board_enable.c
trunk/chipdrivers.h
trunk/chipset_enable.c
trunk/dmi.c
trunk/flash.h
trunk/flashchips.c
trunk/flashchips.h
trunk/flashrom.8.tmpl
trunk/flashrom.c
trunk/ft2232_spi.c
trunk/it8212.c
trunk/print.c
trunk/sb600spi.c
Modified: trunk/Documentation/serprog-protocol.txt
==============================================================================
--- trunk/Documentation/serprog-protocol.txt Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/Documentation/serprog-protocol.txt Wed Aug 6 17:09:15 2014 (r1839)
@@ -74,7 +74,7 @@
Send and receive bytes via SPI.
Maximum slen is Q_WRNMAXLEN in case Q_BUSTYPE returns SPI only or S_BUSTYPE was used
to set SPI exclusively before. Same for rlen and Q_RDNMAXLEN.
- This operation is immediate, meaning it doesnt use the operation buffer.
+ This operation is immediate, meaning it doesn't use the operation buffer.
0x14 (S_SPI_FREQ):
Set the SPI clock frequency. The 32-bit value indicates the
requested frequency in Hertz. Value 0 is reserved and should
Modified: trunk/atavia.c
==============================================================================
--- trunk/atavia.c Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/atavia.c Wed Aug 6 17:09:15 2014 (r1839)
@@ -113,7 +113,7 @@
}
msg_pdbg2("\n%s: %s after %d tries (access=0x%02x, status=0x%02x)\n",
- __func__, ready ? "suceeded" : "failed", try, access, status);
+ __func__, ready ? "succeeded" : "failed", try, access, status);
atavia_prettyprint_access(access);
return ready;
}
Modified: trunk/board_enable.c
==============================================================================
--- trunk/board_enable.c Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/board_enable.c Wed Aug 6 17:09:15 2014 (r1839)
@@ -2374,7 +2374,7 @@
{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},
{0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},
{0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},
- {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise},
+ {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, OK, intel_ich_gpio16_raise},
{0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b0, 0x1043, 0x8179, "^P5LD2-MQ$", NULL, NULL, P3, "ASUS", "P5LD2-MQ", 0, OK, intel_ich_gpio16_raise},
{0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, NT, intel_ich_gpio16_raise},
{0x8086, 0x27b0, 0x1043, 0x8179, 0x8086, 0x2770, 0x1043, 0x817a, "^P5LD2-VM DH$", NULL, NULL, P3, "ASUS", "P5LD2-VM DH", 0, OK, intel_ich_gpio16_raise},
@@ -2422,11 +2422,12 @@
{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
{0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
{0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
- {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60", 0, OK, p2_whitelist_laptop},
- {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60(s)", 0, OK, p2_whitelist_laptop},
- {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "Lenovo", "X60(s)", 0, OK, p2_whitelist_laptop},
- {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "Lenovo", "X201", 0, OK, p2_whitelist_laptop},
- {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "Lenovo", "X230", 0, OK, p2_whitelist_laptop},
+ {0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop},
+ {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop},
+ {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop},
+ {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X201", 0, OK, p2_whitelist_laptop},
+ {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X230", 0, OK, p2_whitelist_laptop},
+ {0x8086, 0x27A0, 0x17AA, 0x2017, 0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X60(s)", 0, OK, p2_whitelist_laptop},
{0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
{0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0, 0, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},
{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
Modified: trunk/chipdrivers.h
==============================================================================
--- trunk/chipdrivers.h Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/chipdrivers.h Wed Aug 6 17:09:15 2014 (r1839)
@@ -158,7 +158,6 @@
/* m29f400bt.c */
int probe_m29f400bt(struct flashctx *flash);
int write_m29f400bt(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
-void protect_m29f400bt(struct flashctx *flash, chipaddr bios);
/* sst28sf040.c */
int erase_chip_28sf040(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
Modified: trunk/chipset_enable.c
==============================================================================
--- trunk/chipset_enable.c Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/chipset_enable.c Wed Aug 6 17:09:15 2014 (r1839)
@@ -608,7 +608,7 @@
if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) {
uint8_t buc = mmio_readb(rcrb + 0x3414);
- msg_pdbg("Top Swap : %s\n", (buc & 1) ? "enabled (A16(+) inverted)" : "not enabled");
+ msg_pdbg("Top Swap: %s\n", (buc & 1) ? "enabled (A16(+) inverted)" : "not enabled");
}
/* Handle FWH-related parameters and initialization */
Modified: trunk/dmi.c
==============================================================================
--- trunk/dmi.c Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/dmi.c Wed Aug 6 17:09:15 2014 (r1839)
@@ -188,7 +188,7 @@
/* - If a short entry is found (less than 4 bytes), not only it
* is invalid, but we cannot reliably locate the next entry.
* - If the length value indicates that this structure spreads
- * accross the table border, something is fishy too.
+ * across the table border, something is fishy too.
* Better stop at this point, and let the user know his/her
* table is broken.
*/
Modified: trunk/flash.h
==============================================================================
--- trunk/flash.h Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/flash.h Wed Aug 6 17:09:15 2014 (r1839)
@@ -187,7 +187,7 @@
* elements or set the function pointer to NULL.
*/
struct block_eraser {
- struct eraseblock{
+ struct eraseblock {
unsigned int size; /* Eraseblock size in bytes */
unsigned int count; /* Number of contiguous blocks with that size */
} eraseblocks[NUM_ERASEREGIONS];
Modified: trunk/flashchips.c
==============================================================================
--- trunk/flashchips.c Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/flashchips.c Wed Aug 6 17:09:15 2014 (r1839)
@@ -1994,7 +1994,7 @@
.total_size = 512,
.page_size = 256,
.feature_bits = FEATURE_WRSR_WREN,
- .tested = TEST_UNTESTED,
+ .tested = TEST_OK_PREW,
.probe = probe_spi_at25f,
.probe_timing = TIMING_ZERO,
.block_erasers =
@@ -2477,7 +2477,7 @@
/* does not support EWSR nor WREN and has no writable status register bits whatsoever */
/* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */
.feature_bits = FEATURE_OTP,
- .tested = TEST_UNTESTED,
+ .tested = TEST_OK_PREW,
.probe = probe_spi_at45db,
.probe_timing = TIMING_ZERO,
.block_erasers =
@@ -3158,7 +3158,7 @@
.total_size = 64,
.page_size = 0, /* unused */
.feature_bits = 0,
- .tested = TEST_OK_PR,
+ .tested = {.probe = OK, .read = OK, .erase = BAD, .write = BAD },
.probe = probe_jedec, /* FIXME! */
.probe_timing = TIMING_ZERO,
.block_erasers =
@@ -5433,7 +5433,7 @@
.page_size = 256,
/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 (B version only) */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
- .tested = TEST_UNTESTED,
+ .tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
.block_erasers =
@@ -6627,7 +6627,7 @@
.block_erase = spi_block_erase_c7,
},
},
- .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: Continously Program (CP) mode */
+ .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: Continuously Program (CP) mode */
.unlock = spi_disable_blockprotect,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */
@@ -7641,7 +7641,7 @@
.block_erasers =
{
{
- .eraseblocks = { {64 * 1024, 8}, },
+ .eraseblocks = { {64 * 1024, 8} },
.block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
@@ -10242,9 +10242,9 @@
}
},
.printlock = spi_prettyprint_status_register_bp3_srwd,
- .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */
+ .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */
.write = spi_chip_write_256,
- .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */
+ .read = spi_chip_read, /* Fast read (0x0B) and dual I/O (0x3B) supported */
.voltage = {2700, 3600},
},
@@ -10276,15 +10276,15 @@
}
},
.printlock = spi_prettyprint_status_register_bp3_srwd,
- .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */
+ .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */
.write = spi_chip_write_256,
- .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */
+ .read = spi_chip_read, /* Fast read (0x0B) and dual I/O (0x3B) supported */
.voltage = {2700, 3600},
},
{
.vendor = "Spansion",
- .name = "S25FL116K/S25FL216K",
+ .name = "S25FL116K/S25FL216K", /* FIXME: separate them */
.bustype = BUS_SPI,
.manufacture_id = SPANSION_ID,
.model_id = SPANSION_S25FL216,
@@ -10311,9 +10311,9 @@
}
},
.printlock = spi_prettyprint_status_register_bp3_srwd,
- .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */
+ .unlock = spi_disable_blockprotect_bp3_srwd, /* #WP pin write-protects SRWP bit. */
.write = spi_chip_write_256,
- .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */
+ .read = spi_chip_read, /* Fast read (0x0B) and dual I/O (0x3B) supported */
.voltage = {2700, 3600},
},
@@ -10702,10 +10702,10 @@
{
.vendor = "SST",
- .name = "SST25VF512A",
+ .name = "SST25VF512(A)",
.bustype = BUS_SPI,
.manufacture_id = SST_ID,
- .model_id = SST_SST25VF512A_REMS,
+ .model_id = SST_SST25VF512_REMS,
.total_size = 64,
.page_size = 256,
.feature_bits = FEATURE_WRSR_EWSR,
@@ -10722,25 +10722,25 @@
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { {32 * 1024, 2} },
- .block_erase = spi_block_erase_d8,
+ .block_erase = spi_block_erase_d8, /* Supported by SST25VF512A only */
}, {
.eraseblocks = { {64 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {64 * 1024, 1} },
- .block_erase = spi_block_erase_c7,
+ .block_erase = spi_block_erase_c7, /* Supported by SST25VF512A only */
},
},
.printlock = spi_prettyprint_status_register_sst25, /* FIXME: No BP2 & 3 */
.unlock = spi_disable_blockprotect,
.write = spi_chip_write_1, /* AAI supported, but opcode is 0xAF */
- .read = spi_chip_read, /* Fast read (0x0B) supported */
+ .read = spi_chip_read, /* Fast read (0x0B) supported by SST25VF512A only */
.voltage = {2700, 3600},
},
{
.vendor = "SST",
- .name = "SST25VF010",
+ .name = "SST25VF010(A)",
.bustype = BUS_SPI,
.manufacture_id = SST_ID,
.model_id = SST_SST25VF010_REMS,
@@ -10760,19 +10760,19 @@
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { {32 * 1024, 4} },
- .block_erase = spi_block_erase_d8,
+ .block_erase = spi_block_erase_d8, /* Supported by SST25VF010A only */
}, {
.eraseblocks = { {128 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {128 * 1024, 1} },
- .block_erase = spi_block_erase_c7,
+ .block_erase = spi_block_erase_c7, /* Supported by SST25VF010A only */
},
},
.printlock = spi_prettyprint_status_register_sst25, /* FIXME: No BP2 & 3 */
.unlock = spi_disable_blockprotect,
.write = spi_chip_write_1, /* AAI supported, but opcode is 0xAF */
- .read = spi_chip_read, /* Fast read (0x0B) supported */
+ .read = spi_chip_read, /* Fast read (0x0B) supported by SST25VF010A only */
.voltage = {2700, 3600},
},
@@ -12157,7 +12157,7 @@
.block_erasers =
{
{
- .eraseblocks = { {64 * 1024, 8}, },
+ .eraseblocks = { {64 * 1024, 8} },
.block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
@@ -12249,7 +12249,7 @@
.block_erasers =
{
{
- .eraseblocks = { {16 * 1024, 8}, },
+ .eraseblocks = { {16 * 1024, 8} },
.block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {128 * 1024, 1} },
@@ -12276,7 +12276,7 @@
.block_erasers =
{
{
- .eraseblocks = { {64 * 1024, 8}, },
+ .eraseblocks = { {64 * 1024, 8} },
.block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
@@ -12335,7 +12335,7 @@
},
.block_erase = erase_sector_stm50,
}, {
- .eraseblocks = { {64 * 1024, 8}, },
+ .eraseblocks = { {64 * 1024, 8} },
.block_erase = erase_block_82802ab,
}
},
@@ -12368,7 +12368,7 @@
},
.block_erase = erase_sector_stm50,
}, {
- .eraseblocks = { {64 * 1024, 8}, },
+ .eraseblocks = { {64 * 1024, 8} },
.block_erase = erase_block_82802ab,
}
},
@@ -12401,7 +12401,7 @@
},
.block_erase = erase_sector_stm50,
}, {
- .eraseblocks = { {64 * 1024, 16}, },
+ .eraseblocks = { {64 * 1024, 16} },
.block_erase = erase_block_82802ab,
}
},
@@ -12435,7 +12435,7 @@
},
.block_erase = erase_sector_stm50,
}, {
- .eraseblocks = { {64 * 1024, 16}, },
+ .eraseblocks = { {64 * 1024, 16} },
.block_erase = erase_block_82802ab,
}
},
@@ -12495,7 +12495,7 @@
.block_erasers =
{
{
- .eraseblocks = { {64 * 1024, 32}, },
+ .eraseblocks = { {64 * 1024, 32} },
.block_erase = erase_block_82802ab,
}
},
@@ -12520,7 +12520,7 @@
.block_erasers =
{
{
- .eraseblocks = { {64 * 1024, 8}, },
+ .eraseblocks = { {64 * 1024, 8} },
.block_erase = erase_block_82802ab,
}
},
@@ -12545,7 +12545,7 @@
.block_erasers =
{
{
- .eraseblocks = { {64 * 1024, 16}, },
+ .eraseblocks = { {64 * 1024, 16} },
.block_erase = erase_block_82802ab,
}
},
@@ -12570,7 +12570,7 @@
.block_erasers =
{
{
- .eraseblocks = { {64 * 1024, 16}, },
+ .eraseblocks = { {64 * 1024, 16} },
.block_erase = erase_block_82802ab,
}
},
@@ -14318,7 +14318,7 @@
.block_erasers =
{
{
- .eraseblocks = { {64 * 1024, 16}, },
+ .eraseblocks = { {64 * 1024, 16} },
.block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {1024 * 1024, 1} },
@@ -14347,7 +14347,7 @@
.block_erasers =
{
{
- .eraseblocks = { {64 * 1024, 8}, },
+ .eraseblocks = { {64 * 1024, 8} },
.block_erase = erase_sector_jedec,
}, {
.eraseblocks = { {512 * 1024, 1} },
Modified: trunk/flashchips.h
==============================================================================
--- trunk/flashchips.h Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/flashchips.h Wed Aug 6 17:09:15 2014 (r1839)
@@ -75,6 +75,7 @@
#define AMD_AM29F800BT 0xD6
#define AMD_AM29LV001BB 0x6D
#define AMD_AM29LV001BT 0xED
+#define AMD_AM29LV010B 0x6E /* 1Mb, uniform */
#define AMD_AM29LV002BB 0xC2
#define AMD_AM29LV002BT 0x40
#define AMD_AM29LV004BB 0xB6
@@ -156,6 +157,10 @@
#define ATMEL_AT26DF161A 0x4601
#define ATMEL_AT26DF321 0x4700 /* Same as 25DF321 */
#define ATMEL_AT26F004 0x0400
+#define ATMEL_AT29LV512 0x3D
+#define ATMEL_AT29LV010A 0x35 /* Same as AT29BV010A, the latter works down to 2.7V */
+#define ATMEL_AT29LV020 0xBA
+#define ATMEL_AT29BV040A 0xC4
#define ATMEL_AT29C040A 0xA4
#define ATMEL_AT29C010A 0xD5
#define ATMEL_AT29C020 0xDA
@@ -187,13 +192,15 @@
#define ATMEL_AT45DB321D 0x2701 /* Buggy data sheet */
#define ATMEL_AT45DB642 /* No ID (opcode) available for AT45DB642 */
#define ATMEL_AT45DB642D 0x2800
-#define ATMEL_AT49BV512 0x03
+#define ATMEL_AT49BV512 0x03 /* Same as AT49F512 */
+#define ATMEL_AT49F001N 0x05 /* Same as AT49F001 */
+#define ATMEL_AT49F001NT 0x04 /* Same as AT49F001T */
#define ATMEL_AT49F002N 0x07 /* for AT49F002(N) */
#define ATMEL_AT49LH002 0xE9
#define ATMEL_AT49LH00B4 0xED
#define ATMEL_AT49LH004 0xEE
#define ATMEL_AT49F002NT 0x08 /* for AT49F002(N)T */
-#define ATMEL_AT49F010 0x17 /* Same as AT49HF010 */
+#define ATMEL_AT49F010 0x17 /* Same as AT49HF010 (some erroneous datasheets say 0x87), AT49BV010, AT49HBV010, AT49HLV010 */
#define ATMEL_AT49F020 0x0B
#define ATMEL_AT49F040 0x13
#define ATMEL_AT49F080 0x23
@@ -261,7 +268,7 @@
#define EON_EN25F80 0x3114
#define EON_EN25F16 0x3115
#define EON_EN25F32 0x3116
-#define EON_EN25F64 0x3117 /* guessed */
+#define EON_EN25F64 0x3117
#define EON_EN25Q40 0x3013
#define EON_EN25Q80 0x3014
#define EON_EN25Q16 0x3015 /* Same as EN25D16 */
@@ -561,7 +568,7 @@
* second byte is the device code,
* third byte is a dummy byte.
*/
-#define SANYO_ID 0x62 /* Sanyo */
+#define SANYO_ID 0x62 /* Sanyo */
#define SANYO_LE25FW203A 0x1600
#define SANYO_LE25FW403A 0x1100
#define SANYO_LE25FW106 0x15
@@ -644,8 +651,13 @@
#define SST_SST25WF020 0x2503
#define SST_SST25WF040 0x2504
#define SST_SST25WF080 0x2505
-#define SST_SST25VF512A_REMS 0x48 /* REMS or RES opcode */
-#define SST_SST25VF010_REMS 0x49 /* REMS or RES opcode */
+/* There exist some successors to members of the SST25WF family with alphabetic suffixes. They have very weird
+ * IDs and were not spotted in the wild yet. Their datasheets show a 4 byte long response w/o a vendor ID. */
+#define SST_SST25WF020A /* 0x62 0x16 0x12 0x00 */
+#define SST_SST25WF040B /* 0x62 0x16 0x13 0x00 */
+#define SST_SST25WF080B /* 0x62 0x16 0x14 0x00 */
+#define SST_SST25VF512_REMS 0x48 /* REMS or RES opcode, same as SST25VF512A */
+#define SST_SST25VF010_REMS 0x49 /* REMS or RES opcode, same as SST25VF010A */
#define SST_SST25VF020_REMS 0x43 /* REMS or RES opcode, same as SST25LF020A */
#define SST_SST25VF020B 0x258C
#define SST_SST25VF040_REMS 0x44 /* REMS or RES opcode, same as SST25LF040A */
@@ -667,6 +679,7 @@
#define SST_SST27VF010 0xA9
#define SST_SST27VF020 0xAA
#define SST_SST28SF040 0x04
+#define SST_SST29LE512 0x3D /* Same as SST29VE512 */
#define SST_SST29EE512 0x5D
#define SST_SST29EE010 0x07
#define SST_SST29LE010 0x08 /* Same as SST29VE010 */
@@ -685,6 +698,10 @@
#define SST_SST39VF020 0xD6 /* Same as 39LF020 */
#define SST_SST39VF040 0xD7 /* Same as 39LF040 */
#define SST_SST39VF080 0xD8 /* Same as 39LF080/39VF080/39VF088 */
+#define SST_SST45VF512 0x41 /* REMS, read opcode 0xFF */
+#define SST_SST45LF010 0x42 /* REMS, read opcode 0xFF, 'funny' other opcodes */
+#define SST_SST45VF010 0x45 /* REMS, read opcode 0xFF */
+#define SST_SST45VF020 0x43 /* REMS, read opcode 0xFF */
#define SST_SST49LF040B 0x50
#define SST_SST49LF040 0x51
#define SST_SST49LF020 0x61
@@ -785,6 +802,10 @@
#define SM_MVC_29C51002B 0xA2 /* Identical chips: {F,S,V}29C51002B */
#define SM_MVC_29C51004B 0xA3 /* Identical chips: {F,S,V}29C51004B */
+#define TENX_ID 0x7F7F5E /* Tenx Technologies */
+#define TENX_ID_NOPREFIX 0x5E
+#define TENX_ICE25P05 0x01 /* Maybe? */
+
#define TI_ID 0x97 /* Texas Instruments */
#define TI_OLD_ID 0x01 /* TI chips from last century */
#define TI_TMS29F002RT 0xB0
@@ -820,18 +841,18 @@
#define WINBOND_ID 0xDA /* Winbond */
#define WINBOND_W19B160BB 0x49
#define WINBOND_W19B160BT 0xC4
-#define WINBOND_W19B320SB 0x2A /* Same as W19L320SB */
-#define WINBOND_W19B320ST 0xBA /* Same as W19L320ST */
+#define WINBOND_W19B320SB 0x2A /* Same as W19L320SB */
+#define WINBOND_W19B320ST 0xBA /* Same as W19L320ST */
#define WINBOND_W19B322MB 0x92
#define WINBOND_W19B322MT 0x10
#define WINBOND_W19B323MB 0x94
#define WINBOND_W19B323MT 0x13
#define WINBOND_W19B324MB 0x97
#define WINBOND_W19B324MT 0x16
-#define WINBOND_W29C010 0xC1 /* Same as W29C010M, W29C011A, W29EE011, W29EE012, and ASD AE29F1008 */
-#define WINBOND_W29C020 0x45 /* Same as W29C020C, W29C022 and ASD AE29F2008 */
-#define WINBOND_W29C040 0x46 /* Same as W29C040P */
-#define WINBOND_W29C512A 0xC8 /* Same as W29EE512 */
+#define WINBOND_W29C010 0xC1 /* Same as W29C010M, W29C011A, W29EE011, W29EE012, and ASD AE29F1008 */
+#define WINBOND_W29C020 0x45 /* Same as W29C020C, W29C022 and ASD AE29F2008 */
+#define WINBOND_W29C040 0x46 /* Same as W29C040P */
+#define WINBOND_W29C512A 0xC8 /* Same as W29EE512 */
#define WINBOND_W29GL032CHL 0x7E1D01 /* Uniform Sectors, WP protects Top OR Bottom sector */
#define WINBOND_W29GL032CB 0x7E1A00 /* Top Boot Sector, WP protects Top 2 sectors */
#define WINBOND_W29GL032CT 0x7E1A01 /* Bottom Boot Sector, WP protects Bottom 2 sectors */
@@ -848,13 +869,13 @@
#define WINBOND_W39L512 0x38
#define WINBOND_W39V040A 0x3D
#define WINBOND_W39V040FA 0x34
-#define WINBOND_W39V040B 0x54 /* Same as W39V040FB */
-#define WINBOND_W39V040C 0x50 /* Same as W39V040FC */
+#define WINBOND_W39V040B 0x54 /* Same as W39V040FB */
+#define WINBOND_W39V040C 0x50 /* Same as W39V040FC */
#define WINBOND_W39V080A 0xD0
#define WINBOND_W39V080FA 0xD3
-#define WINBOND_W39V080FA_DM 0x93 /* W39V080FA dual mode */
-#define WINBOND_W49F002 0x25 /* Same as W49F002B */
-#define WINBOND_W49F002U 0x0B /* Same as W49F002N and ASD AE49F2008 */
+#define WINBOND_W39V080FA_DM 0x93 /* W39V080FA dual mode */
+#define WINBOND_W49F002 0x25 /* Same as W49F002B */
+#define WINBOND_W49F002U 0x0B /* Same as W49F002N and ASD AE49F2008 */
#define WINBOND_W49F020 0x8C
#define WINBOND_W49V002A 0xB0
#define WINBOND_W49V002FA 0x32
Modified: trunk/flashrom.8.tmpl
==============================================================================
--- trunk/flashrom.8.tmpl Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/flashrom.8.tmpl Wed Aug 6 17:09:15 2014 (r1839)
@@ -229,7 +229,7 @@
.sp
Some programmers have optional or mandatory parameters which are described
in detail in the
-.B PROGRAMMER SPECIFIC INFO
+.B PROGRAMMER-SPECIFIC INFORMATION
section. Support for some programmers can be disabled at compile time.
.B "flashrom \-h"
lists all supported programmers.
@@ -242,11 +242,11 @@
.BR <logfile> .
If the file already exists, it will be overwritten. This is the recommended
way to gather logs from flashrom because they will be verbose even if the
-on-screen messages are not verbose.
+on-screen messages are not verbose and don't require output redirection.
.TP
.B "\-R, \-\-version"
Show version information and exit.
-.SH PROGRAMMER SPECIFIC INFO
+.SH PROGRAMMER-SPECIFIC INFORMATION
Some programmer drivers accept further parameters to set programmer-specific
parameters. These parameters are separated from the programmer name by a
colon. While some programmers take arguments at fixed positions, other
@@ -474,7 +474,7 @@
.sp
.B " flashrom \-p internal:laptop=this_is_not_a_laptop"
.sp
-to tell flashrom (at your own risk) that it does not running on a laptop.
+to tell flashrom (at your own risk) that it is not running on a laptop.
.SS
.BR "dummy " programmer
The dummy programmer operates on a buffer in memory only. It provides a safe
@@ -595,7 +595,7 @@
.SS
.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\
, " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\
-, " satamv" , " atahpt" ", " atavia " and " it8212 " programmers
+, " satamv" , " atahpt", " atavia " and " it8212 " programmers
These programmers have an option to specify the PCI address of the card
your want to use, which must be specified if more than one card supported
by the selected programmer is installed in your system. The syntax is
@@ -782,7 +782,7 @@
.B value
can be
.BR 1 " or " 2
-to select target chip 1 or 2 repectively. The default is target chip 1.
+to select target chip 1 or 2 respectively. The default is target chip 1.
.SS
.BR "rayer_spi " programmer
The default I/O base address used for the parallel port is 0x378 and you can use
@@ -998,7 +998,7 @@
paragraph in the
.B internal programmer
subsection of the
-.B PROGRAMMER SPECIFIC INFO
+.B PROGRAMMER-SPECIFIC INFORMATION
section and the information in our wiki at
.BR "http://www.flashrom.org/Laptops " .
.SS
Modified: trunk/flashrom.c
==============================================================================
--- trunk/flashrom.c Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/flashrom.c Wed Aug 6 17:09:15 2014 (r1839)
@@ -1757,7 +1757,7 @@
* depending on compiler flags, e.g. the target architecture, and can sometimes be 0.
* For 'flashchips' we export the size explicitly to work around this and to be able to implement the
* checks below. */
- if (flashchips_size <= 1 || flashchips[flashchips_size-1].name != NULL) {
+ if (flashchips_size <= 1 || flashchips[flashchips_size - 1].name != NULL) {
msg_gerr("Flashchips table miscompilation!\n");
ret = 1;
} else {
Modified: trunk/ft2232_spi.c
==============================================================================
--- trunk/ft2232_spi.c Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/ft2232_spi.c Wed Aug 6 17:09:15 2014 (r1839)
@@ -69,7 +69,7 @@
{FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"},
{OLIMEX_VID, OLIMEX_ARM_OCD_PID, NT, "Olimex", "ARM-USB-OCD"},
{OLIMEX_VID, OLIMEX_ARM_TINY_PID, OK, "Olimex", "ARM-USB-TINY"},
- {OLIMEX_VID, OLIMEX_ARM_OCD_H_PID, NT, "Olimex", "ARM-USB-OCD-H"},
+ {OLIMEX_VID, OLIMEX_ARM_OCD_H_PID, OK, "Olimex", "ARM-USB-OCD-H"},
{OLIMEX_VID, OLIMEX_ARM_TINY_H_PID, OK, "Olimex", "ARM-USB-TINY-H"},
{0},
Modified: trunk/it8212.c
==============================================================================
--- trunk/it8212.c Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/it8212.c Wed Aug 6 17:09:15 2014 (r1839)
@@ -28,7 +28,7 @@
#define PCI_VENDOR_ID_ITE 0x1283
const struct dev_entry devs_it8212[] = {
- {PCI_VENDOR_ID_ITE, 0x8212, OK, "ITE", "8212F PATA RAID"},
+ {PCI_VENDOR_ID_ITE, 0x8212, NT, "ITE", "8212F PATA RAID"},
{},
};
Modified: trunk/print.c
==============================================================================
--- trunk/print.c Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/print.c Wed Aug 6 17:09:15 2014 (r1839)
@@ -662,6 +662,7 @@
B("ASUS", "DSAN-DX", NT, "http://www.asus.com/Server_Workstation/Server_Motherboards/DSANDX/", NULL),
B("ASUS", "E35M1-I DELUXE", OK, "http://www.asus.com/Motherboards/AMD_CPU_on_Board/E35M1I_DELUXE/", NULL),
B("ASUS", "F1A75-V PRO", OK, "http://www.asus.com/Motherboard/F1A75V_PRO/", NULL),
+ B("ASUS", "F2A85-M", DEP, "https://www.asus.com/Motherboards/F2A85M/", "UEFI builds v6404 and above disable access to some parts of the flash, cf. http://www.coreboot.org/ASUS_F2A85-M#UEFI_builds_that_allow_flash_chip_acce…"),
B("ASUS", "K8N", OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8N/", NULL),
B("ASUS", "K8V", OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8V/", NULL),
B("ASUS", "K8V SE Deluxe", OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8V_SE_Deluxe/", NULL),
@@ -675,6 +676,7 @@
B("ASUS", "M2NBP-VM CSM", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2NBPVM_CSM/", NULL),
B("ASUS", "M2N-E", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2NE/", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html"),
B("ASUS", "M2N-E SLI", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2NE_SLI/", NULL),
+ B("ASUS", "M2N-MX SE Plus", OK, "http://www.asus.com/Motherboards/M2NMX_SE_Plus/", NULL),
B("ASUS", "M2NPV-VM", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2NPVVM/", NULL),
B("ASUS", "M2N-SLI Deluxe", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2NSLI_Deluxe/", NULL),
B("ASUS", "M2V", OK, "http://www.asus.com/Motherboards/AMD_AM2/M2V/", NULL),
@@ -748,7 +750,7 @@
B("ASUS", "P5KPL-CM", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KPLCM/", NULL),
B("ASUS", "P5L-MX", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LMX/", NULL),
B("ASUS", "P5L-VM 1394", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LVM_1394/", NULL),
- B("ASUS", "P5LD2", NT, NULL, "Untested board enable."),
+ B("ASUS", "P5LD2", OK, NULL, NULL),
B("ASUS", "P5LD2-MQ", OK, "http://support.asus.com/download.aspx?SLanguage=en&p=8&s=12&m=Vintage-PH2&o…", "Found in ASUS Vintage-PH2 barebones."),
B("ASUS", "P5LD2-VM", NT, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM/", "Untested board enable."),
B("ASUS", "P5LD2-VM DH", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM_DH/", NULL),
@@ -1005,6 +1007,7 @@
B("MSI", "MS-7376 (K9A2 Platinum V1)", OK, "http://www.msi.com/product/mb/K9A2-Platinum.html", NULL),
B("MSI", "MS-7379 (G31M)", OK, "http://www.msi.com/product/mb/G31M.html", NULL),
B("MSI", "MS-7399 1.1 (Persian)", OK, "http://acersupport.com/acerpanam/desktop/0000/Acer/AspireM5640/AspireM5640s…", "This is an OEM board used by Acer in e.g. Aspire M5640/M3640."),
+ B("MSI", "MS-7502", OK, NULL, "This is an OEM board used by Medion in e.g. Medion MD8833."),
B("MSI", "MS-7522 (MSI X58 Pro-E)", OK, "http://www.msi.com/product/mb/X58_ProE.html", NULL),
B("MSI", "MS-7529 (G31M3-L(S) V2)", OK, "http://www.msi.com/product/mb/G31M3-L-V2---G31M3-LS-V2.html", NULL),
B("MSI", "MS-7529 (G31TM-P21)", OK, "http://www.msi.com/product/mb/G31TM-P21.html", NULL),
@@ -1046,6 +1049,7 @@
B("RCA", "RM4100", OK, "http://www.settoplinux.org/index.php?title=RCA_RM4100", NULL),
B("Samsung", "Polaris 32", OK, NULL, NULL),
B("SAPPHIRE", "IPC-E350M1", OK, "http://www.sapphiretech.com/presentation/product/?pid=1034&lid=1", NULL),
+ B("Shuttle", "AB61", OK, "http://www.shuttle.eu/_archive/older/de/ab61.htm", NULL),
B("Shuttle", "AK31", OK, "http://www.motherboard.cz/mb/shuttle/AK31.htm", NULL),
B("Shuttle", "AK38N", OK, "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/", NULL),
B("Shuttle", "AV11V30", OK, NULL, NULL),
@@ -1149,7 +1153,8 @@
B("ZOTAC", "GeForce 8200", OK, NULL, NULL),
B("ZOTAC", "H61-ITX WiFi (H61ITX-A-E)", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."),
B("ZOTAC", "H67-ITX WiFi (H67ITX-C-E)", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."),
- B("ZOTAC", "IONITX-A", OK, NULL, NULL),
+ B("ZOTAC", "IONITX-A-E", OK, NULL, NULL),
+ B("ZOTAC", "IONITX-F-E", OK, NULL, NULL),
B("ZOTAC", "nForce 630i Supreme (N73U-Supreme)", OK, NULL, NULL),
B("ZOTAC", "ZBOX AD02 (PLUS)", OK, NULL, NULL),
B("ZOTAC", "ZBOX HD-ID11", OK, NULL, NULL),
@@ -1171,16 +1176,17 @@
B("Dell", "Latitude CPi A366XT", BAD, "http://www.coreboot.org/Dell_Latitude_CPi_A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop."),
B("Dell", "Vostro 3700", BAD, NULL, "Locked ME, see http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html."),
B("Dell", "Latitude E6520", BAD, NULL, "Locked ME, see http://www.flashrom.org/pipermail/flashrom/2012-June/009420.html."),
- B("Elitegroup", "A928", OK, NULL, "Bootsector is locked and needs to be skipped with a layout file (writeable address range is 00000000:0003bfff"),
+ B("Elitegroup", "A928", OK, NULL, "Bootsector is locked and needs to be skipped with a layout file (writeable address range is 00000000:0003bfff)."),
B("HP/Compaq", "EliteBook 8560p", BAD, NULL, "SPI lock down, SMM protection, PR in BIOS region, read-only descriptor, locked ME region."),
B("HP/Compaq", "nx9005", BAD, "http://h18000.www1.hp.com/products/quickspecs/11602_na/11602_na.HTML", "Shuts down when probing for a chip. http://www.flashrom.org/pipermail/flashrom/2010-May/003321.html"),
B("HP/Compaq", "nx9010", BAD, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)."),
- B("IBM/Lenovo", "Thinkpad T40p", BAD, "http://www.thinkwiki.org/wiki/Category:T40p", NULL),
- B("IBM/Lenovo", "Thinkpad T420", BAD, "http://www.thinkwiki.org/wiki/Category:T420", "Probing works (Macronix MX25L6405, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."),
- B("IBM/Lenovo", "Thinkpad T410s", BAD, "http://www.thinkwiki.org/wiki/Category:T410s", "Probing works (Winbond W25X64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."),
- B("IBM/Lenovo", "Thinkpad X1", BAD, "http://www.thinkwiki.org/wiki/Category:X1", "Probing works (ST M25PX64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."),
- B("IBM/Lenovo", "240", BAD, "http://www.stanford.edu/~bresnan//tp240.html", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later."),
- B("Lenovo", "3000 V100 TF05Cxx", OK, "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…", NULL),
+ B("IBM/Lenovo", "ThinkPad T40p", BAD, "http://www.thinkwiki.org/wiki/Category:T40p", NULL),
+ B("IBM/Lenovo", "ThinkPad T420", BAD, "http://www.thinkwiki.org/wiki/Category:T420", "Probing works (Macronix MX25L6405, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."),
+ B("IBM/Lenovo", "ThinkPad T410s", BAD, "http://www.thinkwiki.org/wiki/Category:T410s", "Probing works (Winbond W25X64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."),
+ B("IBM/Lenovo", "ThinkPad X1", BAD, "http://www.thinkwiki.org/wiki/Category:X1", "Probing works (ST M25PX64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."),
+ B("IBM/Lenovo", "ThinkPad T530", OK, "http://www.thinkwiki.org/wiki/Category:T530", "Works fine but only with coreboot (due to locked regions and additional PR restrictions)."),
+ B("IBM/Lenovo", "ThinkPad 240", BAD, "http://www.stanford.edu/~bresnan//tp240.html", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later."),
+ B("IBM/Lenovo", "3000 V100 TF05Cxx", OK, "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…", NULL),
//B("MSI", "GT60-2OD", OK, "http://www.msi.com/product/nb/GT60_2OD.html", NULL), requires layout patches
#endif
Modified: trunk/sb600spi.c
==============================================================================
--- trunk/sb600spi.c Wed Aug 6 16:36:27 2014 (r1838)
+++ trunk/sb600spi.c Wed Aug 6 17:09:15 2014 (r1839)
@@ -191,7 +191,7 @@
return SPI_INVALID_LENGTH;
}
- unsigned int maxreadcnt = flash->mst->spi.max_data_read + 3;
+ unsigned int maxreadcnt = flash->mst->spi.max_data_read;
if (readcnt > maxreadcnt) {
msg_pinfo("%s: SPI controller can not receive %d bytes, it is limited to %d bytes\n",
__func__, readcnt, maxreadcnt);
1
0